OSDN Git Service
Jason Ekstrand [Wed, 13 Dec 2017 19:03:32 +0000 (11:03 -0800)]
intel/tools: Switch aubinator_error_decode over to the gen_print_batch
The shared framework can now do everything that aubinator_error_decode
ever did and more. It's time to make the switch.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 13 Dec 2017 17:46:39 +0000 (09:46 -0800)]
intel/batch-decoder: Decode graphics shaders
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 13 Dec 2017 17:19:57 +0000 (09:19 -0800)]
intel/batch-decoder: Decode vertex and index buffers
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 13 Dec 2017 16:01:03 +0000 (08:01 -0800)]
intel/batch-decoder: Decode MEDIA_INTERFACE_DESCRIPTOR_LOAD
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 13 Dec 2017 08:10:12 +0000 (00:10 -0800)]
intel/tools: Add the start of a generic batch decoder
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 13 Dec 2017 16:23:50 +0000 (08:23 -0800)]
intel/decoder: Expose the raw field value in the iterator
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 13 Dec 2017 07:26:51 +0000 (23:26 -0800)]
intel/disasm: Take a devinfo in gen_disasm_create
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 13 Dec 2017 01:36:47 +0000 (17:36 -0800)]
intel/decoder: Take a bit offset in gen_print_group
Previously, if a group was nested in another group such that it didn't
start on a dword boundary, we would decode it as if it started at the
start of its first dword. This changes things to work even more in
terms of bits so that we can properly decode these structs. This
affects MOCS, attribute swizzles, and several other things.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 13 Dec 2017 01:05:38 +0000 (17:05 -0800)]
intel/decoder: Stop rounding down to the nearest dword
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 13 Dec 2017 00:51:54 +0000 (16:51 -0800)]
intel/decoder: Convert the iterator to work entirely in bits
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 13 Dec 2017 00:12:16 +0000 (16:12 -0800)]
intel/decoder: Drop gen_field_decode helper
It's unused
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Samuel Pitoiset [Tue, 12 Dec 2017 17:10:23 +0000 (18:10 +0100)]
amd/common: add ac_build_waitcnt()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 12 Dec 2017 17:10:22 +0000 (18:10 +0100)]
amd/common: more use of i32_1
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 12 Dec 2017 17:10:21 +0000 (18:10 +0100)]
amd/common: more use of i32_0
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 12 Dec 2017 17:10:20 +0000 (18:10 +0100)]
radeonsi: make use of ac_build_fdiv()
And move the comment to amd/common.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Dec 2017 12:51:47 +0000 (13:51 +0100)]
radv: export SampleMask from pixel shaders at full rate
Use 16_ABGR instead of 32_ABGR if Z isn't written.
Ported from RadeonSI.
No CTS regressions on Polaris.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Dec 2017 12:51:46 +0000 (13:51 +0100)]
radeonsi: make use of ac_get_spi_shader_z_format()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Dec 2017 12:51:45 +0000 (13:51 +0100)]
amd/common: add ac_get_spi_shader_z_format()
ac_shader_util.c will contain shader helpers for RadeonSI
and RADV.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Dec 2017 16:32:41 +0000 (17:32 +0100)]
radv: do not load the local invocation index when it's unused
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Dec 2017 15:48:03 +0000 (16:48 +0100)]
radv: do not load unused gl_LocalInvocationID/gl_WorkGroupID components
We should also not load the input SGPRs and VGPRS, but
let's start with this for now.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Dec 2017 15:48:02 +0000 (16:48 +0100)]
amd/common: scan which components of gl_LocalInvocationID are used
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Dec 2017 15:48:01 +0000 (16:48 +0100)]
amd/common: scan which components of gl_WorkGroupID are used
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Dec 2017 14:51:20 +0000 (15:51 +0100)]
radv: set FORCE_SIMD_DIST(1) for compute when profitable
Ported from RadeonSI.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Dec 2017 14:51:19 +0000 (15:51 +0100)]
radv: calculate best compute resource limits
Ported from RadeonSI.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Dec 2017 14:51:18 +0000 (15:51 +0100)]
radv: store the dispatch initiator into the device
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Dec 2017 11:51:07 +0000 (12:51 +0100)]
radv: replace grid_components_used by uses_grid_size
Use a boolean instead because the number of needed SGPRs
is always 3.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Dec 2017 11:51:06 +0000 (12:51 +0100)]
radv: always emit all compute block components
The number of grid components is always 3 when gl_NumWorkGroups
is declared, because it relies on the number of components of
nir_instrinsic_load_num_work_groups.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Emil Velikov [Thu, 14 Dec 2017 13:52:11 +0000 (13:52 +0000)]
docs: update calendar, add news item and link release notes for 17.2.7
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 14 Dec 2017 13:49:09 +0000 (13:49 +0000)]
docs: add sha256 checksums for 17.2.7
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 14 Dec 2017 13:27:23 +0000 (13:27 +0000)]
docs: add release notes for 17.2.7
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Harish Krupo [Fri, 8 Dec 2017 15:59:39 +0000 (21:29 +0530)]
egl/android: Provide an option for the backend to expose KHR_image
From android cts 8.0_r4, a new test case checks if all the required egl
extensions are exposed. In the current implementation we expose KHR_image
if KHR_image_base and KHR_image_pixmap are supported but KHR_image spec
does not mandate the existence of both the extensions.
This patch preserves the current check and also provides the backend
with an option to expose the KHR_image extension.
Test: run cts -m CtsOpenGLTestCases -t \
android.opengl.cts.OpenGlEsVersionTest#testRequiredEglExtensions
Signed-off-by: Harish Krupo <harish.krupo.kps@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Bas Nieuwenhuizen [Tue, 12 Dec 2017 21:16:55 +0000 (22:16 +0100)]
radv: Don't advertise VK_EXT_debug_report.
We never supported it. Missed during copy and pasting.
Fixes:
17201a2eb0b "radv: port to using updated anv entrypoint/extension generator."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Kenneth Graunke [Wed, 13 Dec 2017 17:45:49 +0000 (09:45 -0800)]
i965: Don't allocate an MCS for 16x MSAA and width > 8192.
The hardware doesn't support this, and isl_surf_get_mcs_surf will fail.
I feel a bit bad replicating this logic, but we want to decide up front.
This fixes the following test when run with --deqp-surface-width=16384:
- GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_error_blitframebuffer_multisampled_framebuffers_different_sample_count
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Rob Herring [Wed, 13 Dec 2017 21:06:08 +0000 (15:06 -0600)]
Android: fix missing generation of vtn_gather_types.c
Commit
bb1e6ff161c9 ("spirv: Add a prepass to set types on vtn_values")
added generation of vtn_gather_types.c, but forgot to add it to the
Android build files.
Fixes:
bb1e6ff161c9 ("spirv: Add a prepass to set types on vtn_values")
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Dylan Baker [Tue, 12 Dec 2017 19:48:31 +0000 (11:48 -0800)]
mesa: Add glSpecializeShaderARB to common_desktop_functions
CC: Nicolai Hähnle <nicolai.haehnle@amd.com>
CC: Mark Janes <mark.a.janes@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104231
Fixes:
46b21b8f906 ("mesa: add GL_ARB_gl_spirv boilerplate")
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tomasz Figa [Mon, 4 Dec 2017 18:22:39 +0000 (19:22 +0100)]
egl/android: Partially handle HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED
There is no API available to properly query the IMPLEMENTATION_DEFINED
format. As a workaround we rely here on gralloc allocating either
an arbitrary YCbCr 4:2:0 or RGBX_8888, with the latter being recognized
by lock_ycbcr failing.
Reviewed-on: https://chromium-review.googlesource.com/566793
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Bruce Cherniak [Mon, 20 Nov 2017 17:32:55 +0000 (11:32 -0600)]
swr: Correct texture allocation and limit max size to 2GB
This patch fixes piglit tex3d-maxsize by correcting 4 things:
The total_size calculation was using 32-bit math, therefore a >4GB
allocation request overflowed and was not returning false (unsupported).
Changed AlignedMalloc arguments from "unsigned int" to size_t, to handle
>4GB allocations.
Added error checking on texture allocations to fail gracefully.
Finally, temporarily decreased supported max texture size from 4GB to 2GB.
The gallivm texture-sampler needs some additional work to correctly handle
larger than 2GB textures (offsets to LLVMBuildGEP are signed).
I'm working on a follow-on patch to allow up to 4GB textures, as this is
useful in HPC visualization applications.
Fixes piglit tex3d-maxsize.
v2: Updated patch description to clarify ">4GB".
Reviewed-By: George Kyriazis <george.kyriazis@intel.com>
Bruce Cherniak [Tue, 12 Dec 2017 23:18:23 +0000 (17:18 -0600)]
swr: Fix KNOB_MAX_WORKER_THREADS thread creation override.
Environment variable KNOB_MAX_WORKER_THREADS allows the user to override
default thread creation and thread binding. Previous commit to adjust
linux cpu topology caused setting this KNOB to bind all threads to a single
core.
This patch restores correct functionality of override.
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Dylan Baker [Tue, 12 Dec 2017 18:23:48 +0000 (10:23 -0800)]
meson: fix glx-test race
This test should rely on dispatch.h being generated, but it doesn't.
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Brian Paul [Wed, 13 Dec 2017 03:32:06 +0000 (20:32 -0700)]
gallium/docs: document behavior of set_sample_mask()
The sample mask is used even if msaa is not explicity enabled when we
have a framebuffer with multisampled surfaces. That's DX behavior and
what the Radeon drivers do. Not sure about other drivers at this point.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Brian Paul [Tue, 12 Dec 2017 22:11:21 +0000 (15:11 -0700)]
glsl: trivial whitespace fixes in link_varyings.cpp
Jordan Justen [Tue, 12 Dec 2017 19:44:01 +0000 (11:44 -0800)]
program: Don't reset SamplersValidated when restoring from shader cache
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103988
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Kai Wasserbäch [Tue, 12 Dec 2017 15:20:06 +0000 (16:20 +0100)]
mesa: remove second include of errors.h in src/mesa/main/glspirv.c
Fixes:
5bc03d2508 ("mesa: implement SPIR-V loading in glShaderBinary")
Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Timothy Arceri [Thu, 23 Nov 2017 01:59:01 +0000 (12:59 +1100)]
radeonsi: create get_tcs_tes_buffer_address helper
This will be shared between the NIR and TGSI backends.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Tue, 12 Dec 2017 05:10:24 +0000 (16:10 +1100)]
ac: fix nir_op_f2f64
Without this we get the error "FPExt only operates on FP" when
converting the following:
vec1 32 ssa_5 = b2f ssa_4
vec1 64 ssa_6 = f2f64 ssa_5
Which results in:
%44 = and i32 %43,
1065353216
%45 = fpext i32 %44 to double
With this patch we now get:
%44 = and i32 %43,
1065353216
%45 = bitcast i32 %44 to float
%46 = fpext float %45 to double
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Timothy Arceri [Tue, 12 Dec 2017 02:52:50 +0000 (13:52 +1100)]
nir: fix shift for uint64_t
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Tue, 12 Dec 2017 02:49:41 +0000 (13:49 +1100)]
st/glsl_to_nir: skip forced array splitting for tcs
nir_lower_io_to_temporaries() does not support tcs so we cannot
assume there are no indirects here. Also the radeonsi backend
(the only backend to support tess) has support for tcs indirects
so there is no need to lower them anyway.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Francisco Jerez [Tue, 12 Dec 2017 04:24:53 +0000 (20:24 -0800)]
intel/fs/bank_conflicts: Don't touch Gen7 MRF hack registers.
Fixes:
af2c320190f3c731 "intel/fs: Implement GRF bank conflict mitigation pass."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104199
Reported-by: Darius Spitznagel <d.spitznagel@goodbytez.de>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kevin Rogovin [Tue, 12 Dec 2017 12:17:27 +0000 (14:17 +0200)]
i965: compute scratch space size correctly for Gen9+
Fixes:
8ecdbb61360 "i965: Pretend there are 4 subslices for compute shader threads on Gen9+."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104005
Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Eero Tamminen <eero.t.tamminen@intel.com>
Kevin Rogovin [Tue, 12 Dec 2017 12:17:26 +0000 (14:17 +0200)]
i965: Program MEDIA_VFE_STATE in a more readable fashion.
This patch is purely for readability improvements when programming
the MEDIA_VFE_STATE.
Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Brian Paul [Fri, 8 Dec 2017 04:11:40 +0000 (21:11 -0700)]
cso: add point rasterization sanity check assertion
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Brian Paul [Thu, 7 Dec 2017 15:52:36 +0000 (08:52 -0700)]
gallium/u_blitter: replace tabs with spaces
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Fri, 8 Dec 2017 16:31:08 +0000 (09:31 -0700)]
xlib: call _mesa_warning() instead of fprintf()
We use _mesa_warning() everywhere else in this code. Change requested
by Rick Irons of Mathworks.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Brian Paul [Thu, 7 Dec 2017 22:00:49 +0000 (15:00 -0700)]
gallium/util: don't pass a pipe_resource to util_resource_is_array_texture()
No need to pass a pipe_resource when we can just pass the target.
This makes the function potentially more usable. Rename it too.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Thu, 7 Dec 2017 21:47:32 +0000 (14:47 -0700)]
gallium/aux: include nr_samples in util_resource_size() computation
This function is only used in two places:
1. VMware driver, but only for HUD reporting
2. st/nine state tracker, used for texture memory accounting
Fixes:
a69efa9482d ("util: add new util_resource_size() function in
u_resource.[ch]")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Thu, 7 Dec 2017 21:30:29 +0000 (14:30 -0700)]
svga: trivial whitespace/formatting fixes in svga_pipe_rasterizer.c
Brian Paul [Thu, 7 Dec 2017 20:33:57 +0000 (13:33 -0700)]
st/mesa: trivial whitespace/formatting fixes in st_atom_rasterizer.c
Jason Ekstrand [Fri, 8 Dec 2017 07:42:16 +0000 (23:42 -0800)]
spirv: Handle image and sampler function parameters
Jason Ekstrand [Fri, 8 Dec 2017 07:42:15 +0000 (23:42 -0800)]
spirv/cfg: Refactor the function parameter loop a bit
Jason Ekstrand [Fri, 8 Dec 2017 07:42:14 +0000 (23:42 -0800)]
spirv/cfg: Be a bit more precise about function parameters
Pointers with no storage type are converted to inout variables but SSA
values and pointers with a storage type (which turns into a uint or
uvec2) are just input variables.
Jason Ekstrand [Fri, 8 Dec 2017 07:42:13 +0000 (23:42 -0800)]
spirv: Make sampled images a real type
Previously, we just gave them exactly the same type as the respective
image (which already had a sampler2D or similar type). Now they have
their own base type and a pointer to the vtn_type for the image.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Eric Engestrom [Mon, 4 Dec 2017 14:30:13 +0000 (14:30 +0000)]
i915: add missing 0 defines
Thanks to Emil's -Wundef, t_dd_dmatmp.h now complains that intel_render.c
is missing a couple `#define`s.
Assigning them to 0 keeps the existing behaviour; I'll let someone else
turn them on if this is the behaviour that was intended.
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Nicolai Hähnle [Sat, 10 Jun 2017 17:57:18 +0000 (19:57 +0200)]
mesa: refuse to compile SPIR-V shaders or link mixed shaders
Note that gl_shader::CompileStatus will also indicate whether a shader
has been successfully specialized.
v2: Use the 'spirv_data' member of gl_shader to know if it is a SPIR-V
shader, instead of a dedicated flag. (Timothy Arceri)
v3: Use bool instead of GLboolean. (Ian Romanick)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Nicolai Hähnle [Sat, 10 Jun 2017 17:46:58 +0000 (19:46 +0200)]
mesa/shaderapi: add a getter for GL_SPIR_V_BINARY_ARB
v2: Use the 'spirv_data' member of gl_shader instead of a
dedicated flag. (Timothy Arceri)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Nicolai Hähnle [Sat, 10 Jun 2017 18:35:21 +0000 (20:35 +0200)]
mesa: implement SPIR-V loading in glShaderBinary
v2: * Add a gl_shader_spirv_data member to gl_shader, which already
encapsulates a gl_spirv_module where the binary will be saved.
(Eduardo Lima)
* Just use the 'spirv_data' member to know whether a gl_shader has
the SPIR_V_BINARY_ARB state. (Timothy Arceri)
* Remove redundant argument checks. Move extension presence check
to API entry point where the rest of checks are. Retype 'n' and
'length'arguments to use the correct and more standard types.
(Ian Romanick)
* Fix some nitpicks. (Ian Romanick)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eduardo Lima Mitev [Mon, 13 Nov 2017 12:57:46 +0000 (13:57 +0100)]
mesa/glspirv: Add struct gl_shader_spirv_data
This is a per-shader structure holding the SPIR-V data associated with the
shader (binary module, specialization constants and entry-point).
This is needed because both gl_shader and gl_linked_shader need to share this
data. Instead of copying the data, we pass a reference to it upon program
linking. That's why it is reference-counted.
This struct is created and associated with the shader upon calling
glShaderBinary(), then subsequently filled up by the call to
glSpecializeShaderARB().
v2: Readability improvements (Ian Romanick)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Nicolai Hähnle [Sat, 10 Jun 2017 18:14:44 +0000 (20:14 +0200)]
mesa/glspirv: Add struct gl_spirv_module
v2: * Make the SPIR-V module struct part of a larger gl_shader_spirv_data
struct that will be introduced later, and don't reference it directly
in gl_shader. (Eduardo Lima)
* Readability improvements (Ian Romanick)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Nicolai Hähnle [Sat, 10 Jun 2017 17:39:02 +0000 (19:39 +0200)]
mesa: add GL_ARB_gl_spirv boilerplate
v2: * Add meson build bits (Eric Engestrom)
* Return INVALID_OPERATION error on SpecializeShaderARB (Ian Romanick)
v3: Include boilerplate for the GL 4.6 alias of glSpecializeShaderARB
(Neil Roberts)
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Jason Ekstrand [Wed, 6 Dec 2017 18:01:22 +0000 (10:01 -0800)]
spirv: Add support for all bit sizes in OpSwitch
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101560
Jason Ekstrand [Wed, 6 Dec 2017 18:09:28 +0000 (10:09 -0800)]
spirv: Restructure the case loop in OpSwitch handling
Instead of calling vtn_add_case for the default case and then looping,
add an is_default variable and do everything inside the loop. This will
make the next commit easier.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Jason Ekstrand [Wed, 6 Dec 2017 17:35:10 +0000 (09:35 -0800)]
spirv: Add better parameter validation for vector and matrix types
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Jason Ekstrand [Wed, 6 Dec 2017 17:14:20 +0000 (09:14 -0800)]
spirv: Add type validation for OpSelect
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Jason Ekstrand [Wed, 6 Dec 2017 06:51:53 +0000 (22:51 -0800)]
spirv: Add basic type validation for OpLoad, OpStore, and OpCopyMemory
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Jason Ekstrand [Wed, 6 Dec 2017 06:31:02 +0000 (22:31 -0800)]
spirv: Add a prepass to set types on vtn_values
This autogenerated pass will automatically find and set the type field
on all vtn_values. This way we always have the type and can use it for
validation and other checks.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Jason Ekstrand [Wed, 6 Dec 2017 05:39:51 +0000 (21:39 -0800)]
spirv: Add a vtn_type field to all vtn_values
At the moment, this just lets us drop the const_type for constants and
unify things a bit. Eventually, we will use this to store the types of
all SPIR-V SSA values.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Samuel Iglesias Gonsálvez [Tue, 31 Oct 2017 10:47:57 +0000 (11:47 +0100)]
anv: fix bug when using component qualifier in FS outputs
We can write to the same output but in different components, like
in this example:
layout(location = 0, component = 0) out ivec2 dEQP_FragColor_0;
layout(location = 0, component = 2) out ivec2 dEQP_FragColor_1;
Therefore, they are not two different outputs but only one.
Fixes:
dEQP-VK.glsl.440.linkage.varying.component.frag_out.*
v3:
- Remove FRAG_RESULT_MAX.
- Add const and use sizeof (Ian).
- Do three-pass to set properly the locations of fragment
outputs when having arrays (Jason).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Ilia Mirkin [Sat, 2 Dec 2017 16:20:46 +0000 (11:20 -0500)]
st/mesa: swizzle argument when there's a vector size mismatch
GLSL IR operation arguments can sometimes have an implicit swizzle as a
result of a vector arg and a scalar arg, where the scalar argument is
implicitly expanded to the size of the vector argument.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103955
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Roland Scheidegger [Tue, 12 Dec 2017 03:22:28 +0000 (04:22 +0100)]
gallivm: fix texture wrapping for texture gather for mirror modes
Care must be taken that all coords end up correct, the tests are very
sensitive that everything is correctly rounded. This doesn't matter
for bilinear filter (since picking a wrong texel with weight zero is
ok), and we could also switch the per-sample coords mistakenly.
While here, also optimize the coord_mirror helper a bit (we can do the
mirroring directly by exploiting float rounding, no need for fixing up
odd/even manually).
I did not touch the mirror_clamp and mirror_clamp_to_border modes.
In contrast to mirror_clamp_to_edge and mirror_repeat these are legacy
modes. They are specified against old gl rules, which actually does
the mirroring not per sample (so you get swapped order if the coord
is in the mirrored section). I think the idea though is that they should
follow the respecified mirror_clamp_to_edge rules so the order would be
correct.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Jason Ekstrand [Mon, 11 Dec 2017 23:31:22 +0000 (15:31 -0800)]
spirv: Allow ignoring decorations for workgroup variables
Since we switched over to lowering SLM access directly in SPIR-V -> NIR,
we no longer have vtn_variables for SLM. It's all safe as with UBOs and
SSBOs but we need to let it through in the assert.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104213
Fixes:
8761a04d0d9332d9c0c99164faf855fc3c741f7c
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Wed, 6 Dec 2017 17:13:29 +0000 (09:13 -0800)]
spirv: Set lengths on scalar and vector types
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Bas Nieuwenhuizen [Sun, 10 Dec 2017 22:31:45 +0000 (23:31 +0100)]
ac/nir: Support vulkan_resource_reindex.
Fixes:
93b4cb61eb2 "spirv: Allow OpPtrAccessChain for block indices"
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sun, 10 Dec 2017 22:18:32 +0000 (23:18 +0100)]
ac/nir: Don't load the descriptor in vulkan_resource_index.
To support the reindex intrinsic, we need the result to be
something on which we can adjust the index/address.
Since it is all within a basic block, the compiler should be
able to merge any extra loads.
v2: Change visit_get_buffer_size too.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Marek Olšák [Mon, 11 Dec 2017 15:29:40 +0000 (16:29 +0100)]
winsys/amdgpu: disable local BOs again due to worse performance
Cc: 17.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 26 Jul 2017 13:21:45 +0000 (15:21 +0200)]
drirc: whitelist glthread for Mount and Blade Warband again
Bas Nieuwenhuizen [Sun, 10 Dec 2017 14:34:54 +0000 (15:34 +0100)]
radv: Don't use local BOs when allocating with export options.
If the app does not plan to put a buffer or image in it
(why? But it is allowed and CTS does it), they do not need to
allocate it with the deciate allocation struct.
Fixes:
a639d40f133 "radv: add support for local bos. (v3)"
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sun, 3 Dec 2017 14:35:39 +0000 (15:35 +0100)]
spirv: Fix loading an entire block at once.
There is no chain, so checking the length ends with a SEGFAULT.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103579
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jason Ekstrand [Sat, 2 Dec 2017 00:10:48 +0000 (16:10 -0800)]
anv: Enable UBO pushing
Push constants on Intel hardware are significantly more performant than
pull constants. Since most Vulkan applications don't actively use push
constants on Vulkan or at least don't use it heavily, we're pulling way
more than we should be. By enabling pushing chunks of UBOs we can get
rid of a lot of those pulls.
On my SKL GT4e, this improves the performance of Dota 2 and Talos by
around 2.5% and improves Aztec Ruins by around 2%.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Sun, 3 Dec 2017 06:34:47 +0000 (22:34 -0800)]
i965/fs: Handle !supports_pull_constants and push UBOs properly
In Vulkan, we don't support classic pull constants and everything the
client asks us to push, we push. However, for pushed UBOs, we still
want to fall back to conventional pulls if we run out of space.
Jason Ekstrand [Sat, 2 Dec 2017 00:07:23 +0000 (16:07 -0800)]
anv/device: Increase the UBO alignment requirement to 32
Push constants work in terms of 32-byte chunks so if we want to be able
to push UBOs, every thing needs to be 32-byte aligned. Currently, we
only require 16-byte which is too small.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Fri, 1 Dec 2017 22:28:46 +0000 (14:28 -0800)]
anv/cmd_buffer: Add support for pushing UBO ranges
In order to do this we have to modify push constant set up to handle
ranges. We also have to tweak the way we handle dirty bits a bit so
that we re-push whenever a descriptor set changes.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Fri, 1 Dec 2017 22:43:25 +0000 (14:43 -0800)]
anv/cmd_buffer: Add some stage asserts
There are several places where we look up opcodes in an array of stages.
Assert that the we don't end up going out-of-bounds.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Fri, 1 Dec 2017 12:25:05 +0000 (04:25 -0800)]
anv/cmd_buffer: Add some helpers for working with descriptor sets
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Fri, 1 Dec 2017 11:18:51 +0000 (03:18 -0800)]
anv/pipeline: Translate vulkan_resource_index to a constant when possible
We want to call brw_nir_analyze_ubo_ranges immedately after
anv_nir_apply_pipeline_layout and it badly wants constants. We could
run an optimization step and let constant folding do it but that's way
more expensive than needed. It's really easy to just handle constants
in apply_pipeline_layout.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Sun, 3 Dec 2017 06:32:59 +0000 (22:32 -0800)]
i965/fs: Rewrite assign_constant_locations
This rewires the logic for assigning uniform locations to work in terms
of "complex alignments". The basic idea is that, as we walk the list of
instructions, we keep track of the alignment and continuity requirements
of each slot and assert that the alignments all match up. We then use
those alignments in the compaction stage to ensure that everything gets
placed at a properly aligned register. The old mechanism handled
alignments by special-casing each of the bit sizes and placing 64-bit
values first followed by 32-bit values.
The old scheme had the advantage of never leaving a hole since all the
64-bit values could be tightly packed and so could the 32-bit values.
However, the new scheme has no type size special cases so it handles not
only 32 and 64-bit types but should gracefully extend to 16 and 8-bit
types as the need arises.
Tested-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 8 Dec 2017 23:39:00 +0000 (15:39 -0800)]
anv: Disable VK_KHR_16bit_storage
The testing for this extension is currently very poor. The CTS tests
only test accessing UBOs and SSBOs at dynamic offsets so none of our
constant-offset paths get triggered at all. Also, there's an assertion
in our handling of nir_intrinsic_load_uniform that offset % 4 == 0 which
is never triggered indicating that nothing every gets loaded from an
offset which is not a dword. Both push constants and the constant
offset pull paths are complex enough, we really don't want to ship
without tests. We'll turn the extension back on once we have decent
tests.
Leo Liu [Thu, 7 Dec 2017 17:04:59 +0000 (12:04 -0500)]
radeon/vce: move destroy command before feedback command
VCE processing IBs starts from session and task info at first level,
other commands processed subsequently. The task info for destroy is
embedded to destroy command, resulting that feedback command is not
properly procoessed. This is causing kernel spin VM fault messages on
Polaris and Vega10 card when running ends at encode application.
The fix is also verified on VCE physical mode card.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Cc: mesa-stable@lists.freedesktop.org
Acked-by: Christian König <christian.koenig@amd.com>
Ben Crocker [Mon, 27 Nov 2017 19:44:58 +0000 (14:44 -0500)]
docs/llvmpipe: document ppc64le as alternative architecture to x86.
Power8, Power8NV, and Power9 are supported on an equal footing
with X86.
Cc: "17.2" "17.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ben Crocker <bcrocker@redhat.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
[Eric: changed formatting, reworded a bit (with Ben's ack)]
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Emil Velikov [Fri, 8 Dec 2017 13:59:27 +0000 (13:59 +0000)]
docs/release-calendar: drop 17.3.0 from the table
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Fri, 8 Dec 2017 13:56:01 +0000 (13:56 +0000)]
docs: add news item and link release notes for 17.3.0
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Fri, 8 Dec 2017 13:53:30 +0000 (13:53 +0000)]
docs: add sha256 checksums for 17.3.0
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
49a612d1580b3316392273a069d20d93967126a8)