OSDN Git Service
Francis Visoiu Mistrih [Thu, 14 Dec 2017 10:02:58 +0000 (10:02 +0000)]
[CodeGen] Print external symbols as $symbol in both MIR and debug output
Work towards the unification of MIR and debug output by printing
`$symbol` instead of `<es:symbol>`.
Only debug syntax is affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320681
91177308-0d34-0410-b5e6-
96231b3b80d8
Igor Laevsky [Thu, 14 Dec 2017 09:33:58 +0000 (09:33 +0000)]
[Verifier] Check that GEP indexes has correct types
Differential Revision: https://reviews.llvm.org/D40391
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320680
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam Parker [Thu, 14 Dec 2017 09:31:01 +0000 (09:31 +0000)]
[DAGCombine] Move AND nodes to multiple load leaves
Recommitting rL319773, which was reverted due to a recursive issue
causing timeouts. This happened because I failed to check whether
the discovered loads could be narrowed further. In the case of a tree
with one or more narrow loads, that could not be further narrowed, as
well as a node that would need masking, an AND could be introduced
which could then be visited and recombined again with the same load.
This could again create the masking load, with would be combined
again... We now check that the load can be narrowed so that this
process stops.
Original commit message:
Search from AND nodes to find whether they can be propagated back to
loads, so that the AND and load can be combined into a narrow load.
We search through OR, XOR and other AND nodes and all bar one of the
leaves are required to be loads or constants. The exception node then
needs to be masked off meaning that the 'and' isn't removed, but the
loads(s) are narrowed still.
Differential Revision: https://reviews.llvm.org/D41177
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320679
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 14 Dec 2017 08:26:00 +0000 (08:26 +0000)]
[X86] Make ANY_EXTEND from vXi1 Custom for more types.
We should be able to support ANY_EXTEND for any types we support ZERO_EXTEND for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320675
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 14 Dec 2017 08:25:58 +0000 (08:25 +0000)]
[SelectionDAG][X86] Improve legalization of v32i1 CONCAT_VECTORS of v16i1 for AVX512F.
A v32i1 CONCAT_VECTORS of v16i1 uses promotion to v32i8 to legalize the v32i1. This results in a bunch of extract_vector_elts and a build_vector that ultimately gets scalarized.
This patch checks to see if v16i8 is legal and inserts a any_extend to that so that we can concat v16i8 to v32i8 and avoid creating the extracts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320674
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 14 Dec 2017 08:25:53 +0000 (08:25 +0000)]
[X86] Remove redundant setOperationAction calls.
These calls already exist earlier under AVX2 feature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320673
91177308-0d34-0410-b5e6-
96231b3b80d8
Dorit Nuzman [Thu, 14 Dec 2017 07:56:31 +0000 (07:56 +0000)]
[LV] Support efficient vectorization of an induction with redundant casts
D30041 extended SCEVPredicateRewriter to improve handling of Phi nodes whose
update chain involves casts; PSCEV can now build an AddRecurrence for some
forms of such phi nodes, under the proper runtime overflow test. This means
that we can identify such phi nodes as an induction, and the loop-vectorizer
can now vectorize such inductions, however inefficiently. The vectorizer
doesn't know that it can ignore the casts, and so it vectorizes them.
This patch records the casts in the InductionDescriptor, so that they could
be marked to be ignored for cost calculation (we use VecValuesToIgnore for
that) and ignored for vectorization/widening/scalarization (i.e. treated as
TriviallyDead).
In addition to marking all these casts to be ignored, we also need to make
sure that each cast is mapped to the right vector value in the vector loop body
(be it a widened, vectorized, or scalarized induction). So whenever an
induction phi is mapped to a vector value (during vectorization/widening/
scalarization), we also map the respective cast instruction (if exists) to that
vector value. (If the phi-update sequence of an induction involves more than one
cast, then the above mapping to vector value is relevant only for the last cast
of the sequence as we allow only the "last cast" to be used outside the
induction update chain itself).
This is the last step in addressing PR30654.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320672
91177308-0d34-0410-b5e6-
96231b3b80d8
Gadi Haber [Thu, 14 Dec 2017 07:26:08 +0000 (07:26 +0000)]
[X86][AES]: Adding full coverage of MC encoding for the AES and AVXAES isa sets.<NFC>
NFC.
Adding MC regressions tests to cover the AES and AVXAES ISA sets both 32 and 64 bit.
This patch is part of a larger task to cover MC encoding of all X86 ISA Sets.
started in revision: https://reviews.llvm.org/D39952
Reviewers: zvi, craig.topper, m_zuckerman, RKSimon
Differential Revision: https://reviews.llvm.org/D41154
Change-Id: I2564f9797628d0c070c4766f837f399337fb87d2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320670
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 14 Dec 2017 06:49:07 +0000 (06:49 +0000)]
[SelectionDAG] When legalizing the result type of CONCAT_VECTORS, take into account whether the input type also needs to be promoted.
If so go ahead and get the promoted input vector to extract from. Previously, we would create a bunch of any_extends of extract_vector_elts with illegal input type that needs to be promoted. The legalization of those extract_vector_elts would then potentially introduce a truncate. So now we have a bunch of any_extends of truncates. By legalizing both parts together we avoid creating these extra nodes.
The test changes seem to be because we were previously combining the build_vector with the any_extend before the any_extend got combined with the truncate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320669
91177308-0d34-0410-b5e6-
96231b3b80d8
Matthias Braun [Thu, 14 Dec 2017 03:59:24 +0000 (03:59 +0000)]
MC/AsmPrinter: Reduce code duplication.
Factor out duplicated code emitting mach-o version-min specifiers.
This should be NFC but happens to fix a bug where the code in
MCMachoStreamer didn't take the version skew between darwin and macos
versions into account.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320666
91177308-0d34-0410-b5e6-
96231b3b80d8
Matthias Braun [Thu, 14 Dec 2017 00:12:46 +0000 (00:12 +0000)]
MC: Add support for mach-o build_version
LC_BUILD_VERSION is a new load command superseding the previously used
LC_XXX_MIN_VERSION commands. This adds an assembler directive along with
encoding/streaming support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320661
91177308-0d34-0410-b5e6-
96231b3b80d8
Petr Hosek [Wed, 13 Dec 2017 23:49:51 +0000 (23:49 +0000)]
[CMake] Pass LLVM_HAVE_LINK_VERSION_SCRIPT to external projects
Some external projects depend on this LLVM CMake variable.
Differential Revision: https://reviews.llvm.org/D41205
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320658
91177308-0d34-0410-b5e6-
96231b3b80d8
Shoaib Meenai [Wed, 13 Dec 2017 23:38:12 +0000 (23:38 +0000)]
[cmake] Add support for case-sensitive Windows SDKs
When the Windows SDK is hosted on a case-sensitive filesystem (e.g. when
compiling on Linux and not using ciopfs), we can automatically generate
a VFS overlay for headers and symlinks for libraries.
Differential Revision: https://reviews.llvm.org/D41156
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320657
91177308-0d34-0410-b5e6-
96231b3b80d8
Shoaib Meenai [Wed, 13 Dec 2017 23:12:38 +0000 (23:12 +0000)]
[cmake] Support host architectures other than x64
Allow building for other architectures when cross-compiling for Windows.
Differential Revision: https://reviews.llvm.org/D41158
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320656
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 13 Dec 2017 23:11:30 +0000 (23:11 +0000)]
Recommit r320461 "[X86] Use regular expressions more aggressively to reduce the number of scheduler entries needed for FMA3 instructions."
I've hopefully sidestepped the MSVC issue that caused it to be reverted. We no longer include the Sched enum from X86GenInstrInfo.inc on the X86 target. So hopefully MSVC's preprocessor will skip over it and nothing will notice the 11000 character enum name.
Original commit message:
When the scheduler tables are generated by tablegen, the instructions are divided up into groups based on their default scheduling information and how they are referenced by groups for each processor. For any set of instructions that are matched by a specific InstRW line, that group of instructions is guaranteed to not be in a group with any other instructions. So in general, the more InstRW class definitions are created, the more groups we end up with in the generated files. Particularly if a lot of the InstRW lines only match to single instructions, which is true of a large number of the Intel scheduler models.
This change alone reduces the number of instructions groups from ~6000 to ~5500. And there's lots more we could do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320655
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 13 Dec 2017 22:57:35 +0000 (22:57 +0000)]
[EarlyCSE] recognize swapped variants of abs/nabs as equivalent
Extends https://reviews.llvm.org/rL320640
Differential Revision: https://reviews.llvm.org/D41136
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320653
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 22:43:55 +0000 (22:43 +0000)]
[X86] Add missing MULX32 schedule test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320651
91177308-0d34-0410-b5e6-
96231b3b80d8
Yaxun Liu [Wed, 13 Dec 2017 22:38:09 +0000 (22:38 +0000)]
CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value
Two issues were found about machine inst scheduler when compiling ProRender
with -g for amdgcn target:
GCNScheduleDAGMILive::schedule tries to update LiveIntervals for DBG_VALUE, which it
should not since DBG_VALUE is not mapped in LiveIntervals.
when DBG_VALUE is the last instruction of MBB, ScheduleDAGInstrs::buildSchedGraph and
ScheduleDAGMILive::scheduleMI does not move RPTracker properly, which causes assertion.
This patch fixes that.
Differential Revision: https://reviews.llvm.org/D41132
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320650
91177308-0d34-0410-b5e6-
96231b3b80d8
Zachary Turner [Wed, 13 Dec 2017 22:33:58 +0000 (22:33 +0000)]
[CodeView] Teach clang to emit the .debug$H COFF section.
Currently this is an LLVM extension to the COFF spec which is
experimental and intended to speed up linking. For now it is
behind a hidden cl::opt flag, but in the future we can move it
to a "real" cc1 flag and have the driver pass it through whenever
it is appropriate.
The patch to actually make use of this section in lld will come
in a followup.
Differential Revision: https://reviews.llvm.org/D40917
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320649
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 22:21:02 +0000 (22:21 +0000)]
Recover some overzealously removed includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320648
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 13 Dec 2017 22:19:40 +0000 (22:19 +0000)]
[EarlyCSE] add tests for swapped abs/nabs; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320647
91177308-0d34-0410-b5e6-
96231b3b80d8
Hans Wennborg [Wed, 13 Dec 2017 22:12:58 +0000 (22:12 +0000)]
Speculative build fix for llvm-pdbdump on Linux after Michael's #include removals
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320646
91177308-0d34-0410-b5e6-
96231b3b80d8
Hans Wennborg [Wed, 13 Dec 2017 22:12:57 +0000 (22:12 +0000)]
Speculative build fix for lld on Linux after Michael's #include removals
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320645
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 22:09:09 +0000 (22:09 +0000)]
[X86] Add CLWB schedule test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320644
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam Clegg [Wed, 13 Dec 2017 22:02:25 +0000 (22:02 +0000)]
[WebAssembly] Use bitfield types in wasm YAML representation
Differential Revision: https://reviews.llvm.org/D41202
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320642
91177308-0d34-0410-b5e6-
96231b3b80d8
Brian M. Rzycki [Wed, 13 Dec 2017 22:01:17 +0000 (22:01 +0000)]
Reverting [JumpThreading] Preservation of DT and LVI across the pass
Stage 2 bootstrap failed:
http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules-2/builds/14434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320641
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 13 Dec 2017 21:58:15 +0000 (21:58 +0000)]
[EarlyCSE] recognize commuted and swapped variants of min/max as equivalent (PR35642)
As shown in:
https://bugs.llvm.org/show_bug.cgi?id=35642
...we can have different forms of min/max, so we should recognize those here in EarlyCSE
similar to how we already handle binops and compares that can commute.
Differential Revision: https://reviews.llvm.org/D41136
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320640
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam Clegg [Wed, 13 Dec 2017 21:53:40 +0000 (21:53 +0000)]
[WebAssembly] Add linking metatdata test coverage for wasm2yaml
Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish
Differential Revision: https://reviews.llvm.org/D41196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320639
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 21:49:09 +0000 (21:49 +0000)]
[X86] Move ADX schedule tests out of schedule-x86_64.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320637
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:31:19 +0000 (21:31 +0000)]
Remove redundant includes from lib/Target/X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320636
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:31:17 +0000 (21:31 +0000)]
Remove redundant includes from lib/Target/ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320635
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:31:16 +0000 (21:31 +0000)]
Remove redundant includes from lib/Target/AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320634
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:31:14 +0000 (21:31 +0000)]
Remove redundant includes from lib/Target/*.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320633
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:31:13 +0000 (21:31 +0000)]
Remove redundant includes from utils/TableGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320632
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:31:10 +0000 (21:31 +0000)]
Remove redundant includes from tools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320631
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:31:05 +0000 (21:31 +0000)]
Remove redundant includes from unittests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320630
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:31:03 +0000 (21:31 +0000)]
Remove redundant includes from various places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320629
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:31:01 +0000 (21:31 +0000)]
Remove redundant includes from lib/Transforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320628
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:30:58 +0000 (21:30 +0000)]
Remove redundant includes from lib/Support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320627
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:30:57 +0000 (21:30 +0000)]
Remove redundant includes from lib/ProfileData.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320626
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:30:55 +0000 (21:30 +0000)]
Remove redundant includes from lib/Object.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320625
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:30:54 +0000 (21:30 +0000)]
Remove redundant includes from lib/MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320624
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:30:53 +0000 (21:30 +0000)]
Remove redundant includes from lib/LTO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320623
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:30:52 +0000 (21:30 +0000)]
Remove redundant includes from lib/IR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320622
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:30:50 +0000 (21:30 +0000)]
Remove redundant includes from lib/ExecutionEngine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320621
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:30:49 +0000 (21:30 +0000)]
Remove redundant includes from lib/DebugInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320620
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:30:47 +0000 (21:30 +0000)]
Remove redundant includes from lib/CodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320619
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:30:45 +0000 (21:30 +0000)]
Remove redundant includes from lib/Bitcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320618
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zolotukhin [Wed, 13 Dec 2017 21:30:41 +0000 (21:30 +0000)]
Remove redundant includes from lib/Analysis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320617
91177308-0d34-0410-b5e6-
96231b3b80d8
Shoaib Meenai [Wed, 13 Dec 2017 21:12:37 +0000 (21:12 +0000)]
[cmake] Explicitly set VS 2017 compatibility
When cross-compiling using clang-cl 5.0 (which is currently the latest
stable release of the compiler), the default MS compatibility level is
set to VS 2013, which is too low to build LLVM. Explicitly set the
compatibility level to VS 2017 to support cross-compiling LLVM for
Windows using clang-cl 5.0. This will be a no-op when using clang-cl 6.0
and above, where the default MS compatibility level is already VS 2017.
Differential Revision: https://reviews.llvm.org/D41157
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320616
91177308-0d34-0410-b5e6-
96231b3b80d8
Shoaib Meenai [Wed, 13 Dec 2017 21:11:14 +0000 (21:11 +0000)]
[cmake] Determine MSVC host triple correctly when cross-compiling
CMAKE_CL_64 will never be set when cross-compiling with clang-cl, since
CMake relies on an actual VS environment in order to determine it.
Instead, use the size of a void pointer to determine the bit width of
the host compiler (and therefore the host triple), which works for both
native and cross compilation.
Note that, with the impending advent of Windows on AArch64, assuming
that a 64-bit host == x86_64 isn't correct either, but that's something
to be addressed in a follow-up.
Differential Revision: https://reviews.llvm.org/D41155
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320615
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Wed, 13 Dec 2017 21:07:51 +0000 (21:07 +0000)]
AMDGPU: Partially fix disassembly of MIMG instructions
Stores failed to decode at all since they didn't have a
DecoderNamespace set. Loads worked, but did not change
the register width displayed to match the numbmer of
enabled channels.
The number of printed registers for vaddr is still wrong,
but I don't think that's encoded in the instruction so
there's not much we can do about that.
Image atomics are still broken. MIMG is the same
encoding for SI/VI, but the image atomic classes
are split up into encoding specific versions unlike
every other MIMG instruction. They have isAsmParserOnly
set on them for some reason. dmask is also special for
these, so we probably should not have it as an explicit
operand as it is now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320614
91177308-0d34-0410-b5e6-
96231b3b80d8
Brian M. Rzycki [Wed, 13 Dec 2017 20:52:26 +0000 (20:52 +0000)]
[JumpThreading] Preservation of DT and LVI across the pass
Summary:
See D37528 for a previous (non-deferred) version of this
patch and its description.
Preserves dominance in a deferred manner using a new class
DeferredDominance. This reduces the performance impact of
updating the DominatorTree at every edge insertion and
deletion. A user may call DDT->flush() within JumpThreading
for an up-to-date DT. This patch currently has one flush()
at the end of runImpl() to ensure DT is preserved across
the pass.
LVI is also preserved to help subsequent passes such as
CorrelatedValuePropagation. LVI is simpler to maintain and
is done immediately (not deferred). The code to perfom the
preversation was minimally altered and was simply marked
as preserved for the PassManager to be informed.
This extends the analysis available to JumpThreading for
future enhancements. One example is loop boundary threading.
Reviewers: dberlin, kuhar, sebpop
Reviewed By: kuhar, sebpop
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D40146
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320612
91177308-0d34-0410-b5e6-
96231b3b80d8
Aditya Kumar [Wed, 13 Dec 2017 19:40:07 +0000 (19:40 +0000)]
[GVNHoist] Fix: PR35222 gvn-hoist incorrectly erases load
w.r.t. the paper
"A Practical Improvement to the Partial Redundancy Elimination in SSA Form"
(https://sites.google.com/site/jongsoopark/home/ssapre.pdf)
Proper dominance check was missing here, so having a loopinfo should not be required.
Committing this diff as this fixes the bug, if there are
further concerns, I'll be happy to work on them.
Differential Revision: https://reviews.llvm.org/D39781
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320607
91177308-0d34-0410-b5e6-
96231b3b80d8
Adrian Prantl [Wed, 13 Dec 2017 19:10:54 +0000 (19:10 +0000)]
Ignore metainstructions during the shrink wrap analysis
Shrink wrapping should ignore DBG_VALUEs referring to frame indices,
since the presence of debug information must not affect code
generation.
Differential Revision: https://reviews.llvm.org/D41187
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320606
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Devlieghere [Wed, 13 Dec 2017 18:35:39 +0000 (18:35 +0000)]
[dsymutil][test] Fix failing test when no lipo binary available
The invocation without -no-output would try to lipo the different debug
objects together. This wouldn't work on platforms that don't provide
that utility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320605
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 18:09:45 +0000 (18:09 +0000)]
[X86] Add JCC/JECXZ/JECXZ/JRCXZ/LOOP schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320603
91177308-0d34-0410-b5e6-
96231b3b80d8
Amaury Sechet [Wed, 13 Dec 2017 18:04:57 +0000 (18:04 +0000)]
Regenerate test-shrink.ll test results. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320602
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Devlieghere [Wed, 13 Dec 2017 18:03:04 +0000 (18:03 +0000)]
[dsymutil] Re-enable threading
Threading was disabled in r317263 because it broke a test in combination
with `-DLLVM_ENABLE_THREADS=OFF`. This was because a ThreadPool warning
was piped to llvm-dwarfdump which was expecting to read an object from
stdin.
This patch re-enables threading and fixes the offending test.
Unfortunately this required more than just moving the ThreadPool out of
the for loop because of the TempFile refactoring that took place in the
meantime.
Differential revision: https://reviews.llvm.org/D41180
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320601
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 17:50:40 +0000 (17:50 +0000)]
[X86] Add RET/RETF schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320600
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 17:42:25 +0000 (17:42 +0000)]
[X86] Add POP/PUSH schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320598
91177308-0d34-0410-b5e6-
96231b3b80d8
Brian M. Rzycki [Wed, 13 Dec 2017 16:56:18 +0000 (16:56 +0000)]
[Function] Remove trailing end-of-line whitespace. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320595
91177308-0d34-0410-b5e6-
96231b3b80d8
Nemanja Ivanovic [Wed, 13 Dec 2017 15:28:01 +0000 (15:28 +0000)]
Fix link failure on one build bot introduced by r320584.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320589
91177308-0d34-0410-b5e6-
96231b3b80d8
Galina Kistanova [Wed, 13 Dec 2017 15:26:27 +0000 (15:26 +0000)]
Reverted r320229. It broke tests on builder llvm-clang-x86_64-expensive-checks-win.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320588
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 15:12:02 +0000 (15:12 +0000)]
[X86] Add PREFETCH schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320587
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 15:02:10 +0000 (15:02 +0000)]
[X86] Add XCHG schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320586
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 14:51:06 +0000 (14:51 +0000)]
[X86] Add MOVNTI schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320585
91177308-0d34-0410-b5e6-
96231b3b80d8
Nemanja Ivanovic [Wed, 13 Dec 2017 14:47:35 +0000 (14:47 +0000)]
[PowerPC] MachineSSA pass to reduce the number of CR-logical operations
The initial implementation of an MI SSA pass to reduce cr-logical operations.
Currently, the only operations handled by the pass are binary operations where
both CR-inputs come from the same block and the single use is a conditional
branch (also in the same block).
Committing this off by default to allow for a period of field testing. Will
enable it by default in a follow-up patch soon.
Differential Revision: https://reviews.llvm.org/D30431
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320584
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 14:46:33 +0000 (14:46 +0000)]
[X86] Add ENTER/LEAVE schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320583
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 14:24:04 +0000 (14:24 +0000)]
[X86] Add IMUL schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320582
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 14:22:04 +0000 (14:22 +0000)]
[X86] Add RDMSR/WRMSR, RDPMC + RDTSC/RDTSCP schedule tests
Add missing RDTSCP itinerary
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320581
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 13:54:45 +0000 (13:54 +0000)]
[X86] Add ARPL/BOUND schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320580
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Bradbury [Wed, 13 Dec 2017 12:46:55 +0000 (12:46 +0000)]
[RISCV] Define sfence.vma InstAliases to match the GNU RISC-V tools
Unfortunately these aren't defined explicitly in the privileged spec, but the
GNU assembler does accept `sfence.vma` and `sfence.vma rs` as well as the
usual `sfence.vma rs, rt`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320575
91177308-0d34-0410-b5e6-
96231b3b80d8
Igor Laevsky [Wed, 13 Dec 2017 11:49:04 +0000 (11:49 +0000)]
[FuzzMutate] Only generate loads and stores to the first class sized types
Differential Revision: https://reviews.llvm.org/D41109
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320573
91177308-0d34-0410-b5e6-
96231b3b80d8
Igor Laevsky [Wed, 13 Dec 2017 11:47:35 +0000 (11:47 +0000)]
[FuzzMutate] Avoid zero sized aggregates
Differential Revision: https://reviews.llvm.org/D41110
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320572
91177308-0d34-0410-b5e6-
96231b3b80d8
Igor Laevsky [Wed, 13 Dec 2017 11:45:53 +0000 (11:45 +0000)]
[FuzzMutate] Correctly split landingpad blocks
Differential Revision: https://reviews.llvm.org/D41112
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320571
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 11:43:14 +0000 (11:43 +0000)]
[X86][SSE] MOVMSK only uses the sign bit from each vector element
Pass the input vector through SimplifyDemandedBits as we only need the sign bit from each vector element of MOVMSK
We'd probably get more hits if SimplifyDemandedBits was better at handling vectors...
Differential Revision: https://reviews.llvm.org/D41119
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320570
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Bradbury [Wed, 13 Dec 2017 11:37:19 +0000 (11:37 +0000)]
[RISCV] Implement floating point assembler pseudo instructions
Adds the assembler aliases for the floating point instructions
which can be mapped to a single canonical instruction. The missing
pseudo instructions (flw, fld, fsw, fsd) are marked as TODO. Other
things, like for example PCREL_LO, have to be implemented first.
This patch builds upon D40902.
Differential Revision: https://reviews.llvm.org/D41071
Patch by Mario Werner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320569
91177308-0d34-0410-b5e6-
96231b3b80d8
Igor Laevsky [Wed, 13 Dec 2017 11:21:18 +0000 (11:21 +0000)]
Reintroduce r320049, r320014 and r319894.
OpenGL issues should be fixed by now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320568
91177308-0d34-0410-b5e6-
96231b3b80d8
Roger Ferrer Ibanez [Wed, 13 Dec 2017 10:45:21 +0000 (10:45 +0000)]
[DAG] Promote ADDCARRY / SUBCARRY
Add missing case that was not implemented yet.
Differential Revision: https://reviews.llvm.org/D38942
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320567
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Wed, 13 Dec 2017 10:30:59 +0000 (10:30 +0000)]
[CodeGen] Print jump-table index operands as %jump-table.0 in both MIR and debug output
Work towards the unification of MIR and debug output by printing `%jump-table.0` instead of `<jt#0>`.
Only debug syntax is affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320566
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Wed, 13 Dec 2017 10:30:51 +0000 (10:30 +0000)]
[CodeGen] Print target index operands as target-index(target-specific) + 8 in both MIR and debug output
Work towards the unification of MIR and debug output by printing `target-index(target-specific) + 8` instead of `<ti#0+8>` and `target-index(target-specific) + 8` instead of `<ti#0-8>`.
Only debug syntax is affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320565
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Wed, 13 Dec 2017 10:30:45 +0000 (10:30 +0000)]
[CodeGen] Print constant pool index operands as %const.0 + 8 in both MIR and debug output
Work towards the unification of MIR and debug output by printing
`%const.0 + 8` instead of `<cp#0+8>` and `%const.0 - 8` instead of
`<cp#0-8>`.
Only debug syntax is affected.
Differential Revision: https://reviews.llvm.org/D41116
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320564
91177308-0d34-0410-b5e6-
96231b3b80d8
Stefan Maksimovic [Wed, 13 Dec 2017 10:13:35 +0000 (10:13 +0000)]
[mips] Provide additional DSP bitconvert patterns
Previously, v2i16 -> f32 bitcast could not be matched.
Add patterns to support matching this and similar types of bitcasts.
Differential revision: https://reviews.llvm.org/D40959
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320562
91177308-0d34-0410-b5e6-
96231b3b80d8
Pavel Labath [Wed, 13 Dec 2017 10:00:38 +0000 (10:00 +0000)]
[Testing/Support] Make the HasValue matcher composable
Summary:
This makes it possible to run an arbitrary matcher on the value
contained within the Expected<T> object.
To do this, I've needed to fully spell out the matcher, instead of using
the shorthand MATCHER_P macro.
The slight gotcha here is that standard template deduction will fail if
one tries to match HasValue(47) against an Expected<int &> -- the
workaround is to use HasValue(testing::Eq(47)).
The explanations produced by this matcher have changed a bit, since now
we delegate to the nested matcher to print the value. Since these don't
put quotes around the value, I've changed our PrintTo methods to match.
Reviewers: zturner
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41065
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320561
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Bradbury [Wed, 13 Dec 2017 09:57:25 +0000 (09:57 +0000)]
[RISCV][NFC] Update RISCVInstrInfoC.td to match usual instruction naming convention
When an instruction mnemonic contains a '.', we usually name the instruction
with a _ in that place. e.g. fadd.s -> FADD_S.
This patch updates RISCVInstrInfoC.td to do the same, e.g. c.nop -> C_NOP.
Also includes some minor formatting changes in RISCVInstrInfoC.td to better
align it with the formatting conventions in the rest of the backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320560
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Bradbury [Wed, 13 Dec 2017 09:41:21 +0000 (09:41 +0000)]
[RISCV][NFC] Put isSImm6 and simm6 td definition in correct sorted position
We sort these helper functions and td definitions by bit width. simm6 was
previously out-of-order with respect to the others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320559
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Bradbury [Wed, 13 Dec 2017 09:32:55 +0000 (09:32 +0000)]
[RISCV] MC layer support for the remaining RVC instructions
Differential Revision: https://reviews.llvm.org/D40003
Patch by Shiva Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320558
91177308-0d34-0410-b5e6-
96231b3b80d8
Gadi Haber [Wed, 13 Dec 2017 09:13:53 +0000 (09:13 +0000)]
[X86][BMI]: Adding full coverage of MC encoding for the BMI isa set.<NFC>
NFC.
Adding MC regressions tests to cover the BMI1 and BMI2 ISA sets both 32 and 64 bit.
This patch is part of a larger task to cover MC encoding of all X86 ISA Sets.
started in revision: https://reviews.llvm.org/D39952
Reviewers: zvi, craig.topper, m_zuckerman, RKSimon
Differential Revision: https://reviews.llvm.org/D41106
Change-Id: I033ce137b5b82d36e1e601cd5e0534637b43a4a9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320557
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Bradbury [Wed, 13 Dec 2017 09:02:13 +0000 (09:02 +0000)]
[cmake] Fix host tools build in when LLVM_EXPERIMENTAL_TARGETS_TO_BUILD is set
r320413 triggered cmake configure failures when building with
-DLLVM_OPTIMIZED_TABLEGEN=True and with LLVM_EXPERIMENTAL_TARGETS_TO_BUILD set
(e.g. to RISCV). This is because that patch moved to passing through
LLVM_TARGETS_TO_BUILD, and at that point LLVM_EXPERIMENTAL_TARGETS_TO_BUILD
has been merged in to it. LLVM_EXPERIMENTAL_TARGETS_TO_BUILD must be also be
passed through to avoid errors like below:
-- Constructing LLVMBuild project information
CMake Error at CMakeLists.txt:682 (message):
The target `RISCV' does not exist.
It should be one of
AArch64;AMDGPU;ARM;BPF;Hexagon;Lanai;Mips;MSP430;NVPTX;PowerPC;Sparc;SystemZ;X86;XCore
-- Configuring incomplete, errors occurred!
See the thread
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20171211/509225.html
for discussion of this fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320556
91177308-0d34-0410-b5e6-
96231b3b80d8
Serguei Katkov [Wed, 13 Dec 2017 07:39:35 +0000 (07:39 +0000)]
Revert "[CGP] Enable select in complex addr mode"
Causes: Assertion `ScaledReg == nullptr' failed.
This actually a revert of rL320551.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320553
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 13 Dec 2017 07:26:17 +0000 (07:26 +0000)]
[Targets] Don't automatically include the scheduler class enum from *GenInstrInfo.inc with GET_INSTRINFO_ENUM. Make targets request is separately.
Most of the targets don't need the scheduler class enum.
I have an X86 scheduler model change that causes some names in the enum to become about 18000 characters long. This is because using instregex in scheduler models causes the scheduler class to get named with every instruction that matches the regex concatenated together. MSVC has a limit of 4096 characters for an identifier name. Rather than trying to come up with way to reduce the name length, I'm just going to sidestep the problem by not including the enum in X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320552
91177308-0d34-0410-b5e6-
96231b3b80d8
Serguei Katkov [Wed, 13 Dec 2017 06:57:59 +0000 (06:57 +0000)]
[CGP] Enable select in complex addr mode
Enable select instruction handling in complex addr modes.
Reviewers: john.brawn, reames, aaboud
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40634
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320551
91177308-0d34-0410-b5e6-
96231b3b80d8
Dean Michael Berris [Wed, 13 Dec 2017 06:37:13 +0000 (06:37 +0000)]
[XRay][compiler-rt] Reduce XRay log spam
This change makes XRay print the log file output only when the verbosity
level is higher than 0. It reduces the log spam in the default case when
we want XRay running silently, except when there are actual
fatal/serious errors.
We also update the documentation to show how to get the information
after the change to the default behaviour.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320550
91177308-0d34-0410-b5e6-
96231b3b80d8
Serguei Katkov [Wed, 13 Dec 2017 05:32:46 +0000 (05:32 +0000)]
[NFC] Refactor SafepointIRVerifier
Now two classes are responsible for verification: one of them can track GC
pointers and know whether a pointer is relocated or not and another based on
that information can verify uses of GC pointers.
Patch Author: Daniil Suchkov
Reviewers: mkazantsev, anna, apilipenko
Reviewed By: mkazantsev
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40885
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320549
91177308-0d34-0410-b5e6-
96231b3b80d8
Mohammad Shahid [Wed, 13 Dec 2017 03:08:29 +0000 (03:08 +0000)]
[SLP] Vectorize jumbled memory loads.
Summary:
This patch tries to vectorize loads of consecutive memory accesses, accessed
in non-consecutive or jumbled way. An earlier attempt was made with patch D26905
which was reverted back due to some basic issue with representing the 'use mask' of
jumbled accesses.
This patch fixes the mask representation by recording the 'use mask' in the usertree entry.
Change-Id: I9fe7f5045f065d84c126fa307ef6ebe0787296df
Reviewers: mkuper, loladiro, Ayal, zvi, danielcdh
Reviewed By: Ayal
Subscribers: mgrang, dcaballe, hans, mzolotukhin
Differential Revision: https://reviews.llvm.org/D36130
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320548
91177308-0d34-0410-b5e6-
96231b3b80d8
Florian Hahn [Wed, 13 Dec 2017 03:05:20 +0000 (03:05 +0000)]
[CallSiteSplitting] Refactor creating callsites.
Summary:
This change makes the call site creation more general if any of the
arguments is predicated on a condition in the call site's predecessors.
If we find a callsite, that potentially can be split, we collect the set
of conditions for the call site's predecessors (currently only 2
predecessors are allowed). To do that, we traverse each predecessor's
predecessors as long as it only has single predecessors and record the
condition, if it is relevant to the call site. For each condition, we
also check if the condition is taken or not. In case it is not taken,
we record the inverse predicate.
We use the recorded conditions to create the new call sites and split
the basic block.
This has 2 benefits: (1) it is slightly easier to see what is going on
(IMO) and (2) we can easily extend it to handle more complex control
flow.
Reviewers: davidxl, junbuml
Reviewed By: junbuml
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40728
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320547
91177308-0d34-0410-b5e6-
96231b3b80d8
Matthias Braun [Wed, 13 Dec 2017 02:51:04 +0000 (02:51 +0000)]
Rename LiveIntervalAnalysis.h to LiveIntervals.h
Headers/Implementation files should be named after the class they
declare/define.
Also eliminated an `#include "llvm/CodeGen/LiveIntervalAnalysis.h"` in
favor of `class LiveIntarvals;`
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320546
91177308-0d34-0410-b5e6-
96231b3b80d8
Matthias Braun [Wed, 13 Dec 2017 02:51:01 +0000 (02:51 +0000)]
Remove unnecessary includes; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320545
91177308-0d34-0410-b5e6-
96231b3b80d8
Evgeniy Stepanov [Wed, 13 Dec 2017 01:16:34 +0000 (01:16 +0000)]
[hwasan] Inline instrumentation & fixed shadow.
Summary: This brings CPU overhead on bzip2 down from 5.5x to 2x.
Reviewers: kcc, alekseyshl
Subscribers: kubamracek, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D41137
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320538
91177308-0d34-0410-b5e6-
96231b3b80d8