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George Burgess IV [Fri, 23 Dec 2016 01:18:09 +0000 (01:18 +0000)]
Don't consider allocsize functions to be allocation functions.
This patch fixes some ASAN unittest failures on FreeBSD. See the
cfe-commits email thread for r290169 for more on those.
According to the LangRef, the allocsize attribute only tells us about
the number of bytes that exist at the memory location pointed to by the
return value of a function. It does not necessarily mean that the
function will only ever allocate. So, we need to be very careful about
treating functions with allocsize as general allocation functions. This
patch makes us fully conservative in this regard, though I suspect that
we have room to be a bit more aggressive if we want.
This has a FIXME that can be fixed by a relatively straightforward
refactor; I just wanted to keep this patch minimal. If this sticks, I'll
come back and fix it in a few days.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290397
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Sanjoy Das [Fri, 23 Dec 2016 00:41:24 +0000 (00:41 +0000)]
NFC code motion in ImplicitNullChecks
Extract out two large lambdas into top level member functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290395
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Sanjoy Das [Fri, 23 Dec 2016 00:41:21 +0000 (00:41 +0000)]
Reimplement depedency tracking in the ImplicitNullChecks pass
Summary:
This change rewrites a core component in the ImplicitNullChecks pass for
greater simplicity since the original design was over-complicated for no
good reason. Please review this as essentially a new pass. The change
is almost NFC and I've added a test case for a scenario that this new
code handles that wasn't handled earlier.
The implicit null check pass, at its core, is a code hoisting transform.
It differs from "normal" code transforms in that it speculates
potentially faulting instructions (by design), but a lot of the usual
hazard detection logic (register read-after-write etc.) still applies.
We previously detected hazards by keeping track of registers defined and
used by machine instructions over an instruction range, but that was
unwieldy and did not actually confer any performance benefits. The
intent was to have linear time complexity over the number of machine
instructions considered, but it ended up being N^2 is practice.
This new version is more obviously O(N^2) (with N capped to 8 by
default) in hazard detection. It does not attempt to be clever in
tracking register uses or defs (the previous cleverness here was a
source of bugs).
Once this is checked in, I'll extract out the `IsSuitableMemoryOp` and
`CanHoistLoadInst` lambda into member functions (they're too complicated
to be inline lambdas) and do some other related NFC cleanups.
Reviewers: reames, anna, atrick
Subscribers: mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D27592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290394
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Chris Bieneman [Thu, 22 Dec 2016 22:58:07 +0000 (22:58 +0000)]
[ObjectYAML] Fixing a compiler warning
Accidentally re-defined the variable instead of setting it. Oops!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290388
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Quentin Colombet [Thu, 22 Dec 2016 22:50:34 +0000 (22:50 +0000)]
[GlobalISel] More fix for the size vs. type typo. NFC.
I missed those in my previous commit (r290378).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290387
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Chris Bieneman [Thu, 22 Dec 2016 22:44:27 +0000 (22:44 +0000)]
[ObjectYAML] Support for DWARF debug_info section
This patch adds support for YAML<->DWARF for debug_info sections.
This re-lands r290147, reverted in 290148, re-landed in r290204 after fixing the issue that caused bots to fail (thank you UBSan!), and reverted again in r290209 due to failures on big endian systems.
After adding support for preserving endianness, this should be good now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290386
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Ahmed Bougacha [Thu, 22 Dec 2016 22:27:05 +0000 (22:27 +0000)]
[AArch64] Simplify indexed-memory testcase. NFC.
We're only testing the addressing mode on the stores; we don't
need to load/store pointers we can simply pass/return.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290385
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Evgeniy Stepanov [Thu, 22 Dec 2016 22:22:35 +0000 (22:22 +0000)]
[cfi] Emit jump tables as a function-level inline asm.
Use a dummy private function with inline asm calls instead of module
level asm blocks for CFI jumptables.
The main advantage is that now jumptable codegen can be affected by
the function attributes (like target_cpu on ARM). Module level asm
gets the default subtarget based on the target triple, which is often
not good enough.
This change also uses asm constraints/arguments to reference
jumptable targets and aliases directly. We no longer do asm name
mangling in an IR pass.
Differential Revision: https://reviews.llvm.org/D28012
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290384
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Chris Bieneman [Thu, 22 Dec 2016 22:16:04 +0000 (22:16 +0000)]
[ObjectYAML] Fixing big endian bots from r290381
Bot URL:
http://lab.llvm.org:8011/builders/clang-s390x-linux/builds/2505
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290383
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Chris Bieneman [Thu, 22 Dec 2016 21:58:03 +0000 (21:58 +0000)]
[ObjectYAML] MachO support for endianness
This patch adds support to the macho<->yaml tools for preserving endianness in MachO structures and DWARF data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290381
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Quentin Colombet [Thu, 22 Dec 2016 21:56:39 +0000 (21:56 +0000)]
[MachineVerifier] Check that even generic vregs comply to regclass constraints.
We used to not check generic vregs, but that is actually a mistake given
nothing in the GlobalISel pipeline is going to fix the constraints on
target specific instructions. Therefore, the target has to have them
right from the start.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290380
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Quentin Colombet [Thu, 22 Dec 2016 21:56:37 +0000 (21:56 +0000)]
[AArch64] Change a test to use a generic instr instead of a target specific one.
Target specific instructions have requirements that are not compatible
with what we want to test here. Namely, target specific instructions
must have their operands properly mapped on register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290379
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Quentin Colombet [Thu, 22 Dec 2016 21:56:35 +0000 (21:56 +0000)]
[MIRParser] Fix a typo in comment and error message.
We have long switched from size to type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290378
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Quentin Colombet [Thu, 22 Dec 2016 21:56:31 +0000 (21:56 +0000)]
[AArch64][CallLowering] Constraint registers on target specific instruction
The InstructionSelect pass will not look at target specific instructions
since they are already selected. As a result, the operands of target
specific instructions must be properly constrained, because it is not
going to fix them.
This fixes invalid register classes on call instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290377
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Quentin Colombet [Thu, 22 Dec 2016 21:56:29 +0000 (21:56 +0000)]
[MIRParser] Non-generic virtual register may have a type.
When generic virtual registers get constrained, because of a use on a
target specific operation for instance, we end up with regular virtual
registers with a type and that's perfectly fine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290376
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Quentin Colombet [Thu, 22 Dec 2016 21:56:26 +0000 (21:56 +0000)]
[RegisterBankInfo] Allow to set a register class when nothing else is set
This is going to be needed to be able to constraint register class on
target specific instruction while the RegBankSelect pass did not run
yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290375
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Quentin Colombet [Thu, 22 Dec 2016 21:56:19 +0000 (21:56 +0000)]
[GlobalISel] Refactor the logic to constraint registers.
Move the logic to constraint register from InstructionSelector to a
utility function. It will be required by other passes in the GlobalISel
pipeline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290374
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Matt Arsenault [Thu, 22 Dec 2016 21:40:08 +0000 (21:40 +0000)]
AMDGPU: Invert cmp + select with constant
Canonicalize a select with a constant to the false side. This
enables more instruction shrinking opportunities since an
inline immediate can be used for the false side of v_cndmask_b32_e32.
This seems to usually be better but causes some code size regressions
in some tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290372
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Tim Shen [Thu, 22 Dec 2016 20:59:39 +0000 (20:59 +0000)]
[PowerPC] Add ppc support to update_llc_test_checks.py, and ppc tests. NFC.
Reviewers: chandlerc, hfinkel, echristo, iteratee
Subscribers: mehdi_amini, nemanjai, llvm-commits
Differential Revision: https://reviews.llvm.org/D28036
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290370
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Krzysztof Parzyszek [Thu, 22 Dec 2016 19:44:55 +0000 (19:44 +0000)]
[Hexagon] Add DAG mutations for machine pipeliner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290366
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Wei Mi [Thu, 22 Dec 2016 19:44:45 +0000 (19:44 +0000)]
Redo store splitting in CodeGenPrepare.
This is a succeeding patch of https://reviews.llvm.org/D22840 to address the
issue when a value to be merged into an int64 pair is in a different BB. Redoing
the store splitting in CodeGenPrepare so we can match the pattern across multiple
BBs and move some instructions into the same BB. We still keep the code in dag
combine so that we can catch cases that show up after DAG combining runs.
Differential Revision: https://reviews.llvm.org/D25914
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290365
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Wei Mi [Thu, 22 Dec 2016 19:38:22 +0000 (19:38 +0000)]
Change the interface of TLI.isMultiStoresCheaperThanBitsMerge.
This is for splitMergedValStore in DAG Combine to share the target query interface
with similar logic in CodeGenPrepare.
Differential Revision: https://reviews.llvm.org/D24707
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290363
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Petar Jovanovic [Thu, 22 Dec 2016 19:29:50 +0000 (19:29 +0000)]
[mips] Fix compact branch hazard detection, part 2
Follow up to D27209 fix, this patch now properly handles single transient
instruction in basic block.
Patch by Aleksandar Beserminji.
Differential Revision: https://reviews.llvm.org/D27856
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290361
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Krzysztof Parzyszek [Thu, 22 Dec 2016 19:21:20 +0000 (19:21 +0000)]
Add the DAG mutation interface to the software pipeliner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290360
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Reid Kleckner [Thu, 22 Dec 2016 19:12:14 +0000 (19:12 +0000)]
Pass -Wa,-mbig-obj in 64-bit mingw builds
COFF has a 2**16 section limit, and on Win64, every COMDAT function
creates at least 3 sections: .text, .pdata, and .xdata. For MSVC, we
enable bigobj on a file-by-file basis, but GCC appears to hit the limit
on different files.
Fixes PR25953
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290358
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Reid Kleckner [Thu, 22 Dec 2016 19:11:42 +0000 (19:11 +0000)]
Build KillTheDoctor with mingw-w64
compiler-rt uses it in its lit tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290357
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Krzysztof Parzyszek [Thu, 22 Dec 2016 18:49:55 +0000 (18:49 +0000)]
Fix two bugs in the pipeliner in renaming phis in the prolog and epilog
When the pipeliner is renaming phi values, it may need to iterate through
the phi operands to check for other phis. However, the pipeliner should
stop once it reaches a phi that is outside the pipelined loop.
Also, when the generateExistingPhis code is unable to reuse an existing
phi, the default code that computes the PhiOp2 is only to be used when
the pipeliner is generating the kernel. Otherwise, the phi may be a value
computed earlier in the same epilog.
Patch by Brendon Cahoon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290355
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Matt Arsenault [Thu, 22 Dec 2016 16:36:25 +0000 (16:36 +0000)]
AMDGPU: Use i16 for i16 shift amount
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290351
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Davide Italiano [Thu, 22 Dec 2016 16:35:02 +0000 (16:35 +0000)]
[NewGVN] Add the pass to PassRegistry.def.
We need to hook up here to get it working with the new PM.
Add a test while here (and remove a typo).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290350
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Matt Arsenault [Thu, 22 Dec 2016 16:27:14 +0000 (16:27 +0000)]
AMDGPU: Fix missing 16-bit cmpx instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290349
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Matt Arsenault [Thu, 22 Dec 2016 16:27:11 +0000 (16:27 +0000)]
AMDGPU: Use i16 comparison instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290348
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Matt Arsenault [Thu, 22 Dec 2016 16:06:32 +0000 (16:06 +0000)]
AMDGPU: Fixed '!NodePtr->isKnownSentinel()' assert
Caused by dereferencing end iterator when trying to const cast the iterator.
Patch by Martin Sherburn
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290347
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Davide Italiano [Thu, 22 Dec 2016 16:03:48 +0000 (16:03 +0000)]
[GVN] Initial check-in of a new global value numbering algorithm.
The code have been developed by Daniel Berlin over the years, and
the new implementation goal is that of addressing shortcomings of
the current GVN infrastructure, i.e. long compile time for large
testcases, lack of phi predication, no load/store value numbering
etc...
The current code just implements the "core" GVN algorithm, although
other pieces (load coercion, phi handling, predicate system) are
already implemented in a branch out of tree. Once the core is stable,
we'll start adding pieces on top of the base framework.
The test currently living in test/Transform/NewGVN are a copy
of the ones in GVN, with proper `XFAIL` (missing features in NewGVN).
A flag will be added in a future commit to enable NewGVN, so that
interested parties can exercise this code easily.
Differential Revision: https://reviews.llvm.org/D26224
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290346
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Dan Gohman [Thu, 22 Dec 2016 16:03:02 +0000 (16:03 +0000)]
[WebAssembly] Add an "explicit" keyword to a constructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290345
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Dan Gohman [Thu, 22 Dec 2016 16:00:55 +0000 (16:00 +0000)]
[WebAssembly] Don't use variadic operand indices in the MCOperandInfo array.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290344
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Dan Gohman [Thu, 22 Dec 2016 15:15:10 +0000 (15:15 +0000)]
[WebAssembly] Don't old negative load/store offsets in fast-isel.
WebAssembly's load/store offsets are unsigned and don't wrap, so it's not
valid to fold in a negative offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290342
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Sam Kolton [Thu, 22 Dec 2016 12:57:41 +0000 (12:57 +0000)]
[AMDGPU] Add pseudo SDWA instructions
Summary: This is needed for later SDWA support in CodeGen.
Reviewers: vpykhtin, tstellarAMD
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye
Differential Revision: https://reviews.llvm.org/D27412
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290338
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Sam Kolton [Thu, 22 Dec 2016 11:30:48 +0000 (11:30 +0000)]
[AMDGPU] Disassembler: fix for disaasembling v_mac_f32/16_dpp/sdwa
Summary: Real instruction should copy constraints from real instruction. This allows auto-generated disassembler to correctly process tied operands.
Reviewers: nhaustov, vpykhtin, tstellarAMD
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye
Differential Revision: https://reviews.llvm.org/D27847
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290336
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Ayman Musa [Thu, 22 Dec 2016 08:42:46 +0000 (08:42 +0000)]
[X86][AVX2] Passing the appropriate memory operand class to VPMADDWD instruction.
Replacing the memory operand in the ymm version of VPMADDWD from i128mem to i256mem.
Differential Revision: https://reviews.llvm.org/D28024
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290333
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Chandler Carruth [Thu, 22 Dec 2016 07:53:20 +0000 (07:53 +0000)]
[PM] Loosen the check ever so slightly -- MSVC appears to not include
a space after the comma in template arguments with our hacky type name
system.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290331
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Chandler Carruth [Thu, 22 Dec 2016 07:14:35 +0000 (07:14 +0000)]
[PM] Make a couple of CHECK lines a bit more precise, NFC.
I was staring at these and didn't realize these were module-layer
proxies as opposed to some other layer. Justin and I have a plan to
rename things to make the names themselves much easier to reason about,
but I at least want the CHECK lines to be precise for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290328
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Chandler Carruth [Thu, 22 Dec 2016 07:14:33 +0000 (07:14 +0000)]
[PM] Remove now-dead extern template and explicit instantiation
declarations.
We're using a custom class here instead of the helper template, these
bits just didn't get deleted when the other bits did get deleted. This
was found by a really nice MSVC warning about explicitly instantiating
a template where some member functions aren't defined and thus can't be
instantiatied.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290327
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Chandler Carruth [Thu, 22 Dec 2016 06:59:15 +0000 (06:59 +0000)]
[PM] Introduce a reasonable port of the main per-module pass pipeline
from the old pass manager in the new one.
I'm not trying to support (initially) the numerous options that are
currently available to customize the pass pipeline. If we end up really
wanting them, we can add them later, but I suspect many are no longer
interesting. The simplicity of omitting them will help a lot as we sort
out what the pipeline should look like in the new PM.
I've also documented to the best of my ability *why* each pass or group
of passes is used so that reading the pipeline is more helpful. In many
cases I think we have some questionable choices of ordering and I've
left FIXME comments in place so we know what to come back and revisit
going forward. But for now, I've left it as similar to the current
pipeline as I could.
Lastly, I've had to comment out several places where passes are not
ported to the new pass manager or where the loop pass infrastructure is
not yet ready. I did at least fix a few bugs in the loop pass
infrastructure uncovered by running the full pipeline, but I didn't want
to go too far in this patch -- I'll come back and re-enable these as the
infrastructure comes online. But I'd like to keep the comments in place
because I don't want to lose track of which passes need to be enabled
and where they go.
One thing that seemed like a significant API improvement was to require
that we don't build pipelines for O0. It seems to have no real benefit.
I've also switched back to returning pass managers by value as at this
API layer it feels much more natural to me for composition. But if
others disagree, I'm happy to go back to an output parameter.
I'm not 100% happy with the testing strategy currently, but it seems at
least OK. I may come back and try to refactor or otherwise improve this
in subsequent patches but I wanted to at least get a good starting point
in place.
Differential Revision: https://reviews.llvm.org/D28042
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290325
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Adrian Prantl [Thu, 22 Dec 2016 06:10:41 +0000 (06:10 +0000)]
Fix an assertion in DwarfExpression when emitting fragments in vector registers
When DwarfExpression is emitting a fragment that is located in a
register and that fragment is smaller than the register, and the
register must be composed from sub-registers (are you still with me?)
the last DW_OP_piece operation must not be larger than the size of the
fragment itself, since the last piece of the fragment could be smaller
than the last subregister that is being emitted.
rdar://problem/
29779065
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290324
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Adrian Prantl [Thu, 22 Dec 2016 05:27:12 +0000 (05:27 +0000)]
Refactor the DIExpression fragment query interface (NFC)
... so it becomes available to DIExpressionCursor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290322
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Matt Arsenault [Thu, 22 Dec 2016 04:39:45 +0000 (04:39 +0000)]
DAG: Add helper for testing constant values
There are helpers for testing for constant or constant build_vector,
and for splat ConstantFP vectors, but not for a constantfp or
non-splat ConstantFP vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290317
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Matt Arsenault [Thu, 22 Dec 2016 04:39:41 +0000 (04:39 +0000)]
AMDGPU: Fix missing commute table entries for cmpx
No tests because these aren't currently used anywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290316
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Mehdi Amini [Thu, 22 Dec 2016 04:09:29 +0000 (04:09 +0000)]
[ThinLTO] Save 8B per summary entry by rearranging the fields (NFC)
Size goes from 72B to 64B per entry.
Differential Revision: https://reviews.llvm.org/D27970
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290314
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Matt Arsenault [Thu, 22 Dec 2016 04:03:40 +0000 (04:03 +0000)]
AMDGPU: Swap order of operands in fadd/fsub combine
FMA is canonicalized to constant in the middle operand. Do
the same so fmad matches and avoid an extra combine step.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290313
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Matt Arsenault [Thu, 22 Dec 2016 04:03:35 +0000 (04:03 +0000)]
AMDGPU: Check fast math flags in fadd/fsub combines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290312
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Matt Arsenault [Thu, 22 Dec 2016 03:55:35 +0000 (03:55 +0000)]
AMDGPU: Form more FMAs if fusion is allowed
Extend the existing fadd/fsub->fmad combines to produce
FMA if allowed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290311
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Matt Arsenault [Thu, 22 Dec 2016 03:44:42 +0000 (03:44 +0000)]
AMDGPU: Move combines into separate functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290309
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Matt Arsenault [Thu, 22 Dec 2016 03:40:39 +0000 (03:40 +0000)]
AMDGPU: Enable some f32 fadd/fsub combines for f16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290308
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Matt Arsenault [Thu, 22 Dec 2016 03:21:48 +0000 (03:21 +0000)]
AMDGPU: Implement isFMAFasterThanFMulAndFAdd for f16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290307
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Matt Arsenault [Thu, 22 Dec 2016 03:21:45 +0000 (03:21 +0000)]
AMDGPU: setcc test cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290306
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Matt Arsenault [Thu, 22 Dec 2016 03:05:44 +0000 (03:05 +0000)]
AMDGPU: Allow rcp and rsq usage with f16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290302
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Matt Arsenault [Thu, 22 Dec 2016 03:05:41 +0000 (03:05 +0000)]
AMDGPU: Custom lower f16 fdiv
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290301
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Matt Arsenault [Thu, 22 Dec 2016 03:05:37 +0000 (03:05 +0000)]
AMDGPU: Implement f16 fcanonicalize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290300
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Matt Arsenault [Thu, 22 Dec 2016 03:05:30 +0000 (03:05 +0000)]
AMDGPU: Update isFPImmLegal for f16
I don't think this matters because ConstantFP is legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290299
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Peter Collingbourne [Thu, 22 Dec 2016 02:52:23 +0000 (02:52 +0000)]
Clear the PendingTypeTests vector after moving from it.
This is to put the vector into a well defined state. Apparently the state of a
vector after being moved from is valid but unspecified. Found with clang-tidy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290298
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Haicheng Wu [Thu, 22 Dec 2016 01:39:24 +0000 (01:39 +0000)]
[AArch64] Correct the check of signed 9-bit imm in getIndexedAddressParts().
-256 is a legal indexed address part.
Differential Revision: https://reviews.llvm.org/D27537
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290296
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Easwaran Raman [Thu, 22 Dec 2016 01:07:01 +0000 (01:07 +0000)]
Pass GetAssumptionCache to InlineFunctionInfo constructor
Differential revision: https://reviews.llvm.org/D28038
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290295
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David Majnemer [Thu, 22 Dec 2016 00:51:59 +0000 (00:51 +0000)]
[NVVMIntrRange] Only set range metadata if none is already present
The range metadata inserted by NVVMIntrRange is pessimistic, range
metadata already present could be more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290294
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Adrian Prantl [Thu, 22 Dec 2016 00:45:21 +0000 (00:45 +0000)]
Renumber testcase metadata nodes after r290153.
This patch renumbers the metadata nodes in debug info testcases after
https://reviews.llvm.org/D26769. This is a separate patch because it
causes so much churn. This was implemented with a python script that
pipes the testcases through llvm-as - | llvm-dis - and then goes
through the original and new output side-by side to insert all
comments at a close-enough location.
Differential Revision: https://reviews.llvm.org/D27765
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290292
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Adrian Prantl [Thu, 22 Dec 2016 00:29:00 +0000 (00:29 +0000)]
[LLParser] Make the line field of DIMacro(File) optional.
Otherwise these records do not survive roundtrips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290291
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Adrian Prantl [Wed, 21 Dec 2016 23:38:17 +0000 (23:38 +0000)]
Legalize metadata in legacy testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290288
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Adrian Prantl [Wed, 21 Dec 2016 23:36:06 +0000 (23:36 +0000)]
Legalize metadata in legacy testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290287
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Adrian Prantl [Wed, 21 Dec 2016 23:30:35 +0000 (23:30 +0000)]
Legalize metadata in legacy testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290286
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Adrian Prantl [Wed, 21 Dec 2016 23:28:49 +0000 (23:28 +0000)]
Legalize metadata in legacy testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290285
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Ahmed Bougacha [Wed, 21 Dec 2016 23:26:20 +0000 (23:26 +0000)]
[GlobalISel] Add basic Selector-emitter tblgen backend.
This adds a basic tablegen backend that analyzes the SelectionDAG
patterns to find simple ones that are eligible for GlobalISel-emission.
That's similar to FastISel, with one notable difference: we're not fed
ISD opcodes, so we need to map the SDNode operators to generic opcodes.
That's done using GINodeEquiv in TargetGlobalISel.td.
Otherwise, this is mostly boilerplate, and lots of filtering of any kind
of "complicated" pattern. On AArch64, this is sufficient to match G_ADD
up to s64 (to ADDWrr/ADDXrr) and G_BR (to B).
Differential Revision: https://reviews.llvm.org/D26878
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290284
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Ahmed Bougacha [Wed, 21 Dec 2016 23:26:13 +0000 (23:26 +0000)]
[AsmWriter] Remove redundant cast<>s. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290283
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Dan Gohman [Wed, 21 Dec 2016 23:09:42 +0000 (23:09 +0000)]
[WebAssembly] Fix the opcode value for i64.rotr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290281
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Peter Collingbourne [Wed, 21 Dec 2016 23:03:45 +0000 (23:03 +0000)]
IR: Function summary representation for type tests.
Each function summary has an attached list of type identifier GUIDs. The
idea is that during the regular LTO phase we would match these GUIDs to type
identifiers defined by the regular LTO module and store the resolutions in
a top-level "type identifier summary" (which will be implemented separately).
Differential Revision: https://reviews.llvm.org/D27967
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290280
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Mike Aizatsky [Wed, 21 Dec 2016 22:10:01 +0000 (22:10 +0000)]
[sancov] skip duplicated points
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290278
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Mike Aizatsky [Wed, 21 Dec 2016 22:09:57 +0000 (22:09 +0000)]
[sancov] hash prefix results in huge merge files, use shorter prefix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290277
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Haicheng Wu [Wed, 21 Dec 2016 21:40:47 +0000 (21:40 +0000)]
[AArch64] Remove a redundant check. NFC.
The case AM.Scale == 0 is already handled by the code right above.
Differential Revision: https://reviews.llvm.org/D28003
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290275
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Greg Clayton [Wed, 21 Dec 2016 21:37:06 +0000 (21:37 +0000)]
Add the ability for DWARFDie objects to get the parent DWARFDie.
In order for the llvm DWARF parser to be used in LLDB we will need to be able to get the parent of a DIE. This patch adds that functionality by changing the DWARFDebugInfoEntry class to store a depth field instead of a sibling index. Using a depth field allows us to easily calculate the sibling and the parent without increasing the size of DWARFDebugInfoEntry.
I tested llvm-dsymutil on a debug version of clang where this fully parses DWARF in over 1200 .o files to verify there was no serious regression in performance.
Added a full suite of unit tests to test this functionality.
Differential Revision: https://reviews.llvm.org/D27995
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290274
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Justin Bogner [Wed, 21 Dec 2016 21:19:00 +0000 (21:19 +0000)]
cmake: Don't build llvm-config and tblgen concurrently in cross builds
This sets USES_TERMINAL for the native llvm-config build, so that it
doesn't run at the same time as builds of other native tools (namely,
tablegen). Without this, if you're very unlucky with the timing it's
possible to be relinking libSupport as one of the tools is linking,
causing a spurious failure.
The tablegen build adopted USES_TERMINAL for this same reason in
r280748.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290271
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Ed Maste [Wed, 21 Dec 2016 20:51:42 +0000 (20:51 +0000)]
Update mailing list post URL and add libunwind reference
RTDyldMemoryManager.cpp describes the differing __register_frame
API between libunwind and libgcc, with a mailing list posting URL.
The original link was 404; replace it with what I believe is the
intended post, as well as a reference to the "OS X" implementation in
libunwind.
Differential Revision: https://reviews.llvm.org/D27965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290269
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Simon Pilgrim [Wed, 21 Dec 2016 20:00:10 +0000 (20:00 +0000)]
[X86][SSE] Improve lowering of vXi64 multiplies
As mentioned on PR30845, we were performing our vXi64 multiplication as:
AloBlo = pmuludq(a, b);
AloBhi = pmuludq(a, psrlqi(b, 32));
AhiBlo = pmuludq(psrlqi(a, 32), b);
return AloBlo + psllqi(AloBhi, 32)+ psllqi(AhiBlo, 32);
when we could avoid one of the upper shifts with:
AloBlo = pmuludq(a, b);
AloBhi = pmuludq(a, psrlqi(b, 32));
AhiBlo = pmuludq(psrlqi(a, 32), b);
return AloBlo + psllqi(AloBhi + AhiBlo, 32);
This matches the lowering on gcc/icc.
Differential Revision: https://reviews.llvm.org/D27756
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290267
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David Majnemer [Wed, 21 Dec 2016 19:21:59 +0000 (19:21 +0000)]
Revert "[InstCombine] New opportunities for FoldAndOfICmp and FoldXorOfICmp"
This reverts commit r289813, it caused PR31449.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290266
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Tom Stellard [Wed, 21 Dec 2016 19:06:24 +0000 (19:06 +0000)]
AMDGPU/SI: Fix file header
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290265
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Peter Collingbourne [Wed, 21 Dec 2016 19:00:47 +0000 (19:00 +0000)]
TypeMetadataUtils: Simplify; spotted by Mehdi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290264
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Zachary Turner [Wed, 21 Dec 2016 18:50:52 +0000 (18:50 +0000)]
Add missing includes on Windows.
Patch by Andrey Khalyavin
Differential Revision: https://reviews.llvm.org/D27915
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290263
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Michael Kuperstein [Wed, 21 Dec 2016 18:29:47 +0000 (18:29 +0000)]
[LLParser] Parse vector GEP constant expression correctly
The constantexpr parsing was too constrained and rejected legal vector GEPs.
This relaxes it to be similar to the ones for instruction parsing.
This fixes PR30816.
Differential Revision: https://reviews.llvm.org/D28013
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290261
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Michael Kuperstein [Wed, 21 Dec 2016 17:34:21 +0000 (17:34 +0000)]
[ConstantFolding] Fix vector GEPs harder
For vector GEPs, CastGEPIndices can end up in an infinite recursion, because
we compare the vector type to the scalar pointer type, find them different,
and then try to cast a type to itself.
Differential Revision: https://reviews.llvm.org/D28009
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290260
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Simon Pilgrim [Wed, 21 Dec 2016 15:49:01 +0000 (15:49 +0000)]
[CostModel] Pass shuffle mask args with ArrayRef. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290257
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Michael Zuckerman [Wed, 21 Dec 2016 12:48:01 +0000 (12:48 +0000)]
revert first commit . removing empty line in X86.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290255
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Michael Zuckerman [Wed, 21 Dec 2016 12:44:47 +0000 (12:44 +0000)]
First commit adding new line to X86.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290254
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Elena Demikhovsky [Wed, 21 Dec 2016 10:43:36 +0000 (10:43 +0000)]
Added a template for building target specific memory node in DAG.
I added API for creation a target specific memory node in DAG. Today, all memory nodes are common for all targets and their constructors are located in SelectionDAG.cpp.
There are some cases in X86 where we need to create a special node - truncation-with-saturation store, float-to-half-store.
In the current patch I added truncation-with-saturation nodes and I'm using them for intrinsics. In the future I plan to implement DAG lowering for truncation-with-saturation pattern.
Differential Revision: https://reviews.llvm.org/D27899
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290250
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Davide Italiano [Wed, 21 Dec 2016 10:19:00 +0000 (10:19 +0000)]
[AMDGPU] Garbage collect dead code. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290249
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Oren Ben Simhon [Wed, 21 Dec 2016 09:47:31 +0000 (09:47 +0000)]
[X86] Vectorcall Calling Convention - Adding CodeGen Complete Support
Fixing a warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290248
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Oren Ben Simhon [Wed, 21 Dec 2016 09:18:37 +0000 (09:18 +0000)]
[X86] Vectorcall Calling Convention - Adding CodeGen Complete Support
Fixing failing test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290246
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Oren Ben Simhon [Wed, 21 Dec 2016 08:59:42 +0000 (08:59 +0000)]
[X86] Vectorcall Calling Convention - Adding CodeGen Complete Support
Fixing build issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290244
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Oren Ben Simhon [Wed, 21 Dec 2016 08:31:45 +0000 (08:31 +0000)]
[X86] Vectorcall Calling Convention - Adding CodeGen Complete Support
The vectorcall calling convention specifies that arguments to functions are to be passed in registers, when possible.
vectorcall uses more registers for arguments than fastcall or the default x64 calling convention use.
The vectorcall calling convention is only supported in native code on x86 and x64 processors that include Streaming SIMD Extensions 2 (SSE2) and above.
The current implementation does not handle Homogeneous Vector Aggregates (HVAs) correctly and this review attempts to fix it.
This aubmit also includes additional lit tests to cover better HVAs corner cases.
Differential Revision: https://reviews.llvm.org/D27392
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290240
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Adam Nemet [Wed, 21 Dec 2016 04:07:40 +0000 (04:07 +0000)]
[LDist] Match behavior between invoking via optimization pipeline or opt -loop-distribute
In r267672, where the loop distribution pragma was introduced, I tried
it hard to keep the old behavior for opt: when opt is invoked
with -loop-distribute, it should distribute the loop (it's off by
default when ran via the optimization pipeline).
As MichaelZ has discovered this has the unintended consequence of
breaking a very common developer work-flow to reproduce compilations
using opt: First you print the pass pipeline of clang
with -debug-pass=Arguments and then invoking opt with the returned
arguments.
clang -debug-pass will include -loop-distribute but the pass is invoked
with default=off so nothing happens unless the loop carries the pragma.
While through opt (default=on) we will try to distribute all loops.
This changes opt's default to off as well to match clang. The tests are
modified to explicitly enable the transformation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290235
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Sebastian Pop [Wed, 21 Dec 2016 03:37:39 +0000 (03:37 +0000)]
remove pretty-print test that requires debug
There is no need to test the pretty printer. Remove the boggus test to make the
build bots happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290234
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Tim Shen [Wed, 21 Dec 2016 02:39:21 +0000 (02:39 +0000)]
[APFloat] Remove 'else' after return. NFC
Reviewers: kbarton, iteratee, hfinkel, echristo
Subscribers: mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D27934
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290232
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Lang Hames [Wed, 21 Dec 2016 02:08:23 +0000 (02:08 +0000)]
[Orc][RPC] Actually specialize SerializationTraits and RPCTypeName in the right
namespace.
r290226 was a think-o - just qualifying the name doesn't count.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290230
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Sebastian Pop [Wed, 21 Dec 2016 01:41:12 +0000 (01:41 +0000)]
machine combiner: fix pretty printer
we used to print UNKNOWN instructions when the instruction to be printer was not
yet inserted in any BB: in that case the pretty printer would not be able to
compute a TII as the instruction does not belong to any BB or function yet.
This patch explicitly passes the TII to the pretty-printer.
Differential Revision: https://reviews.llvm.org/D27645
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290228
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