OSDN Git Service
Michel Dänzer [Fri, 8 Feb 2019 09:14:58 +0000 (10:14 +0100)]
gitlab-ci: Re-use docker image from the main repo in forked repos
Instead of generating it from scratch in each forked repo. This should
save time, energy and storage. (The xserver & xf86-video-amdgpu CI
scripts do basically the same)
v2:
* Hardcode "mesa" instead of using $CI_PROJECT_NAME, to avoid breakage
if the project name is changed after forking (Eric Engestrom)
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Ilia Mirkin [Sun, 10 Feb 2019 03:36:49 +0000 (22:36 -0500)]
nvc0: we have 16k-sized framebuffers, fix default scissors
For some reason we don't use view volume clipping by default, and use
scissors instead. These scissors were set to an 8k max fb size, while
the driver advertises 16k-sized framebuffers.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
Alyssa Rosenzweig [Fri, 8 Feb 2019 02:28:12 +0000 (02:28 +0000)]
panfrost: Specify supported draw modes per-context
Midgard has native support for QUADS and POLYGONS; Bifrost seemingly
does not. Thus, Midgard generally skips prim_convert whereas Bifrost
needs the pass; this patch allows the setting of allowed primitives to
occur on a per-context basis (for runtime hardware selection).
v2: Use (POLYGONS + 1) instead of LINES_ADJACENCY.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Robert Foss <robert.foss@collabora.com>
Dave Airlie [Fri, 8 Feb 2019 04:27:09 +0000 (14:27 +1000)]
radv: remove alloc parameter from pipeline init
clang points out this isn't used.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dave Airlie [Fri, 8 Feb 2019 05:25:49 +0000 (15:25 +1000)]
radv/llvm: initialise passes member.
Fixes coverity warning
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dave Airlie [Fri, 8 Feb 2019 05:23:46 +0000 (15:23 +1000)]
glsl: glsl to nir fix uninit class member.
The constructor should init this to NULL
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Alyssa Rosenzweig [Sat, 9 Feb 2019 01:14:34 +0000 (01:14 +0000)]
panfrost: Elucidate texture op scheduling comment
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Sat, 9 Feb 2019 01:13:23 +0000 (01:13 +0000)]
panfrost: Remove speculative if 0'd format bit code
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Fri, 8 Feb 2019 02:21:46 +0000 (02:21 +0000)]
panfrost: Remove if 0'd dead code
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Thu, 7 Feb 2019 06:00:11 +0000 (06:00 +0000)]
panfrost: Add kernel-agnostic resource management
Various methods relating to resource management were previously marked
as kernel-specific, forcing them to stay downstream in the vendor
overlay and eventually be duplicated for DRM code. This patch adds back
this code in kernel-neutral space, allowing for code sharing and
minimising the diff to downstream.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Thu, 7 Feb 2019 04:56:13 +0000 (04:56 +0000)]
panfrost: Don't hardcode number of nir_ssa_defs
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Thu, 7 Feb 2019 03:39:25 +0000 (03:39 +0000)]
panfrost: Clean-up one-argument passing quirk
Most Midgard instructions take two-arguments logically; there are always
two arguments at the assembly level. For the few instructions that take
only a single argument, generally the second argument slot is unused,
with a zero inline constant occupying the space. fmov/imov are the
exception, where the first argument is filled with r24 and the logical
argument is in the second slot.
Previously, these constraints were handled by a delicate, buggy series
of hacks. This commit removes these hacks. Instead, we look at the
logical number of arguments (from NIR), switching between two argument
and one-argument-one-zero style. We then introduce a quirk for the
flipped style, which applies to fmov/imov.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Karol Herbst [Sat, 9 Feb 2019 00:22:27 +0000 (01:22 +0100)]
glsl_type: initialize offset and location to -1 for glsl_struct_field
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Fri, 8 Feb 2019 23:57:19 +0000 (15:57 -0800)]
nouveau: Silence unhandled cap warnings
Nouveau apparently uses the u_screen helper but prints a warning in the
default case, so running any GL program would start grumbling.
Fixes:
8fa54bc5490 gallium: Add a PIPE_CAP_NIR_COMPACT_ARRAYS capability bit.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Caio Marcelo de Oliveira Filho [Thu, 7 Feb 2019 21:44:33 +0000 (13:44 -0800)]
intel/compiler: use 0 as sampler in emit_mcs_fetch
The sampler will be ignored since the underlying 'ld_mcs' operation
won't use it, so just fill the field with 0 instead of the texture to
make it clearer that's the case.
This will also avoid is_high_sampler() to kick in unnecessarily, in
case we are using the operation for a texture with index >= 16.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eric Engestrom [Sun, 25 Nov 2018 11:23:26 +0000 (11:23 +0000)]
wsi: query the ICD's max dimensions instead of hard-coding them
anv and radv both happened to already return 2^14 for these, but
querying the ICD is safer and will help if vdreno (or whatever it's
called) doesn't have the same max.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Ian Romanick [Fri, 18 Jan 2019 01:53:40 +0000 (17:53 -0800)]
nir: Convert a bcsel with only phi node sources to a phi node
v2: Remove the original ALU instruciton after all of its readers are
modified to read the new ALU instruction.
v3: Fix an issue where a bcsel that may not be executed on a loop
iteration due to a break statement is converted to a phi (and therefore
incorrectly "executed"). Noticed by Tim.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109216
Fixes:
8fb8ebfbb05 ("intel/compiler: More peephole select")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Ian Romanick [Fri, 18 Jan 2019 01:34:47 +0000 (17:34 -0800)]
nir: Split ALU instructions in loops that read phis
A single shader in Unigine Superposition is affected by this change.
A single iadd is moved to the end of a loop. This iadd is involved in
a complex set of logic to terminate the loop, and an extra mov
instruction is inserted. This shader really needs the optimization
suggested by bugzilla #94747, and I expect that to make this tiny
regression go away.
All Gen7+ platforms had similar results. (Skylake shown)
total instructions in shared programs:
15047543 ->
15047545 (<.01%)
instructions in affected programs: 565 -> 567 (0.35%)
helped: 0
HURT: 2
total cycles in shared programs:
369977253 ->
369978253 (<.01%)
cycles in affected programs: 127910 -> 128910 (0.78%)
helped: 0
HURT: 2
v2: Skip nir_op_vec{2,3,4} and nir_op_[fi]mov instructions to avoid
infinite optimization loops. Remove the original ALU instruciton after
all of its readers are modified to read the new ALU instruction.
v3: Extend to the more general case. The if the prev-block value from
the phi is not undef, this means the ALU instruction has to be
duplicated in both the prev-block and the continue-block.
Fixes:
8fb8ebfbb05 ("intel/compiler: More peephole select")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Ian Romanick [Mon, 14 Jan 2019 23:12:36 +0000 (15:12 -0800)]
nir: Select phi nodes using prev_block instead of continue_block
This simplifies some changes coming later.
Fixes:
8fb8ebfbb05 ("intel/compiler: More peephole select")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Ian Romanick [Mon, 14 Jan 2019 19:36:23 +0000 (11:36 -0800)]
nir: Refactor code that checks phi nodes in opt_peel_loop_initial_if
This will be used in a couple more places soon.
The function name is... horribly long. Neither Matt nor I could think
of any thing that was shorter and still more descriptive than
"is_phi_foo". I'm willing to entertain suggestions.
Fixes:
8fb8ebfbb05 ("intel/compiler: More peephole select")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Ian Romanick [Wed, 16 Jan 2019 19:34:35 +0000 (11:34 -0800)]
nir: Document some fields of nir_loop_terminator
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Ian Romanick [Fri, 25 Jan 2019 01:18:01 +0000 (17:18 -0800)]
intel/compiler: Silence warning about value that may be used uninitialized
For some reason, this warning only occurs for me in release builds.
In file included from src/intel/compiler/brw_nir_lower_mem_access_bit_sizes.c:25:0:
src/intel/compiler/brw_nir_lower_mem_access_bit_sizes.c: In function ‘brw_nir_lower_mem_access_bit_sizes’:
src/compiler/nir/nir_builder.h:501:26: warning: ‘src_swiz[2]’ may be used uninitialized in this function [-Wmaybe-uninitialized]
alu_src.swizzle[i] = swiz[i];
~~~~~~~~~~~~~~~~~~~^~~~~~~~~
src/intel/compiler/brw_nir_lower_mem_access_bit_sizes.c:225:16: note: ‘src_swiz[2]’ was declared here
unsigned src_swiz[4];
^~~~~~~~
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Ian Romanick [Thu, 24 Jan 2019 22:37:16 +0000 (14:37 -0800)]
nir: Silence zillions of unused parameter warnings in release builds
Fixes:
cd56d79b59f "nir: check NIR_SKIP to skip passes by name"
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Eric Engestrom [Fri, 8 Feb 2019 17:43:55 +0000 (17:43 +0000)]
gitlab-ci: workaround docker bug for users with uppercase characters
CI_REGISTRY_IMAGE == lower($CI_REGISTRY/$CI_PROJECT_PATH)
Suggested-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Andrii Simiklit [Tue, 2 Oct 2018 16:16:01 +0000 (19:16 +0300)]
i965: consider a 'base level' when calculating width0, height0, depth0
I guess that when we calculating the width0, height0, depth0
to use for function 'intel_miptree_create' we need to consider
the 'base level' like it is done in the 'intel_miptree_create_for_teximage'
function.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107987
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Sun, 9 Dec 2018 23:23:51 +0000 (10:23 +1100)]
nir: rewrite varying component packing
There are a number of reasons for the rewrite.
1. Adding support for packing tess patch varyings in a sane way.
2. Making use of qsort allowing the code to be much easier to
follow.
3. Fixes a bug where different interp types caused component
packing to be skipped for all varyings in some scenarios.
4. Allows us to add a crude live range analysis for deciding
which components should be packed together. This support can
optionally be added in a future patch.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Sun, 9 Dec 2018 22:42:42 +0000 (09:42 +1100)]
nir: add is_packing_supported_for_type() helper
This will be used in the following patches to determine if we
support packing the components of a varying.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Wed, 6 Feb 2019 01:27:39 +0000 (12:27 +1100)]
nir: add glsl_type_is_32bit() helper
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Sun, 2 Dec 2018 23:42:40 +0000 (10:42 +1100)]
nir: add support for marking used patches when packing varyings
This adds support needed for marking the varyings as used but we
don't actually support packing patches in this patch.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Wed, 6 Feb 2019 09:37:14 +0000 (20:37 +1100)]
st/glsl_to_nir: call nir_remove_dead_variables() after lowing local indirects
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Wed, 6 Feb 2019 01:18:52 +0000 (12:18 +1100)]
util: move BITFIELD macros to util/macros.h
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Karol Herbst [Wed, 16 Jan 2019 14:17:31 +0000 (15:17 +0100)]
st/mesa: require RGBA2, RGB4, and RGBA4 to be renderable
If the driver does not support rendering to these formats but does
support texturing, we can end up in incompatibilities between textures
and renderbuffers that are then copied to.
Fixes KHR-GL45.copy_image.functional on nvc0
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Karol Herbst [Fri, 25 Aug 2017 17:22:03 +0000 (19:22 +0200)]
gallium: add PIPE_CAP_MAX_VARYINGS
Some NVIDIA hardware can accept 128 fragment shader input components,
but only have up to 124 varying-interpolated input components. We add a
new cap to express this cleanly. For most drivers, this will have the
same value as PIPE_SHADER_CAP_MAX_INPUTS for the fragment shader.
Fixes KHR-GL45.limits.max_fragment_input_components
Signed-off-by: Karol Herbst <karolherbst@gmail.com>
[imirkin: rebased, improved docs/commit message]
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark <robdclark@gmail.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Alyssa Rosenzweig [Thu, 7 Feb 2019 02:09:21 +0000 (02:09 +0000)]
kmsro: Silence warning if missing
Regardless of whether the build uses kmsro, kmsro is the default driver
descriptor when the static loader is used. Thus, in an edge case where
the static loader is used, no static targets are loaded, and kmsro is
not compiled, a spurious warning is printed. There's no harm in
executing the stub function in this case, but it's not "an error" to not
have kmsro in the build; the driver missing warning should not printed
kmsro.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Lionel Landwerlin [Wed, 6 Feb 2019 17:48:38 +0000 (17:48 +0000)]
radv: assert that colorAttachment is valid for CmdClearAttachment
This partially reverts a change from
b7a93cbdede05a ("radv: Handle
VK_ATTACHMENT_UNUSED in CmdClearAttachment") which fixed actual issues
but also started to accept invalid values for the colorAttachment
field.
This change asserts that the field is valid for the current pass.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
b7a93cbdede05a ("radv: Handle VK_ATTACHMENT_UNUSED in CmdClearAttachment")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Lionel Landwerlin [Wed, 6 Feb 2019 17:37:58 +0000 (17:37 +0000)]
anv: assert that color attachment are valid
This reverts commit
d76e7779884775bcebf235adb0e8367816b9b95d.
Let's make this obvious that there is an application issue if it tries
to access an attachment that doesn't exist in the current pass.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
d76e7779884775 ("anv: Handle VK_ATTACHMENT_UNUSED in colorAttachment")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Dave Airlie [Thu, 7 Feb 2019 23:06:13 +0000 (09:06 +1000)]
docs: update qbo support for virgl
Signed-off-by: Dave Airlie <airlied@redhat.com>
Eric Engestrom [Thu, 7 Feb 2019 11:36:19 +0000 (11:36 +0000)]
travis: fix osx make build
This variable was removed in commit
087af992a276e7478c9c "travis: remove
unused linux code path" because it looked like it was only used by the
Linux build. Turns out I was wrong, so let's restore it.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Jason Ekstrand [Thu, 7 Feb 2019 15:44:58 +0000 (09:44 -0600)]
README: Drop the badges from the readme
They have been added as badges directly to the GitLab project.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Tue, 22 Jan 2019 16:44:44 +0000 (16:44 +0000)]
driconf: drop unused macro
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Thu, 17 Jan 2019 18:04:42 +0000 (18:04 +0000)]
meson: add script to print the options before configuring a builddir
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Alyssa Rosenzweig [Tue, 5 Feb 2019 05:13:50 +0000 (05:13 +0000)]
panfrost: Include glue for out-of-tree legacy code
In addition to the DRM interface in active development, for legacy
kernels Panfrost has a small, optional, out-of-tree glue repository. For
various reasons, this legacy code should not be included in Mesa proper,
but this commit allows it to coexist peacefully with upstream Panfrost.
If the nondrm repo is cloned/symlinked to the directory
`src/gallium/drivers/panfrost/nondrm`, legacy functionality will be
built. Otherwise, the driver will build normally, though a runtime error
message will be printed if a legacy kernel is detected.
This workaround is icky, but it allows a nearly-upstream Panfrost to
work on real hardware, today. Ideally, this patch will be reverted when
the Panfrost kernel module is mature and we drop legacy support.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Tue, 5 Feb 2019 04:32:27 +0000 (04:32 +0000)]
panfrost: Check in sources for command stream
This patch includes the command stream portion of the driver,
complementing the earlier compiler. It provides a base for future work,
though it does not integrate with any particular winsys.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Tue, 5 Feb 2019 02:19:38 +0000 (02:19 +0000)]
panfrost: Use u_pipe_screen_get_param_defaults
Switching to the defaults function cleans up pan_screen.h markedly and
futureproofs for when new PIPE_CAPs are added.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Suggested-by: Eric Anholt <eric@anholt.net>
Alyssa Rosenzweig [Tue, 5 Feb 2019 02:25:01 +0000 (02:25 +0000)]
kmsro: Move DRM entrypoints to shared block
As kmsro allows an essentially mix-and-match hodgepodge of display
drivers and renderonly GPUs, it doesn't make sense to couple the display
driver entrypoint definition with the driver. Instead, we move *all*
kmsro entrypoints to a shared kmsro block at the end (avoiding clutter
and distraction since this list may snowball in the future).
v2: Alphabetize driver list.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Anholt <eric@anholt.net>
Rhys Perry [Tue, 26 Jun 2018 23:04:41 +0000 (00:04 +0100)]
nvc0: add compute invocation counter
The strategy is to keep a CPU-side counter of the direct invocations,
and a GPU-side counter of the indirect invocations, and then add them
together for queries.
The specific technique is a macro which multiplies a list of integers
together and accumulates the product into SCRATCH registers held inside
of the context. Another macro will read those values out and add them to
the passed-in cpu-side counter to be stored in a query buffer the same
way that all the other statistics are stored.
Original implementation by Rhys Perry, redone by Ilia Mirkin to use the
SCRATCH temporaries.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Karol Herbst [Sun, 1 Jul 2018 07:44:48 +0000 (09:44 +0200)]
gm107/ir: add fp64 rsq
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Karol Herbst [Sat, 30 Jun 2018 21:09:27 +0000 (23:09 +0200)]
gm107/ir: add fp64 rcp
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Karol Herbst [Mon, 14 Aug 2017 21:55:25 +0000 (23:55 +0200)]
gk104/ir: Use the new rcp/rsq in library
[imirkin: add a few more "long" prefixes to safen things up]
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Boyan Ding [Thu, 9 Mar 2017 05:55:19 +0000 (13:55 +0800)]
gk110/ir: Use the new rcp/rsq in library
v2: (Karol Herbst <kherbst@redhat.com>
* fix Value setup for the builtins
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
[imirkin: track the fp64 flag when switching ops to calls]
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Boyan Ding [Thu, 9 Mar 2017 05:55:18 +0000 (13:55 +0800)]
gk110/ir: Add rsq f64 implementation
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Boyan Ding [Thu, 9 Mar 2017 05:55:17 +0000 (13:55 +0800)]
gk110/ir: Add rcp f64 implementation
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Tue, 5 Feb 2019 08:05:33 +0000 (03:05 -0500)]
nvc0: stick zero values for the compute invocation counts
Not quite perfect, but at least we don't end up with random values in
the query buffer.
Fixes KHR-GL45.pipeline_statistics_query_tests_ARB.functional_default_qo_values
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Tue, 5 Feb 2019 03:57:06 +0000 (22:57 -0500)]
nv50,nvc0: use condition for occlusion queries when already complete
For the NO_WAIT variants, we would jump into the ALWAYS case for both
nested and inverted occlusion queries. However if the query had
previously completed, the application could reasonably expect that the
render condition would follow that result.
To resolve this, we remove the nesting distinction which unnecessarily
created an imbalance between the regular and inverted cases (since
there's no "zero" condition mode). We also use the proper comparison if
we know that the query has completed (which could happen as a result of
an earlier get_query_result call).
Fixes KHR-GL45.conditional_render_inverted.functional
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Mon, 4 Feb 2019 02:55:12 +0000 (21:55 -0500)]
nvc0: fix 3d images on kepler
Looks like SUBFM.3D and SUEAU are perfectly capable of dealing with 3d
tiling, they just need the correct inputs. Supply them.
We also have to deal with the case where a 2d "layer" of a 3d image is
bound. In this case, we supply the z coordinate separately to the
shader, which has to optionally treat every 2d case as if it could be a
slice of a 3d texture.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Sat, 2 Feb 2019 07:56:48 +0000 (02:56 -0500)]
nvc0/ir: fix second tex argument after levelZero optimization
We used to pre-set a bunch of extra arguments to a texture instruction
in order to force the RA to allocate a register at the boundary of 4.
However with the levelZero optimization, which removes a LOD argument
when it's uniformly equal to zero, we undid that logic by removing an
extra argument. As a result, we could end up with insufficient alignment
on the second wide texture argument.
Instead we switch to a different method of achieving the same result.
The logic runs during the constraint analysis of the RA, and adds unset
sources as necessary right before being merged into a wide argument.
Fixes MISALIGNED_REG errors in Hitman when run with bindless textures
enabled on a GK208.
Fixes:
9145873b152 ("nvc0/ir: use levelZero flag when the lod is set to 0")
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Sun, 3 Feb 2019 15:06:24 +0000 (10:06 -0500)]
nvc0/ir: always use CG mode for loads from atomic-only buffers
Atomic operations don't update the local cache, which means that we
would have to issue CCTL operations in order to get the updated values.
When we know that a buffer is primarily used for atomic operations, it's
easier to just avoid the caching at that level entirely.
The same issue persists for non-atomic buffers, which will have to be
fixed separately.
Fixes the failing dEQP-GLES31.functional.atomic_counter.* tests.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Sat, 2 Feb 2019 21:23:50 +0000 (16:23 -0500)]
nvc0: add support for handling indirect draws with attrib conversion
The hardware does not natively support FIXED and DOUBLE formats. If
those are used in an indirect draw, they have to be converted. Our
conversion tries to be clever about only converting the data that's
needed. However for indirect, that won't work.
Given that DOUBLE or FIXED are highly unlikely to ever be used with
indirect draws, read the indirect buffer on the CPU and issue draws
directly.
Fixes the failing dEQP-GLES31.functional.draw_indirect.random.* tests.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Kristian H. Kristensen [Wed, 6 Feb 2019 22:10:36 +0000 (14:10 -0800)]
freedreno/a6xx: Use tiling for all resources
We used to restrict this to just PIPE_BIND_SAMPLER_VIEW resources, but
most resources benefit from being tiled.
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Kristian H. Kristensen [Wed, 6 Feb 2019 21:47:32 +0000 (13:47 -0800)]
freedreno/a6xx: Emit blitter dst with OUT_RELOCW
We're writing to the bo and the kernel needs to know for
fd_bo_cpu_prep() to work.
Fixes:
f93e43127252679b ("freedreno/a6xx: Enable blitter")
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Bas Nieuwenhuizen [Thu, 24 Jan 2019 01:06:27 +0000 (02:06 +0100)]
radv: Implement VK_EXT_buffer_device_address.
v2: Also update the release notes.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Fri, 25 Jan 2019 00:56:45 +0000 (01:56 +0100)]
radv: Do not use the bo list for local buffers.
The kernel already does it for us.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Thu, 24 Jan 2019 01:04:10 +0000 (02:04 +0100)]
amd/common: Implement global memory accesses.
Needed for VK_EXT_buffer_device_address.
The pointers are implmemented as i8*, since I could not figure
out how to emulate setting struct offsets in LLVM based on the
SPIR-V offsets (and more weird stuff like row major matrices).
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Thu, 24 Jan 2019 00:28:16 +0000 (01:28 +0100)]
amd/common: Do not use 32-bit loads for shared memory.
We use a straight glsl->llvm type conversion so types should already be right.
Also even though the writemasks were changed we we not actually doing 32-bit
things, so this fails miserably.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Thu, 24 Jan 2019 00:25:50 +0000 (01:25 +0100)]
amd/common: handle nir_deref_cast for shared memory from integers.
Can happen e.g. after a phi.
Fixes:
a2b5cc3c399 "radv: enable variable pointers"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Thu, 24 Jan 2019 00:21:28 +0000 (01:21 +0100)]
amd/common: Handle nir_deref_type_ptr_as_array for shared memory.
Fixes:
a2b5cc3c399 "radv: enable variable pointers"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Wed, 23 Jan 2019 21:50:33 +0000 (22:50 +0100)]
amd/common: Fix stores to derefs with unknown variable.
Fixes:
a2b5cc3c399 "radv: enable variable pointers"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Wed, 23 Jan 2019 21:44:05 +0000 (22:44 +0100)]
amd/common: Use correct writemask for shared memory stores.
The check was for 1 bit being set, which is clearly not what we want.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Wed, 23 Jan 2019 21:41:46 +0000 (22:41 +0100)]
radv: Fix the shader info pass for not having the variable.
For example with VK_EXT_buffer_device_address or
VK_KHR_variable_pointers.
Fixes:
a2b5cc3c399 "radv: enable variable pointers"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Wed, 23 Jan 2019 00:54:39 +0000 (01:54 +0100)]
amd/common: Implement ptr->int casts in ac_to_integer.
For the implicit casts inherent in nir.
This should probably have been done for shared memory for
VK_KHR_variable_pointers.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Wed, 23 Jan 2019 00:53:59 +0000 (01:53 +0100)]
amd/common: Add gep helper for pointer increment.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Tue, 22 Jan 2019 21:29:26 +0000 (22:29 +0100)]
radv: Only look at pImmutableSamples if the descriptor has a sampler.
Equivalent of ANV patch
c7f4a2867ce492d78c1f8e2870c0a593d280572d
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Eric Engestrom [Wed, 6 Feb 2019 16:28:12 +0000 (16:28 +0000)]
xvmc: fix string comparison
Fixes:
6fca18696d0e6a243f6f "g3dvl: Update XvMC unit tests."
Cc: Younes Manton <younes.m@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Wed, 6 Feb 2019 16:21:08 +0000 (16:21 +0000)]
xvmc: fix string comparison
Fixes:
c7b65dcaffeb9d0760c8 "xvmc: Define some Xv attribs to allow users
to specify color standard and procamp"
Cc: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Tue, 29 Jan 2019 08:57:17 +0000 (08:57 +0000)]
gitlab-ci: add meson glvnd build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 21:36:19 +0000 (21:36 +0000)]
travis: remove unused scons code path
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 21:36:08 +0000 (21:36 +0000)]
travis: remove unused linux code path
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 20:48:37 +0000 (20:48 +0000)]
gitlab-ci: add make Gallium ST Other build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 20:40:25 +0000 (20:40 +0000)]
gitlab-ci: add make Gallium ST Clover LLVM-7 build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 20:39:22 +0000 (20:39 +0000)]
gitlab-ci: add make Gallium ST Clover LLVM-6.0 build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 20:37:03 +0000 (20:37 +0000)]
gitlab-ci: add make Gallium ST Clover LLVM-5.0 build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 20:36:25 +0000 (20:36 +0000)]
gitlab-ci: add make Gallium ST Clover LLVM-4.0 build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 20:29:59 +0000 (20:29 +0000)]
gitlab-ci: add make Gallium ST Clover LLVM-3.9 build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 20:24:04 +0000 (20:24 +0000)]
gitlab-ci: add make Gallium Drivers "Other" build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 20:21:44 +0000 (20:21 +0000)]
gitlab-ci: add make Gallium Drivers RadeonSI build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 20:17:12 +0000 (20:17 +0000)]
gitlab-ci: add make Gallium Drivers SWR build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 20:13:33 +0000 (20:13 +0000)]
gitlab-ci: add make loaders/classic DRI build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 18:13:55 +0000 (18:13 +0000)]
gitlab-ci: add meson gallium ST "Other" build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 18:09:24 +0000 (18:09 +0000)]
gitlab-ci: add meson gallium ST Clover (LLVM 7.0) build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 18:07:31 +0000 (18:07 +0000)]
gitlab-ci: add meson gallium ST Clover (LLVM 6.0) build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 18:05:22 +0000 (18:05 +0000)]
gitlab-ci: add meson gallium ST Clover (LLVM 5.0) build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 17:47:09 +0000 (17:47 +0000)]
gitlab-ci: add meson gallium "other drivers" build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 17:45:26 +0000 (17:45 +0000)]
gitlab-ci: add meson gallium RadeonSI build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 17:42:59 +0000 (17:42 +0000)]
gitlab-ci: add meson gallium SWR build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 17:38:17 +0000 (17:38 +0000)]
gitlab-ci: add meson loader/classic DRI build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 16:33:22 +0000 (16:33 +0000)]
gitlab-ci: add scons SWR build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 16:30:36 +0000 (16:30 +0000)]
gitlab-ci: add scons llvm 3.5 build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Wed, 23 Jan 2019 15:46:10 +0000 (15:46 +0000)]
gitlab-ci: add a scons no-llvm build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 21 Jan 2019 09:42:37 +0000 (09:42 +0000)]
gitlab-ci: add a make vulkan build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Sun, 20 Jan 2019 11:26:53 +0000 (11:26 +0000)]
gitlab-ci: add a meson vulkan build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>