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Jack Xiao [Thu, 17 Jan 2019 07:47:36 +0000 (15:47 +0800)]
drm/amdgpu: add ib preemption status in amdgpu_job (v2)
Add ib preemption status in amdgpu_job, so that ring level function
can detect preemption and program for resuming it.
v2: squash in fix to restore job->preamble_status back to status value (Jack)
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 10 Jan 2019 07:50:10 +0000 (15:50 +0800)]
drm/amdgpu: enable the static csa when mcbp enabled
CSA is the Context Save Area for preemption.
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 10 Jan 2019 07:43:33 +0000 (15:43 +0800)]
drm/amdgpu: add mcbp driver parameter
Add mcbp driver parameter, so that mcbp feature can be
enabled/disabled by driver parameter.
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Wed, 31 Oct 2018 12:21:55 +0000 (20:21 +0800)]
drm/amdgpu: Add new ring interface preempt_ib
Used to trigger preemtption
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 10 Jan 2019 06:28:08 +0000 (14:28 +0800)]
drm/amdgpu: add the trailing fence per ring
The trailing fence for ring is used to track the
completion of preemption.
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Mon, 8 Oct 2018 06:55:42 +0000 (14:55 +0800)]
drm/amdgpu: Add helper function amdgpu_ring_set_preempt_cond_exec
can preempt the ring by setting cond_exec to false
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le.Ma [Fri, 5 Jan 2018 08:21:18 +0000 (16:21 +0800)]
drm/amdgpu: enable virtual display feature for navi10
Virtual display is a pure sw implementation of KMS for use
in virtualization and for bring up and emulation.
Signed-off-by: Le.Ma <Le.Ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sat, 16 Feb 2019 14:22:46 +0000 (22:22 +0800)]
drm/amdgpu/psp11: skip ta firmware for navi10
Not used on Navi10.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sat, 16 Feb 2019 14:17:35 +0000 (22:17 +0800)]
drm/amdgpu: declare navi10 asd firmware
So the dependencies are properly handled.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 14 Feb 2019 11:08:22 +0000 (19:08 +0800)]
drm/amdgpu: load smc ucode at first with psp while rlc auto load is supported
This patch loades smc ucode at first with psp while rlc auto load is supported
on navi10.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 31 Jan 2019 04:19:54 +0000 (12:19 +0800)]
drm/amdgpu: enable psp front door loading by default on navi10
Required for production hw and vddgfx.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 12 Dec 2018 17:29:53 +0000 (01:29 +0800)]
drm/amdgpu/psp: skip mec jt when autoload is enabled
When autoload is enabled, there is no need to load mec jt,
RLC will handle it automatically
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 12 Dec 2018 17:21:30 +0000 (01:21 +0800)]
drm/amd/amdgpu: add flag to mark whether autoload is supported or not
rlc autoload is supported since navi10
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 12 Dec 2018 17:23:56 +0000 (01:23 +0800)]
drm/amdgpu/psp: initialize autoload_supported flag in psp_sw_init
RLC autoload is supported since from Navi10
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 10 May 2019 15:58:44 +0000 (10:58 -0500)]
drm/amdgpu/psp: update psp gfx interface to match with psp fw (v2)
new psp gfx cmd is introuduced for rlc autoload
v2: rebase (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 12 Nov 2018 08:33:08 +0000 (16:33 +0800)]
drm/amdgpu/psp: perform tmr_init and asd_init after loading sysdrv/sos
Since from navi10, the tmr_size should be decided by psp sos according to
toc header. Driver should issue LOAD_TOC to psp sos to get the tmr_size needed.
The allocation of tmr_size then should be done only when sos/sysdrv loading
completed
Accordingly, asd_init also move to psp_hw_start after sos fw loading to make
calling sequence consistent.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 9 Nov 2018 10:09:36 +0000 (18:09 +0800)]
drm/amdgpu/psp: switch to use sos_offset_bytes member as sys_bin_size
Navi10 will have toc built-in sos binary so that using header.ucode_size_bytes
minus sos_size_bytes actually is not sys_bin_size.
Using sos_offset_bytes works for both vega20 (psp_firmware_header_v1_0) and
navi10 (psp_firmware_header_v1_1)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 24 Oct 2018 11:41:13 +0000 (19:41 +0800)]
drm/amdgpu/psp: start rlc autoload after psp recieved all gfx firmware
RLC handles firmware loading for gfx to support vddgfx feature.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 24 Oct 2018 07:25:38 +0000 (15:25 +0800)]
drm/amdgpu/psp: add support to load TOC to psp
Add support for the new load TOC command.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 10 May 2019 15:06:19 +0000 (10:06 -0500)]
drm/amdgpu/psp: add structure to support load toc in psp (v2)
Update the psp interface for the new commands.
v2: rebase (Alex)
FIXME:
GFX_CMD_ID_PROG_REG = 0x0000000B, /* program regs */
GFX_CMD_ID_LOAD_TOC = 0x0000000B, /* Load TOC and obtain TMR size */
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 23 Oct 2018 09:55:38 +0000 (17:55 +0800)]
drm/amdgpu/psp: support print out psp firmware header v1_1 info
Support version 1.1.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 23 Oct 2018 09:49:17 +0000 (17:49 +0800)]
drm/amdgpu/psp: print out psp v11 ucode hdr in drm debug mode
Print the psp header data if requested.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 23 Oct 2018 09:46:17 +0000 (17:46 +0800)]
drm/amdgpu: add helper function to print psp hdr
print the psp header data like we do for other firmwares.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 23 Oct 2018 08:49:11 +0000 (16:49 +0800)]
drm/amdgpu: rename rlc autoload to backdoor autoload
This is to differentiate rlc backdoor autoload from rlc
frontdoor autoload
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 23 Oct 2018 08:27:48 +0000 (16:27 +0800)]
drm/amdgpu: use rlc toc from psp sos binary
Instead of putting toc into driver source code, the toc will
be part of psp_sos fw. Driver need to get and parse it from
psp fw
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 22 Oct 2018 12:34:17 +0000 (20:34 +0800)]
drm/amdgpu/psp: support init psp sos microcode with build-in toc
psp_firmware_header_v1_1 is used for psp sos with build-in toc
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 19 Oct 2018 13:46:05 +0000 (21:46 +0800)]
drm/amdgpu: add structure to support build-in toc to psp sos
Table Of Content (TOC) is used by RLC to auto load gc firmwares.
PSP need to parse the toc to calculate the tmr size needed and
load gc firmwares to tmr for RLC to auto load them finally
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Mon, 21 May 2018 08:32:05 +0000 (16:32 +0800)]
drm/amdgpu: Add psp 11.0 support for navi10.
Add psp 11.0 code for navi10. psp 11.0 is not enabled for now.
Will enable it when psp 11.0 firmware is available.
Signed-off-by: Tao Zhou <Tao.Zhou1@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Tue, 18 Jul 2017 11:29:37 +0000 (19:29 +0800)]
drm/amdgpu: set navi10's fw loading type as direct
For bring up.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le.Ma [Thu, 26 Apr 2018 08:15:39 +0000 (16:15 +0800)]
drm/amdgpu: add fw load type flag for rlc autoload
Add another firmware load type AMDGPU_FW_LOAD_RLC_AUTO to support firmware
autoloading new feature in gfx10.
This flag can be leveraged for future engines that need autoload fw.
Signed-off-by: Le.Ma <Le.Ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le.Ma [Thu, 26 Apr 2018 08:13:14 +0000 (16:13 +0800)]
drm/amdgpu: add structures for buffer allocate/release for rlc autoload
Allocate a visible framebuffer to store all gfxip ucodes as the format of TOC.
Signed-off-by: Le.Ma <Le.Ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sun, 3 Mar 2019 05:02:40 +0000 (13:02 +0800)]
drm/amdgpu: add navi10 ih ip block (v3)
IH is the interrupt handler block.
v1: add initial ih support (Ray)
v2: add dummy prescreen iv function for navi10 (Hawking)
v3: squash in additional updates (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 5 Mar 2019 11:52:22 +0000 (19:52 +0800)]
drm/amd/display: move dcn v1_0 irq source header to ivsrcid/dcn/
interrupt source packet definitions for the display block (DCN).
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 5 Dec 2018 21:25:51 +0000 (05:25 +0800)]
drm/amdgpu: add irq sources for vcn v2_0 (v2)
Add the interrupt source packet definitions.
v2: update (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sat, 8 Dec 2018 15:06:41 +0000 (23:06 +0800)]
drm/amdgpu: add irq sources for sdma v5_0
Add the interrupt source packet definitions.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 5 Dec 2018 21:23:34 +0000 (05:23 +0800)]
drm/amdgpu: add irq sources for gfx v10_1
Add the interrupt source packet definitions.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 4 Mar 2019 08:27:14 +0000 (16:27 +0800)]
drm/amdgpu: add gmc v10 ip block for navi10 (v6)
GMC in the GPU memory controller.
v1: add place holder and initial basic implementation (Ray)
v2: retire unused amdgpu_gart_set_defaults (Hawking)
v3: re-work get_vm_pde function (Hawking)
v4: replace legacy amdgpu_vram/gtt_location with
amdgpu_gmc_vram/gtt_location (Hawking)
v5: squash in updates (Alex)
v6: use get_vbios_fb_size (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 4 Mar 2019 05:49:28 +0000 (13:49 +0800)]
drm/amdgpu: add mmhub v2 block for navi10 (v4)
mmhub is the memory controller hub for multi-media (VCN).
v1: add place holder and initial functions (Ray)
v2: replace legacy amdgpu_mc structure with amdgpu_gmc (Hawking)
v3: switch to use amdgpu_gmc_pd_addr (Hawking)
v4: squash in updates (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 4 Mar 2019 08:18:27 +0000 (16:18 +0800)]
drm/amdgpu: add gfxhub v2.0 block for navi10 (v4)
gfxhub is the memory controller hub for gfx and sdma.
v1: add place holder and initial basic functions (Ray)
v2: replace the refernce to legacy mc structure with gmc structure
remove the direct use of gart.table_addr (Hawking)
v3: switch to use amdgpu_gmc_pd_addr (Hawking)
v4: squash in updates (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 22 Feb 2019 07:34:00 +0000 (15:34 +0800)]
drm/amdgpu: refine the PTE encoding of PRT for navi10
Due to GCR change from navi10, the PTE encoding of PRT
needs change VSCTL = 01111 (was 0XX1X).
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 25 Jun 2018 13:03:40 +0000 (21:03 +0800)]
drm/amd/gmc9: rename AMDGPU_PTE_MTYPE to AMDGPU_PTE_MTYPE_VG10
To differentiate the mtypes across asics.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 12 Apr 2019 23:17:24 +0000 (18:17 -0500)]
drm/amdgpu: correct pte mtype field for navi
The MTYPE filed moves from bits 58:57 to 50:48 for NV10
And the size of MTYPE field is now 3bits
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Wed, 13 Feb 2019 10:43:03 +0000 (18:43 +0800)]
drm/amdgpu/athub2: enable athub2 clock gating
Enable athub2 clock gating and light sleep
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sat, 2 Feb 2019 07:03:11 +0000 (15:03 +0800)]
drm/amdgpu: add flag to support IH clock gating
Add new flag for IH (interrupt handler) clockgating.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 29 Aug 2018 13:18:19 +0000 (21:18 +0800)]
drm/amdgpu: add new HDP CG flags
HDP 5.0 supports SRAM power gating. all the LS (Light Sleep)/
DS (Deep Sleep)/SD (Shut Down) modes are supported. However,
only one of these modes can be enabled at one time.
There is no dynamic power mode switch support. clock/power gating
has to be disabled before making any power mode change.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 14 Aug 2018 12:54:35 +0000 (20:54 +0800)]
drm/amdgpu: create mqd for gfx queues on navi10
mqd is the memory queue descriptor for gfx and compute.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 21 Mar 2019 10:20:23 +0000 (18:20 +0800)]
drm/amdgpu: enable async gfx ring by default
VDDGFX requires gfx queue to be installed via MAP_QUEUES packet.
Hence, enable async gfx ring by default.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 31 Jul 2018 07:00:40 +0000 (15:00 +0800)]
drm/amdgpu: add module parameter for async_gfx_ring enablement
0 means disable async_gfx_ring and is the default setting
1 means enable async_gfx_ring
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 11 Mar 2019 14:04:44 +0000 (22:04 +0800)]
drm/amdgpu: enable gfx eop interrupt per gfx pipe
Navi10 has 2 gfx pipe and need to enable gfx eop interrupt
per pipe, instead of enable eop int for all gfx pipes at one
time.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 8 Jan 2019 05:33:46 +0000 (13:33 +0800)]
drm/amdgpu/gfx10: add special unmap_queues packet for preemption
CP introduced a special unmap_queues packet for gfx preemtion.
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 5 Mar 2019 14:05:02 +0000 (22:05 +0800)]
drm/amdgpu: Move common code to amdgpu_gfx.c
move common code to amdgpu_gfx_enable_kcq,so
this function can be shared with gfx8 and gfx9
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Wed, 22 Aug 2018 05:45:25 +0000 (13:45 +0800)]
drm/amdgpu: Add common gfx func Disable kcq via kiq
so can be shared with gfx8 and gfx9
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Wed, 22 Aug 2018 03:44:20 +0000 (11:44 +0800)]
drm/amdgpu: Add struct kiq_pm4_funcs into kiq struct
kiq can support 4 pm4 scheduler packets
set_resource, map_queues, unmap_queues, query_status.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 1 Aug 2018 04:03:20 +0000 (12:03 +0800)]
drm/amdgpu: rename amdgpu_gfx_compute_mqd_sw_init
The function now will create mqd bos for both gfx queue and compute queue
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 31 Jul 2018 07:43:10 +0000 (15:43 +0800)]
drm/amdgpu: add helper function for gfx queue/bitmap transition
Similar to what we do for compute already.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 8 Aug 2018 07:16:43 +0000 (15:16 +0800)]
drm/amdgpu: acquire available gfx queues
currently, amdgpu will owns the first gfx queue of each pipe
they are:
me:0 pipe:0 queue:0
me:0 pipe:1 queue:0
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 3 Aug 2018 09:26:33 +0000 (17:26 +0800)]
drm/amdgpu: add members in amdgpu_me for gfx queue
Update the structure for gfx10.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 4 Sep 2017 09:17:39 +0000 (17:17 +0800)]
drm/amdgpu/gfx10: new approach to load gfx10 me fw (v4)
gfx10 allows to only upload me jumptable while save the whole
me image at gtt memory.
v2: program CP_ME_IC_BASE_CNTL to default value
v3: switch to use amdgpu_bo_create_reserved to create me fw bo
v4: split common code from gfx10 code
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 4 Sep 2017 09:14:47 +0000 (17:14 +0800)]
drm/amdgpu/gfx10: new approach to load ce fw (v4)
gfx10 allows to only upload ce jumptable while save the whole
ce image at gtt memory.
v2: program CP_CE_IC_BASE_CNTL to default value
v3: switch to use amdgpu_bo_create_reserved to create ce fw bo
v4: split common code from gfx10 code
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 10 Jan 2018 10:12:44 +0000 (18:12 +0800)]
drm/amdgpu/gfx10: new approach to load pfp fw (v4)
gfx10 allows to only upload pfp jumptable while save the whole
pfp image at gtt memory.
v2: program CP_PFP_IC_BASE_CNTL to default value
v3: switch to use amdgpu_bo_create_reserved to create pfp fw bo
v4: split common code from gfx10 code
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 12 Apr 2019 21:51:19 +0000 (16:51 -0500)]
drm/amdgpu: add nbio v2.3 for navi10 (v4)
nbio handles bus io functionality.
v1: add place holder and initial basic nbio v2.3 functions (Ray)
v2: implements and expose all functions in format of nbio_v2_3_funcs (Hawking)
v3: squash in updates (Alex)
v4: whitespace fix (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Tue, 16 Oct 2018 13:54:20 +0000 (09:54 -0400)]
drm/amdgpu: add nbio callbacks for vcn doorbell support
For Navi10 VCN2.0, the engine supports Doorbell
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 10 Dec 2018 23:12:16 +0000 (07:12 +0800)]
drm/amdgpu: query vram_width from vram_info table
Driver will get channel_number and channel_width from
vram_info table, then calculate vram_width by multiply
channel_number by channel_width
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 10 Dec 2018 21:20:12 +0000 (05:20 +0800)]
drm/amdgpu: query vram type from atomfirmware vram_info
vram_type is saved in member vram_module[0].memory_type
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 4 Mar 2019 06:29:55 +0000 (14:29 +0800)]
drm/amdgpu: add navi pm4 header
A pm4 header for Navi. PM4 is the packet format used
by the compute and gfx engines.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sun, 3 Mar 2019 05:13:05 +0000 (13:13 +0800)]
drm/amdgpu: add sdma v5 packet header file
Defines the SDMA packet formats.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 9 Aug 2017 12:48:04 +0000 (20:48 +0800)]
drm/amdgpu: add gfx v10 clear state header v2
Clear state for gfx pipe.
v2: squash in updates
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 14 Sep 2017 12:34:37 +0000 (20:34 +0800)]
drm/amdgpu: add v10 structs header (v2)
Header for CP structures (MQD, etc.)
V2: squash in updates
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 13 Jun 2018 04:19:43 +0000 (12:19 +0800)]
drm/amdgpu: parse the new members added by gpu_info ucode v1_1
Parse the new parameters for gfx10.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 13 Jun 2018 03:18:42 +0000 (11:18 +0800)]
drm/amdgpu: add gpu_info_firmware v1_1 structure for navi10
two new members that specific for navi10 are included in v2_0:
num_sc_per_sh and num_packer_per_sc
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Fri, 4 Aug 2017 03:10:15 +0000 (11:10 +0800)]
drm/amdgpu: add navi10 gpu info firmware
gpu info firmware stores configuration data for various
IP blocks.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 12 Jun 2018 09:10:19 +0000 (17:10 +0800)]
drm/amdgpu: add gfx10 specific new member pa_sc_tile_steering_override
New gfx config parameter.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 12 Jun 2018 09:05:59 +0000 (17:05 +0800)]
drm/amdgpu: add gfx10 specific config in amdgpu_gfx_config
The two members are used to cache the values from gpu_info fw accordingly
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 2 May 2018 09:52:39 +0000 (17:52 +0800)]
drm/amdgpu: Add GDDR6 in vram_name arrary
For printing vram type.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Tue, 18 Jul 2017 10:59:24 +0000 (18:59 +0800)]
drm/amdgpu: add GDDR6 vram type
New vram type.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 19 Jul 2017 01:43:26 +0000 (09:43 +0800)]
drm/amdgpu: add NV series gpu family id
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Tue, 18 Jul 2017 11:27:55 +0000 (19:27 +0800)]
drm/amdgpu: add navi10 asic type
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 4 Mar 2019 07:53:41 +0000 (15:53 +0800)]
drm/amdgpu: add navi10 ip offset header
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 12 Apr 2019 19:13:08 +0000 (14:13 -0500)]
drm/amdgpu: add doorbell assignement for navi10
Update mappings for Navi10.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 12 Apr 2019 19:08:00 +0000 (14:08 -0500)]
drm/amdgpu: atomfirmware.h updates for navi10
Updated tables for Navi10.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 4 Mar 2019 07:51:48 +0000 (15:51 +0800)]
drm/amdgpu: add navi10 enums header
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sun, 3 Mar 2019 03:32:16 +0000 (11:32 +0800)]
drm/amdgpu: add SMUIO 11.0 register headers
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sun, 3 Mar 2019 03:30:47 +0000 (11:30 +0800)]
drm/amdgpu: add OSS 5.0 register headers
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sun, 3 Mar 2019 03:29:18 +0000 (11:29 +0800)]
drm/amdgpu: add MMHUB 2.0 register headers
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sun, 3 Mar 2019 03:27:27 +0000 (11:27 +0800)]
drm/amdgpu: add GC 10.1 register headers (v4)
v2: Update regs (Alex)
v3: More updates (Alex)
v4: more updates (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sun, 3 Mar 2019 03:23:35 +0000 (11:23 +0800)]
drm/amdgpu: add VCN 2.0 register headers
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sun, 3 Mar 2019 03:17:25 +0000 (11:17 +0800)]
drm/amdgpu: add NBIO 2.3 register headers
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sun, 3 Mar 2019 03:15:26 +0000 (11:15 +0800)]
drm/amdgpu: add MP 11.0 register headers
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sun, 3 Mar 2019 03:10:29 +0000 (11:10 +0800)]
drm/amdgpu: add HDP 5.0 register headers
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sun, 3 Mar 2019 03:05:29 +0000 (11:05 +0800)]
drm/amdgpu: add DCN 2.0 register headers
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sun, 3 Mar 2019 03:02:58 +0000 (11:02 +0800)]
drm/amdgpu: add CLK 11.0 register headers
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sun, 3 Mar 2019 02:57:10 +0000 (10:57 +0800)]
drm/amdgpu: add ATHUB 2.0 register headers
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 17 Jun 2019 18:10:48 +0000 (13:10 -0500)]
Revert "drm/amd/display: Copy stream updates onto streams"
This reverts commit
6e5155ae6b66054db35d8f3c64f9863b9d0466c1.
Revert this to apply the version that includes DCN2 support.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 17 Jun 2019 18:08:58 +0000 (13:08 -0500)]
Revert "drm/amd/display: Use macro for invalid OPP ID"
This reverts commit
1760bd06c8e94e1b184139ae35201856403638cf.
Revert this to apply the version that includes DCN2 support.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 17 Jun 2019 18:08:40 +0000 (13:08 -0500)]
Revert "drm/amd/display: Rework CRTC color management"
This reverts commit
7cd4b70091a5cfa1f58d3a529535304a116acc95.
Revert this to apply the version that includes DCN2 support.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 17 Jun 2019 18:06:37 +0000 (13:06 -0500)]
Revert "drm/amd/display: move vmid determination logic out of dc"
This reverts commit
11cd74cdb98aa6f4d6f54a0082dd28e0d4743746.
Revert this to apply the version that includes DCN2 support.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 17 Jun 2019 18:06:19 +0000 (13:06 -0500)]
Revert "drm/amd/display: Add Underflow Asserts to dc"
This reverts commit
9ed43ef84d9d1e668acdf43c95510fb7b11f8d71.
Revert this to apply the version that includes DCN2 support.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 17 Jun 2019 18:04:43 +0000 (13:04 -0500)]
Revert "drm/amd/display: make clk_mgr call enable_pme_wa"
This reverts commit
a1651530a3bacf1d796fdb7bc587faef9f305d36.
Revert this to apply the version that includes DCN2 support.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Thu, 20 Jun 2019 12:30:09 +0000 (08:30 -0400)]
Revert "drm/amd/display: Enable fast plane updates when state->allow_modeset = true"
This reverts commit
ebc8c6f18322ad54275997a888ca1731d74b711f.
There are still missing corner cases with cursor interaction and these
fast plane updates on Picasso and Raven2 leading to endless PSTATE
warnings for typical desktop usage depending on the userspace.
This change should be reverted until these issues have been resolved.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110949
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: David Francis <david.francis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Zhang [Thu, 20 Jun 2019 05:44:47 +0000 (13:44 +0800)]
drm/amdgpu/sriov: fix Tonga load driver failed
Tonga sriov need to use smu to load firmware.
Remove sriov flag because the default return value is zero.
Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Reviewed-by: Trigger Huang <Trigger.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>