use LLVM's standard CMakeLists.txt layout for llvm-xray

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331455 91177308-0d34-0410-b5e6-96231b3b80d8

[CodeGen][X86][NFC] Copy two selectcc tests from AArch64.

These tests are for DAGCombiner::foldSelectCCToShiftAnd().
Right now, they were only tested for AArch64,
but given the upcoming X86 changes to the hasAndNot(),
the test coverage needs to be added.

These tests originated from D27489 / rL289738

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331454 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Split WriteVecALU/WritePHAdd into XMM and YMM/ZMM scheduler classes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331453 91177308-0d34-0410-b5e6-96231b3b80d8

ARM: don't try to over-align large vectors as arguments.

By default LLVM thinks very large vectors get aligned to their size when
passed across functions. Unfortunately no-one told the ARM backend so it
doesn't trigger stack realignment and so accesses can cause the usual
misalignment issues (e.g. a data abort).

This changes the ABI alignment to the stack alignment, which in practice
(and as a bonus) also coincides with the alignment "natural" vectors get.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331451 91177308-0d34-0410-b5e6-96231b3b80d8

perform DSE through launder.invariant.group

Summary:
Alias Analysis knows that llvm.launder.invariant.group
returns pointer that mustalias argument, but this information
wasn't used, therefor we didn't DSE through launder.invariant.group

Reviewers: chandlerc, dberlin, bogner, hfinkel, efriedma

Reviewed By: dberlin

Subscribers: amharc, llvm-commits, nlewycky, rsmith

Differential Revision: https://reviews.llvm.org/D31581

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331449 91177308-0d34-0410-b5e6-96231b3b80d8

Rename invariant.group.barrier to launder.invariant.group

Summary:
This is one of the initial commit of "RFC: Devirtualization v2" proposal:
https://docs.google.com/document/d/16GVtCpzK8sIHNc2qZz6RN8amICNBtvjWUod2SujZVEo/edit?usp=sharing

Reviewers: rsmith, amharc, kuhar, sanjoy

Subscribers: arsenm, nhaehnle, javed.absar, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D45111

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331448 91177308-0d34-0410-b5e6-96231b3b80d8

[X86][AVX512] VPAVG instructions should be tagged as SchedWriteVecALU

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331446 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Split WriteVecIMul/WriteVecPMULLD/WriteMPSAD/WritePSADBW into XMM and YMM/ZMM scheduler classes

Also retagged VDBPSADBW instructions as SchedWritePSADBW instead of SchedWriteVecIMul which matches the behaviour on SkylakeServer (the only thing that supports it...)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331445 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Update MMX instructions to be tagged with X86SchedWriteWidths types

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331443 91177308-0d34-0410-b5e6-96231b3b80d8

[WebAssembly] MC: Don't litter test directory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331442 91177308-0d34-0410-b5e6-96231b3b80d8

Revert "[SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)"

This reverts SVN r331337, see PR37321 for details on the regression
it introduced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331441 91177308-0d34-0410-b5e6-96231b3b80d8

[TableGen][NFC] Make ResourceCycles definitions more explicit.

https://reviews.llvm.org/D46356

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331439 91177308-0d34-0410-b5e6-96231b3b80d8

[LoopIdiomRecognize] When looking for 'x & (x -1)' for popcnt, make sure the left hand side of the 'and' matches the left hand side of the 'subtract'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331437 91177308-0d34-0410-b5e6-96231b3b80d8

[LoopIdiomRecognize] Add a test case showing that we transform to ctpop without fully checking the 'x & (x-1)' part.

The code fails to check that the same value is used twice. We only make sure the left hand side of the and is part of the loop recurrence. The 'x' in the subtract can be any value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331436 91177308-0d34-0410-b5e6-96231b3b80d8

[LoopIdiomRecognize] Remove unnecessary cast from BinaryOperator to Instruction. NFC

BinaryOperator is a sub class of Instruction. We don't need an explicit cast back to Instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331432 91177308-0d34-0410-b5e6-96231b3b80d8

lit: flesh out `SubsituteCaptures` further

Add overloads for `__len__` and `__getitem__` to allow use of this class
on Linux as well as Windows.  With these overloads, lit can be used on
both hosts for the swift testsuite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331431 91177308-0d34-0410-b5e6-96231b3b80d8

Re-enable "[SCEV] Make computeExitLimit more simple and more powerful"

This patch was temporarily reverted because it has exposed bug 37229 on
PowerPC platform. The bug is unrelated to the patch and was just a general
bug in the optimization done for PowerPC platform only. The bug was fixed
by the patch rL331410.

This patch returns the disabled commit since the bug was fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331427 91177308-0d34-0410-b5e6-96231b3b80d8

[Support] Support building LLVM for Fuchsia

These are necessary changes to support building LLVM for Fuchsia.
While these are not sufficient to run on Fuchsia, they are still
useful when cross-compiling LLVM libraries and runtimes for Fuchsia.

Differential Revision: https://reviews.llvm.org/D46345

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331423 91177308-0d34-0410-b5e6-96231b3b80d8

[ObjCARC] Convert an if to an early continue. NFC

This reduces nesting and makes the logic slightly easier to follow.

Differential Revision: https://reviews.llvm.org/D46371

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331422 91177308-0d34-0410-b5e6-96231b3b80d8

Commit r331416 breaks the big-endian PPC bot. On the big endian build, we
actually encounter constants wider than 64-bits. Add the guard to prevent
tripping the assert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331420 91177308-0d34-0410-b5e6-96231b3b80d8

[gcov] Switch to an explicit if clunky array to satisfy some compilers
on various build bots that are unhappy with using makeArrayRef with an
initializer list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331418 91177308-0d34-0410-b5e6-96231b3b80d8

MachineInst support mapping SDNode fast math flags for support in Back End code generation

Summary:
Machine Instruction flags for fast math support and MIR print support

Reviewers: spatel, arsenm

Reviewed By: arsenm

Subscribers: wdng

Differential Revision: https://reviews.llvm.org/D45781

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331417 91177308-0d34-0410-b5e6-96231b3b80d8

[PowerPC] Implement isMaskAndCmp0FoldingBeneficial

Sinking the and closer to a compare against zero is beneficial on PPC as it
allows us to emit record-form instructions. In the future, we may expand this
to a larger set of operations that feed compares against zero since PPC has
lots of record-form instructions.

Differential revision: https://reviews.llvm.org/D46060

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331416 91177308-0d34-0410-b5e6-96231b3b80d8

[WebAssembly] MC: Create and use first class section symbols

Differential Revision: https://reviews.llvm.org/D46335

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331413 91177308-0d34-0410-b5e6-96231b3b80d8

[MC] Factor MCObjectStreamer::addFragmentAtoms out of MachO streamer.

This code previously existed only in MCMachOStreamer but is
useful for WebAssembly too.  See: D46335

Differential Revision: https://reviews.llvm.org/D46297

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331412 91177308-0d34-0410-b5e6-96231b3b80d8

[PowerPC] No CTR loop if the candidate exiting block is in a different loop

The CTR loops pass will insert the decrementing branch instruction in an exiting
block for the loop being transformed. However if that block is part of another
loop as well (whether a nested loop or with irreducible CFG), it is not valid
to use that exiting block. In fact, if the loop hass irreducible CFG, we don't
bother analyzing it and we just bail on the transformation. In practice, this
doesn't lead to a noticeable reduction in the number of loops transformed by
this pass.

Fixes https://bugs.llvm.org/show_bug.cgi?id=37229

Differential Revision: https://reviews.llvm.org/D46162

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331410 91177308-0d34-0410-b5e6-96231b3b80d8

[GCOV] Emit the writeout function as nested loops of global data.

Summary:
Prior to this change, LLVM would in some cases emit *massive* writeout
functions with many 10s of 1000s of function calls in straight-line
code. This is a very wasteful way to represent what are fundamentally
loops and creates a number of scalability issues. Among other things,
register allocating these calls is extremely expensive. While D46127 makes this
less severe, we'll still run into scaling issues with this eventually. If not
in the compile time, just from the code size.

Now the pass builds up global data structures modeling the inputs to
these functions, and simply loops over the data structures calling the
relevant functions with those values. This ensures that the code size is
a fixed and only data size grows with larger amounts of coverage data.

A trivial change to IRBuilder is included to make it easier to build
the constants that make up the global data.

Reviewers: wmi, echristo

Subscribers: sanjoy, mcrosier, llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D46357

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331407 91177308-0d34-0410-b5e6-96231b3b80d8

[llvm-rc] Default to writing the output next to the input, if no output is specified

This matches what rc.exe does if no output is specified.

Differential Revision: https://reviews.llvm.org/D46239

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331403 91177308-0d34-0410-b5e6-96231b3b80d8

[llvm-cvtres] Allow parameters preceded by '-' in addition to '/'

The real cvtres.exe also allows parameters in either form.

Differential Revision: https://reviews.llvm.org/D46358

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331402 91177308-0d34-0410-b5e6-96231b3b80d8

[llvm-objcopy] Add --discard-all (-x) option

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331400 91177308-0d34-0410-b5e6-96231b3b80d8

[GlobalISel][InstructionSelect] Making Coverage Info generation optional on per-match table basis

to make sure that Testgen always has access to coverage info even if
the match table used by the selector itself is stripped off that
information for performance reasons.

Reviewers: dsanders, aemerson

Reviewed By: dsanders

Subscribers: rovka, kristof.beyls, llvm-commits, dsanders

Differential Revision: https://reviews.llvm.org/D46098

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331398 91177308-0d34-0410-b5e6-96231b3b80d8

[llvm-objcopy] Add --weaken option

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331397 91177308-0d34-0410-b5e6-96231b3b80d8

[GlobalISel][InstructionSelect] Refactoring buildMatchTable out, NFC

to share it between the Instruction Selector in optimized and
non-optimized modes both and the Testgen.

Reviewers: dsanders, aemerson

Reviewed By: dsanders

Subscribers: rovka, kristof.beyls, llvm-commits, dsanders

Differential Revision: https://reviews.llvm.org/D46097

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331396 91177308-0d34-0410-b5e6-96231b3b80d8

[GlobalISel][InstructionSelect] Refactoring out a getMatchTable virtual method + other small NFC's

The main goal is to share getMatchTable between the Instruction
Selector and the Testgen.

The commit also contains some NFC only loosely related to refactoring
out the getMatchTable, but strongly related to the initial Testgen
patch (see https://reviews.llvm.org/D43962)

Reviewers: dsanders, aemerson

Reviewed By: dsanders

Subscribers: rovka, kristof.beyls, llvm-commits, dsanders

Differential Revision: https://reviews.llvm.org/D46096

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331395 91177308-0d34-0410-b5e6-96231b3b80d8

[llvm-rc] Add rudimentary support for codepages

Only support UTF-8 (since LLVM contains UTF-8 parsing support
already, and the code even does that already) and Windows-1252
(where most code points has the same value in unicode). Keep the
existing default as only allowing ASCII input.

Using the option type JoinedOrSeparate, since the real rc.exe
handles options in this form, even if llvm-rc uses Separate for
other similar existing options.

Rename the struct SearchParams to WriterParams since it's now used
for more than just include paths.

Add a missing getResourceTypeName method to the BundleResource class,
to fix error printing from within STRINGTABLE resources (used in
tests).

Differential Revision: https://reviews.llvm.org/D46238

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331391 91177308-0d34-0410-b5e6-96231b3b80d8

[X86][SNB] Fix scheduling of MMX integer multiply instructions.

The entries were being bound to the wrong class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331388 91177308-0d34-0410-b5e6-96231b3b80d8

Move the TestPlugin project into the Tests folder in CMake.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331387 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Split WriteShuffle/WriteVarShuffle + WriteBlend/WriteVarBlend into XMM and YMM/ZMM scheduler classes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331386 91177308-0d34-0410-b5e6-96231b3b80d8

[COFF, ARM64] Hook up a few remaining relocations

Differential Revision: https://reviews.llvm.org/D46355

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331384 91177308-0d34-0410-b5e6-96231b3b80d8

[AMDGPU] A trivial fix for a buildbot failure caused by "commit 224a839fcbbead221f872cd32a1dd0c308d37299".

Author: FarhanaAleen

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331383 91177308-0d34-0410-b5e6-96231b3b80d8

[reassociate] Fix excessive revisits when processing long chains of reassociatable instructions.

Summary:
Some of our internal testing detected a major compile time regression which I've
tracked down to:
    r278938 - Revert "Reassociate: Reprocess RedoInsts after each inst".
It appears that processing long chains of reassociatable instructions causes
non-linear (potentially exponential) growth in the number of times an
instruction is revisited. For example, the included test revisits instructions
220 times in a 20-instruction test.

It appears that r278938 reversed the order instructions were visited and that
this is preventing scheduled revisits from being cancelled as a result of
visiting the instructions naturally during normal processing. However, simply
reversing the order also harmed the generated code. Upon closer inspection, it
was discovered that revisits occurred in the opposite order to the first pass
(Thanks to escha for spotting that).

This patch makes the revisit order consistent with the first pass which allows
more revisits to be cancelled. This does appear to have a small impact on the
generated code in few cases but it significantly reduces compile-time.

After this patch, our internal test that was most affected by the regression
dropped from ~2 million revisits to ~4k resulting in Reassociate having 0.46%
of the runtime it had before (99.54% improvement).

Here's the summaries reported by lnt for the LLVM test-suite with --benchmarking-only:
| metric         | geomean before patch | geomean after patch | delta   |
| -----          | -----                | -----               | -----   |
| compile time   | 0.1956               | 0.1261              | -35.54% |
| execution time | 0.3240               | 0.3237              | -       |
| code size      | 7365.4459            | 7365.6079           | -       |

The results have a few wins and losses on compile-time, mostly in the +/- 2.5% range. There was one outlier though:
| Performance Regressions - compile_time | Δ | Previous | Current |
| MultiSource/Benchmarks/ASC_Sequoia/CrystalMk/CrystalMk | 9.82% | 2.0473 | 2.2483 |

Reviewers: javed.absar, dberlin

Reviewed By: dberlin

Subscribers: kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45734

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331381 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Cleanup WriteFShuffle/WriteFVarShuffle (+256 variants) scheduler classes with more common default values

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331380 91177308-0d34-0410-b5e6-96231b3b80d8

Add assertion to padding size calculation, NFC

The size of an object cannot be less than the emitted size of all the
contained elements. This would cause an overflow in padding size
calculation. Add an assert to catch this.

Patch by Suyog Sarda.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331376 91177308-0d34-0410-b5e6-96231b3b80d8

Revert "[AMDGPU] performAddCombine should run after DAG is legalized."

This reverts commit 6b97d2995566b4dddd6bf0d75579ff44501d4494.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331371 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Convert most remaining XOP uses of X86SchedWritePair scheduler classes to X86SchedWriteWidths.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331369 91177308-0d34-0410-b5e6-96231b3b80d8

[AMDGPU] performAddCombine should run after DAG is legalized.

Summary: performAddCombine should run after DAG is legalized; Otherwise generic optimization
         in the DAGCombiner can optimize an addcarry+trunc into an addcarry instruction with
         illegal types.

Author: FarhanaAleen

Reviewed By: rampitec

Subscribers: llvm-commits, AMDGPU

Differential Revision: https://reviews.llvm.org/D46337

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331368 91177308-0d34-0410-b5e6-96231b3b80d8

Fix line-endings. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331367 91177308-0d34-0410-b5e6-96231b3b80d8

Re-land rL331357 "[X86] Fix scheduling info for VMPSADBWYrmi."

Without the rebase mess.

https://reviews.llvm.org/D46356

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331362 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Cleanup WriteFMul scheduler classes with more common default values

Intel models were targeting x87 instead of packed sse.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331360 91177308-0d34-0410-b5e6-96231b3b80d8

Fix '32-bit shift implicitly converted to 64 bits' warning by using APInt::setBit instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331359 91177308-0d34-0410-b5e6-96231b3b80d8

Revert rL331355 "[X86] Fix scheduling info for VMPSADBWYrmi."

It contains unrelated changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331357 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Fix scheduling info for (V?)SQRTPDm on silvermont.

https://reviews.llvm.org/D46356

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331356 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Fix scheduling info for VMPSADBWYrmi.

https://reviews.llvm.org/D46356

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331355 91177308-0d34-0410-b5e6-96231b3b80d8

[MIPS] Fix DIV/DIVU scheduling classes.

https://reviews.llvm.org/D46356.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331354 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Convert most remaining AVX512 uses of X86SchedWritePair scheduler classes to X86SchedWriteWidths.

We've dealt with the majority already.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331353 91177308-0d34-0410-b5e6-96231b3b80d8

[AArch64][SVE] Asm: Support for LDR/STR fill and spill instructions.

Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar

Reviewed By: samparker

Differential Revision: https://reviews.llvm.org/D46270

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331352 91177308-0d34-0410-b5e6-96231b3b80d8

[TableGen] Don't quote variable name when printing !foreach.

An input !foreach expression such as !foreach(a, lst, !add(a, 1))
would be re-emitted by llvm-tblgen -print-records with the first
argument in quotes, giving !foreach("a", lst, !add(a, 1)), which isn't
valid TableGen input syntax.

Reviewers: nhaehnle

Reviewed By: nhaehnle

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46352

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331351 91177308-0d34-0410-b5e6-96231b3b80d8

[AArch64][SVE] Asm: Support for scatter ST1 store instructions.

Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D46248

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331349 91177308-0d34-0410-b5e6-96231b3b80d8

Revert "[mips] Correct the predicates of sign extension instructions"

I accidently committed this patch after asking for a review, but it has not
been reviewed yet.

This reverts r331346.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331348 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Convert most remaining uses of X86SchedWritePair scheduler classes to X86SchedWriteWidths.

We've dealt with the majority already.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331347 91177308-0d34-0410-b5e6-96231b3b80d8

[mips] Correct the predicates of sign extension instructions

And eliminate the duplication of those instructions for microMIPS32r6.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331346 91177308-0d34-0410-b5e6-96231b3b80d8

[AArch64][SVE] Asm: Support for non-temporal, contiguous LDNT1/STNT1 load/store instructions.

Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar

Reviewed By: samparker

Differential Revision: https://reviews.llvm.org/D46269

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331343 91177308-0d34-0410-b5e6-96231b3b80d8

[LoopInterchange] Update some loops to use range base for loops (NFC).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331342 91177308-0d34-0410-b5e6-96231b3b80d8

[mips] Correct the predicates for shifts.

Reviewers: smaksimovic, abeserminji, atanasyan

Differential Revision: https://reviews.llvm.org/D46123

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331341 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Cleanup WriteFAdd/WriteFCmp scheduler classes with more common default values

Intel models were targeting x87 instead of packed sse.

Also fixes XOP's VFRCZ to use WriteFAdd/WriteFAddY.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331340 91177308-0d34-0410-b5e6-96231b3b80d8

[AArch64][SVE] Asm: Support for LD1RQ load-and-replicate quad-word vector instructions.

Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D46250

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331339 91177308-0d34-0410-b5e6-96231b3b80d8

Mark invariant.group.barrier as inaccessiblememonly

It turned out that readonly argmemonly is not enough.

  store 42, %p
  %b = barrier(%p)
  store 43, %b
the first store is dead, but because barrier was marked as
reading argument memory, it was considered alive. With
inaccessiblememonly it doesn't read the argument, but
it also can't be CSEd.

based on: https://reviews.llvm.org/D32006

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331338 91177308-0d34-0410-b5e6-96231b3b80d8

[SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)

Summary:
This is a follow up to rL331182. A PHI node can be split up into
several MIR PHI nodes when being selected. When there is a
dbg.value intrinsic that uses the result of such a PHI node we
need to select several DBG_VALUE instructions, with fragment
expressions, in order to do a correct selection.

Reviewers: rnk, aprantl, vsk

Reviewed By: vsk

Subscribers: mattd, llvm-commits, JDevlieghere, aprantl, gbedwell, rnk

Tags: #debug-info

Differential Revision: https://reviews.llvm.org/D46329

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331337 91177308-0d34-0410-b5e6-96231b3b80d8

[XRay][tools] Rename llvm-xray filenames from .cc -> .cpp (NFC)

Summary:
This brings the filenames in accordance to the style guide and LLVM
conventions for C++ filenames.

As suggested by rnk@ in D46068.

Reviewers: rnk

Subscribers: mgorny, mgrang, llvm-commits

Differential Revision: https://reviews.llvm.org/D46301

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331321 91177308-0d34-0410-b5e6-96231b3b80d8

Fix release build breakage

This function was added in rL331220 but wasn't
testing in release configurations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331320 91177308-0d34-0410-b5e6-96231b3b80d8

[WebAssembly] Fix debug printing of symbol types

The Info.Kind field is a uint8_t which the OS was
trying to print as an ascii char.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331317 91177308-0d34-0410-b5e6-96231b3b80d8

[llvm-mca] Lift the logic of the RetireControlUnit from the Dispatch translation unit into its own translation unit. NFC

The logic remains the same.  Eventually, I see the RCU acting as its own separate stage in the instruction pipeline.

Differential Revision: https://reviews.llvm.org/D46331

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331316 91177308-0d34-0410-b5e6-96231b3b80d8

[AMDGPU] Support horizontal vectorization.

Author: FarhanaAleen

Reviewed By: rampitec, arsenm

Subscribers: llvm-commits, AMDGPU

Differential Revision: https://reviews.llvm.org/D46213

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331313 91177308-0d34-0410-b5e6-96231b3b80d8

[CFLGraph][NFC] Simplify/reorder switch in visitConstantExpr

Reviewers: hfinkel, efriedma, spatel, dsanders, Danil, rjmccall

Reviewed By: rjmccall

Subscribers: dberlin, llvm-commits

Differential Revision: https://reviews.llvm.org/D46259

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331312 91177308-0d34-0410-b5e6-96231b3b80d8

[AggressiveInstCombine] convert a chain of 'or-shift' bits into masked compare

and (or (lshr X, C), ...), 1 --> (X & C') != 0

I initially thought about implementing the minimal pattern in instcombine as mentioned here:
https://bugs.llvm.org/show_bug.cgi?id=37098#c6

...but we need to do better to catch the more general sequence from the motivating test
(more than 2 bits in the compare). And a test-suite run with statistics showed that this
pattern only happened 2 times currently. It would potentially happen more often if
reassociation worked better (D45842), but it's probably still not too frequent?

This is small enough that I didn't see a need to create a whole new class/file within
AggressiveInstCombine. There are likely other relatively small matchers like what was
discussed in D44266 that would slide under foldUnusualPatterns() (name suggestions welcome).
We could potentially also consolidate matchers for ctpop, bswap, etc under here.

Differential Revision: https://reviews.llvm.org/D45986

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331311 91177308-0d34-0410-b5e6-96231b3b80d8

[AggressiveInstCombine] add more bitfield test patterns; NFC

Add another baseline for D45986 and a pattern that won't be
matched with that patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331309 91177308-0d34-0410-b5e6-96231b3b80d8

[PhaseOrdering] add tests for bittest patterns from bitfields; NFC

As mentioned in D45986, there's a potential ordering dependency
between instcombine and aggressive-instcombine for detecting these,
so I'm adding a few tests to confirm that the expected folds occur
using -O3 (because aggressive-instcombine only runs at -O3 currently).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331308 91177308-0d34-0410-b5e6-96231b3b80d8

Create a MachineBasicBlock for created IR-level BasicBlock

While running the lit tests for the most recent version of D45916
(https://reviews.llvm.org/D45916), I found that a couple tests for this pass
suddenly started segfaulting. Since the outliner wasn't actually doing anything
to the code in either of these tests I got curious.

I found that the pass doesn’t completely create the machine-level constructs
necessary to actually add a MachineFunction and MachineBasicBlock to the
module. This patch adds in those missing bits. After this, adding the
outliner before this pass won’t cause it to segfault.

You can recreate this behaviour by adding the MachineOutliner directly before
the pass and having it return false immediately.

https://reviews.llvm.org/D46330

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331307 91177308-0d34-0410-b5e6-96231b3b80d8

[AArch64] Add more tests for 64-bit immediate lowering.

This adds a some more tests, and adds some notes to tests which are using
a suboptimal lowering.

The constants with suboptimal lowerings seem to be relatively rare in
practice, but it might be a fun project to work on improvements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331304 91177308-0d34-0410-b5e6-96231b3b80d8

[DAGCombiner] Fix SDLoc in a (zext (zextload x)) combine (4/N)

The logic for this combine is almost identical to the logic for a
(sext (sextload x)) combine.

This commit factors out the logic so it can be shared by both combines,
and corrects the SDLoc assigned in the zext version of the combine.

Prior to this patch, for the given test case, we would apply the
location associated with the udiv instruction to instructions which
perform the load.

Part of: llvm.org/PR37262

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331303 91177308-0d34-0410-b5e6-96231b3b80d8

[DAGCombiner] Fix SDLoc in a (sext (sextload x)) combine (3/N)

Prior to this patch, for the given test case, we would apply the
location associated with the sdiv instruction to instructions which
perform the load.

Part of: llvm.org/PR37262.

Differential Revision: https://reviews.llvm.org/D46222

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331302 91177308-0d34-0410-b5e6-96231b3b80d8

[DAGCombiner] Change the SDLoc on split extloads (2/N)

In DAGCombiner, we try to simplify this pattern:

  ([s|z]ext (load ...))

Conceptually, a new extload which is created while splitting the load
should have the same debug location as the load.

Making this change affects the IROrder of the new load, causing some
test case churn.

In practice, the new location is never different from the location of
the [s|z]ext, at least not during check-llvm or a stage2 build.

Part of: llvm.org/PR37262

Differential Revision: https://reviews.llvm.org/D46156

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331301 91177308-0d34-0410-b5e6-96231b3b80d8

[DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N)

Setting the right SDLoc on a newly-created zextload fixes a line table
bug which resulted in non-linear stepping behavior.

Several backend tests contained CHECK lines which relied on the IROrder
inherited from the wrong SDLoc. This patch breaks that dependence where
feasbile and regenerates test cases where not.

In some cases, changing a node's IROrder may alter register allocation
and spill behavior. This can affect performance. I have chosen not to
prevent this by applying a "known good" IROrder to SDLocs, as this may
hide a more general bug in the scheduler, or cause regressions on other
test inputs.

rdar://33755881, Part of: llvm.org/PR37262

Differential Revision: https://reviews.llvm.org/D45995

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331300 91177308-0d34-0410-b5e6-96231b3b80d8

AMDGPU: Remove remnants of gfx901 (it was deprecated some time ago)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331298 91177308-0d34-0410-b5e6-96231b3b80d8

[X86][AMD][Bulldozer] Fix Bulldozer Model 2 detection.

Summary:
I have discovered an issue by accident.
```
$ lscpu
Architecture:        x86_64
CPU op-mode(s):      32-bit, 64-bit
Byte Order:          Little Endian
CPU(s):              8
On-line CPU(s) list: 0-7
Thread(s) per core:  2
Core(s) per socket:  4
Socket(s):           1
NUMA node(s):        1
Vendor ID:           AuthenticAMD
CPU family:          21
Model:               2
Model name:          AMD FX(tm)-8350 Eight-Core Processor
Stepping:            0
CPU MHz:             3584.018
CPU max MHz:         4000.0000
CPU min MHz:         1400.0000
BogoMIPS:            8027.22
Virtualization:      AMD-V
L1d cache:           16K
L1i cache:           64K
L2 cache:            2048K
L3 cache:            8192K
NUMA node0 CPU(s):   0-7
Flags:               fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 popcnt aes xsave avx f16c lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs xop skinit wdt lwp fma4 tce nodeid_msr tbm topoext perfctr_core perfctr_nb cpb hw_pstate vmmcall bmi1 arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold
```
So this is model-2 bulldozer AMD CPU.

GCC agrees:
```
$ echo | gcc -E - -march=native -###
<...>
 /usr/lib/gcc/x86_64-linux-gnu/7/cc1 -E -quiet -imultiarch x86_64-linux-gnu - "-march=bdver2" -mmmx -mno-3dnow -msse -msse2 -msse3 -mssse3 -msse4a -mcx16 -msahf -mno-movbe -maes -mno-sha -mpclmul -mpopcnt -mabm -mlwp -mfma -mfma4 -mxop -mbmi -mno-sgx -mno-bmi2 -mtbm -mavx -mno-avx2 -msse4.2 -msse4.1 -mlzcnt -mno-rtm -mno-hle -mno-rdrnd -mf16c -mno-fsgsbase -mno-rdseed -mprfchw -mno-adx -mfxsr -mxsave -mno-xsaveopt -mno-avx512f -mno-avx512er -mno-avx512cd -mno-avx512pf -mno-prefetchwt1 -mno-clflushopt -mno-xsavec -mno-xsaves -mno-avx512dq -mno-avx512bw -mno-avx512vl -mno-avx512ifma -mno-avx512vbmi -mno-avx5124fmaps -mno-avx5124vnniw -mno-clwb -mno-mwaitx -mno-clzero -mno-pku -mno-rdpid --param "l1-cache-size=16" --param "l1-cache-line-size=64" --param "l2-cache-size=2048" "-mtune=bdver2"
<...>
```

But clang does not: (look for `bdver1`)
```
$ echo | clang -E - -march=native -###
clang version 7.0.0- (trunk)
Target: x86_64-pc-linux-gnu
Thread model: posix
InstalledDir: /usr/local/bin
 "/usr/lib/llvm-7/bin/clang" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-E" "-disable-free" "-disable-llvm-verifier" "-discard-value-names" "-main-file-name" "-" "-mrelocation-model" "static" "-mthread-model" "posix" "-mdisable-fp-elim" "-fmath-errno" "-masm-verbose" "-mconstructor-aliases" "-munwind-tables" "-fuse-init-array" "-target-cpu" "bdver1" "-target-feature" "+sse2" "-target-feature" "+cx16" "-target-feature" "+sahf" "-target-feature" "+tbm" "-target-feature" "-avx512ifma" "-target-feature" "-sha" "-target-feature" "-gfni" "-target-feature" "+fma4" "-target-feature" "-vpclmulqdq" "-target-feature" "+prfchw" "-target-feature" "-bmi2" "-target-feature" "-cldemote" "-target-feature" "-fsgsbase" "-target-feature" "-xsavec" "-target-feature" "+popcnt" "-target-feature" "+aes" "-target-feature" "-avx512bitalg" "-target-feature" "-xsaves" "-target-feature" "-avx512er" "-target-feature" "-avx512vnni" "-target-feature" "-avx512vpopcntdq" "-target-feature" "-clwb" "-target-feature" "-avx512f" "-target-feature" "-clzero" "-target-feature" "-pku" "-target-feature" "+mmx" "-target-feature" "+lwp" "-target-feature" "-rdpid" "-target-feature" "+xop" "-target-feature" "-rdseed" "-target-feature" "-waitpkg" "-target-feature" "-ibt" "-target-feature" "+sse4a" "-target-feature" "-avx512bw" "-target-feature" "-clflushopt" "-target-feature" "+xsave" "-target-feature" "-avx512vbmi2" "-target-feature" "-avx512vl" "-target-feature" "-avx512cd" "-target-feature" "+avx" "-target-feature" "-vaes" "-target-feature" "-rtm" "-target-feature" "+fma" "-target-feature" "+bmi" "-target-feature" "-rdrnd" "-target-feature" "-mwaitx" "-target-feature" "+sse4.1" "-target-feature" "+sse4.2" "-target-feature" "-avx2" "-target-feature" "-wbnoinvd" "-target-feature" "+sse" "-target-feature" "+lzcnt" "-target-feature" "+pclmul" "-target-feature" "-prefetchwt1" "-target-feature" "+f16c" "-target-feature" "+ssse3" "-target-feature" "-sgx" "-target-feature" "-shstk" "-target-feature" "+cmov" "-target-feature" "-avx512vbmi" "-target-feature" "-movbe" "-target-feature" "-xsaveopt" "-target-feature" "-avx512dq" "-target-feature" "-adx" "-target-feature" "-avx512pf" "-target-feature" "+sse3" "-dwarf-column-info" "-debugger-tuning=gdb" "-resource-dir" "/usr/lib/llvm-7/lib/clang/7.0.0" "-internal-isystem" "/usr/local/include" "-internal-isystem" "/usr/lib/llvm-7/lib/clang/7.0.0/include" "-internal-externc-isystem" "/usr/include/x86_64-linux-gnu" "-internal-externc-isystem" "/include" "-internal-externc-isystem" "/usr/include" "-fdebug-compilation-dir" "/build/llvm-build-Clang-release" "-ferror-limit" "19" "-fmessage-length" "271" "-fobjc-runtime=gcc" "-fdiagnostics-show-option" "-fcolor-diagnostics" "-o" "-" "-x" "c" "-"
```

So clang, unlike gcc, considers this to be `bdver1`.

After some digging, i've come across `getAMDProcessorTypeAndSubtype()` in `Host.cpp`.
I have added the following debug printf after the call to that function in `sys::getHostCPUName()`:
```
errs() << "Family " << Family << " Model " << Model << " Type " << Type "\n";
```
Which produced:
```
Family 21 Model 2 Type 5
```
Which matches the `lscpu` output.

As it was pointed in the review by @craig.topper:
>>! In D46314#1084123, @craig.topper wrote:
> I dont' think this is right. Here is what I found on wikipedia. https://en.wikipedia.org/wiki/List_of_AMD_CPU_microarchitectures.
>
> AMD Bulldozer Family 15h - the successor of 10h/K10. Bulldozer is designed for processors in the 10 to 220W category, implementing XOP, FMA4 and CVT16 instruction sets. Orochi was the first design which implemented it. For Bulldozer, CPUID model numbers are 00h and 01h.
> AMD Piledriver Family 15h (2nd-gen) - successor to Bulldozer. CPUID model numbers are 02h (earliest "Vishera" Piledrivers) and 10h-1Fh.
> AMD Steamroller Family 15h (3rd-gen) - third-generation Bulldozer derived core. CPUID model numbers are 30h-3Fh.
> AMD Excavator Family 15h (4th-gen) - fourth-generation Bulldozer derived core. CPUID model numbers are 60h-6Fh, later updated revisions have model numbers 70h-7Fh.
>
>
> So there's a weird exception where model 2 should go with 0x10-0x1f.

Though It does not help that the code can't be tested at the moment.
With this logical change, the `bdver2` is properly detected.
```
$ echo | /build/llvm-build-Clang-release/bin/clang -E - -march=native -###
clang version 7.0.0 (trunk 331249) (llvm/trunk 331256)
Target: x86_64-unknown-linux-gnu
Thread model: posix
InstalledDir: /build/llvm-build-Clang-release/bin
 "/build/llvm-build-Clang-release/bin/clang-7" "-cc1" "-triple" "x86_64-unknown-linux-gnu" "-E" "-disable-free" "-main-file-name" "-" "-mrelocation-model" "static" "-mthread-model" "posix" "-mdisable-fp-elim" "-fmath-errno" "-masm-verbose" "-mconstructor-aliases" "-munwind-tables" "-fuse-init-array" "-target-cpu" "bdver2" "-target-feature" "+sse2" "-target-feature" "+cx16" "-target-feature" "+sahf" "-target-feature" "+tbm" "-target-feature" "-avx512ifma" "-target-feature" "-sha" "-target-feature" "-gfni" "-target-feature" "+fma4" "-target-feature" "-vpclmulqdq" "-target-feature" "+prfchw" "-target-feature" "-bmi2" "-target-feature" "-cldemote" "-target-feature" "-fsgsbase" "-target-feature" "-xsavec" "-target-feature" "+popcnt" "-target-feature" "+aes" "-target-feature" "-avx512bitalg" "-target-feature" "-movdiri" "-target-feature" "-xsaves" "-target-feature" "-avx512er" "-target-feature" "-avx512vnni" "-target-feature" "-avx512vpopcntdq" "-target-feature" "-clwb" "-target-feature" "-avx512f" "-target-feature" "-clzero" "-target-feature" "-pku" "-target-feature" "+mmx" "-target-feature" "+lwp" "-target-feature" "-rdpid" "-target-feature" "+xop" "-target-feature" "-rdseed" "-target-feature" "-waitpkg" "-target-feature" "-movdir64b" "-target-feature" "-ibt" "-target-feature" "+sse4a" "-target-feature" "-avx512bw" "-target-feature" "-clflushopt" "-target-feature" "+xsave" "-target-feature" "-avx512vbmi2" "-target-feature" "-avx512vl" "-target-feature" "-avx512cd" "-target-feature" "+avx" "-target-feature" "-vaes" "-target-feature" "-rtm" "-target-feature" "+fma" "-target-feature" "+bmi" "-target-feature" "-rdrnd" "-target-feature" "-mwaitx" "-target-feature" "+sse4.1" "-target-feature" "+sse4.2" "-target-feature" "-avx2" "-target-feature" "-wbnoinvd" "-target-feature" "+sse" "-target-feature" "+lzcnt" "-target-feature" "+pclmul" "-target-feature" "-prefetchwt1" "-target-feature" "+f16c" "-target-feature" "+ssse3" "-target-feature" "-sgx" "-target-feature" "-shstk" "-target-feature" "+cmov" "-target-feature" "-avx512vbmi" "-target-feature" "-movbe" "-target-feature" "-xsaveopt" "-target-feature" "-avx512dq" "-target-feature" "-adx" "-target-feature" "-avx512pf" "-target-feature" "+sse3" "-dwarf-column-info" "-debugger-tuning=gdb" "-resource-dir" "/build/llvm-build-Clang-release/lib/clang/7.0.0" "-internal-isystem" "/usr/local/include" "-internal-isystem" "/build/llvm-build-Clang-release/lib/clang/7.0.0/include" "-internal-externc-isystem" "/usr/include/x86_64-linux-gnu" "-internal-externc-isystem" "/include" "-internal-externc-isystem" "/usr/include" "-fdebug-compilation-dir" "/build/llvm-build-Clang-release" "-ferror-limit" "19" "-fmessage-length" "271" "-fobjc-runtime=gcc" "-fdiagnostics-show-option" "-fcolor-diagnostics" "-o" "-" "-x" "c" "-"
```

Reviewers: craig.topper, GBuella, RKSimon, asbirlea, echristo, bkramer, spatel, andreadb, GGanesh

Reviewed By: craig.topper

Subscribers: sdardis, aprantl, arichardson, JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D46314

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331294 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Split WriteFMul/WriteFDiv into XMM and YMM/ZMM scheduler classes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331293 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-symbolizer: Handle function definitions nested within other functions

LLVM always puts function definition DIEs at the top level, but under
some circumstances GCC does not (at least in this case with member
functions of a function-local type).

To ensure that doesn't appear as though the local type's member function
is unduly inlined within the outer function - ensure the inline
discovery DIE parent walk stops at the first DW_TAG_subprogram.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331291 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Split WriteFRcp/WriteFRsqrt/WriteFSqrt into XMM and YMM/ZMM scheduler classes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331290 91177308-0d34-0410-b5e6-96231b3b80d8

Use no-op opt run to eliminate the difference in bb pred comment, per chandler's suggestion. It is better than using sed on portability.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331286 91177308-0d34-0410-b5e6-96231b3b80d8

AMDGPU: Add missing gfx904 tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331284 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Split WriteFCmp into XMM and YMM/ZMM scheduler classes

Removes more WriteFCmp InstRW overrides

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331283 91177308-0d34-0410-b5e6-96231b3b80d8

Support: assume `std::is_final` with MSVC

According to MSDN, Visual Studio 2015 included support for
std::is_final. Additionally, a bug in the Visual Studio compiler results
in the incorrect definition of __cplusplus. Due to the conditions in the
else case not holding either, we end up with no definition of
LLVM_IS_FINAL when building with MSVC. This has not yet been a problem
with LLVM/clang, however, the uses of LLVM_IS_FINAL is more prevalent in
swift, which uses the ADT library and causes issues when building lldb
with Visual Studio.

Workaround the issue by always assuming that the definition of
std::is_final is available with Visual Studio. Since we currently
require VS 2015+ for building LLVM, this condition should always hold
for the users in LLVM/clang (and for swift).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331282 91177308-0d34-0410-b5e6-96231b3b80d8

[LV] Move test/Transforms/LoopVectorize/pr23997.ll

Summary:
This fixes a build break with r331269.

test/Transforms/LoopVectorize/pr23997.ll

should be in:

test/Transforms/LoopVectorize/X86/pr23997.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331281 91177308-0d34-0410-b5e6-96231b3b80d8

Fix the sed command in test which doesn't work well on BSD.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331280 91177308-0d34-0410-b5e6-96231b3b80d8

[WebAssembly] llvm-readobj: display symbols names in relocations

Differential Revision: https://reviews.llvm.org/D46296

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331279 91177308-0d34-0410-b5e6-96231b3b80d8

AMDGPU/NFC: Use enum values for first/last machs instead of numbers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331278 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Split WriteFAdd into XMM and YMM/ZMM scheduler classes

Removes more WriteFAdd InstRW overrides

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331276 91177308-0d34-0410-b5e6-96231b3b80d8

Remove @brief commands from doxygen comments, too.

This is a follow-up to r331272.

We've been running doxygen with the autobrief option for a couple of
years now. This makes the \brief markers into our comments
redundant. Since they are a visual distraction and we don't want to
encourage more \brief markers in new code either, this patch removes
them all.

Patch produced by
  for i in $(git grep -l '\@brief'); do perl -pi -e 's/\@brief //g' $i & done

https://reviews.llvm.org/D46290

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331275 91177308-0d34-0410-b5e6-96231b3b80d8

[SLP] Add additional test for transposable binary operations with reuse

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331274 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Convert all uses of WriteFAdd to X86SchedWriteWidths.

In preparation of splitting WriteFAdd by vector width.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331273 91177308-0d34-0410-b5e6-96231b3b80d8