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Sinclair Yeh [Thu, 23 Mar 2017 21:23:20 +0000 (14:23 -0700)]
drm/vmwgfx: Add and connect connector helper function
These helpers won't be called until we flip on the atomic support
flag or set drm_crtc_funcs->set_config to using the atomic
helper.
v2
Use drm_atomic_helper_best_encoder() rather than a vmwgfx-specific one
Signed-off-by: Sinclair Yeh <syeh@vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Acked-by: Daniel Vetter <daniel@ffwll.ch>
Sinclair Yeh [Thu, 23 Mar 2017 21:18:32 +0000 (14:18 -0700)]
drm/vmwgfx: Add and connect plane helper functions
Refactor previous FB and cursor plane update code into their
atomic counterparts: check, update, prepare, cleanup, and disable.
These helpers won't be called until we flip on the atomic support
flag or set drm_crtc_funcs->set_config to using the atomic
helper.
v2:
* Removed unnecessary pinning of cursor surface
* Added a few function headers
v3:
* Set clip region equal to the destination region
* Fixed surface pinning policy
* Enable SVGA mode in vmw_sou_primary_plane_prepare_fb
Signed-off-by: Sinclair Yeh <syeh@vmware.com>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Sinclair Yeh [Thu, 23 Mar 2017 20:14:54 +0000 (13:14 -0700)]
drm/vmwgfx: Add and connect CRTC helper functions
Atomic mode set requires us to refactor existing vmw_stdu_crtc_set_config
code into sections that check the validity of the new mode, and sections
that actually program the hardware state.
vmw_du_crtc_atomic_check() takes CRTC-related checking code. In a later
patch, vmw_du_primary_plane_atomic_check() will take framebuffer-related
checking code.
These helpers won't be called until we flip on the atomic support
flag or set drm_crtc_funcs->set_config to using the atomic
helper.
v2:
* The state->num_connector is actually the total number of potential
connectors, not just the one associated with the display unit.
The proper one to check is ->connector_mask.
* Add the check to only allow plane state to be the same as crtc state
(Thanks to mlankhorst)
* Make sure to turn on SVGA mode before using VRAM. SVGA mode is
disabled in master_drop if dbdev is not running.
v3:
* Moved dot clock override to crtc_atomic_check
Signed-off-by: Sinclair Yeh <syeh@vmware.com>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Acked-by: Daniel Vetter <daniel@ffwll.ch>
Sinclair Yeh [Thu, 23 Mar 2017 18:48:44 +0000 (11:48 -0700)]
drm/vmwgfx: Connector atomic state
Add connector handling functions. Start tracking is_implicity in
the connector state. Eventually, this field should be tracked
exclusively in a connector state.
Now that plane and connector states have been created, we can also
activate the code that use CRTC state.
Signed-off-by: Sinclair Yeh <syeh@vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Sinclair Yeh [Thu, 23 Mar 2017 18:36:05 +0000 (11:36 -0700)]
drm/vmwgfx: Plane atomic state
Add plane state handling functions.
We have to keep track of a few plane states so we cannot use the
DRM helper for this.
Created vmw_plane_state along with functions to reset, duplicate,
and destroty it.
v2
* Removed cursor clean up special case
Signed-off-by: Sinclair Yeh <syeh@vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Acked-by: Daniel Vetter <daniel@ffwll.ch>
Sinclair Yeh [Thu, 23 Mar 2017 18:33:39 +0000 (11:33 -0700)]
drm/vmwgfx: CRTC atomic state
Create and Add CRTC state. We currently do not track any properties
or custom states so we can technically use the DRM helpers. Creating
this code just to make potential future additions easier.
Most of the new code will be compiled but not enabled until
plane/connector state handling code is also in place.
This is the first of a series to enable atomic mode set for vmwgfx.
The atomic enabling effort was done in collaboration with Thomas
Hellstrom and the VMware Graphics Team.
Signed-off-by: Sinclair Yeh <syeh@vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Sinclair Yeh [Thu, 23 Mar 2017 18:28:11 +0000 (11:28 -0700)]
drm/vmwgfx: Add universal plane support
Universal support is prerequisite for atomic mode set.
Explicitly create planes for the cursor and the primary FB. With
a functional cursor plane, the DRM will no longer use the legacy
cursor_set2 and cursor_move entry points.
Signed-off-by: Sinclair Yeh <syeh@vmware.com>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Sinclair Yeh [Thu, 23 Mar 2017 16:59:26 +0000 (09:59 -0700)]
drm/vmwgfx: Removed unused snooper.crtc field
This field is not being used anymore
Signed-off-by: Sinclair Yeh <syeh@vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Dave Airlie [Fri, 31 Mar 2017 01:47:18 +0000 (11:47 +1000)]
Merge branch 'drm-next-4.12' of git://people.freedesktop.org/~agd5f/linux into drm-next
New stuff for 4.12:
- Preliminary vega10 support
- Support for multi-level page tables
- GPU sensor stuff for mesa
- job tracing improvements
- PRT support for sparse buffers
- Additional SR-IOV improvements
- ttm improvements
- misc bug fixes and code cleanups
* 'drm-next-4.12' of git://people.freedesktop.org/~agd5f/linux: (315 commits)
drm/amdgpu: Fix 32bit x86 compilation warning
drm/amdgpu: just disallow reading untouched registers
drm/amdgpu: remove duplicate allowed reg CP_CPF_BUSY_STAT
drm/amdgpu/soc15: enable psp block for SRIOV
drm/amdgpu/soc15: bypass pp block for vf
drm/amdgpu/psp: add check sOS sign
drm/amd/amdgpu: Correct ring wptr address in debugfs (v2)
drm/amdgpu: Fix multi-level page table bugs for large BOs v3
drm/amdgpu: Fix Vega10 VM initialization
drm/amdgpu: Make max_pfn 64-bit
drm/amdgpu: drop GB_GPU_ID from the golden settings
drm/amdgpu: fix vm pte pde flags to 64-bit for sdma (v3)
drm/amd/amdgpu: fix Tonga S3 resume hang on rhel6.8
drm/ttm: decrease ttm bo priority number
drm/amd/amdgpu: fix performance drop when VRAM pressure
drm/amdgpu: Couple small warning fixes
drm/amdgpu: Clean up GFX 9 VM fault messages
drm/amdgpu: Register UTCL2 as a source of VM faults
drm/amdgpu/soc15: drop support for reading some registers
drm/amdgpu/soc15: return cached values for some registers (v2)
...
Alex Xie [Thu, 30 Mar 2017 17:30:00 +0000 (13:30 -0400)]
drm/amdgpu: Fix 32bit x86 compilation warning
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c:187:2: warning: right shift count >= width of type [enabled by default]
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:173:2: warning: right shift count >= width of type [enabled by default]
drivers/gpu/drm/amd/amdgpu/vega10_ih.c:106:3: warning: right shift count >= width of type [enabled by default]
v2: Add a space between "&" and "0xff"
Reported by: kbuild-all@01.org
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 24 Mar 2017 13:32:50 +0000 (14:32 +0100)]
drm/amdgpu: just disallow reading untouched registers
Not sure what the original intention was here, but returning a random piece of
kernel memory to userspace because we didn't set the value at all is clearly
not a good idea.
This patch disallows reading the register and returns
a proper error code instead.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 24 Mar 2017 13:05:37 +0000 (14:05 +0100)]
drm/amdgpu: remove duplicate allowed reg CP_CPF_BUSY_STAT
Remove duplicate mmCP_CPF_BUSY_STAT from the allowed registers.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Tue, 28 Mar 2017 11:16:42 +0000 (19:16 +0800)]
drm/amdgpu/soc15: enable psp block for SRIOV
SRIOV can support for loading ucode with PSP block, enable it.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Tue, 28 Feb 2017 09:26:40 +0000 (17:26 +0800)]
drm/amdgpu/soc15: bypass pp block for vf
Disable pp block if device is vf.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Tue, 28 Mar 2017 11:48:10 +0000 (19:48 +0800)]
drm/amdgpu/psp: add check sOS sign
Confirm if sys driver and sOS are already been loaded through sOS
sign register, skip loading sys driver and sOS if finding the sign.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom St Denis [Wed, 29 Mar 2017 17:01:30 +0000 (13:01 -0400)]
drm/amd/amdgpu: Correct ring wptr address in debugfs (v2)
On gfx9 hardware the value is not wrapped and is a 64-bit value. So
we reduce it modulo the ring size.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
(v2) use buf_mask instead of computing on the fly
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Wed, 29 Mar 2017 00:36:12 +0000 (20:36 -0400)]
drm/amdgpu: Fix multi-level page table bugs for large BOs v3
Fix the start/end address calculation for address ranges that span
multiple page directories in amdgpu_vm_alloc_levels.
Add error messages if page tables aren't found. Otherwise the page
table update would just fail silently.
v2:
* Change WARN_ON to WARN_ON_ONCE
* Move masking of high address bits to caller
* Add range-check for "from" and "to"
v3:
* Replace WARN_ON_ONCE in get_pt with pr_err in caller
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Wed, 29 Mar 2017 00:31:20 +0000 (20:31 -0400)]
drm/amdgpu: Fix Vega10 VM initialization
adev->family is not initialized yet when amdgpu_get_block_size is
called. Use adev->asic_type instead.
Minimum VM size is 512GB, not 256GB, for a single page table entry
in the root page table.
gmc_v9_0_vm_init is called after adev->vm_manager.max_pfn is
initialized. Move the minimum VM-size enforcement ahead of max_pfn
initializtion. Cast to 64-bit before the left-shift.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Wed, 29 Mar 2017 00:24:53 +0000 (20:24 -0400)]
drm/amdgpu: Make max_pfn 64-bit
With 4-level page tables the maximum VM size is 256TB. That's 64G
pages, which can't be represented in 32-bit.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 22 Mar 2017 09:29:45 +0000 (10:29 +0100)]
drm/amdgpu: drop GB_GPU_ID from the golden settings
That register is marked deprecated, reading it results in a bus error.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Junwei Zhang [Tue, 28 Mar 2017 08:52:07 +0000 (16:52 +0800)]
drm/amdgpu: fix vm pte pde flags to 64-bit for sdma (v3)
v2: fix for all sdma engines
v3: squash in fix for SI/CI
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jim Qu [Tue, 28 Mar 2017 09:18:15 +0000 (17:18 +0800)]
drm/amd/amdgpu: fix Tonga S3 resume hang on rhel6.8
1. security firmware loading has moved to sw init, so this code
is useless.
2. it seems that driver could not call request_firmware on
kernel 2.6, when S3 resume. for request firmware depends on
userspace, at this time, userspace is freeze.
Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roger.He [Tue, 28 Mar 2017 01:34:16 +0000 (09:34 +0800)]
drm/ttm: decrease ttm bo priority number
decrease and also reserve priority number for KFD using
Signed-off-by: Roger.He <Hongbo.He@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roger.He [Mon, 27 Mar 2017 11:38:11 +0000 (19:38 +0800)]
drm/amd/amdgpu: fix performance drop when VRAM pressure
When VRAM pressue and trigger huge evictions there is performance drop,
this patch fix it.
Signed-off-by: Roger.He <Hongbo.He@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Harry Wentland [Tue, 28 Mar 2017 15:29:53 +0000 (11:29 -0400)]
drm/amdgpu: Couple small warning fixes
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Tue, 28 Mar 2017 17:42:31 +0000 (13:42 -0400)]
drm/amdgpu: Clean up GFX 9 VM fault messages
Clean up the VM fault message format and use rate-limiting similar
to other ASICs.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Tue, 28 Mar 2017 17:41:11 +0000 (13:41 -0400)]
drm/amdgpu: Register UTCL2 as a source of VM faults
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 27 Mar 2017 18:40:36 +0000 (14:40 -0400)]
drm/amdgpu/soc15: drop support for reading some registers
The RB harvest registers are not necessary, the driver already
exposes this info via the info ioctl. GB_BACKEND_MAP has
been deprecated since SI and is not relevant to the RB mapping.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 24 Mar 2017 19:05:07 +0000 (15:05 -0400)]
drm/amdgpu/soc15: return cached values for some registers (v2)
Required for SR-IOV and saves MMIO transactions.
v2: drop cached RB harvest registers
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 24 Mar 2017 18:47:18 +0000 (14:47 -0400)]
drm/amdgpu/gfx9: use hweight for calculating num_rbs
Match what we do for other asics.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 28 Mar 2017 16:19:31 +0000 (12:19 -0400)]
drm/amdgpu: refine the logic in amdgpu_need_post()
We check the mem config register to make sure it's been
programmed by the vbios to determine if we need to post
so we check for a non-0 value. However, when the asic
comes out of reset, we may see all ones here, so check
for that too.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andrey Grodzovsky [Thu, 23 Mar 2017 19:33:07 +0000 (15:33 -0400)]
drm/amdgpu: Add interrupt entries for CRTC_VERTICAL_INTERRUPT0.
This used by DAL ISR logic for VBLANK handling.
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Wed, 15 Mar 2017 04:18:57 +0000 (12:18 +0800)]
drm/amdgpu:changes in gfx DMAframe scheme (v2)
1) Adapt to vulkan:
Now use double SWITCH BUFFER to replace the 128 nops w/a,
because when vulkan introduced, umd can insert 7 ~ 16 IBs
per submit which makes 256 DW size cannot hold the whole
DMAframe (if we still insert those 128 nops), CP team suggests
use double SWITCH_BUFFERs, instead of tricky 128 NOPs w/a.
2) To fix the CE VM fault issue when MCBP introduced:
Need one more COND_EXEC wrapping IB part (original one us
for VM switch part).
this change can fix vm fault issue caused by below scenario
without this change:
>CE passed original COND_EXEC (no MCBP issued this moment),
proceed as normal.
>DE catch up to this COND_EXEC, but this time MCBP issued,
thus DE treats all following packages as NOP. The following
VM switch packages now looks just as NOP to DE, so DE
dosen't do VM flush at all.
>Now CE proceeds to the first IBc, and triggers VM fault,
because DE didn't do VM flush for this DMAframe.
3) change estimated alloc size for gfx9.
with new DMAframe scheme, we need modify emit_frame_size
for gfx9
4) No need to insert 128 nops after gfx8 vm flush anymore
because there was double SWITCH_BUFFER append to vm flush,
and for gfx7 we already use double SWITCH_BUFFER following
after vm_flush so no change needed for it.
5) Change emit_frame_size for gfx8
v2: squash in BUG removal from Monk
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Thu, 23 Mar 2017 08:32:13 +0000 (16:32 +0800)]
drm/amdgpu:fix missing programing critical registers
those MC_VM registers won't be programed by VBIOS in VF
so driver is responsible to programe them.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Thu, 23 Mar 2017 08:10:04 +0000 (16:10 +0800)]
drm/amdgpu:fix ring_write_multiple
ring_write_multiple should use buf_mask instead of ptr_mask
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Wed, 22 Mar 2017 10:01:59 +0000 (18:01 +0800)]
drm/amdgpu:fix gmc_v9 vm fault process for SRIOV
for SRIOV we cannot use access register when in IRQ routine
with regular KIQ method
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Wed, 22 Mar 2017 10:02:40 +0000 (18:02 +0800)]
drm/amdgpu:no cg for soc15 of SRIOV
no CG for SRIOV on SOC15
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Tue, 21 Mar 2017 10:58:53 +0000 (18:58 +0800)]
drm/amdgpu:two fixings for sdma v4 for SRIOV
no hw_fini for SRIOV, otherwise other VF will be affected
no CG for SRIOV
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Fri, 24 Feb 2017 04:06:22 +0000 (12:06 +0800)]
drm/amdgpu:change sequence of SDMA v4 init
must set minor_update.enable before write smaller value
to wptr/doorbell, so for sriov we need set that register
bit in hw_init period.
this could fix the SDMA ring test fail after guest reboot
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Tue, 21 Mar 2017 10:48:45 +0000 (18:48 +0800)]
drm/amdgpu:fix ring init sequence
ring->buf_mask need be set prior to ring_clear_ring invoke
and fix ring_clear_ring as well which should use buf_mask
instead of ptr_mask
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Tue, 21 Mar 2017 08:41:01 +0000 (16:41 +0800)]
drm/amdgpu:virt_init_setting invoke is missed!
this must be invoked during early init
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Wed, 8 Mar 2017 07:38:54 +0000 (15:38 +0800)]
uapi/drm:add new flag for Preemption
when MCBP supported, we will set pre_enb bit for those
IBs with PREEMPT flag tagged
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Wed, 8 Mar 2017 07:37:00 +0000 (15:37 +0800)]
uapi/drm:change Preamble Description
Preamble in linux doesn't mean it is CE PREAMBLE IB,
instead it means this IB could be dropped if no
ctx switch happens.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Wed, 8 Mar 2017 07:53:19 +0000 (15:53 +0800)]
drm/amdgpu:enable MCBP for SR-IOV (v2)
Apply the new IB during IB emit for SRIOV with MCBP
v2: agd: use define instead of magic number
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Tue, 21 Mar 2017 03:50:43 +0000 (11:50 +0800)]
drm/amdgpu:enable mcbp for gfx9(v2)
set bit 21 of IB.control filed to actually enable
MCBP for SRIOV
v2:
add flag for preemption enable bit for soc15 and use
this flag instead of hardcode.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Fri, 24 Mar 2017 04:07:52 +0000 (12:07 +0800)]
drm/amdgpu:implement cond_exec for gfx8
when MCBP enabled for gfx8, the cond_exec must also
be implemented, otherwise there will be odds to meet
cross engine (ce and me) deadlock when world switch
happens.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Mon, 27 Mar 2017 07:14:53 +0000 (15:14 +0800)]
drm/amdgpu:fix the check in cs_ib_fill for SRIOV
1,the check is only appliable for SRIOV GFX engine.
2,use chunk_ib instead of ib.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Ken Wang <Qingqing.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Wed, 8 Mar 2017 07:51:13 +0000 (15:51 +0800)]
drm/amdgpu:protect cs submit
to prevent submit two or more IBs with PREEMPT flags.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Tue, 28 Mar 2017 03:00:03 +0000 (11:00 +0800)]
drm/amdgpu:fix cs_ib_fill
should use chunk_ib instead of ib, otherwise the logic
is incorrect.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Ken Wang <Qingqing.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicolai Hähnle [Thu, 23 Mar 2017 18:34:11 +0000 (19:34 +0100)]
drm/amdgpu: clear freed mappings immediately when BO may be freed
Also, add the fence of the clear operations to the BO to ensure that
the underlying memory can only be re-used after all PTEs pointing to
it have been cleared.
This avoids the following sequence of events that could be triggered
by user space:
1. Submit a CS that accesses some BO _without_ adding that BO to the
buffer list.
2. Free that BO.
3. Some other task re-uses the memory underlying the BO.
4. The CS is submitted to the hardware and accesses memory that is
now already in use by somebody else.
By clearing the page tables immediately in step 2, a GPU VM fault will
be triggered in step 4 instead of wild memory accesses.
v2: use amdgpu_bo_fence directly
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Mon, 27 Mar 2017 05:44:45 +0000 (13:44 +0800)]
drm/amdgpu: enable four level VMPT for gmc9
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Thu, 23 Mar 2017 09:38:34 +0000 (17:38 +0800)]
drm/amdgpu: set page table depth by num_level
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Mon, 27 Mar 2017 03:53:12 +0000 (11:53 +0800)]
drm/amdgpu: adapt vm size for multi vmpt
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Mon, 27 Mar 2017 03:43:35 +0000 (11:43 +0800)]
drm/amdgpu: limit block size to one page
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Mon, 27 Mar 2017 03:36:57 +0000 (11:36 +0800)]
drm/amdgpu: abstract block size to one function
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 27 Oct 2016 18:04:38 +0000 (20:04 +0200)]
drm/amdgpu: add alloc/free for multi level PDs V2
Allocate and free page directories on demand.
V2:
a. clear entries allocation
b. fix entries index calculation
c. need alloc sub level even parent bo was allocated
Signed-off-by: Christian König <christian.koenig@amd.com> (v1)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1)
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> (v2)
Acked-by: Alex Deucher <alexander.deucher@amd.com> (v2)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 25 Oct 2016 13:52:28 +0000 (15:52 +0200)]
drm/amdgpu: handle multi level PD during PT updates
Not the best solution, but good enough for now.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 12 Oct 2016 13:13:52 +0000 (15:13 +0200)]
drm/amdgpu: handle multi level PD updates V2
Update all levels of the page directory.
V2:
a. sub level pdes always are written to incorrect place.
b. sub levels need to update regardless of parent updates.
Signed-off-by: Christian König <christian.koenig@amd.com> (V1)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (V1)
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> (V2)
Acked-by: Alex Deucher <alexander.deucher@amd.com> (V2)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 13 Oct 2016 08:20:53 +0000 (10:20 +0200)]
drm/amdgpu: handle multi level PD in the LRU
Move all levels to the end after command submission.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 12 Oct 2016 13:36:57 +0000 (15:36 +0200)]
drm/amdgpu: handle multi level PD during validation
All page directory levels should be in place after this.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 19 Oct 2016 09:03:57 +0000 (11:03 +0200)]
drm/amdgpu: handle multi level PD size calculation (v2)
Allows us to get the size for all levels as well.
v2: agd: fix warning
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 12 Oct 2016 12:46:26 +0000 (14:46 +0200)]
drm/amdgpu: generalize page table level
No functional change, but the base for multi level page tables.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 17 Oct 2016 13:08:10 +0000 (15:08 +0200)]
drm/amdgpu: add num_level to the VM manager
Needs to be filled with handling.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 13 Oct 2016 13:09:08 +0000 (15:09 +0200)]
drm/amdgpu: add the VM pointer to the amdgpu_pte_update_params as well
This way we save passing it through the different functions.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 12 Oct 2016 11:20:52 +0000 (13:20 +0200)]
drm/amdgpu: rename page_directory_fence to last_dir_update
Decribes better what this is used for.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Mon, 27 Mar 2017 07:32:59 +0000 (15:32 +0800)]
drm/amd/powerplay: reduce sample period time
for power readings.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Fri, 24 Mar 2017 03:52:23 +0000 (11:52 +0800)]
drm/amdgpu: add get_clockgating callback for mmhub v1
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Fri, 24 Mar 2017 03:04:27 +0000 (11:04 +0800)]
drm/amdgpu: add get_clockgating for sdma v4
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Fri, 24 Mar 2017 02:46:16 +0000 (10:46 +0800)]
drm/amdgpu: add get_clockgating callback for soc15 (v3)
v2: squash register typo fix from Ray
v3: fix spelling
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Fri, 24 Mar 2017 02:12:32 +0000 (10:12 +0800)]
drm/amdgpu: add get_clockgating callback for nbio v6.1
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Fri, 24 Mar 2017 01:58:11 +0000 (09:58 +0800)]
drm/amdgpu: add get_clockgating callback for gfx v9
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 23 Mar 2017 17:05:55 +0000 (13:05 -0400)]
drm/amdgpu/gfx9: further KIQ parameter cleanup
The ring structure already has what we need.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 23 Mar 2017 16:52:23 +0000 (12:52 -0400)]
drm/amdgpu/gfx9: store the eop gpu addr in the ring structure
Avoids passing around additional parameters during setup.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 23 Mar 2017 16:41:59 +0000 (12:41 -0400)]
drm/amdgpu/gfx9: reduce the functon params for mpq setup
Everything we need is in the ring structure. No need to
pass all the bits explicitly.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 23 Mar 2017 16:30:41 +0000 (12:30 -0400)]
drm/amdgpu/gfx9: reserve kiq eop object before unmapping it
It's required.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 27 Mar 2017 20:54:06 +0000 (16:54 -0400)]
drm/amdgpu/gfx9: reserve mqd objects before mapping them
It's required.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 27 Mar 2017 20:52:40 +0000 (16:52 -0400)]
drm/amdgpu/gfx9: rename some functions
To better match where they are used. Called from sw_init
and sw_fini.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 23 Mar 2017 16:19:15 +0000 (12:19 -0400)]
drm/amdgpu/gfx9: whitespace cleanup
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Harry Wentland [Wed, 15 Mar 2017 20:32:30 +0000 (16:32 -0400)]
drm/amd/amdgpu: Fix some warnings in vce4
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Mon, 13 Mar 2017 03:10:12 +0000 (11:10 +0800)]
drm/amdgpu/vce4: impl vce & mmsch sriov start
For MM sriov, need use MMSCH to init engine and the init procedures
are all saved in mm table.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Mon, 13 Mar 2017 03:03:35 +0000 (11:03 +0800)]
drm/amdgpu: add mmsch structures
For MM SRIOV, need to prepare MM table send send it to MMSCH to
initial UVD & VCE engine. Create new header file for the structures.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Wed, 8 Mar 2017 06:35:16 +0000 (14:35 +0800)]
drm/amdgpu/vce4: Ignore vce ring/ib test temporarily
In order to not break SRIOV gfx development, will revert
this patch after vce proved working.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Tue, 7 Mar 2017 08:40:55 +0000 (16:40 +0800)]
drm/amdgpu/vce4: alloc mm table for MM sriov
Allocate MM table for sriov device.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Tue, 28 Feb 2017 09:24:52 +0000 (17:24 +0800)]
drm/amdgpu/virt: add structure for MM table
Add new structure for MM table for multi media scheduler of sriov.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Wed, 15 Feb 2017 09:25:43 +0000 (17:25 +0800)]
drm/amdgpu: disable uvd for sriov
disable uvd for sriov temporarily.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Tue, 7 Mar 2017 06:52:24 +0000 (14:52 +0800)]
drm/amdgpu/vce4: enable doorbell for SRIOV
VCE SRIOV need use doorbell and only works on VCN0 ring now
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Tue, 7 Mar 2017 06:45:25 +0000 (14:45 +0800)]
drm/amdgpu: Don't touch PG&CG for SRIOV MM
For SRIOV, MM don't need to care about PG & CG, skip it.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Fri, 30 Dec 2016 08:18:56 +0000 (16:18 +0800)]
drm/amdgpu/vega10:fix DOORBELL64 scheme
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 22 Mar 2017 14:49:25 +0000 (10:49 -0400)]
drm/amdgpu:vega10: enable virtual display if set via module option
Enable virtual displays if the user has enabled them via the
kernel command line. Useful in virtual or headless environments.
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Tue, 28 Feb 2017 09:22:03 +0000 (17:22 +0800)]
drm/amdgpu/soc15: enable virtual dce for vf
VF need virtual dce, enable it if device is vf.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Wed, 8 Mar 2017 07:06:47 +0000 (15:06 +0800)]
drm/amdgpu/soc15: init virt ops for vf
If gpu device is vf, set virt ops so that guest can talk with GPU
hypervisor.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Fri, 10 Mar 2017 06:18:17 +0000 (14:18 +0800)]
drm/amdgpu/virt: impl mailbox for ai
Implement mailbox protocol for AI so that guest vf can communicate
with GPU hypervisor.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Tue, 14 Feb 2017 08:08:18 +0000 (16:08 +0800)]
drm/amdgpu/dce_virtual: bypass DPM for vf
If enable DPM for VF, always get lot of warn_slow_patch_null in
dmesg and vf doesn't support DPM.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Tue, 28 Feb 2017 09:06:36 +0000 (17:06 +0800)]
drm/amdgpu/gmc9: no need use kiq in vega10 tlb flush
two reasons:
1. there is a spinlock around;
2. vm register is pf/vf copy, vf can access via mmio safely.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Tue, 28 Feb 2017 08:59:28 +0000 (16:59 +0800)]
drm/amdgpu/soc15: bypass PSP for VF
Bypass PSP block for VF device.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Thu, 15 Dec 2016 05:56:53 +0000 (13:56 +0800)]
drm/amdgpu/sdma4:re-org SDMA initial steps for sriov
Rework sdma init to support SR-IOV.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Mon, 12 Dec 2016 09:18:37 +0000 (17:18 +0800)]
drm/amdgpu:bypass RLC init for SRIOV
one issue unresolved for RLC:
rlc will go wrong completely if there is a soft_reset
before RLC ucode loading.
to workaround above issue, we can totally ignore RLC
in guest driver side due to there was already full
initialization on RLC side by GIM
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Tue, 7 Mar 2017 05:56:03 +0000 (13:56 +0800)]
drm/amdgpu/gfx9: impl gfx9 meta data emit
Insert ce meta prior to cntx_cntl and de follow it.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Fri, 18 Nov 2016 09:16:36 +0000 (17:16 +0800)]
drm/amdgpu:impl gfx9 cond_exec (v2)
it is needed for virtualization
v2: squash in wptr value fix
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Tue, 28 Feb 2017 08:48:47 +0000 (16:48 +0800)]
drm/amdgpu: init kiq and kcq for vega10
Init kiq via cpu mmio and init kcq through kiq.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>