OSDN Git Service
George Rimar [Thu, 16 Aug 2018 12:23:22 +0000 (12:23 +0000)]
[yaml2elf] - Simplify code, add a test. NFC.
This simplifies the code allowing to set the sh_info
for relocations sections. And adds a missing test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339870
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Sam Parker [Thu, 16 Aug 2018 11:54:09 +0000 (11:54 +0000)]
[ARM] Allow zext in ARMCodeGenPrepare
Treat zext instructions as roots, like we do for truncs.
Differential Revision: https://reviews.llvm.org/D50759
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339868
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Alex Bradbury [Thu, 16 Aug 2018 11:26:37 +0000 (11:26 +0000)]
[RISCV][MC] Don't fold symbol differences if requiresDiffExpressionRelocations is true
When emitting the difference between two symbols, the standard behavior is
that the difference will be resolved to an absolute value if both of the
symbols are offsets from the same data fragment. This is undesirable on
architectures such as RISC-V where relaxation in the linker may cause the
computed difference to become invalid. This caused an issue when compiling to
object code, where the size of a function in the debug information was already
calculated even though it could change as a consequence of relaxation in the
subsequent linking stage.
This patch inhibits the resolution of symbol differences to absolute values
where the target's AsmBackend has declared that it does not want these to be
folded.
Differential Revision: https://reviews.llvm.org/D45773
Patch by Edward Jones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339864
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Simon Pilgrim [Thu, 16 Aug 2018 11:08:23 +0000 (11:08 +0000)]
[ADT] Replace APInt::WORD_MAX with APInt::WORDTYPE_MAX
The windows SDK defines WORD_MAX, so any poor soul that wants to use LLVM in a project that depends on the windows SDK gets a build error.
Given that it actually describes the maximal value of WordType, it actually fits even better than WORD_MAX
Patch by: @miscco
Differential Revision: https://reviews.llvm.org/D50777
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339863
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Sam Parker [Thu, 16 Aug 2018 10:05:39 +0000 (10:05 +0000)]
[ARM] Allow signed icmps in ARMCodeGenPrepare
Originally committed in r339755 which was reverted in r339806 due to
an asan issue. The issue was caused by my assumption that operands to
a CallInst mapped to the FunctionType Params. CallInsts are now
handled by iterating over their ArgOperands instead of Operands.
Original Message:
Treat signed icmps as 'sinks', allowing them to be in the use-def
tree, enabling more promotions to be performed. As a sink, any
promoted incoming values need to be truncated before being used by
the signed icmp.
Differential Revision: https://reviews.llvm.org/D50067
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339858
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Simon Atanasyan [Thu, 16 Aug 2018 08:43:17 +0000 (08:43 +0000)]
[mips] Remove dead code from MipsPassConfig
Found by GCC's -Wunused-function.
Patch by Kim Gräsman.
Differential revision: https://reviews.llvm.org/D50612
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339847
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Max Kazantsev [Thu, 16 Aug 2018 08:30:15 +0000 (08:30 +0000)]
[NFC] Remove const modifier to allow further development in LICM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339846
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Max Kazantsev [Thu, 16 Aug 2018 06:28:04 +0000 (06:28 +0000)]
[NFC] Add missing const modifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339844
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Craig Topper [Thu, 16 Aug 2018 06:20:24 +0000 (06:20 +0000)]
[X86] Remove masking from the 512-bit padds and psubs intrinsics. Use select in IR instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339842
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Craig Topper [Thu, 16 Aug 2018 06:20:22 +0000 (06:20 +0000)]
[X86] Remove the unused masked 128 and 256-bit masked padds/psubs intrinsics.
Still need to remove masking from the 512-bit versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339841
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Craig Topper [Thu, 16 Aug 2018 06:20:19 +0000 (06:20 +0000)]
[X86] Correct some bad FileCheck prefixes in tests. Add test cases for v64i8 padd/psub saturation intrinsics.
For some reason we had the 128/256-bit tests, but no the 512-bit tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339840
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Chandler Carruth [Thu, 16 Aug 2018 01:22:19 +0000 (01:22 +0000)]
[x86] Actually initialize the SLH pass with the x86 backend and use
a shorter name ('x86-slh') for the internal flags and pass name.
Without this, you can't use the -stop-after or -stop-before
infrastructure. I seem to have just missed this when originally adding
the pass.
The shorter name solves two problems. First, the flag names were ...
really long and hard to type/manage. Second, the pass name can't be the
exact same as the flag name used to enable this, and there are already
some users of that flag name so I'm avoiding changing it unnecessarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339836
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Easwaran Raman [Thu, 16 Aug 2018 00:26:59 +0000 (00:26 +0000)]
[BFI] Use rounding while computing profile counts.
Summary:
Profile count of a block is computed by multiplying its block frequency
by entry count and dividing the result by entry block frequency. Do
rounded division in the last step and update test cases appropriately.
Reviewers: davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D50822
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339835
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George Burgess IV [Wed, 15 Aug 2018 22:15:35 +0000 (22:15 +0000)]
[Metadata] Replace a SmallVector with an array; NFC
MDNode::get takes an ArrayRef, so these should be equivalent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339824
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Andrea Di Biagio [Wed, 15 Aug 2018 22:11:05 +0000 (22:11 +0000)]
[llvm-mca] Minor style changes. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339823
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Guozhi Wei [Wed, 15 Aug 2018 22:08:26 +0000 (22:08 +0000)]
[CodeGenPrepare] Add BothExtension type to PromotedInsts
This patch fixes PR38125.
Instruction extension types are recorded in PromotedInsts, it can be used later in function canGetThrough. If an instruction has two users with different extension types, it will be inserted into PromotedInsts two times in function promoteOperandForOther. The second one overwrites the first one, and the final extension type is wrong, later causes problem in canGetThrough.
This patch changes the simple bool extension type to 2-bit enum type, add a BothExtension type in addition to zero/sign extension. When an user sees BothExtension for an instruction, it actually knows nothing about how that instruction is extended.
Differential Revision: https://reviews.llvm.org/D49512
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339822
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Matt Arsenault [Wed, 15 Aug 2018 21:46:27 +0000 (21:46 +0000)]
AMDGPU: Fold fneg into fmed3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339821
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Matt Arsenault [Wed, 15 Aug 2018 21:34:06 +0000 (21:34 +0000)]
AMDGPU: Improve extract_vector_elt reduction combine
Handle fmul, fsub and preserve flags.
Also really test minnum/maxnum reductions.
The existing tests were only checking from
minnum/maxnum matched from a fast math compare
and select which is not the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339820
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Matt Arsenault [Wed, 15 Aug 2018 21:25:20 +0000 (21:25 +0000)]
AMDGPU: Implement llvm.amdgcn.icmp/fcmp for i16/f16
Also support these on targets without support for these,
since it will allow us to freely create these in instcombine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339819
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Craig Topper [Wed, 15 Aug 2018 21:21:52 +0000 (21:21 +0000)]
[X86] Improve AVX1 shuffle lowering for v8f32 shuffles where the low half comes from V1 and the high half comes from V2 and the halves do the same operation
To lower this we now create a new V1 containing the low half of both sources and a new V2 containing the upper half of both sources. Then we created a repeated lane shuffle of those new sources to create the final result.
This fixes PR35833
Differential Revison: https://reviews.llvm.org/D41794
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339818
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Matt Arsenault [Wed, 15 Aug 2018 21:14:25 +0000 (21:14 +0000)]
AMDGPU: Stop producing icmp/fcmp intrinsics with invalid types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339815
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Matt Arsenault [Wed, 15 Aug 2018 21:03:55 +0000 (21:03 +0000)]
AMDGPU: Address todo for handling 1/(2 pi)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339814
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Matt Arsenault [Wed, 15 Aug 2018 21:03:44 +0000 (21:03 +0000)]
DAG: Use getObjectOffset helper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339813
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Simon Pilgrim [Wed, 15 Aug 2018 20:41:19 +0000 (20:41 +0000)]
[TableGen] Remove unnecessary TypeSetByHwMode -> ValueTypeByHwMode -> TypeSetByHwMode conversions in getPatternSize
I noticed this during profiling of tablegen (PR28222) that we were calling Child->getType(0) which creates a ValueTypeByHwMode on the fly from the requested internal TypeSetByHwMode type and returns it by value, we then treat it as a TypeSetByHwMode reference which involves constructing a new TypeSetByHwMode on the stack with a large amount of std::map iterating/copying all along the way.
I am not an expert on tablegen, but AFAICT this is all unnecessary and we should be calling Child->getExtType(0) which returns the original TypeSetByHwMode by reference.
This gives me a 90sec reduction in msvc debug builds of x86 -gen-dag-isel.
Differential Revision: https://reviews.llvm.org/D50789
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339812
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Matt Arsenault [Wed, 15 Aug 2018 20:34:54 +0000 (20:34 +0000)]
DAG: Try to custom lower when promoting float operands
For some reason this wasn't done for floats like
integers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339811
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Lang Hames [Wed, 15 Aug 2018 20:11:21 +0000 (20:11 +0000)]
[MCJIT] Fix a case of Error::success() being passed to report_fatal_error.
MCJIT::getSymbolAddress was handling a non-fatal error condition of JITSymbol
as fatal. JITSymbol::operator bool returns false if no address is available
but no error is set. This can occur e.g. if the symbol name was not found.
Patch by Jascha Wetzel. Thanks Jascha!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339809
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Vitaly Buka [Wed, 15 Aug 2018 20:09:35 +0000 (20:09 +0000)]
Revert "[ARM] Allow signed icmps in ARMCodeGenPrepare"
use-after-poison in check-llvm under asan
This reverts commit r339755.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339806
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Lang Hames [Wed, 15 Aug 2018 18:42:11 +0000 (18:42 +0000)]
[Support] Add a basic C API for llvm::Error.
Summary:
The C-API supports consuming errors, converting an error to a string error
message, and querying an error's type. Other LLVM C APIs that wish to use
llvm::Error can supply error-type-id checkers and custom
error-to-structured-type converters for any custom errors they provide.
Reviewers: bogner, zturner, labath, dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D50716
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339802
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Thomas Lively [Wed, 15 Aug 2018 18:15:18 +0000 (18:15 +0000)]
[WebAssembly][NFC] Standardize SIMD multiclass format
Summary:
This CL changes the ExtractLane ISEL multiclass to more closely mirror
the structure of the splat and replace_lane multiclasses.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D50794
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339801
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Peter Collingbourne [Wed, 15 Aug 2018 17:58:22 +0000 (17:58 +0000)]
llvm-readobj: Fix addend in relocations for android packed format
If a relocation group doesn't have the RELOCATION_GROUP_HAS_ADDEND_FLAG set, then this implies the group's addend equals zero.
In this case android packed format won't encode an explicit addend delta, instead we need to set Addend, the "previous addend" variable, to zero by ourself.
Patch by Yi-Yo Chiang!
Differential Revision: https://reviews.llvm.org/D50601
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339799
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Thomas Lively [Wed, 15 Aug 2018 17:50:22 +0000 (17:50 +0000)]
[WebAssembly] Test commit
Changes a comment and some whitespace to test commit access.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339798
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Amara Emerson [Wed, 15 Aug 2018 17:46:22 +0000 (17:46 +0000)]
[InstCombine] Fix IC trying to create a xor of pointer types.
rdar://
42473741
Differential Revision: https://reviews.llvm.org/D50775
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339796
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Alina Sbirlea [Wed, 15 Aug 2018 17:34:55 +0000 (17:34 +0000)]
[MemorySSA] Expose the verify as a debug option.
Summary: Expose VerifyMemorySSA as a debug option. If set, passes will call the MSSA->verifyMemorySSA() after calling into the updater's APIs when MemorySSA should be valid.
Reviewers: george.burgess.iv
Subscribers: sanjoy, jlebar, Prazek, llvm-commits
Differential Revision: https://reviews.llvm.org/D50749
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339795
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Sanjay Patel [Wed, 15 Aug 2018 17:06:21 +0000 (17:06 +0000)]
[AArch64] add tests for poor vector intrinsic lowering via legalization (PR38527); NFC
These correspond to the x86 tests added with rL339790 / rL339791, but I widened
the non-fsin tests to v3f32 to show the problem because AArch supports v2f32 ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339793
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Krzysztof Parzyszek [Wed, 15 Aug 2018 17:04:58 +0000 (17:04 +0000)]
[RegisterCoalescer] Ensure that both registers have subranges if one does
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339792
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Sanjay Patel [Wed, 15 Aug 2018 16:56:09 +0000 (16:56 +0000)]
[x86] add fabs test for vector intrinsic to potential libcall bug; NFC
This is a negative test for x86 because it has custom lowering for fabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339791
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Sanjay Patel [Wed, 15 Aug 2018 16:35:50 +0000 (16:35 +0000)]
[x86] add tests for poor vector intrinsic lowering via legalization (PR38527); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339790
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Krzysztof Parzyszek [Wed, 15 Aug 2018 16:21:53 +0000 (16:21 +0000)]
[RegisterCoalescer] Reset VNInfo def when copying segments over
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339788
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Derek Schuff [Wed, 15 Aug 2018 16:18:51 +0000 (16:18 +0000)]
[WebAssembly] SIMD replace_lane
Implement and test replace_lane instructions.
Patch by Thomas Lively
Differential Revision: https://reviews.llvm.org/D50750
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339786
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Krzysztof Parzyszek [Wed, 15 Aug 2018 16:07:47 +0000 (16:07 +0000)]
[RegAlloc] Check that subreg liveness tracking applies to given virtual reg
Subregister liveness applies selectively to register classes with certain
properties. Make sure that when it's enabled, it applies to a given virtual
register (in virtual register rewriter).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339784
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Krzysztof Parzyszek [Wed, 15 Aug 2018 15:43:13 +0000 (15:43 +0000)]
[SystemZ] Add testcase for r339778
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339780
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Nemanja Ivanovic [Wed, 15 Aug 2018 15:30:36 +0000 (15:30 +0000)]
[PowerPC] Enhance the selection(ISD::VSELECT) of vector type
To make ISD::VSELECT available(legal) so long as there are altivec instruction,
otherwise it's default behavior is expanding.
Use xxsel to match vselect if vsx is open, or use vsel.
In order to do not write many patterns in td file, promote (for vector it's
bitcast) all other type into v4i32 and only pattern match vselect of v4i32 into
vsel or xxsel.
Patch by wuzish
Differential revision: https://reviews.llvm.org/D49531
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339779
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Krzysztof Parzyszek [Wed, 15 Aug 2018 15:21:23 +0000 (15:21 +0000)]
[SystemZ] Replace subreg_r with subreg_h
Change
subreg_r32 -> subreg_h32
subreg_r64 -> subreg_h64
subreg_hr32 -> subreg_hh32
The subregisters subreg_r32 and subreg_r64 were added to emphasize the
fact that modifying these subregisters may clobber the entire register.
This is not necessarily the case for subreg_h32, et al.
However, the ability to compose subreg_h64 with subreg_r32, and with
subreg_h32 and subreg_l32 at the same time makes the compositions be
treated as non-overlapping (leading to problems when tracking subreg
liveness). See D50468 for more details.
Differential Revision: https://reviews.llvm.org/D50725
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339778
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Marcello Maggioni [Wed, 15 Aug 2018 15:06:53 +0000 (15:06 +0000)]
[GVN] Fix typo in IsValueFullyAvailableInBlock. NFC.
DenseMap insert() method return a pair<iterator, bool>
not pair<iterator, char>
Noticed it and thought I might just fix it ...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339777
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Jonas Paulsson [Wed, 15 Aug 2018 15:04:49 +0000 (15:04 +0000)]
[SystemZ] New CL option to enable subreg liveness
This option is needed to enable subreg liveness tracking during register
allocation.
Review: Ulrich Weigand
https://reviews.llvm.org/D50779
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339776
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Chijun Sima [Wed, 15 Aug 2018 13:56:21 +0000 (13:56 +0000)]
[SimplifyCFG] Remove pointer from SmallPtrSet before deletion
Summary:
Previously, `eraseFromParent()` calls `delete` which invalidates the value of the pointer. Copying the value of the pointer later is undefined behavior in C++11 and implementation-defined (which may cause a segfault on implementations having strict pointer safety) in C++14.
This patch removes the BasicBlock pointer from related SmallPtrSet before `delete` invalidates it in the SimplifyCFG pass.
Reviewers: kuhar, dmgreen, davide, trentxintong
Reviewed By: kuhar, dmgreen
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D50717
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339773
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George Rimar [Wed, 15 Aug 2018 13:55:22 +0000 (13:55 +0000)]
[yaml2obj] - Teach yaml2obj to produce SHT_GROUP section with a custom Info field.
This allows to set custom Info field value for SHT_GROUP sections.
It is useful to allow this because we would be able to replace at least one binary
object committed in LLD and replace it with the yaml2obj based test.
Differential revision: https://reviews.llvm.org/D50776
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339772
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Sam Parker [Wed, 15 Aug 2018 13:29:50 +0000 (13:29 +0000)]
[ARM] TypeSize lower bound for ARMCodeGenPrepare
We only try to promote types with are smaller than 16-bits, but we
also need to check that the type is not less than 8-bits.
Differential Revision: https://reviews.llvm.org/D50769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339770
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Nemanja Ivanovic [Wed, 15 Aug 2018 12:58:13 +0000 (12:58 +0000)]
[PowerPC] Don't run BV DAG Combine before legalization if it assumes legal types
When trying to combine a DAG that builds a vector out of sign-extensions of
vector extracts, the code assumes legal input types. Due to that, we have to
disable this combine prior to legalization.
In some cases, the DAG will look slightly different after legalization so
account for that in the matching code.
This is a fix for https://bugs.llvm.org/show_bug.cgi?id=38087
Differential Revision: https://reviews.llvm.org/D49080
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339769
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Andrea Di Biagio [Wed, 15 Aug 2018 12:53:38 +0000 (12:53 +0000)]
[llvm-mca] Fix PR38575: Avoid an invalid implicit truncation of a processor resource mask (an uint64_t value) to unsigned.
This patch fixes a regression introduced at revision 338702.
A processor resource mask was incorrectly implicitly truncated to an unsigned
quantity. Later on, the truncated mask was used to initialize an element of a
vector of processor resource descriptors.
On targets with more than 32 processor resources, some elements of the vector
are left uninitialized. As a consequence, this bug might have eventually caused
a crash due to null dereference in the Scheduler.
This patch fixes PR38575, and adds a test for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339768
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Simon Pilgrim [Wed, 15 Aug 2018 12:32:09 +0000 (12:32 +0000)]
Remove lambda default argument to fix gcc pedantic warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339767
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George Rimar [Wed, 15 Aug 2018 11:43:00 +0000 (11:43 +0000)]
[yaml2obj] - Teach tool to produce SHT_GROUP section with a custom type.
Currently, it is possible to use yaml2obj for producing SHT_GROUP sections
of type GRP_COMDAT. For LLD test case I need to produce an object with
a broken (different from GRP_COMDAT) type.
The patch teaches tool to do such things.
Differential revision: https://reviews.llvm.org/D50761
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339764
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Simon Pilgrim [Wed, 15 Aug 2018 11:11:05 +0000 (11:11 +0000)]
[TargetLowering] Minor cleanup of TargetLowering::BuildSDIV. NFCI.
Pull out some types to match layout in TargetLowering::BuildUDIV. Early step towards adding non-uniform vector support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339763
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David Green [Wed, 15 Aug 2018 10:59:41 +0000 (10:59 +0000)]
[UnJ] Rename hasInvariantIterationCount to hasIterationCountInvariantInParent NFC
This hopefully describes the API of the function more precisely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339762
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Simon Pilgrim [Wed, 15 Aug 2018 10:59:29 +0000 (10:59 +0000)]
[X86][SSE] Add sdiv by nonuniform constant vector tests
Tests cover each TargetLowering::BuildSDIV path separately plus combos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339761
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Aleksandr Urakov [Wed, 15 Aug 2018 10:54:06 +0000 (10:54 +0000)]
[X86] Add sibling-call test cases
This commit adds new sibling-call test cases, so it will be possible to see
how these test cases will be changed after applying D45653.
See D45653 for details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339760
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Simon Pilgrim [Wed, 15 Aug 2018 10:11:13 +0000 (10:11 +0000)]
[TargetLowering] Minor refactor to TargetLowering::BuildUDIV to merge scalar/vector magic value collection. NFCI.
Use the same ISD::matchUnaryPredicate pattern that was used in D50392.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339758
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Simon Pilgrim [Wed, 15 Aug 2018 10:02:54 +0000 (10:02 +0000)]
[DagCombiner] Don't bother adding to the work list if TLI.BuildSDIVPow2 failed. NFCI.
Matches the code in BuildSDIV/BuildUDIV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339757
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Simon Pilgrim [Wed, 15 Aug 2018 09:35:12 +0000 (09:35 +0000)]
[TargetLowering] Add support for non-uniform vectors to BuildExactSDIV
This patch refactors the existing BuildExactSDIV implementation to support non-uniform constant vector denominators.
Differential Revision: https://reviews.llvm.org/D50392
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339756
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Sam Parker [Wed, 15 Aug 2018 08:23:03 +0000 (08:23 +0000)]
[ARM] Allow signed icmps in ARMCodeGenPrepare
Treat signed icmps as 'sinks', allowing them to be in the use-def
tree, enabling more promotions to be performed. As a sink, any
promoted incoming values need to be truncated before being used by
the signed icmp.
Differential Revision: https://reviews.llvm.org/D50067
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339755
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Sam Parker [Wed, 15 Aug 2018 07:52:35 +0000 (07:52 +0000)]
[ARM] Allow pointer values in ARMCodeGenPrepare
Add pointers to the list of allowed types, but don't try to promote
them. Also fixed a bug with the promotion of undef values, so a new
value is now created instead of mutating in place. We also now only
promote if there's an instruction in the use-def chains other than
the icmp, sinks and sources.
Differential Revision: https://reviews.llvm.org/D50054
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339754
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Max Kazantsev [Wed, 15 Aug 2018 06:21:02 +0000 (06:21 +0000)]
[AliasSetTracker] Do not treat experimental_guard intrinsic as memory writing instruction
The `experimental_guard` intrinsic has memory write semantics to model the thread-exiting
logic, but does not do any actual writes to memory. Currently, `AliasSetTracker` treats it as a
normal memory write. As result, a loop-invariant load cannot be hoisted out of loop because
the guard may possibly alias with it.
This patch makes `AliasSetTracker` so that it doesn't treat guards as memory writes.
Differential Revision: https://reviews.llvm.org/D50497
Reviewed By: reames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339753
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Max Kazantsev [Wed, 15 Aug 2018 05:55:43 +0000 (05:55 +0000)]
[NFC] Refactoring of LoopSafetyInfo, step 1
Turn structure into class, encapsulate methods, add clarifying comments.
Differential Revision: https://reviews.llvm.org/D50693
Reviewed By: reames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339752
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Max Kazantsev [Wed, 15 Aug 2018 05:50:38 +0000 (05:50 +0000)]
[NFC] Add sanitizing assertion to ICF tracker
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339751
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Max Kazantsev [Wed, 15 Aug 2018 02:49:12 +0000 (02:49 +0000)]
[NFC][LICM] Make hoist method void
Method hoist always returns true. This patch makes it void.
Differential Revision: https://reviews.llvm.org/D50696
Reviewed By: hiraditya
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339750
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Craig Topper [Wed, 15 Aug 2018 01:23:00 +0000 (01:23 +0000)]
[X86] Change legacy SSE scalar fp to integer intrinsics to use specific ISD opcodes instead of keeping as intrinsics. Unify SSE and AVX512 isel patterns.
AVX512 added new versions of these intrinsics that take a rounding mode. If the rounding mode is 4 the new intrinsics are equivalent to the old intrinsics.
The AVX512 intrinsics were being lowered to ISD opcodes, but the legacy SSE intrinsics were left as intrinsics. This resulted in the AVX512 instructions needing separate patterns for the ISD opcodes and the legacy SSE intrinsics.
Now we convert SSE intrinsics and AVX512 intrinsics with rounding mode 4 to the same ISD opcode so we can share the isel patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339749
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Chandler Carruth [Wed, 15 Aug 2018 01:22:50 +0000 (01:22 +0000)]
[SDAG] Update the AVR backend for the SelectionDAG API changes in
r339740, fixing the build for this target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339748
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Evgeniy Stepanov [Wed, 15 Aug 2018 00:39:35 +0000 (00:39 +0000)]
[hwasan] Add a basic API.
Summary:
Add user tag manipulation functions:
__hwasan_tag_memory
__hwasan_tag_pointer
__hwasan_print_shadow (very simple and ugly, for now)
Reviewers: vitalybuka, kcc
Subscribers: kubamracek, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D50746
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339746
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Derek Schuff [Wed, 15 Aug 2018 00:30:27 +0000 (00:30 +0000)]
[WebAssembly] SIMD Splats
Implement and test SIMD splat ops.
Patch by Thomas Lively
Differential Revision: https://reviews.llvm.org/D50741
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339744
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Chandler Carruth [Tue, 14 Aug 2018 23:30:32 +0000 (23:30 +0000)]
[SDAG] Remove the reliance on MI's allocation strategy for
`MachineMemOperand` pointers attached to `MachineSDNodes` and instead
have the `SelectionDAG` fully manage the memory for this array.
Prior to this change, the memory management was deeply confusing here --
The way the MI was built relied on the `SelectionDAG` allocating memory
for these arrays of pointers using the `MachineFunction`'s allocator so
that the raw pointer to the array could be blindly copied into an
eventual `MachineInstr`. This creates a hard coupling between how
`MachineInstr`s allocate their array of `MachineMemOperand` pointers and
how the `MachineSDNode` does.
This change is motivated in large part by a change I am making to how
`MachineFunction` allocates these pointers, but it seems like a layering
improvement as well.
This would run the risk of increasing allocations overall, but I've
implemented an optimization that should avoid that by storing a single
`MachineMemOperand` pointer directly instead of allocating anything.
This is expected to be a net win because the vast majority of uses of
these only need a single pointer.
As a side-effect, this makes the API for updating a `MachineSDNode` and
a `MachineInstr` reasonably different which seems nice to avoid
unexpected coupling of these two layers. We can map between them, but we
shouldn't be *surprised* at where that occurs. =]
Differential Revision: https://reviews.llvm.org/D50680
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339740
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Heejin Ahn [Tue, 14 Aug 2018 22:14:51 +0000 (22:14 +0000)]
[WebAssembly] Delete a specific push number from test expectations
Summary:
This shouldn't have been a specific number but rather a regex. This was
a part of rL339474 which got reverted.
Reviewers: aardappel
Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D50728
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339736
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Cameron McInally [Tue, 14 Aug 2018 22:13:11 +0000 (22:13 +0000)]
[FPEnv] Scalarize StrictFP vector operations
Add a helper function to scalarize constrained FP operations as needed.
Differential Revision: https://reviews.llvm.org/D50720
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339735
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Eli Friedman [Tue, 14 Aug 2018 22:10:25 +0000 (22:10 +0000)]
[ARM] Make PerformSHLSimplify add nodes to the DAG worklist correctly.
Intentionally excluding nodes from the DAGCombine worklist is likely to
lead to weird optimizations and infinite loops, so it's generally a bad
idea.
To avoid the infinite loops, fix DAGCombine to use the
isDesirableToCommuteWithShift target hook before performing the
transforms in question, and implement the target hook in the ARM backend
disable the transforms in question.
Fixes https://bugs.llvm.org/show_bug.cgi?id=38530 . (I don't have a
reduced testcase for that bug. But we should have sufficient test
coverage for PerformSHLSimplify given that we're not playing weird
tricks with the worklist. I can try to bugpoint it if necessary,
though.)
Differential Revision: https://reviews.llvm.org/D50667
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339734
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Matt Morehouse [Tue, 14 Aug 2018 22:04:34 +0000 (22:04 +0000)]
[SanitizerCoverage] Add associated metadata to PC guards.
Summary:
Without this metadata LLD strips unused PC table entries
but won't strip unused guards. This metadata also seems
to influence the linker to change the ordering in the PC
guard section to match that of the PC table section.
The libFuzzer runtime library depends on the ordering
of the PC table and PC guard sections being the same. This
is not generally guaranteed, so we may need to redesign
PC tables/guards/counters in the future.
Reviewers: eugenis
Reviewed By: eugenis
Subscribers: kcc, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D50483
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339733
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Stephen Kelly [Tue, 14 Aug 2018 21:25:49 +0000 (21:25 +0000)]
Remove vestiges of configure buildsystem
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D50528
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339729
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Alina Sbirlea [Tue, 14 Aug 2018 20:49:19 +0000 (20:49 +0000)]
Add proper headers in CFGUpdate.h and add CFGDiff.h in the list of delayed headers for LLVM_intrinsic_gen.
Summary:
Fix module build after r339694.
Add headers needed in CFGUpdate.h.
Add CFGDiff.h in the list of delayed headers for LLVM_intrinsic_gen.
Up for post-commit review.
Subscribers: sanjoy, jlebar, llvm-commits
Differential Revision: https://reviews.llvm.org/D50734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339724
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Anna Thomas [Tue, 14 Aug 2018 20:25:13 +0000 (20:25 +0000)]
NFC: Clarify comment in loop vectorization legality
Clarifying the comment about PSCEV and external IV users by referencing
the bug in question.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339722
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Adrian Prantl [Tue, 14 Aug 2018 19:35:34 +0000 (19:35 +0000)]
[DebugInfoMetadata] Added DIFlags interface in DIBasicType.
Flags in DIBasicType will be used to pass attributes used in
DW_TAG_base_type, such as DW_AT_endianity.
Patch by Chirag Patel!
Differential Revision: https://reviews.llvm.org/D49610
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339714
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Sanjay Patel [Tue, 14 Aug 2018 19:13:07 +0000 (19:13 +0000)]
[InstCombine] fix typos in tests; NFC
See D50036.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339713
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Heejin Ahn [Tue, 14 Aug 2018 19:10:50 +0000 (19:10 +0000)]
[WebAssembly] SIMD encoding tests
Modifies existing SIMD tests to also check that SIMD instructions are
lowered to the expected bytes. This CL depends on D50597.
Reviewers: aheejin
Subscribers: sunfish, jgravelle-google, sbc100, llvm-commits
Differential Revision: https://reviews.llvm.org/D50660
Patch by Thomas Lively (tlively)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339712
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Sanjay Patel [Tue, 14 Aug 2018 19:05:37 +0000 (19:05 +0000)]
[InstCombine] add tests for pow->sqrt; NFC
D50036 should fix the missed optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339711
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Heejin Ahn [Tue, 14 Aug 2018 19:03:36 +0000 (19:03 +0000)]
[WebAssembly] Fix encoding of non-SIMD vector-typed instructions
Previously SIMD_I was the same as a normal instruction except for the
addition of a HasSIM128 predicate. However, rL339186 changed the
encoding of SIMD_I instructions to automatically contain the SIMD
prefix byte. This broke the encoding of non-SIMD vector-typed
instructions, which had instantiated SIMD_I. This CL corrects this
error.
Reviewers: aheejin
Subscribers: sunfish, jgravelle-google, sbc100, llvm-commits
Differential Revision: https://reviews.llvm.org/D50682
Patch by Thomas Lively (tlively)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339710
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Zachary Turner [Tue, 14 Aug 2018 18:54:28 +0000 (18:54 +0000)]
[MS Demangler] Fix some minor formatting bugs.
1) We print __restrict twice on member pointers. This is fixed
and relevant tests are re-enabled.
2) Several tests were disabled because of printing slightly
different output than undname. These were confirmed to be
bugs in undname, so we just re-enable the tests.
3) The test for printing reference temporaries is re-enabled. This
is a clang mangling extension, so we have some flexibility with
how we demangle it. The output currently looks fine, so we just
re-enable the test with no fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339708
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Heejin Ahn [Tue, 14 Aug 2018 18:53:27 +0000 (18:53 +0000)]
[WebAssembly] SIMD extract_lane
Implement instruction selection for all versions of the extract_lane
instruction. Use explicit sext/zext to differentiate between
extract_lane_s and extract_lane_u for applicable types, otherwise
default to extract_lane_u.
Reviewers: aheejin
Subscribers: sunfish, jgravelle-google, sbc100, llvm-commits
Differential Revision: https://reviews.llvm.org/D50597
Patch by Thomas Lively (tlively)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339707
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Andrea Di Biagio [Tue, 14 Aug 2018 18:36:54 +0000 (18:36 +0000)]
[Tablegen][MCInstPredicate] Removed redundant template argument from class TIIPredicate, and implemented verification rules for TIIPredicates.
This patch removes redundant template argument `TargetName` from TIIPredicate.
Tablegen can always infer the target name from the context. So we don't need to
force users of TIIPredicate to always specify it.
This allows us to better modularize the tablegen class hierarchy for the
so-called "function predicates". class FunctionPredicateBase has been added; it
is currently used as a building block for TIIPredicates. However, I plan to
reuse that class to model other function predicate classes too (i.e. not just
TIIPredicates). For example, this can be a first step towards implementing
proper support for dependency breaking instructions in tablegen.
This patch also adds a verification step on TIIPredicates in tablegen.
We cannot have multiple TIIPredicates with the same name. Otherwise, this will
cause build errors later on, when tablegen'd .inc files are included by cpp
files and then compiled.
Differential Revision: https://reviews.llvm.org/D50708
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339706
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Anna Thomas [Tue, 14 Aug 2018 18:22:19 +0000 (18:22 +0000)]
[LV] Teach about non header phis that have uses outside the loop
Summary:
This patch teaches the loop vectorizer to vectorize loops with non
header phis that have have outside uses. This is because the iteration
dependence distance for these phis can be widened upto VF (similar to
how we do for induction/reduction) if they do not have a cyclic
dependence with header phis. When identifying reduction/induction/first
order recurrence header phis, we already identify if there are any cyclic
dependencies that prevents vectorization.
The vectorizer is taught to extract the last element from the vectorized
phi and update the scalar loop exit block phi to contain this extracted
element from the vector loop.
This patch can be extended to vectorize loops where instructions other
than phis have outside uses.
Reviewers: Ayal, mkuper, mssimpso, efriedma
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D50579
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339703
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Bruno Cardoso Lopes [Tue, 14 Aug 2018 17:54:41 +0000 (17:54 +0000)]
Revert "[DebugInfo] Generate DWARF debug information for labels. (Fix leak problems)"
This reverts commit
cb8c5e417d55141f3f079a8a876e786f44308336 / r339676.
This causing a test to fail in http://green.lab.llvm.org/green/job/clang-stage1-configure-RA/48406/
LLVM :: DebugInfo/Generic/debug-label.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339700
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Alina Sbirlea [Tue, 14 Aug 2018 17:43:24 +0000 (17:43 +0000)]
[GraphDiff] Make InverseGraph a property of a GraphDiff.
Summary:
Treating a graph in reverse is a property of the GraphDiff and should instead be a template argument, just like IsPostDom is one for DomTrees.
If it's just an argument to all methods, we could have mismatches between the constructor of the GraphDiff which may reverse the updates when filtering them, and the calls retrieving the filtered delete/insert updates.
Also, since this will be used in IDF, where we're using a DomTree, this creates a cleaner interface for the GraphTraits to use the existing template argument of DomTreeBase.
Separate patch from the one adding GraphDiff, so get a clear diff of what changed.
Reviewers: timshen, kuhar
Subscribers: sanjoy, llvm-commits, jlebar
Differential Revision: https://reviews.llvm.org/D50687
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339699
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Simon Pilgrim [Tue, 14 Aug 2018 17:22:37 +0000 (17:22 +0000)]
[X86][SSE] Avoid duplicate shuffle input sources in combineX86ShufflesRecursively
rL339686 added the case where a faux shuffle might have repeated shuffle inputs coming from either side of the OR().
This patch improves the insertion of the inputs into the source ops lists to account for this, as well as making it trivial to add support for shuffles with more than 2 inputs in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339696
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Alina Sbirlea [Tue, 14 Aug 2018 17:12:30 +0000 (17:12 +0000)]
[DomTree] Cleanup Update and LegalizeUpdate API moved to Support header.
Summary:
Clean-up following D50479.
Make Update and LegalizeUpdate refer to the utilities in Support/CFGUpdate.
Reviewers: kuhar
Subscribers: sanjoy, jlebar, mgrang, llvm-commits
Differential Revision: https://reviews.llvm.org/D50669
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339694
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David Bolvansky [Tue, 14 Aug 2018 17:03:47 +0000 (17:03 +0000)]
[NFC] Tests for select with binop fold - FP opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339692
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Alina Sbirlea [Tue, 14 Aug 2018 16:44:28 +0000 (16:44 +0000)]
Expose CFG Update struct. Define GraphTraits to get children given a snapshot CFG.
Summary:
Certain passes or analysis need to view a CFG snapshot rather than the actual CFG. This patch provides GraphTraits to offer such a view.
The patch defines GraphTraits for BasicBlock* and Inverse<BasicBlock*> to provide CFG successors and predecessors based on a list of CFG updates.
An Update is defined as a triple {InsertOrDeleteKind, BlockStartOfEdge, BlockEndOfEdge}.
A GraphDiff is defined as a list of Updates that has been preprocessed to treat the CFG as a graph rather than a multi-graph. As such, there can only exist a single Update given two nodes. All duplicates will be filtered and Insert/Delete edges that cancel out will be ignored.
The methods GraphDiff exposes are:
- Determine if an existing child needs to be ignored, i.e. an Update exists in the correct direction to assume the removal of that edge.
- Return a list of new children to be considered, i.e. an Update exists in the correct direction for each child in the list to assume the insertion of that edge.
Reviewers: timshen, kuhar, chandlerc
Subscribers: sanjoy, jlebar, llvm-commits
Differential Revision: https://reviews.llvm.org/D50479
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339689
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Nirav Dave [Tue, 14 Aug 2018 16:20:43 +0000 (16:20 +0000)]
[DAG] Avoid redundant chain transversal in store merge cycle check. NFCI.
Patch by Henric Karlsson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339688
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Simon Pilgrim [Tue, 14 Aug 2018 16:00:05 +0000 (16:00 +0000)]
[X86][SSE] Add shuffle combine support for OR(PSHUFB,PSHUFB) style patterns.
If each element is zero from one (or both) inputs then we can combine these into a single shuffle mask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339686
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Simon Pilgrim [Tue, 14 Aug 2018 15:21:26 +0000 (15:21 +0000)]
[X86][SSE] Add shuffle combine tests for OR(PSHUFB,PSHUFB) style patterns.
We generate these shuffle patterns but we fail to combine them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339684
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Sanjay Patel [Tue, 14 Aug 2018 15:21:13 +0000 (15:21 +0000)]
[InstCombine] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339683
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Fedor Sergeev [Tue, 14 Aug 2018 15:19:14 +0000 (15:19 +0000)]
[Inliner] add inliner stats to new pm version of inliner
Increment existing NumInlined and NumDeleted stats in InlinerPass::run.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339682
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Sanjay Patel [Tue, 14 Aug 2018 15:18:52 +0000 (15:18 +0000)]
[InstCombine] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339681
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Simon Pilgrim [Tue, 14 Aug 2018 14:00:14 +0000 (14:00 +0000)]
[X86][SSE] Generalize lowerVectorShuffleAsBlendOfPSHUFBs to work with any vXi8 type.
We still only use this for v16i8, but this cleans up the code to support v32i8/v64i8 sometime in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339679
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Hsiangkai Wang [Tue, 14 Aug 2018 13:50:59 +0000 (13:50 +0000)]
[DebugInfo] Generate DWARF debug information for labels. (Fix leak problems)
There are two forms for label debug information in DWARF format.
1. Labels in a non-inlined function:
DW_TAG_label
DW_AT_name
DW_AT_decl_file
DW_AT_decl_line
DW_AT_low_pc
2. Labels in an inlined function:
DW_TAG_label
DW_AT_abstract_origin
DW_AT_low_pc
We will collect label information from DBG_LABEL. Before every DBG_LABEL,
we will generate a temporary symbol to denote the location of the label.
The symbol could be used to get DW_AT_low_pc afterwards. So, we create a
mapping between 'inlined label' and DBG_LABEL MachineInstr in DebugHandlerBase.
The DBG_LABEL in the mapping is used to query the symbol before it.
The AbstractLabels in DwarfCompileUnit is used to process labels in inlined
functions.
We also keep a mapping between scope and labels in DwarfFile to help to
generate correct tree structure of DIEs.
It also generates label debug information under global isel.
Differential Revision: https://reviews.llvm.org/D45556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339676
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