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Alexandre Belloni [Thu, 20 Dec 2018 14:44:31 +0000 (15:44 +0100)]
pinctrl: ocelot: add MSCC Jaguar2 support
Jaguar2 has the same register layout as Ocelot but it has 64 pins, meaning
that there are 2 registers instead of one.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Rafał Miłecki [Tue, 18 Dec 2018 15:58:08 +0000 (16:58 +0100)]
pinctrl: bcm: ns: support updated DT binding as syscon subnode
Documentation has been recently updated specifying that pinctrl should
be subnode of the CRU "syscon". Support that by using parent node for
regmap and reading "offset" property from the DT.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Rafał Miłecki [Tue, 18 Dec 2018 15:57:44 +0000 (16:57 +0100)]
dt-bindings: pinctrl: bcm4708-pinmux: rework binding to use syscon
As pointed by Rob, CRU is a kind of block that can't be guaranteed to
have everything exposed as subnodes. It's a set of various registers
that aren't tied to any single device. It could be described much more
accurately as MFD (Multi-Function Device).
Some hardware blocks may indeed want to access a register or two of the
CRU which requires describing it as the "syscon".
While at it replace exmple node name with the standard "pinctrl" (also
pointed out by Rob).
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Ludovic Desroches [Thu, 8 Nov 2018 13:14:42 +0000 (14:14 +0100)]
MAINTAINERS: merge at91 pinctrl entries
In order to be aware of all changes related to at91 pinctrl drivers,
merge the two entries. Make use of the opportunity to replace Atmel by
Microchip.
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Aisheng Dong [Mon, 17 Dec 2018 15:38:15 +0000 (15:38 +0000)]
pinctrl: imx8qxp: break the dependency on SOC_IMX8QXP
ARM64 SoC does not encourage people to add more finegrained SoC
config options rather than a single ARCH_<family> in arch Kconfig.
So this patch aims to break the dependency on SOC_IMX8QXP.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Masahiro Yamada [Fri, 14 Dec 2018 08:44:46 +0000 (17:44 +0900)]
pinctrl: uniphier: constify uniphier_pinctrl_socdata
These are constant data.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Ryder Lee [Thu, 13 Dec 2018 02:27:50 +0000 (10:27 +0800)]
pinctrl: mediatek: improve Kconfig dependencies
Remove prompts to make all pinctrl cores to non-visible symbols and
make sure the target SoCs would be coupled with the corresponding
cores.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com
Acked-by: Sean Wang <sean.wang@kernel.org>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Arnd Bergmann [Mon, 10 Dec 2018 20:59:45 +0000 (21:59 +0100)]
pinctrl: msm: mark PM functions as __maybe_unused
Without CONFIG_PM_SLEEP, we get annoying warnings about unused functions:
drivers/pinctrl/qcom/pinctrl-msm.c:1082:12: error: 'msm_pinctrl_resume' defined but not used [-Werror=unused-function]
static int msm_pinctrl_resume(struct device *dev)
^~~~~~~~~~~~~~~~~~
drivers/pinctrl/qcom/pinctrl-msm.c:1075:12: error: 'msm_pinctrl_suspend' defined but not used [-Werror=unused-function]
static int msm_pinctrl_suspend(struct device *dev)
Mark them as __maybe_unused to shut up the warning and silently drop
the functions without having to add ugly #ifdefs.
Fixes:
977d057ad346 ("pinctrl: msm: Add sleep pinctrl state transitions")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Evan Green <evgreen@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Maxime Ripard [Mon, 17 Dec 2018 13:16:26 +0000 (14:16 +0100)]
dt-bindings: pinctrl: sunxi: Add supply properties
The pinctrl node can have multiple regulators for each of its GPIO banks.
Add the property descriptions.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Martin Blumenstingl [Sun, 9 Dec 2018 19:50:55 +0000 (20:50 +0100)]
pinctrl: meson: meson8b: add the missing GPIO_GROUPs for BOOT and CARD
Add the BOOT and CARD pins as GROUP_GROUPs as well so they can be
configured in devicetree using groups = BOOTx or groups = CARDx. This
makes the behavior consistent with other pins inside the same driver as
well as with the BOOT and CARD pins of the GXBB and GXL pinctrl drivers.
Fixes:
0fefcb6876d0d6 ("pinctrl: Add support for Meson8b")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Martin Blumenstingl [Sun, 9 Dec 2018 19:50:54 +0000 (20:50 +0100)]
pinctrl: meson: meson8: add the missing GPIO_GROUPs for BOOT and CARD
Add the BOOT and CARD pins as GROUP_GROUPs as well so they can be
configured in devicetree using groups = BOOTx or groups = CARDx. This
makes the behavior consistent with other pins inside the same driver as
well as with the BOOT and CARD pins of the GXBB and GXL pinctrl drivers.
Fixes:
6ac730951104a4 ("pinctrl: add driver for Amlogic Meson SoCs")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Martin Blumenstingl [Sun, 9 Dec 2018 19:50:52 +0000 (20:50 +0100)]
pinctrl: meson: meson8: rename the "gpio" function to "gpio_periphs"
Rename the existing "gpio" function to "gpio_periphs". This makes it
consistent with the "gpio_aobus" function. Also GXBB and GXL are also
using the "gpio_periphs" naming, so this makes the code here consistent
with other Amlogic pinctrl drivers.
No functional changes since thee "gpio" function is currently not used.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Martin Blumenstingl [Sun, 9 Dec 2018 19:50:53 +0000 (20:50 +0100)]
pinctrl: meson: meson8: rename the "gpio" function to "gpio_periphs"
Rename the existing "gpio" function to "gpio_periphs". This makes it
consistent with the "gpio_aobus" function. Also GXBB and GXL are also
using the "gpio_periphs" naming, so this makes the code here consistent
with other Amlogic pinctrl drivers.
No functional changes since thee "gpio" function is currently not used.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Martin Blumenstingl [Sun, 9 Dec 2018 19:50:51 +0000 (20:50 +0100)]
pinctrl: meson: meson8b: fix the GPIO function for the GPIOAO pins
The GPIOAO pins (as well as the two exotic GPIO_BSD_EN and GPIO_TEST_N)
only belong to the pin controller in the AO domain. With the current
definition these pins cannot be referred to in .dts files as group
(which is possible on GXBB and GXL for example).
Add a separate "gpio_aobus" function to fix the mapping between the pin
controller and the GPIO pins in the AO domain. This is similar to how
the GXBB and GXL drivers implement this functionality.
Fixes:
9dab1868ec0db4 ("pinctrl: amlogic: Make driver independent from two-domain configuration")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Martin Blumenstingl [Sun, 9 Dec 2018 19:50:50 +0000 (20:50 +0100)]
pinctrl: meson: meson8: fix the GPIO function for the GPIOAO pins
The GPIOAO pins (as well as the two exotic GPIO_BSD_EN and GPIO_TEST_N)
only belong to the pin controller in the AO domain. With the current
definition these pins cannot be referred to in .dts files as group
(which is possible on GXBB and GXL for example).
Add a separate "gpio_aobus" function to fix the mapping between the pin
controller and the GPIO pins in the AO domain. This is similar to how
the GXBB and GXL drivers implement this functionality.
Fixes:
9dab1868ec0db4 ("pinctrl: amlogic: Make driver independent from two-domain configuration")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Martin Schiller [Fri, 14 Dec 2018 07:48:25 +0000 (08:48 +0100)]
pinctrl: xway: fix gpio-hog related boot issues
This patch is based on commit
a86caa9ba5d7 ("pinctrl: msm: fix gpio-hog
related boot issues").
It fixes the issue that the gpio ranges needs to be defined before
gpiochip_add().
Therefore, we also have to swap the order of registering the pinctrl
driver and registering the gpio chip.
You also have to add the "gpio-ranges" property to the pinctrl device
node to get it finally working.
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
Acked-by: John Crispin <john@phrozen.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Nathan Chancellor [Tue, 11 Dec 2018 00:05:06 +0000 (17:05 -0700)]
pinctrl: aspeed: Wrap -Woverride-init with cc-option
Clang does not support this option:
warning: unknown warning option '-Woverride-init'; did you mean
'-Woverride-module'? [-Wunknown-warning-option]
1 warning generated.
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Maxime Ripard [Thu, 6 Dec 2018 14:02:03 +0000 (15:02 +0100)]
pinctrl: sunxi: Deal with per-bank regulators
The Allwinner SoCs have on most of their GPIO banks a regulator input.
This issue was mainly ignored so far because either the regulator was a
static regulator that would be providing power anyway, or the bank was used
for a feature unsupported so far (CSI). For the odd cases, enabling it in
the bootloader was the preferred option.
However, now that we are starting to support those features, and that we
can't really rely on the bootloader for this, we need to model those
regulators as such in the DT.
This is slightly more complicated than what it looks like, since some
regulators will be tied to the PMIC, and in order to have access to the
PMIC bus, you need to mux its pins, which will need the pinctrl driver,
that needs the regulator driver to be registered. And this is how you get a
circular dependency.
In practice however, the hardware cannot fall into this case since it would
result in a completely unusable bus. In order to avoid that circular
dependency, we can thus get and enable the regulators at pin_request time.
We'll then need to account for the references of all the pins of a
particular branch to know when to put the reference, but it works pretty
nicely once implemented.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Rob Herring [Wed, 5 Dec 2018 19:50:36 +0000 (13:50 -0600)]
pinctrl: Use of_node_name_eq for node name comparisons
Convert string compares of DT node names to use of_node_name_eq helper
instead. This removes direct access to the node name pointer.
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Tomasz Figa <tomasz.figa@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Thu, 13 Dec 2018 13:02:18 +0000 (14:02 +0100)]
Merge tag 'intel-pinctrl-v4.21-1' of git://git./linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v4.21-1
Switch to generic ->probe() callbacks.
Simplify getting .driver_data.
Code formatting fixes and headers clean up.
Special case is the driver for Intel Cherryview SoC, where GPIO enabling bit
was mistakenly cleared when pin gets freed. It's fixed now.
The below commit went to v4.20-rc3, that's why duplication.
-
ad774315c3765ffb27abb6db987a2121d871a942 MAINTAINERS: Add tree link for Intel pin control driver
The following is an automated git shortlog grouped by driver:
baytrail:
- Code formatting fixes
- simplify getting .driver_data
broxton:
- Code formatting fixes
- Get rid of unneeded ->probe() stub
cannonlake:
- Code formatting fixes
- Get rid of unneeded ->probe() stub
cedarfork:
- Replace acpi.h with mod_devicetable.h
- Get rid of unneeded ->probe() stub
cherryview:
- Stop clearing the GPIO_EN bit from chv_gpio_disable_free
- Add chv_gpio_clear_triggering() helper function
- simplify getting .driver_data
denverton:
- Replace acpi.h with mod_devicetable.h
- Get rid of unneeded ->probe() stub
geminilake:
- Code formatting fixes
icelake:
- Code formatting fixes
- Get rid of unneeded ->probe() stub
intel:
- Unexport intel_pinctrl_probe()
- simplify getting .driver_data
lewisburg:
- Replace acpi.h with mod_devicetable.h
- Get rid of unneeded ->probe() stub
MAINTAINERS:
- Add tree link for Intel pin control driver
merrifield:
- include bits.h instead of bitops.h
sunrisepoint:
- Get rid of unneeded ->probe() stub
Linus Walleij [Fri, 7 Dec 2018 12:42:35 +0000 (13:42 +0100)]
Merge tag 'sh-pfc-for-v4.21-tag2' of git://git./linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.21 (take two)
- Two small fixes for RZ/N1.
Masahiro Yamada [Wed, 5 Dec 2018 12:53:39 +0000 (21:53 +0900)]
pinctrl: uniphier: convert to SPDX License Identifier
checkpatch.pl suggests to use SPDX license tag. I am happy to
follow it.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Chen-Yu Tsai [Mon, 3 Dec 2018 15:41:00 +0000 (23:41 +0800)]
pinctrl: sunxi: a64: Rename function ts0 to ts
The A64 only has one TS (transport stream) controller. The datasheet
also lists the function as TS_XXX instead of TS0_XXX.
Rename the function names now before any there are any users.
Fixes:
96851d391d02 ("drivers: pinctrl: add driver for Allwinner A64 SoC")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Chen-Yu Tsai [Mon, 3 Dec 2018 15:40:59 +0000 (23:40 +0800)]
pinctrl: sunxi: a64: Rename function csi0 to csi
The A64 only has one CSI (camera sensor interface) controller. The
datasheet also lists the function as CSI_XXX instead of CSI0_XXX.
Rename the function names now before any there are any users.
Fixes:
96851d391d02 ("drivers: pinctrl: add driver for Allwinner A64 SoC")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Nicholas Mc Guire [Sun, 2 Dec 2018 10:04:17 +0000 (11:04 +0100)]
pinctrl: sx150x: handle failure case of devm_kstrdup
devm_kstrdup() may return NULL if internal allocation failed.
Thus using label, name is unsafe without checking. Therefor
in the unlikely case of allocation failure, sx150x_probe() simply
returns -ENOMEM.
Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org>
Fixes:
9e80f9064e73 ("pinctrl: Add SX150X GPIO Extender Pinctrl Driver")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Yangtao Li [Fri, 30 Nov 2018 16:36:17 +0000 (11:36 -0500)]
pinctrl: Change to use DEFINE_SHOW_ATTRIBUTE macro
Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code.
Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Nicholas Mc Guire [Fri, 23 Nov 2018 16:12:58 +0000 (17:12 +0100)]
pinctrl: nuvoton: check for devm_kasprintf() failure
devm_kasprintf() may return NULL on failure of internal allocation thus
the assignment to .label is not safe if not checked. On error
npcm7xx_gpio_of() returns negative values so -ENOMEM in the
(unlikely) failure case of devm_kasprintf() should be fine here.
Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org>
Fixes:
3b588e43ee5c ("pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Hans de Goede [Tue, 4 Dec 2018 19:42:47 +0000 (20:42 +0100)]
pinctrl: cherryview: Stop clearing the GPIO_EN bit from chv_gpio_disable_free
Clearing the GPIO_EN bit from chv_gpio_disable_free is a bad idea and
pinctrl-cherryview.c is the only Intel pinctrl driver doing something
like this.
Clearing the GPIO_EN bit means that if the pin was an output it is now
effectively floating. The datasheet is not clear what happens to pull ups /
downs in this case, but from testing it looks like these are disabled too,
also floating input pins.
One example where this is causing issues is the soc_button_array input
driver, this parses ACPI tables to create 2 platform devices for the
gpio_keys input driver. The list of GPIOs is passed through struct
gpio_keys_platform_data which uses gpio numbers rather then gpio_desc
pointers.
The buttons handled by this drivers short the pin to ground when pressed
and the volume buttons rely on the SoC's internal pull-up to pull the
pin high when the button is not pressed.
To get the gpio number, the soc_button_array code calls gpiod_get_index
followed by a desc_to_gpio call and then gpiod_put on the gpio_desc.
This last call causes chv_gpio_disable_free to clear the GPIO_EN bit.
When the gpio_keys driver then loads next it gets the gpio_desc again
causing the GPIO_EN bit to be set again and immediately reads the GPIO
value which for the volume buttons reads 0 at this time, causing a spurious
press of the volume buttons to get reported.
Putting a small delay between the gpio_desc request and the read fixes
this, I assume that this is caused by the pull-up being temporarily
disabled while the GPIO_EN bit is cleared as the powerbutton which also
has its GPIO_EN bit cleared does not have this problem.
The soc_button_array code is not the only code temporarily requesting GPIOs
the DWC3 PCI code also does this, to set the enable and reset GPIOs for the
external phy, so that the code instantiating the ULPI phy can read the
vendor and product ID registers from the phy. These GPIOs are released
after this so that the PHY driver can claim and use them when it loads.
Another example of temporary GPIO usage would be a user-space set_gpio
utility using the userspace ioctls to set a GPIO as output value 0 or 1,
having the GPIO revert to floating as soon as this utility exits would
certainly be unexpected behavior.
One argument in favor of clearing the GPIO_EN bit is if the GPIO is going
to be muxed to another function after being released, but in that case
chv_pinmux_set_mux() already clears it.
TL;DR: Clearing the GPIO_EN bit from is a bad idea, this commit therefor
removes the clearing from chv_gpio_disable_free(), replacing it with code
to clear the interrupt-trigger condition so that the GPIO stops generating
interrupts when released, as pinctrl-baytrail.c does.
Note this commit adds a !chv_pad_locked() condition to the trigger clearing
call, which the original GPIO_EN clearing code was missing.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Hans de Goede [Tue, 4 Dec 2018 19:42:46 +0000 (20:42 +0100)]
pinctrl: cherryview: Add chv_gpio_clear_triggering() helper function
This is a preparation patch for clearing the interrupt trigger from
chv_gpio_disable_free().
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Phil Edworthy [Fri, 23 Nov 2018 10:54:28 +0000 (10:54 +0000)]
pinctrl: rzn1: Fix of_get_child_count() error check
If we assign the result of of_get_child_count() to an unsigned int,
the code will not detect any errors. Therefore assign it to an int
instead.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Phil Edworthy [Fri, 23 Nov 2018 10:54:27 +0000 (10:54 +0000)]
pinctrl: rzn1: Fix check for used MDIO bus
This fixes the check for unused mdio bus setting and the following static
checker warning:
drivers/pinctrl/pinctrl-rzn1.c:198 rzn1_pinctrl_mdio_select()
warn: always true condition '(ipctl->mdio_func[mdio] >= 0) => (0-u32max >= 0)'
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Shawn Guo [Tue, 20 Nov 2018 05:45:22 +0000 (13:45 +0800)]
pinctrl: qcom: spmi-gpio: add compatible for pms405 GPIO
Let's add "qcom,pms405-gpio" to match table, as commit
ed80f6eb799a
("dt-bindings: pinctrl: qcom-pmic-gpio: Add pms405 support") already
adds the compatible.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Shawn Guo [Tue, 20 Nov 2018 05:45:21 +0000 (13:45 +0800)]
dt-bindings: pinctrl: fix qcom-pmic-gpio for pms405
Rather than gpio1-gpio11 for pms405, there are 12 GPIOs for pms405.
But gpio1, gpio9 and gpio10 are not available. Fix the bindings doc
to make it correct for pms405.
Fixes:
ed80f6eb799a ("dt-bindings: pinctrl: qcom-pmic-gpio: Add pms405 support")
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Sun, 25 Nov 2018 22:53:01 +0000 (23:53 +0100)]
Merge tag 'sh-pfc-for-v4.21-tag1' of git://git./linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.21
- Fix VIN (Video IN) versioned groups on R-Car V2H, H3, and M3-W,
- Add I2C[0-3], DU1, VIN, QSPI1, and SDHI pin groups on RZ/G1C,
- Add audio, SDHI, VIN, HSCIF, and CAN(FD) support on R-Car E3,
- Add QSPI pin groups on R-Car V3M and V3H,
- Add VIN and CAN(FD) pin groups on R-Car M3-N,
- Add I2C[035] pin groups on R-Car H3 and M3-W,
- Add pinctrl and GPIO support for the new RZ/A2M (R7S9210) SoC,
- Small cleanups,
- Maintainership updates.
Mesih Kilinc [Sun, 25 Nov 2018 07:43:14 +0000 (10:43 +0300)]
pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs)
The suniv F1C100s chip (several new F-series SoCs) of Allwinner has a
pin
controller like other SoCs from Allwinner.
Add support for it.
Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Mesih Kilinc [Sun, 25 Nov 2018 07:43:13 +0000 (10:43 +0300)]
dt-bindings: pinctrl: Add Allwinner suniv F1C100s pinctrl
Add compatible string for Allwinner suniv F1C100s SoC's pinctrl.
Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Chris Brandt [Thu, 15 Nov 2018 16:15:27 +0000 (11:15 -0500)]
pinctrl: Add RZ/A2 pin and gpio controller
Adds support for the pin and gpio controller found in R7S9210 (RZ/A2) SoCs.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Chris Brandt [Thu, 15 Nov 2018 16:15:28 +0000 (11:15 -0500)]
dt-bindings: pinctrl: Add RZ/A2 pinctrl and GPIO
Add device tree binding documentation and header file for Renesas R7S9210
(RZ/A2) SoCs.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Dmitry Shifrin [Mon, 19 Nov 2018 17:30:06 +0000 (20:30 +0300)]
pinctrl: sh-pfc: r8a77980: Add QSPI pins, groups, and functions
Add the QSPI{0|1} pins/groups/functions to the R8A77980 PFC driver.
[Sergei: ported to the upstream driver, fixed up the swapped QSPI0 SPCLK/
SSL pins, fixed up the comments, moved the QSPI pins/groups/functions to
be in the alphanumeric order, removed unneeded empty lines, renamed the
patch.]
Signed-off-by: Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Rob Herring [Fri, 16 Nov 2018 22:05:40 +0000 (16:05 -0600)]
pinctrl: mediatek: Convert to using %pOFn instead of device_node.name
In preparation to remove the node name pointer from struct device_node,
convert printf users to use the %pOFn format specifier.
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: linux-mediatek@lists.infradead.org
Cc: linux-gpio@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Sean Wang <sean.wang@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Evan Green [Fri, 16 Nov 2018 18:58:53 +0000 (10:58 -0800)]
pinctrl: msm: Add sleep pinctrl state transitions
Add PM suspend callbacks to the msm core driver that select the
sleep and default pinctrl states. Then wire those callbacks up
in the sdm845 driver, for those boards that may have GPIO hogs
that need to change state during suspend.
Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Ryder Lee [Mon, 12 Nov 2018 01:45:06 +0000 (09:45 +0800)]
dt-bindings: pinctrl: update bindings for MT7629 SoC
This updates bindings for MT7629 pinctrl driver.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Sean Wang <sean.wang@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Ryder Lee [Mon, 12 Nov 2018 01:45:05 +0000 (09:45 +0800)]
pinctrl: mediatek: add pinctrl support for MT7629 SoC
This adds MT7629 pinctrl driver based on MediaTek pinctrl-moore core.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Acked-by: Sean Wang <sean.wang@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
A.s. Dong [Mon, 12 Nov 2018 15:25:48 +0000 (15:25 +0000)]
pinctrl: imx: fix NO_PAD_CTL setting for MMIO pads
After patch
b96eea718bf6 ("pinctrl: fsl: add scu based pinctrl support"),
NO_PAD_CTL pads map are not skipped anymore which results in
a possible memory corruption. As we actually only need to create config
maps for SCU pads and MMIO pads which are not using the default config
(a.k.a IMX_NO_PAD_CTL), so let's add a proper check before creating
the config maps. And during MMIO pads parsing, we also need update the
list_p point as SCU case to ensure the pin data next parsed is correct.
Cc: Linus Walleij <linus.walleij@linaro.org>
Fixes:
b96eea718bf6 ("pinctrl: fsl: add scu based pinctrl support")
Reported-by: Martin Kaiser <martin@kaiser.cx>
Suggested-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Martin Kaiser <martin@kaiser.cx>
Tested-by: Leonard Crestez <leonard.crestez@nxp.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Saravanan Sekar [Thu, 15 Nov 2018 12:47:47 +0000 (13:47 +0100)]
pinctrl: actions: Add Actions Semi S700 pinctrl driver
Add pinctrl and gpio driver for Actions Semi S700 SoC. The driver
supports pinctrl, pinmux, pinconf, gpio and interrupt functionalities
through a range of registers common to both gpio driver and pinctrl driver.
Signed-off-by: Parthiban Nallathambi <pn@denx.de>
Signed-off-by: Saravanan Sekar <sravanhome@gmail.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Saravanan Sekar [Thu, 15 Nov 2018 12:47:46 +0000 (13:47 +0100)]
dt-bindings: pinctrl: Add bindings for Actions Semi S700 SoC
Add pinctrl and pio bindings for Actions Semi S700 SoC.
Signed-off-by: Parthiban Nallathambi <pn@denx.de>
Signed-off-by: Saravanan Sekar <sravanhome@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Saravanan Sekar [Thu, 15 Nov 2018 12:47:45 +0000 (13:47 +0100)]
pinctrl: actions: define pad control configurtion to SoC specific
pad control for s900 and s700 are differs in number of
pull control configuraions
s900 has 4 pull controls - high impedence, pull up, pull down, repeater
s700, s500 has 2 pull controls - pull up and pull down
so pad control configuration has to SoC specific, moved out from pinctrl
common to s900 specific.
Signed-off-by: Parthiban Nallathambi <pn@denx.de>
Signed-off-by: Saravanan Sekar <sravanhome@gmail.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Saravanan Sekar [Thu, 15 Nov 2018 12:47:44 +0000 (13:47 +0100)]
pinctrl: actions: define constructor generic to Actions Semi SoC's
Move generic defines common to the Owl family out of S900 driver.
Signed-off-by: Parthiban Nallathambi <pn@denx.de>
Signed-off-by: Saravanan Sekar <sravanhome@gmail.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Benjamin Gaignard [Tue, 13 Nov 2018 09:51:41 +0000 (10:51 +0100)]
pinctrl: stm32: protect configuration registers with a hwspinlock
If a hwspinlock if defined in device tree use it to protect
configuration registers.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Benjamin Gaignard [Tue, 13 Nov 2018 09:51:40 +0000 (10:51 +0100)]
dt-bindings: pinctrl: stm32: Document hwlocks properties
Add hwlocks as optional property
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Takeshi Kihara [Sun, 18 Nov 2018 17:29:03 +0000 (18:29 +0100)]
pinctrl: sh-pfc: r8a77990: Add CAN FD pins, groups and functions
This patch adds CAN FD{0,1} pins, groups and functions to the R8A77990
SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
[geert: Move canfd from common to automotive]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Takeshi Kihara [Sun, 18 Nov 2018 17:29:02 +0000 (18:29 +0100)]
pinctrl: sh-pfc: r8a77990: Add CAN pins, groups and functions
This patch adds CAN{0,1} pins, groups and functions to the R8A77990 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Takeshi Kihara [Sun, 18 Nov 2018 17:29:01 +0000 (18:29 +0100)]
pinctrl: sh-pfc: r8a77965: Add CAN FD pins, groups and functions
This patch adds CAN FD{0,1} pins, groups and functions to the R8A77965
SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Takeshi Kihara [Sun, 18 Nov 2018 17:29:00 +0000 (18:29 +0100)]
pinctrl: sh-pfc: r8a77965: Add CAN pins, groups and functions
This patch adds CAN{0,1} pins, groups and functions to the R8A77965 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Takeshi Kihara [Fri, 16 Nov 2018 07:20:51 +0000 (15:20 +0800)]
pinctrl: sh-pfc: r8a7796: Add I2C{0,3,5} pins, groups and functions
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC.
These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Takeshi Kihara [Fri, 16 Nov 2018 07:20:50 +0000 (15:20 +0800)]
pinctrl: sh-pfc: r8a7795-es1: Add I2C{0,3,5} pins, groups and functions
This patch adds I2C{0,3,5} pins, groups and functions to
the R8A7795 ES1.x SoC.
These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Takeshi Kihara [Fri, 16 Nov 2018 07:20:49 +0000 (15:20 +0800)]
pinctrl: sh-pfc: r8a7795: Add I2C{0,3,5} pins, groups and functions
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7795 SoC.
These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Ulrich Hecht [Fri, 16 Nov 2018 07:20:48 +0000 (15:20 +0800)]
pinctrl: sh-pfc: Add physical pin multiplexing helper macros
Used by I2C controllers 0, 3 and 5 in R8A7795 and R8A7796 SoCs.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Geert Uytterhoeven [Mon, 19 Nov 2018 10:16:51 +0000 (11:16 +0100)]
pinctrl: sh-pfc: r8a77995: Remove unused PINMUX_IPSR_{MSEL2,PHYS}()
The PINMUX_IPSR_MSEL2() and PINMUX_IPSR_PHYS() macros are unused, and
will conflict with generic macros that are to be added.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Takeshi Kihara [Thu, 15 Nov 2018 16:47:07 +0000 (01:47 +0900)]
pinctrl: sh-pfc: r8a77990: Add HSCIF pins, groups, and functions
This patch adds HSCIF{0,1,2,3,4} pins, groups and functions to
the R8A77990 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Heiko Stuebner [Sun, 11 Nov 2018 21:00:47 +0000 (22:00 +0100)]
pinctrl: rockchip: add rk3188 routes to switch between nand and emmc
The rk3188 has pins that are not handled through the regular iomuxing
for handling either nand-flash or an emmc and are set through only one
specifal setting. So utilize the routing function to simply do that
setting depending on one of the core nand/emmc signals that are actually
regular pins handled through pinctrl.
Signed-off-by: Heiko Stuebner <heiko.stuebner@bq.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Heiko Stuebner [Sun, 11 Nov 2018 21:00:46 +0000 (22:00 +0100)]
pinctrl: rockchip: allow specifying the regmap location for pin-routes
Right now we expect the pin-rounting settings to be in the same area
as the iomux setting itself. And while that seems to be true for all
newer Rockchip socs, back in the wild west days of old this wasn't true.
Nowadays pin settings in the GRF normally stay in the GRF and the same
is true for pins configured from PMU registers. But old socs like the
rk3188 really sprinkle pin settings somewhat randomly through both
for its bank0.
Therefore add the option to specify a location for the route setting,
so that we can map older socs correctly. We'll keep "same" as the
default, so that we only need to specify a location in the corner-cases
described above.
Signed-off-by: Heiko Stuebner <heiko.stuebner@bq.com>
Reviewed-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Brian Masney [Sun, 11 Nov 2018 01:34:11 +0000 (20:34 -0500)]
pinctrl: qcom: ssbi-gpio: fix gpio-hog related boot issues
When attempting to setup up a gpio hog, device probing will repeatedly
fail with -EPROBE_DEFERED errors. It is caused by a circular dependency
between the gpio and pinctrl frameworks. If the gpio-ranges property is
present in device tree, then the gpio framework will handle the gpio pin
registration and eliminate the circular dependency.
See Christian Lamparter's commit
a86caa9ba5d7 ("pinctrl: msm: fix
gpio-hog related boot issues") for a detailed commit message that
explains the issue in much more detail. The code comment in this commit
came from Christian's commit.
I did not test this change against any hardware supported by this
particular driver, however I was able to validate this same fix works
for pinctrl-spmi-gpio.c using a LG Nexus 5 (hammerhead) phone.
Signed-off-by: Brian Masney <masneyb@onstation.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Stefan Wahren [Sat, 10 Nov 2018 16:15:11 +0000 (17:15 +0100)]
pinctrl: bcm2835: Switch to SPDX identifier
Adopt the SPDX license identifier headers to ease license compliance
management.
Cc: Simon Arlott <simon@arlott.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tomer Maimon [Wed, 7 Nov 2018 13:44:34 +0000 (15:44 +0200)]
pinctrl: nuvoton: modify NPCM7xx pin configuration function
Modify GPIO direction setting in pin configuration function by using
generic GPIO functions to set the GPIO direction instead of direct
access to the GPIO direction register.
Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Tested-by: Kun Yi <kunyi@google.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Manivannan Sadhasivam [Wed, 7 Nov 2018 17:48:44 +0000 (23:18 +0530)]
pinctrl: mediatek: Add initial pinctrl driver for MT6797 SoC
Add initial pinctrl driver for Mediatek MT6797 SoC supporting only
GPIO and pinmux configurations.
Tested-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Sean Wang <sean.wang@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Manivannan Sadhasivam [Wed, 7 Nov 2018 17:48:41 +0000 (23:18 +0530)]
dt-bindings: pinctrl: Add devicetree bindings for MT6797 SoC Pinctrl
Add devicetree bindings for Mediatek MT6797 SoC Pin Controller.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Neil Armstrong [Wed, 7 Nov 2018 10:42:38 +0000 (11:42 +0100)]
pinctrl: meson-gxl: remove invalid GPIOX tsin_a pins
The GPIOX tsin_a pins wrongly uses the SDCard pinctrl bits, this
patch completely removes these pins entries until we find out what
are the correct bits and registers to be used instead.
Fixes:
5a6ae9b80139 ("pinctrl: meson-gxl: add tsin_a pins")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Olof Johansson [Fri, 2 Nov 2018 02:57:28 +0000 (19:57 -0700)]
pinctrl: mediatek: Fix dependencies for EINT_MTK
Fixes the following config-time warning:
WARNING: unmet direct dependencies detected for EINT_MTK
Depends on [n]: PINCTRL [=y] && (ARCH_MEDIATEK [=y] || COMPILE_TEST [=n]) && (PINCTRL_MTK [=n] || PINCTRL_MTK_MOORE [=n] || COMPILE_TEST [=n])
Selected by [y]:
- PINCTRL_MTK_PARIS [=y] && PINCTRL [=y] && OF [=y] && (ARCH_MEDIATEK [=y] || COMPILE_TEST [=n])
Fixes:
805250982bb5 ("pinctrl: mediatek: add pinctrl-paris that implements the vendor dt-bindings")
Signed-off-by: Olof Johansson <olof@lixom.net>
Acked-by: Sean Wang <sean.wang@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Jacopo Mondi [Thu, 8 Nov 2018 16:07:24 +0000 (17:07 +0100)]
pinctrl: sh-pfc: r8a77990: Add VIN[4|5] groups/functions
Add pin, mux and functions definitions for VIN4 and VIN5 for R-Car E3.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Jacopo Mondi [Thu, 8 Nov 2018 16:07:23 +0000 (17:07 +0100)]
pinctrl: sh-pfc: r8a77965: Add VIN[4|5] groups/functions
The VIN4 and VIN5 interfaces support parallel video input.
Add pin, mux and functions definitions for VIN4 and VIN5 for R-Car M3-N.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Jacopo Mondi [Thu, 8 Nov 2018 16:07:27 +0000 (17:07 +0100)]
pinctrl: sh-pfc: r8a7796: Fix VIN versioned groups
Versioned VIN groups can appear on different sets of pins. Using the
VIN_DATA_PIN_GROUP macro now supports proper naming of said groups
through an optional 'version' argument.
Use the 'version' argument for said macro to fix naming of versioned
groups for the R-Car M3-W R8A7796 SoC.
Fixes:
a5c2949ff7bd ("pinctrl: sh-pfc: r8a7796: Deduplicate VIN4 pin definitions")
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Jacopo Mondi [Thu, 8 Nov 2018 16:07:26 +0000 (17:07 +0100)]
pinctrl: sh-pfc: r8a7795: Fix VIN versioned groups
Versioned VIN groups can appear on different sets of pins. Using the
VIN_DATA_PIN_GROUP macro now supports proper naming of said groups
through an optional 'version' argument.
Use the 'version' argument for said macro to fix naming of versioned
groups for the R-Car H3 R8A7795 SoC.
Fixes:
9942a5b52990 ("pinctrl: sh-pfc: r8a7795: Deduplicate VIN4 pin definitions")
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Jacopo Mondi [Thu, 8 Nov 2018 16:07:25 +0000 (17:07 +0100)]
pinctrl: sh-pfc: r8a7792: Fix VIN versioned groups
Versioned VIN groups can appear on different sets of pins. Using the
VIN_DATA_PIN_GROUP macro now supports proper naming of said groups
through an optional 'version' argument.
Use the 'version' argument for said macro to fix naming of versioned
groups for the R-Car V2H R8A7792 SoC.
Fixes:
7dd74bb1f058 ("pinctrl: sh-pfc: r8a7792: Add VIN pin groups")
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Jacopo Mondi [Thu, 8 Nov 2018 16:07:22 +0000 (17:07 +0100)]
pinctrl: sh-pfc: Add optional arg to VIN_DATA_PIN_GROUP
VIN data groups may appear on different sets of pins, usually named
"vinX_data_[a|b]". The existing VIN_DATA_PIN_GROUP() does not support
appending the '_a' or '_b' suffix, leading to the definition of group
names not consistent with the ones defined using the SH_PFC_PIN_GROUP()
macro.
Fix this by making the VIN_DATA_PIN_GROUP macro a variadic one,
which accepts an optional 'version' argument.
Fixes:
423caa52534f ("pinctrl: sh-pfc: r8a779[01]: Move 'union vin_data' to shared header file")
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Dmitry Shifrin [Tue, 6 Nov 2018 18:52:55 +0000 (21:52 +0300)]
pinctrl: sh-pfc: r8a77970: Add QSPI pins, groups, and functions
Add the QSPI{0|1} pins/groups/functions to the R8A77970 PFC driver.
[Sergei: ported to the upstream driver, fixed up the swapped QSPI0 SPCLK/
SSL pins, fixed up the comments, moved the QSPI pins/groups/functions to
be in the alphanumeric order, removed unneeded empty lines, renamed the
patch.]
Signed-off-by: Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Takeshi Kihara [Mon, 5 Nov 2018 21:40:12 +0000 (22:40 +0100)]
pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHI
This patch supports the {get,set}_io_voltage operations of SDHI.
This operates the IOCTRL30 register on the R8A77990 SoC and makes
1.8V/3.3V signal voltage switch possible.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Takeshi Kihara [Mon, 5 Nov 2018 21:40:11 +0000 (22:40 +0100)]
pinctrl: sh-pfc: r8a77990: Add SDHI pins, groups and functions
This patch adds SDHI{0,1,3} pins, groups and functions to the R8A77990
SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
A.s. Dong [Fri, 2 Nov 2018 09:13:03 +0000 (09:13 +0000)]
pinctrl: fsl: imx7ulp: change to use imx legacy binding
We already had an earlier conclusion that all new i.MX Socs will keep
using the legacy i.MX Pinctrl bindings instead of generic pin config.
However, MX7ULP generic pin config binding support has already been in
tree before that time. Per SoC maintainers' suggestions, in order to
get a better consistency for all i.MX devices, we'd like to go back to
imx legacy binding for MX7ULP as well.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
A.s. Dong [Fri, 2 Nov 2018 09:12:58 +0000 (09:12 +0000)]
dt-bindings: pinctrl: imx7ulp: back to imx legacy binding for consistency
We already had an earlier conclusion that all new i.MX Socs will keep
using the legacy i.MX Pinctrl bindings instead of generic pin config.
However, MX7ULP generic pin config binding support has already been in
tree before that time. Per SoC maintainers' suggestions, in order to
get a better consistency for all i.MX devices, we'd like to go back to
imx legacy binding for MX7ULP as well.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: linux-gpio@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Nathan Chancellor [Wed, 7 Nov 2018 08:56:40 +0000 (01:56 -0700)]
pinctrl: zynq: Use define directive for PIN_CONFIG_IO_STANDARD
Clang warns when one enumerated type is implicitly converted to another:
drivers/pinctrl/pinctrl-zynq.c:985:18: warning: implicit conversion from
enumeration type 'enum zynq_pin_config_param' to different enumeration
type 'enum pin_config_param' [-Wenum-conversion]
{"io-standard", PIN_CONFIG_IOSTANDARD, zynq_iostd_lvcmos18},
~ ^~~~~~~~~~~~~~~~~~~~~
drivers/pinctrl/pinctrl-zynq.c:990:16: warning: implicit conversion from
enumeration type 'enum zynq_pin_config_param' to different enumeration
type 'enum pin_config_param' [-Wenum-conversion]
= { PCONFDUMP(PIN_CONFIG_IOSTANDARD, "IO-standard", NULL, true),
~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
./include/linux/pinctrl/pinconf-generic.h:163:11: note: expanded from
macro 'PCONFDUMP'
.param = a, .display = b, .format = c, .has_arg = d \
^
2 warnings generated.
It is expected that pinctrl drivers can extend pin_config_param because
of the gap between PIN_CONFIG_END and PIN_CONFIG_MAX so this conversion
isn't an issue. Most drivers that take advantage of this define the
PIN_CONFIG variables as constants, rather than enumerated values. Do the
same thing here so that Clang no longer warns.
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Nathan Chancellor [Thu, 1 Nov 2018 15:00:08 +0000 (08:00 -0700)]
pinctrl: lpc18xx: Use define directive for PIN_CONFIG_GPIO_PIN_INT
Clang warns when one enumerated type is implicitly converted to another:
drivers/pinctrl/pinctrl-lpc18xx.c:643:29: warning: implicit conversion
from enumeration type 'enum lpc18xx_pin_config_param' to different
enumeration type 'enum pin_config_param' [-Wenum-conversion]
{"nxp,gpio-pin-interrupt", PIN_CONFIG_GPIO_PIN_INT, 0},
~ ^~~~~~~~~~~~~~~~~~~~~~~
drivers/pinctrl/pinctrl-lpc18xx.c:648:12: warning: implicit conversion
from enumeration type 'enum lpc18xx_pin_config_param' to different
enumeration type 'enum pin_config_param' [-Wenum-conversion]
PCONFDUMP(PIN_CONFIG_GPIO_PIN_INT, "gpio pin int", NULL, true),
~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
./include/linux/pinctrl/pinconf-generic.h:163:11: note: expanded from
macro 'PCONFDUMP'
.param = a, .display = b, .format = c, .has_arg = d \
^
2 warnings generated.
It is expected that pinctrl drivers can extend pin_config_param because
of the gap between PIN_CONFIG_END and PIN_CONFIG_MAX so this conversion
isn't an issue. Most drivers that take advantage of this define the
PIN_CONFIG variables as constants, rather than enumerated values. Do the
same thing here so that Clang no longer warns.
Link: https://github.com/ClangBuiltLinux/linux/issues/140
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Nathan Chancellor [Thu, 1 Nov 2018 00:46:54 +0000 (17:46 -0700)]
pinctrl: bcm2835: Use define directive for BCM2835_PINCONF_PARAM_PULL
Clang warns when one enumerated type is implicitly converted to another:
drivers/pinctrl/bcm/pinctrl-bcm2835.c:707:40: warning: implicit
conversion from enumeration type 'enum bcm2835_pinconf_param' to
different enumeration type 'enum pin_config_param' [-Wenum-conversion]
configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
~~~~~~~~~~~~~~~~~~~~~~~~ ^~~~~~~~~~~~~~~~~~~~~~~~~~
1 warning generated.
It is expected that pinctrl drivers can extend pin_config_param because
of the gap between PIN_CONFIG_END and PIN_CONFIG_MAX so this conversion
isn't an issue. Most drivers that take advantage of this define the
PIN_CONFIG variables as constants, rather than enumerated values. Do the
same thing here so that Clang no longer warns.
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Nathan Chancellor [Thu, 1 Nov 2018 00:44:10 +0000 (17:44 -0700)]
pinctrl: sprd: Use define directive for sprd_pinconf_params values
Clang warns when one enumerated type is implicitly converted to another:
drivers/pinctrl/sprd/pinctrl-sprd.c:845:19: warning: implicit conversion
from enumeration type 'enum sprd_pinconf_params' to different
enumeration type 'enum pin_config_param' [-Wenum-conversion]
{"sprd,control", SPRD_PIN_CONFIG_CONTROL, 0},
~ ^~~~~~~~~~~~~~~~~~~~~~~
drivers/pinctrl/sprd/pinctrl-sprd.c:846:22: warning: implicit conversion
from enumeration type 'enum sprd_pinconf_params' to different
enumeration type 'enum pin_config_param' [-Wenum-conversion]
{"sprd,sleep-mode", SPRD_PIN_CONFIG_SLEEP_MODE, 0},
~ ^~~~~~~~~~~~~~~~~~~~~~~~~~
It is expected that pinctrl drivers can extend pin_config_param because
of the gap between PIN_CONFIG_END and PIN_CONFIG_MAX so this conversion
isn't an issue. Most drivers that take advantage of this define the
PIN_CONFIG variables as constants, rather than enumerated values. Do the
same thing here so that Clang no longer warns.
Link: https://github.com/ClangBuiltLinux/linux/issues/138
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Reviewed-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Nathan Chancellor [Thu, 1 Nov 2018 00:50:21 +0000 (17:50 -0700)]
pinctrl: max77620: Use define directive for max77620_pinconf_param values
Clang warns when one enumerated type is implicitly converted to another:
drivers/pinctrl/pinctrl-max77620.c:56:12: warning: implicit conversion
from enumeration type 'enum max77620_pinconf_param' to different
enumeration type 'enum pin_config_param' [-Wenum-conversion]
.param = MAX77620_ACTIVE_FPS_SOURCE,
^~~~~~~~~~~~~~~~~~~~~~~~~~
It is expected that pinctrl drivers can extend pin_config_param because
of the gap between PIN_CONFIG_END and PIN_CONFIG_MAX so this conversion
isn't an issue. Most drivers that take advantage of this define the
PIN_CONFIG variables as constants, rather than enumerated values. Do the
same thing here so that Clang no longer warns.
Link: https://github.com/ClangBuiltLinux/linux/issues/139
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Brian Masney [Thu, 1 Nov 2018 00:11:47 +0000 (20:11 -0400)]
pinctrl: qcom: spmi-gpio: fix gpio-hog related boot issues
When attempting to setup up a gpio hog, device probing would repeatedly
fail with -EPROBE_DEFERED errors. It was caused by a circular dependency
between the gpio and pinctrl frameworks. If the gpio-ranges property is
present in device tree, then the gpio framework will handle the gpio pin
registration and eliminate the circular dependency.
See Christian Lamparter's commit
a86caa9ba5d7 ("pinctrl: msm: fix
gpio-hog related boot issues") for a detailed commit message that
explains the issue in much more detail. The code comment in this commit
came from Christian's commit.
Signed-off-by: Brian Masney <masneyb@onstation.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Colin Ian King [Wed, 31 Oct 2018 18:42:41 +0000 (18:42 +0000)]
pinctrl: mediatek: clean up indentation issues, add missing tab
Trivial fix to clean up indentation issues, add one level of
indentation on two if statements.
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Andy Shevchenko [Wed, 17 Oct 2018 16:16:31 +0000 (19:16 +0300)]
pinctrl: baytrail: Code formatting fixes
Remove comma from terminator line to allow compiler fail
in case an entry has been put in a wrong place by any weird reason.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko [Wed, 17 Oct 2018 16:16:31 +0000 (19:16 +0300)]
pinctrl: icelake: Code formatting fixes
Remove comma from terminator line to allow compiler fail
in case an entry has been put in a wrong place by any weird reason.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko [Wed, 17 Oct 2018 16:16:31 +0000 (19:16 +0300)]
pinctrl: cannonlake: Code formatting fixes
Remove comma from terminator line to allow compiler fail
in case an entry has been put in a wrong place by any weird reason.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko [Wed, 17 Oct 2018 16:16:31 +0000 (19:16 +0300)]
pinctrl: geminilake: Code formatting fixes
Remove comma from terminator line to allow compiler fail
in case an entry has been put in a wrong place by any weird reason.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko [Wed, 17 Oct 2018 16:16:31 +0000 (19:16 +0300)]
pinctrl: broxton: Code formatting fixes
Remove comma from terminator line to allow compiler fail
in case an entry has been put in a wrong place by any weird reason.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko [Thu, 4 Oct 2018 16:00:15 +0000 (19:00 +0300)]
pinctrl: lewisburg: Replace acpi.h with mod_devicetable.h
There is no need to include acpi.h since driver doesn't use anything from it
except the propagation of mod_devicetable.h.
Include latter directly instead.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko [Thu, 4 Oct 2018 16:00:15 +0000 (19:00 +0300)]
pinctrl: denverton: Replace acpi.h with mod_devicetable.h
There is no need to include acpi.h since driver doesn't use anything from it
except the propagation of mod_devicetable.h.
Include latter directly instead.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko [Thu, 4 Oct 2018 16:00:15 +0000 (19:00 +0300)]
pinctrl: cedarfork: Replace acpi.h with mod_devicetable.h
There is no need to include acpi.h since driver doesn't use anything from it
except the propagation of mod_devicetable.h.
Include latter directly instead.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko [Wed, 17 Oct 2018 15:49:04 +0000 (18:49 +0300)]
pinctrl: merrifield: include bits.h instead of bitops.h
The reason of including <linux/bitops.h> here is just for BIT() and Co macros.
Since commit
8bd9cb51daac8
("... Move some macros from <linux/bitops.h> to a new <linux/bits.h> file"),
<linux/bits.h> is enough for such compile-time macros.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko [Wed, 17 Oct 2018 16:10:27 +0000 (19:10 +0300)]
pinctrl: intel: Unexport intel_pinctrl_probe()
Since there are no more users, unexport it and make static.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko [Thu, 4 Oct 2018 15:15:54 +0000 (18:15 +0300)]
pinctrl: sunrisepoint: Get rid of unneeded ->probe() stub
The local ->probe() stub does nothing except calling
a generic Intel pin control probe function. Thus,
it's not needed and generic function may be called directly.
Convert the driver accordingly.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko [Thu, 4 Oct 2018 15:15:54 +0000 (18:15 +0300)]
pinctrl: icelake: Get rid of unneeded ->probe() stub
The local ->probe() stub does nothing except calling
a generic Intel pin control probe function. Thus,
it's not needed and generic function may be called directly.
Convert the driver accordingly.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko [Thu, 4 Oct 2018 15:15:54 +0000 (18:15 +0300)]
pinctrl: cannonlake: Get rid of unneeded ->probe() stub
The local ->probe() stub does nothing except calling
a generic Intel pin control probe function. Thus,
it's not needed and generic function may be called directly.
Convert the driver accordingly.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>