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Hans Wennborg [Mon, 19 Mar 2018 13:05:37 +0000 (13:05 +0000)]
build_llvm_package.bat: Drop LLDB from the package.
I don't think anyone ever got this to work, what with getting exactly
the right Python dependency and so on. Removing it simplifies the
script, removes a number of hairy dependencies, and cuts ~30 MB off the
installer size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327835
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Jonas Paulsson [Mon, 19 Mar 2018 13:05:22 +0000 (13:05 +0000)]
[SystemZ] Bugfix of CC liveness in emitMemMemWrapper (CLC).
If DoneMBB becomes empty it must have CC added to its live-in list, since it
will fall-through into EndMBB. This happens when the CLC loop does the
complete range.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327834
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Hans Wennborg [Mon, 19 Mar 2018 12:55:58 +0000 (12:55 +0000)]
HexagonISelLowering.cpp: fix 'enum in bool context' warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327832
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Alex Bradbury [Mon, 19 Mar 2018 11:54:28 +0000 (11:54 +0000)]
[RISCV] Peephole optimisation for load/store of global values or constant addresses
(load (add base, off), 0) -> (load base, off)
(store val, (add base, off)) -> (store val, base, off)
This is similar to an equivalent peephole optimisation in PPCISelDAGToDAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327831
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Alexander Potapenko [Mon, 19 Mar 2018 10:08:04 +0000 (10:08 +0000)]
[MSan] fix the types of RegSaveAreaPtrPtr and OverflowArgAreaPtrPtr
Despite their names, RegSaveAreaPtrPtr and OverflowArgAreaPtrPtr
used to be i8* instead of i8**.
This is important, because these pointers are dereferenced twice
(first in CreateLoad(), then in getShadowOriginPtr()), but for some
reason MSan allowed this - most certainly because it was possible
to optimize getShadowOriginPtr() away at compile time.
Differential revision: https://reviews.llvm.org/D44520
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327830
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Alexander Potapenko [Mon, 19 Mar 2018 10:03:47 +0000 (10:03 +0000)]
[MSan] Don't create zero offsets in getShadowPtrForArgument(). NFC
For MSan instrumentation with MS.ParamTLS and MS.ParamOriginTLS being
TLS variables, the CreateAdd() with ArgOffset==0 is a no-op, because
the compiler is able to fold the addition of 0.
But for KMSAN, which receives ParamTLS and ParamOriginTLS from a call
to the runtime library, this introduces a stray instruction which
complicates reading/testing the IR.
Differential revision: https://reviews.llvm.org/D44514
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327829
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Alexander Potapenko [Mon, 19 Mar 2018 09:59:44 +0000 (09:59 +0000)]
[MSan] Introduce insertWarningFn(). NFC
This is a step towards the upcoming KMSAN implementation patch.
KMSAN is going to use a different warning function,
__msan_warning_32(uptr origin), so we'd better create the warning
calls in one place.
Differential Revision: https://reviews.llvm.org/D44513
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327828
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Mikhail Maltsev [Mon, 19 Mar 2018 09:48:58 +0000 (09:48 +0000)]
[ARM] Fix warnings about missing parentheses in ARMAsmParser
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327827
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Serguei Katkov [Mon, 19 Mar 2018 08:32:09 +0000 (08:32 +0000)]
[SCEV] Factor out isKnownViaInduction. NFC.
This just extracts the isKnownViaInduction from isKnownPredicate.
Reviewers: sanjoy, mkazantsev, reames
Reviewed By: mkazantsev
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44554
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327824
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Serguei Katkov [Mon, 19 Mar 2018 06:35:30 +0000 (06:35 +0000)]
[SCEV] Re-land: Fix isKnownPredicate
This is re-land of https://reviews.llvm.org/rL327362 with a fix
and regression test.
The crash was due to it is possible that for found MDL loop,
LHS or RHS may contain an invariant unknown SCEV which
does not dominate the MDL. Please see regression
test for an example.
Reviewers: sanjoy, mkazantsev, reames
Reviewed By: mkazantsev
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44553
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327822
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Craig Topper [Mon, 19 Mar 2018 04:21:42 +0000 (04:21 +0000)]
[X86] Merge XADD8rr regular expression with XADD16rr/XADD32rr/XADD64rr in a couple scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327821
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Craig Topper [Mon, 19 Mar 2018 04:21:40 +0000 (04:21 +0000)]
[X86] Add ADD16i16/ADD32i32/ADD64i32 and similar to the scheduler models to match ADD8i8.
Also move ADC8i8 and SBB8i8 in the Sandy Bridge model to the same class as ADC8ri and SBB8ri. That seems more accurate since its the 8i8 is just the register forced to AL instead of coming from modrm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327820
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Craig Topper [Mon, 19 Mar 2018 02:07:32 +0000 (02:07 +0000)]
[X6] Remove two unused InstrItinClass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327819
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Craig Topper [Mon, 19 Mar 2018 00:56:12 +0000 (00:56 +0000)]
[X86] Use IIC_CMOV64_RR/RM on 64-bit cmov instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327817
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Craig Topper [Mon, 19 Mar 2018 00:56:11 +0000 (00:56 +0000)]
[X86] Merge 32 and 64-bit RORX/SHLX/SARX/SHRX into single regular expressions in scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327816
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Craig Topper [Mon, 19 Mar 2018 00:56:09 +0000 (00:56 +0000)]
[X86] Merge 8-bit instructions into instregex with 16/32/64 instructions in the scheduler models as much as possible. NFCI
This reduces the total number of generated scheduler classes from 5404 to 5316.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327815
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Dylan McKay [Mon, 19 Mar 2018 00:55:50 +0000 (00:55 +0000)]
[AVR] Lower i128 divisions to runtime library calls
This patch adds i128 division support by instruction LLVM to lower
128-bit divisions to the __udivmodti4 and __divmodti4 rtlib functions.
This also adds test for 64-bit division and 128-bit division.
Patch by Peter Nimmervoll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327814
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Craig Topper [Sun, 18 Mar 2018 22:16:54 +0000 (22:16 +0000)]
[Mips] Remove duplicate lines from MipsScheduleP5600.td and enable FullInstRWOverlapCheck.
This fixes the errors found by the new check added in r327808.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327813
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Craig Topper [Sun, 18 Mar 2018 22:16:53 +0000 (22:16 +0000)]
[AArch64] Fix a few InstRWs in the A53 scheduler model and enable FullInstRWOverlapCheck.
This fixes the errors found by the new check added in r327808.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327812
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Craig Topper [Sun, 18 Mar 2018 21:28:11 +0000 (21:28 +0000)]
[SelectionDAG] Don't default the SelectionDAG* parameter to SDValue::dump to nullptr. Use two different signatures instead.
This matches what we do in SDNode.
This should allow SDValue::dump to be used in the debugger without getting an error if you don't pass an argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327811
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Craig Topper [Sun, 18 Mar 2018 19:56:15 +0000 (19:56 +0000)]
[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.
This is similar to the check later when we remap some of the instructions from one class to a new one. But if we reuse the class we don't get to do that check.
So many CPUs have violations of this check that I had to add a flag to the SchedMachineModel to allow it to be disabled. Hopefully we can get those cleaned up quickly and remove this flag.
A lot of the violations are due to overlapping regular expressions, but that's not the only kind of issue it found.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327808
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Simon Pilgrim [Sun, 18 Mar 2018 19:54:42 +0000 (19:54 +0000)]
[X86][Btver2] Fix crc32 schedule costs
The default is currently FAdd for some reason
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327807
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Simon Pilgrim [Sun, 18 Mar 2018 18:55:34 +0000 (18:55 +0000)]
[X86][Btver2] Add crc32 resource tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327805
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Simon Pilgrim [Sun, 18 Mar 2018 18:45:57 +0000 (18:45 +0000)]
[X86][Btver2] FADD/FHADD ymm instructions are double pumped on the JFPA functional pipe
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327804
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Simon Pilgrim [Sun, 18 Mar 2018 17:10:12 +0000 (17:10 +0000)]
[X86][Btver2] Float bitwise ymm instructions are double pumped on the JFPX (JFPA/JFPM) functional pipes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327803
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Simon Pilgrim [Sun, 18 Mar 2018 15:59:51 +0000 (15:59 +0000)]
[X86][Btver2] F16C instructions are performed on the JSTC functional pipe
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327801
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Anastasis Grammenos [Sun, 18 Mar 2018 15:59:19 +0000 (15:59 +0000)]
[LICM] Salvage DI from dying Instructions
LICM deletes trivially dead instructions which it won't attempt to sink.
Attempt to salvage debug values which reference these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327800
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Roman Lebedev [Sun, 18 Mar 2018 15:53:02 +0000 (15:53 +0000)]
[InstCombine] peek through unsigned FP casts for zero-equality compares (PR36682)
Summary:
This pattern came up in PR36682 / D44390
https://bugs.llvm.org/show_bug.cgi?id=36682
https://reviews.llvm.org/D44390
https://godbolt.org/g/oKvT5H
See also D44416
Reviewers: spatel, majnemer, efriedma, arsenm
Reviewed By: spatel
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44424
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327799
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Andrea Di Biagio [Sun, 18 Mar 2018 15:33:27 +0000 (15:33 +0000)]
[llvm-mca] Allow the definition of multiple register files.
This is a refactoring in preparation for other two changes that will allow
scheduling models to define multiple register files. This is the first step
towards fixing PR36662.
class RegisterFile (in Dispatch.h) now can emulate multiple register files.
Internally, it tracks the number of available physical registers in each
register file (described by class RegisterFileInfo).
Each register file is associated to a list of MCRegisterClass indices. Knowing
the register class indices allows to map physical registers to register files.
The long term goal is to allow processor models to optionally specify how many
register files are implemented via tablegen.
Differential Revision: https://reviews.llvm.org/D44488
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327798
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Sanjay Patel [Sun, 18 Mar 2018 14:32:54 +0000 (14:32 +0000)]
[InstCombine] add nnan requirement for sqrt(x) * sqrt(y) -> sqrt(x*y)
This is similar to D43765.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327797
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Sanjay Patel [Sun, 18 Mar 2018 14:12:25 +0000 (14:12 +0000)]
[InstSimplify] loosen FMF for sqrt(X) * sqrt(X) --> X
As shown in the code comment, we don't need all of 'fast',
but we do need reassoc + nsz + nnan.
Differential Revision: https://reviews.llvm.org/D43765
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327796
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Simon Pilgrim [Sun, 18 Mar 2018 13:16:11 +0000 (13:16 +0000)]
[X86][Btver2] Strip default latency/resource values. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327795
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Simon Pilgrim [Sun, 18 Mar 2018 13:05:09 +0000 (13:05 +0000)]
[X86][Btver2] SSE4A EXTRQ/INSERTQ instructions are performed on the JVALU0/JVALU1 functional pipes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327794
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Simon Pilgrim [Sun, 18 Mar 2018 12:37:35 +0000 (12:37 +0000)]
[X86][Btver2] Modelled float bitwise instructions as being performed on the float cluster (FPA/FPM) not the integer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327793
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Jonas Devlieghere [Sun, 18 Mar 2018 12:27:05 +0000 (12:27 +0000)]
[dsymutil] Fix add_llvm_tool_symlink
Update the arguments to add_llvm_tool_symlink to symlink llvm-dsymutil
to dsymutil.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327792
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Simon Pilgrim [Sun, 18 Mar 2018 12:09:17 +0000 (12:09 +0000)]
[X86][Btver2] Correctly distinguish between scheduling pipe and functional unit for JWriteResFpuPair defs
Jaguar's FPU has 2 scheduler pipes (JFPU0/JFPU1) which forward to multiple functional sub-units each. We need to model that an micro-op will both consume the scheduler pipe and a functional unit.
This patch just handles the ops defined through JWriteResFpuPair, I'll go through the custom cases later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327791
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Jonas Devlieghere [Sun, 18 Mar 2018 11:38:41 +0000 (11:38 +0000)]
[dsymutil] Rename llvm-dsymutil -> dsymutil
Now that almost all functionality of Apple's dsymutil has been
upstreamed, the open source variant can be used as a drop in
replacement. Hence we feel it's no longer necessary to have the llvm
prefix.
Differential revision: https://reviews.llvm.org/D44527
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327790
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Simon Pilgrim [Sun, 18 Mar 2018 10:22:35 +0000 (10:22 +0000)]
[X86][Btver2] Merge equivalent VBLENDVY + VPERMILY schedule groups
Thanks to Craig Topper for noticing this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327789
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Simon Pilgrim [Sun, 18 Mar 2018 09:32:38 +0000 (09:32 +0000)]
[X86][Btver2] Add llvm-mca tests to show pipe resource usage of most vector instructions
Hopefully these tests can be easily reused should any other subtarget get in depth llvm-mca coverage (we can either copy the tests or move them into a common dir and run it with multiple prefixes).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327788
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Craig Topper [Sun, 18 Mar 2018 08:38:06 +0000 (08:38 +0000)]
[X86] Fix a bunch of overlapping regular expressions in the scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327787
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Craig Topper [Sun, 18 Mar 2018 08:38:04 +0000 (08:38 +0000)]
[X86] Fix a couple typos in the Zen scheduler model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327786
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Craig Topper [Sun, 18 Mar 2018 08:38:03 +0000 (08:38 +0000)]
[TableGen] Remove unnecessary uses of make_range.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327785
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Craig Topper [Sun, 18 Mar 2018 08:38:02 +0000 (08:38 +0000)]
[TableGen] Move some variables into for loop declaration. NFC
They aren't needed after the loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327784
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Craig Topper [Sun, 18 Mar 2018 03:24:42 +0000 (03:24 +0000)]
[X86] Remove MMX_MASKMOVQ64 and VMASKMOVDQU from scheduler models.
The information was so wildly inaccurate and incomplete its better to just remove it.
MMX_MASKMOVQ64 showed up twice in several scheduler models. In Haswell and Broadwell they were on adjacent lines. On Skylake the copies had different information.
MMX_MASKMOVQ and MASKMOVDQU were completely missing.
MMX_MASKMOVQ64 was listed on Haswell/Broadwell as 1 cycle on port 1 despite it being a store instruction.
Filed PR36780 to track fixing this right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327783
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Martin Storsjo [Sat, 17 Mar 2018 20:08:48 +0000 (20:08 +0000)]
[AArch64] Skip an unnecessary getCopyToReg in DYNAMIC_STACKALLOC
Differential Revision: https://reviews.llvm.org/D44586
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327779
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Nirav Dave [Sat, 17 Mar 2018 19:24:54 +0000 (19:24 +0000)]
Revert "[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172""
as it times out building test-suite on PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327778
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Nirav Dave [Sat, 17 Mar 2018 17:42:10 +0000 (17:42 +0000)]
[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"
Reland ISel cycle checking improvements after simplifying and reducing
node id invariant traversal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327777
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Sylvestre Ledru [Sat, 17 Mar 2018 17:30:08 +0000 (17:30 +0000)]
Fix some user facing typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327776
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Matt Arsenault [Sat, 17 Mar 2018 15:17:48 +0000 (15:17 +0000)]
AMDGPU/GlobalISel: Cleanup constant legality
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327774
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Matt Arsenault [Sat, 17 Mar 2018 15:17:45 +0000 (15:17 +0000)]
AMDGPU/GlobalISel: Basic G_GEP legality
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327773
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Matt Arsenault [Sat, 17 Mar 2018 15:17:41 +0000 (15:17 +0000)]
AMDGPU/GlobalISel: Basic legality for load/store
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327772
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Chandler Carruth [Sat, 17 Mar 2018 15:12:52 +0000 (15:12 +0000)]
[bindings/go] Add a missing `,` in the test code to fix a go compile
failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327771
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Oren Ben Simhon [Sat, 17 Mar 2018 13:29:46 +0000 (13:29 +0000)]
[X86] Added support for nocf_check attribute for indirect Branch Tracking
X86 Supports Indirect Branch Tracking (IBT) as part of Control-Flow Enforcement Technology (CET).
IBT instruments ENDBR instructions used to specify valid targets of indirect call / jmp.
The `nocf_check` attribute has two roles in the context of X86 IBT technology:
1. Appertains to a function - do not add ENDBR instruction at the beginning of the function.
2. Appertains to a function pointer - do not track the target function of this pointer by adding nocf_check prefix to the indirect-call instruction.
This patch implements `nocf_check` context for Indirect Branch Tracking.
It also auto generates `nocf_check` prefixes before indirect branchs to jump tables that are guarded by range checks.
Differential Revision: https://reviews.llvm.org/D41879
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327767
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Jonas Paulsson [Sat, 17 Mar 2018 09:15:13 +0000 (09:15 +0000)]
[SystemZ] Add 'REQUIRES: asserts' to test case using debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327766
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Jonas Paulsson [Sat, 17 Mar 2018 08:32:12 +0000 (08:32 +0000)]
[SystemZ] computeKnownBitsForTargetNode() / ComputeNumSignBitsForTargetNode()
Improve/implement these methods to improve DAG combining. This mainly
concerns intrinsics.
Some constant operands to SystemZISD nodes have been marked Opaque to avoid
transforming back and forth between generic and target nodes infinitely.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327765
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Jonas Paulsson [Sat, 17 Mar 2018 08:04:00 +0000 (08:04 +0000)]
[SelectionDAG] Handle big endian target BITCAST in computeKnownBits()
The BITCAST handling in computeKnownBits() previously only worked for little
endian.
This patch reverses the iteration over elements for a big endian target which
allows this to work in this case also.
SystemZ test case.
Review: Eli Friedman
https://reviews.llvm.org/D44249
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327764
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Chandler Carruth [Fri, 16 Mar 2018 23:51:33 +0000 (23:51 +0000)]
[GlobalsAA] Fix a pretty terrible bug that has been in GlobalsAA for
a long time.
The key thing is that we need to create value handles for every function
that we create a `FunctionInfo` object around. Without this, when that
function is deleted we can end up creating a new function that collides
with its address and look up a stale AA result. With that AA result we
can in turn miscompile code in ways that break.
This is seriously one of the most absurd miscompiles I've seen. It only
reproduced for us recently and only when building a very large server
with both ThinLTO and PGO.
A *HUGE* shout out to Wei Mi who tracked all of this down and came up
with this patch. I'm just landing it because I happened to still by at
a computer.
He or I can work on crafting a test case to hit this (now that we know
what to target) but it'll take a while, and we've been chasing this for
a long time and need it fix Right Now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327761
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Jessica Paquette [Fri, 16 Mar 2018 22:53:34 +0000 (22:53 +0000)]
[MachineOutliner] Make KILLs invisible
At the point the outliner runs, KILLs don't impact anything, but they're still
considered unique instructions. This commit makes them invisible like
DebugValues so that they can still be outlined without impacting outlining
decisions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327760
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Andrea Di Biagio [Fri, 16 Mar 2018 22:21:52 +0000 (22:21 +0000)]
[llvm-mca] Remove method getSchedModel() from the Backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327756
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Andrea Di Biagio [Fri, 16 Mar 2018 22:02:47 +0000 (22:02 +0000)]
[llvm-mca] Remove unused methods from Backend. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327749
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David L Kreitzer [Fri, 16 Mar 2018 21:21:23 +0000 (21:21 +0000)]
Quiet unused variable warnings. NFC.
Differential revision: https://reviews.llvm.org/D44583
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327745
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Craig Topper [Fri, 16 Mar 2018 21:10:07 +0000 (21:10 +0000)]
[X86] Pass SelectionDAG into X86ISelAddressMode::dump and on to SDNode::dump.
This prevents a crash in SelectionDAGDumper with -debug when trying to print mem operands if one of the registers in the addressing mode comes from a load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327744
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Sanjay Patel [Fri, 16 Mar 2018 20:55:55 +0000 (20:55 +0000)]
[InstSimplify] add NaN constant diversity; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327743
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Krzysztof Parzyszek [Fri, 16 Mar 2018 20:55:49 +0000 (20:55 +0000)]
[Hexagon] Avoid bank conflicts in post-RA scheduler
Avoid scheduling two loads in such a way that they would end up in the
same packet. If there is a load in a packet, try to schedule a non-load
next.
Patch by Brendon Cahoon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327742
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Krzysztof Parzyszek [Fri, 16 Mar 2018 20:21:43 +0000 (20:21 +0000)]
[Hexagon] Add lit testcases for atomic intrinsics
Patch by Ben Craig.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327737
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Reid Kleckner [Fri, 16 Mar 2018 20:13:32 +0000 (20:13 +0000)]
[IR] Avoid the need to prefix MS C++ symbols with '\01'
Now the Windows mangling modes ('w' and 'x') do not do any mangling for
symbols starting with '?'. This means that clang can stop adding the
hideous '\01' leading escape. This means LLVM debug logs are less likely
to contain ASCII escape characters and it will be easier to copy and
paste MS symbol names from IR.
Finally.
For non-Windows platforms, names starting with '?' still get IR
mangling, so once clang stops escaping MS C++ names, we will get extra
'_' prefixing on MachO. That's fine, since it is currently impossible to
construct a triple that uses the MS C++ ABI in clang and emits macho
object files.
Differential Revision: https://reviews.llvm.org/D7775
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327734
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Reid Kleckner [Fri, 16 Mar 2018 20:11:55 +0000 (20:11 +0000)]
Revert r327721 "This patch fixes the invalid usage of OptSize in Machine Combiner."
It causes asserts when compiling Chromium on Win32 with optimizations.
We compile many things with -Os.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327733
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Craig Topper [Fri, 16 Mar 2018 18:25:59 +0000 (18:25 +0000)]
[X86] Merge ADDSUB/SUBADD detection into single methods that can detect either and indicate what they found.
Previously, we called the same functions twice with a bool flag determining whether we should look for ADDSUB or SUBADD. It would be more efficient to run the code once and detect either pattern with a flag to tell which type it found.
Differential Revision: https://reviews.llvm.org/D44540
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327730
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Craig Topper [Fri, 16 Mar 2018 18:18:47 +0000 (18:18 +0000)]
[CorrelatedValuePropagation] Use SelectInst::getCondition/getTrueValue/getFalseValue instead of getOperand for readability. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327728
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Farhana Aleen [Fri, 16 Mar 2018 18:12:00 +0000 (18:12 +0000)]
[AMDGPU] Supported ds_write_b128 generation.
Summary: This is a follow-on patch of https://reviews.llvm.org/D44210
Author: FarhanaAleen
Reviewed By: msearles
Subscribers: llvm-commits, AMDGPU
Differential Revision: https://reviews.llvm.org/D44319
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327726
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Craig Topper [Fri, 16 Mar 2018 17:13:42 +0000 (17:13 +0000)]
[X86] Post process the DAG after isel to remove vector moves that were added to zero upper bits.
We previously avoided inserting these moves during isel in a few cases which is implemented using a whitelist of opcodes. But it's too difficult to generate a perfect list of opcodes to whitelist. Especially with AVX512F without AVX512VL using 512 bit vectors to implement some 128/256 bit operations. Since isel is done bottoms up, we'd have to check the VT and opcode and subtarget in order to determine whether an EXTRACT_SUBREG would be generated for some operations.
So instead of doing that, this patch adds a post processing step that detects when the moves are unnecesssary after isel. At that point any EXTRACT_SUBREGs would have already been created and appear in the DAG. So then we just need to ensure the input to the move isn't one.
Differential Revision: https://reviews.llvm.org/D44289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327724
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Dmitry Preobrazhensky [Fri, 16 Mar 2018 16:38:04 +0000 (16:38 +0000)]
[AMDGPU][MC][GFX8][GFX9][DISASSEMBLER] Added "_e32" suffix to 32-bit VINTRP opcodes
See bug 36751: https://bugs.llvm.org/show_bug.cgi?id=36751
Differential Revision: https://reviews.llvm.org/D44529
Reviewers: artem.tamazov, arsenm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327723
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Philip Reames [Fri, 16 Mar 2018 16:33:49 +0000 (16:33 +0000)]
[LICM/mustexec] Extend first iteration must execute logic to fcmps
This builds on the work from https://reviews.llvm.org/D44287. It turned out supporting fcmp was much easier than I realized, so let's do that now.
As an aside, our -O3 handling of a floating point IVs leaves a lot to be desired. We do convert the float IV to an integer IV, but do so late enough that many other optimizations are missed (e.g. we don't vectorize).
Differential Revision: https://reviews.llvm.org/D44542
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327722
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Andrew V. Tischenko [Fri, 16 Mar 2018 16:06:24 +0000 (16:06 +0000)]
This patch fixes the invalid usage of OptSize in Machine Combiner.
Differential Revision: https://reviews.llvm.org/D43813
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327721
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Dmitry Preobrazhensky [Fri, 16 Mar 2018 15:40:27 +0000 (15:40 +0000)]
[AMDGPU][MC] Corrected default values for unused SDWA operands
See bug 36355: https://bugs.llvm.org/show_bug.cgi?id=36355
Differential Revision: https://reviews.llvm.org/D44481
Reviewers: artem.tamazov, arsenm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327720
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Sanjay Patel [Fri, 16 Mar 2018 15:27:39 +0000 (15:27 +0000)]
[InstCombine] add nnan requirement to potential fabs folds tests; NFC
As noted in D44550, we can't guarantee preserving the sign-bit of NaN
if we convert these to fabs().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327718
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Jonas Paulsson [Fri, 16 Mar 2018 15:21:26 +0000 (15:21 +0000)]
[SystemZ] Make AnyRegBitRegClass unallocatable.
AnyReg is just for the assembler and it is better to have it as not
allocatable in order to simplify (make more intuitive) the RegPressureSets.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327715
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Aditya Nandakumar [Fri, 16 Mar 2018 15:14:18 +0000 (15:14 +0000)]
[GISel]: Remove unused header include in MachineIRBuilder.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327714
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Brian M. Rzycki [Fri, 16 Mar 2018 15:13:47 +0000 (15:13 +0000)]
[JumpThreading] Track unreachable BBs to avoid processing
JumpThreading iterates over F until the IR quiesces. Transforming
unreachable BBs increases compile time and it is also possible to
never stabilize causing JumpThreading to hang. An older attempt at
fixing this problem was D3991 where removeUnreachableBlocks(F)
was called before JumpThreading began. This has a few drawbacks:
* expensive - the routine attempts to fix up the IR to identify
additional BBs that can be removed along with unreachable BBs.
* aggressive - does not identify and preserve the shape of the IR.
At a minimum it does not preserve loop hierarchies.
* invasive - altering reachable blocks it may disrupt IR shapes
that could have otherwise been JumpThreaded.
This patch avoids removeUnreachableBlocks(F) and instead tracks
unreachable BBs in a SmallPtrSet using DominatorTree to validate the
initial state of all BBs. We then rely on subsequent passes to identify
and remove these unreachable blocks from F.
Reviewers: dberlin, sebpop, kuhar, dinesh.d
Reviewed by: sebpop, kuhar
Subscribers: hiraditya, uabelho, llvm-commits
Differential Revision: https://reviews.llvm.org/D44177
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327713
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Krzysztof Parzyszek [Fri, 16 Mar 2018 15:03:37 +0000 (15:03 +0000)]
[Hexagon] Fix zero-extending non-HVX bool vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327712
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Mikhail Maltsev [Fri, 16 Mar 2018 14:10:56 +0000 (14:10 +0000)]
[ARM] Convert more invalid NEON immediate loads
Summary:
Currently the LLVM MC assembler is able to convert e.g.
vmov.i32 d0, #0xabababab
(which is technically invalid) into a valid instruction
vmov.i8 d0, #0xab
this patch adds support for vmov.i64 and for cases with the resulting
load types other than i8, e.g.:
vmov.i32 d0, #0xab00ab00 ->
vmov.i16 d0, #0xab00
Reviewers: olista01, rengolin
Reviewed By: rengolin
Subscribers: rengolin, javed.absar, kristof.beyls, rogfer01, llvm-commits
Differential Revision: https://reviews.llvm.org/D44467
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327709
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Simon Pilgrim [Fri, 16 Mar 2018 14:01:01 +0000 (14:01 +0000)]
[X86][Btver2] Add correct mul/imul schedule costs
Integer multiply is performed on the JMul function unit and i64 requires double pumping
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327707
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Simon Pilgrim [Fri, 16 Mar 2018 13:43:55 +0000 (13:43 +0000)]
[X86][Btver2] Add correct lzcnt/tzcnt/popcnt schedule costs
Don't use WriteIMul defaults
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327706
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Mikhail Maltsev [Fri, 16 Mar 2018 12:46:49 +0000 (12:46 +0000)]
[ARM] Fix a check in vmov/vmvn immediate parsing
Summary:
Currently the check is incorrect and the following invalid
instruction is accepted and incorrectly assembled:
vmov.i32 d2, #0x00a500a6
This patch fixes the issue.
Reviewers: olista01, rengolin
Reviewed By: rengolin
Subscribers: SjoerdMeijer, javed.absar, rogfer01, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D44460
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327704
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Matthew Simpson [Fri, 16 Mar 2018 11:34:15 +0000 (11:34 +0000)]
[AArch64] Implement getArithmeticReductionCost
This patch provides an implementation of getArithmeticReductionCost for
AArch64. We can specialize the cost of add reductions since they are computed
using the 'addv' instruction.
Differential Revision: https://reviews.llvm.org/D44490
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327702
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Pavel Labath [Fri, 16 Mar 2018 10:30:26 +0000 (10:30 +0000)]
HashTableTest: squelch some "comparison of integers of different signs" warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327701
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Pavel Labath [Fri, 16 Mar 2018 10:02:16 +0000 (10:02 +0000)]
DWARFVerifier: Enhance validation of .debug_names hash tables
Summary:
This patch adds more checks to the .debug_names validator. Specifically,
they check for:
- buckets claiming to be non-empty but pointing to mismatched hashes
(most consumers would interpret this as an empty bucket, but it
questionable whether the generator meant that)
- hashes that are not reachable from any bucket
- names with incorrect hashes
Together, these checks ensure that any name in the index can be reached
through the hash table using the regular lookup algorithm. We also warn
if we encounter a name index without a hash table.
Reviewers: JDevlieghere, aprantl, dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327699
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Matthew Simpson [Fri, 16 Mar 2018 10:00:30 +0000 (10:00 +0000)]
[TTI, AArch64] Allow the cost model analysis to test vector reduce intrinsics
This patch considers the experimental vector reduce intrinsics in the default
implementation of getIntrinsicInstrCost. The cost of these intrinsics is
computed with getArithmeticReductionCost and getMinMaxReductionCost. This patch
also adds a test case for AArch64 that indicates the costs we currently compute
for vector reduce intrinsics. These costs are inaccurate and will be updated in
a follow-on patch.
Differential Revision: https://reviews.llvm.org/D44489
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327698
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Sjoerd Meijer [Fri, 16 Mar 2018 08:06:25 +0000 (08:06 +0000)]
[ARM] FP16 codegen support for VSEL
This implements lowering of SELECT_CC for f16s, which enables
codegen of VSEL with f16 types.
Differential Revision: https://reviews.llvm.org/D44518
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327695
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Max Kazantsev [Fri, 16 Mar 2018 05:02:24 +0000 (05:02 +0000)]
[NFC] Void variables used for asserts only
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327693
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Sanjay Patel [Fri, 16 Mar 2018 01:06:33 +0000 (01:06 +0000)]
[InstCombine] add more tests for fcmp+select -> fabs; NFC
This should correspond to the patterns in D44091 and might
make handling these in the DAG unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327689
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Simon Pilgrim [Thu, 15 Mar 2018 23:46:12 +0000 (23:46 +0000)]
[X86][Btver2] Add support for multiple pipelines stages for x86 scalar schedules. NFCI.
This allows us to use JWriteResIntPair for complex schedule classes (like WriteIDiv) as well as single pipe instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327686
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Simon Pilgrim [Thu, 15 Mar 2018 23:15:11 +0000 (23:15 +0000)]
[X86][Btver2] Tweak pipes test to remove register dependencies
It gives us a better view of pipe usage in the timeline which is what the test is trying to show.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327685
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Craig Topper [Thu, 15 Mar 2018 23:04:11 +0000 (23:04 +0000)]
[SelectionDAG][ARM][X86] Teach PromoteIntRes_SETCC to do a better job picking the result type for the setcc.
Previously if getSetccResultType returned an illegal type we just fell back to using the default promoted type. This appears to have been to handle the case where for vectors getSetccResultType returns the input type, but the input type itself isn't legal and will need to be promoted. Without the legality check we would never reach a legal type.
But just picking the promoted type to be the setcc type can create strange setccs where the result type is 128 bits and the operand type is 256 bits. If for example the result type was promoted to v8i16 from v8i1, but the input type was promoted from v8i23 to v8i32. We currently handle this with custom lowering code in X86.
This legality check also caused us reject the getSetccResultType when the input type needed to be widened or split. Even though that result wouldn't have caused legalization to get stuck.
This patch tries to fix this by detecting the getSetccResultType needs to be promoted. If its input type also needs to be promoted we'll try a ask for a new setcc result type based on its eventual promoted value. Otherwise we fall back to default type to promote to.
For any other illegal values we might get back from the initial call to getSetccResultType we just keep and allow it to be re-legalized later via splitting or widening or scalarizing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327683
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Simon Pilgrim [Thu, 15 Mar 2018 23:00:47 +0000 (23:00 +0000)]
[X86][Btver2] Fix ymm div/sqrt to use fmul unit
YMM FDiv/FSqrt are dispatched on pipe JFPU1 but should be performed on the JFPM unit - that is where most of the cycles are spent.
This matches the pipes for WriteFSqrt/WriteFDiv definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327682
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Sean Silva [Thu, 15 Mar 2018 22:51:55 +0000 (22:51 +0000)]
Use standard `print(dbgs())` pattern to implement DebugLoc::dump
The open-coded implementation had a bug. It didn't print filenames.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327681
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Sanjay Patel [Thu, 15 Mar 2018 22:48:23 +0000 (22:48 +0000)]
[InstCombine] add tests for fcmp+select -> fabs; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327680
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Zachary Turner [Thu, 15 Mar 2018 22:47:04 +0000 (22:47 +0000)]
Fix PDB injected sources test.
This test was originally disabled because it was failing on a bot.
It turns out I had run dos2unix on the file, and that removed a
necessary byte from the file. I'm just recomitting the proper
file and updating the test to test a little bit more now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327679
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Simon Pilgrim [Thu, 15 Mar 2018 22:34:24 +0000 (22:34 +0000)]
[X86][Btver2] Add test to show timeline of fpu instructions on different pipes/units
Try to demonstrate the scheduling from fpu0/fpu1 pipes to the valu0/vimul/fpa or valu1/stc/fpm functional units
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327676
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Zachary Turner [Thu, 15 Mar 2018 22:31:00 +0000 (22:31 +0000)]
[PDB] Fix a bug where we were serializing hash tables incorrectly.
There was some code that tried to calculate the number of 4-byte
words required to hold N bits, but it was instead computing the
number of bytes required to hold N bits. This was leading to
extraneous data being output into the hash table, which would
cause certain operations in DIA (the Microsoft PDB reader) to
fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327675
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