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6 years ago[Inliner] add inliner stats to new pm version of inliner
Fedor Sergeev [Tue, 14 Aug 2018 15:19:14 +0000 (15:19 +0000)]
[Inliner] add inliner stats to new pm version of inliner

Increment existing NumInlined and NumDeleted stats in InlinerPass::run.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339682 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] regenerate checks; NFC
Sanjay Patel [Tue, 14 Aug 2018 15:18:52 +0000 (15:18 +0000)]
[InstCombine] regenerate checks; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339681 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86][SSE] Generalize lowerVectorShuffleAsBlendOfPSHUFBs to work with any vXi8 type.
Simon Pilgrim [Tue, 14 Aug 2018 14:00:14 +0000 (14:00 +0000)]
[X86][SSE] Generalize lowerVectorShuffleAsBlendOfPSHUFBs to work with any vXi8 type.

We still only use this for v16i8, but this cleans up the code to support v32i8/v64i8 sometime in the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339679 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[DebugInfo] Generate DWARF debug information for labels. (Fix leak problems)
Hsiangkai Wang [Tue, 14 Aug 2018 13:50:59 +0000 (13:50 +0000)]
[DebugInfo] Generate DWARF debug information for labels. (Fix leak problems)

There are two forms for label debug information in DWARF format.

1. Labels in a non-inlined function:

DW_TAG_label
  DW_AT_name
  DW_AT_decl_file
  DW_AT_decl_line
  DW_AT_low_pc

2. Labels in an inlined function:

DW_TAG_label
  DW_AT_abstract_origin
  DW_AT_low_pc

We will collect label information from DBG_LABEL. Before every DBG_LABEL,
we will generate a temporary symbol to denote the location of the label.
The symbol could be used to get DW_AT_low_pc afterwards. So, we create a
mapping between 'inlined label' and DBG_LABEL MachineInstr in DebugHandlerBase.
The DBG_LABEL in the mapping is used to query the symbol before it.

The AbstractLabels in DwarfCompileUnit is used to process labels in inlined
functions.

We also keep a mapping between scope and labels in DwarfFile to help to
generate correct tree structure of DIEs.

It also generates label debug information under global isel.

Differential Revision: https://reviews.llvm.org/D45556

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339676 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[GlobalISel][IRTranslator] Fix a bug in handling repeating struct types during argume...
Amara Emerson [Tue, 14 Aug 2018 12:04:25 +0000 (12:04 +0000)]
[GlobalISel][IRTranslator] Fix a bug in handling repeating struct types during argument lowering.

Differential Revision: https://reviews.llvm.org/D49442

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339674 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[TableGen] Pass string/vector types by const reference (PR37666). NFCI
Simon Pilgrim [Tue, 14 Aug 2018 11:17:38 +0000 (11:17 +0000)]
[TableGen] Pass string/vector types by const reference (PR37666). NFCI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339670 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFix MSVC "compiler limit: blocks nested too deeply" error. NFCI.
Simon Pilgrim [Tue, 14 Aug 2018 10:04:14 +0000 (10:04 +0000)]
Fix MSVC "compiler limit: blocks nested too deeply" error. NFCI.

MSVC only accepts if-else chains up to 127 blocks long. I've had to merge a number of intrinsic cases together to get back below this limit, resulting in some duplication of string matches; this shouldn't cause any notable increase in runtime (and even then only for old IR, nothing that clang currently emits).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339666 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Constant folding of adds/subs intrinsics
Tomasz Krupa [Tue, 14 Aug 2018 09:04:01 +0000 (09:04 +0000)]
[X86] Constant folding of adds/subs intrinsics

Summary: This adds constant folding of signed add/sub with saturation intrinsics.

Reviewers: craig.topper, spatel, RKSimon, chandlerc, efriedma

Reviewed By: craig.topper

Subscribers: rnk, llvm-commits

Differential Revision: https://reviews.llvm.org/D50499

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339659 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[RISCV] Fix incorrect use of MCInstBuilder
Roger Ferrer Ibanez [Tue, 14 Aug 2018 08:30:42 +0000 (08:30 +0000)]
[RISCV] Fix incorrect use of MCInstBuilder

This is a fix for r339314.

MCInstBuilder uses the named parameter idiom and an 'operator MCInst&' to ease
the creation of MCInsts. As the object of MCInstBuilder owns the MCInst is
manipulating, the lifetime of the MCInst is bound to that of MCInstBuilder.

In r339314 I bound a reference to the MCInst in an initializer. The
temporary of MCInstBuilder (and also its MCInst) is destroyed at the end of
the declaration leading to a dangling reference.

Fix this by using MCInstBuilder inside an argument of a function call.
Temporaries in function calls are destroyed in the enclosing full expression,
so the the reference to MCInst is still valid when emitToStreamer executes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339654 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoTest commit: fix punctuation
Chih-Mao Chen [Tue, 14 Aug 2018 08:08:39 +0000 (08:08 +0000)]
Test commit: fix punctuation

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339652 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Lowering addus/subus intrinsics to native IR
Tomasz Krupa [Tue, 14 Aug 2018 08:00:56 +0000 (08:00 +0000)]
[X86] Lowering addus/subus intrinsics to native IR

Summary: This revision improves previous version (rL330322) which has been reverted due to crashes.

This is the patch that lowers x86 intrinsics to native IR
in order to enable optimizations. The patch also includes folding
of previously missing saturation patterns so that IR emits the same
machine instructions as the intrinsics.

Reviewers: craig.topper, spatel, RKSimon

Reviewed By: craig.topper

Subscribers: mike.dvoretsky, DavidKreitzer, sroland, llvm-commits

Differential Revision: https://reviews.llvm.org/D46179

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339650 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ARM] ParallelDSP: add option to enable/disable the pass
Sjoerd Meijer [Tue, 14 Aug 2018 07:43:49 +0000 (07:43 +0000)]
[ARM] ParallelDSP: add option to enable/disable the pass

Differential Revision: https://reviews.llvm.org/D50511

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339645 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[NFC] Modify comment to make it more precise
Max Kazantsev [Tue, 14 Aug 2018 07:40:08 +0000 (07:40 +0000)]
[NFC] Modify comment to make it more precise

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339644 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[NFC] Add comprehensive test of AliasSetTracker with guards
Max Kazantsev [Tue, 14 Aug 2018 06:37:39 +0000 (06:37 +0000)]
[NFC] Add comprehensive test of AliasSetTracker with guards

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339643 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ThinLTO] Fix printing of WPD remarks
Teresa Johnson [Tue, 14 Aug 2018 03:00:16 +0000 (03:00 +0000)]
[ThinLTO] Fix printing of WPD remarks

Summary:
When WPD is performed in a ThinLTO backend, the function may be created
if it isn't already in that module. Module::getOrInsertFunction may
add a bitcast, in which case the returned Constant is not a Function and
doesn't have a name. Invoke stripPointerCasts() on the returned value
where we access its name.

Reviewers: pcc

Subscribers: mehdi_amini, inglorion, eraman, steven_wu, dexonsmith, llvm-commits

Differential Revision: https://reviews.llvm.org/D49959

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339640 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[CMake] Split -gx strip flag into -g -x
Petr Hosek [Tue, 14 Aug 2018 02:00:21 +0000 (02:00 +0000)]
[CMake] Split -gx strip flag into -g -x

llvm-strip doesn't handle -gx spelling, so we need to split these
as two separate flags.

Differential Revision: https://reviews.llvm.org/D50684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339639 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ThinLTO] Handle optional args in assembly format for ConstVCalls
Teresa Johnson [Tue, 14 Aug 2018 01:49:33 +0000 (01:49 +0000)]
[ThinLTO] Handle optional args in assembly format for ConstVCalls

Summary:
The AsmWriter was only writing the Args for a ConstVCall if it was
non-empty, however, the LLParser was always expecting it. To aid
in making it optional, surround the ConstVCall VFuncId and Args in
parentheses when writing, then make the Args optional when reading.

Reviewers: pcc

Subscribers: mehdi_amini, inglorion, eraman, steven_wu, dexonsmith, llvm-commits

Differential Revision: https://reviews.llvm.org/D49960

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339637 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[BasicAA] Don't assume tail calls with byval don't alias allocas
Reid Kleckner [Tue, 14 Aug 2018 01:24:35 +0000 (01:24 +0000)]
[BasicAA] Don't assume tail calls with byval don't alias allocas

Summary:
Calls marked 'tail' cannot read or write allocas from the current frame
because the current frame might be destroyed by the time they run.
However, a tail call may use an alloca with byval. Calling with byval
copies the contents of the alloca into argument registers or stack
slots, so there is no lifetime issue. Tail calls never modify allocas,
so we can return just ModRefInfo::Ref.

Fixes PR38466, a longstanding bug.

Reviewers: hfinkel, nlewycky, gbiv, george.burgess.iv

Subscribers: hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D50679

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339636 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRevert "[WebAssembly] Added default stack-only instruction mode for MC."
Wouter van Oortmerssen [Mon, 13 Aug 2018 23:12:49 +0000 (23:12 +0000)]
Revert "[WebAssembly] Added default stack-only instruction mode for MC."

This reverts commit 917a99b71ce21c975be7bfbf66f4040f965d9f3c.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339630 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Support] NFC: Allow modifying access/modification times independently in sys::fs...
Jordan Rupprecht [Mon, 13 Aug 2018 23:03:45 +0000 (23:03 +0000)]
[Support] NFC: Allow modifying access/modification times independently in sys::fs::setLastModificationAndAccessTime.

Summary:
Add an overload to sys::fs::setLastModificationAndAccessTime that allows setting last access and modification times separately. This will allow tools to use this API when they want to preserve both the access and modification times from an input file, which may be different.

Also note that both the POSIX (futimens/futimes) and Windows (SetFileTime) APIs take the two timestamps in the order of (1) access (2) modification time, so this renames the method to "setLastAccessAndModificationTime" to make it clear which timestamp is which.

For existing callers, the 1-arg overload just sets both timestamps to the same thing.

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D50521

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339628 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AST] Minor formatting cleanup [NFC]
Philip Reames [Mon, 13 Aug 2018 22:34:14 +0000 (22:34 +0000)]
[AST] Minor formatting cleanup [NFC]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339627 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AST] Cleanup code by using MemoryLocation utility [NFC]
Philip Reames [Mon, 13 Aug 2018 22:25:16 +0000 (22:25 +0000)]
[AST] Cleanup code by using MemoryLocation utility [NFC]

Differential Revision: https://reviews.llvm.org/D50588

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339625 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Don't ignore 0x66 prefix on relative jumps in 64-bit mode. Fix opcode selection...
Craig Topper [Mon, 13 Aug 2018 22:06:28 +0000 (22:06 +0000)]
[X86] Don't ignore 0x66 prefix on relative jumps in 64-bit mode. Fix opcode selection of relative jumps in 16-bit mode. Treat jno/jo like other jcc instructions.

The behavior in 64-bit mode is different between Intel and AMD CPUs. Intel ignores the 0x66 prefix. AMD does not. objump doesn't ignore the 0x66 prefix. Since LLVM aims to match objdump behavior, we should do the same.

While I was trying to fix this I had change brtarget16/32 to use ENCODING_IW/ID instead of ENCODING_Iv to get the 0x66+REX.W case to act sort of sanely. It's still wrong, but that's a problem for another day.

The change in encoding exposed the fact that 16-bit mode disassembly of relative jumps was creating JMP_4 with a 2 byte immediate. It should have been JMP_2. From just printing you can't tell the difference, but if you dumped the encoding it wouldn't have matched what we started with.

While fixing that, it exposed that jo/jno opcodes were missing from the switch that this patch deleted and there were no test cases for them.

Fixes PR38537.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339622 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] Re-land: Optimize redundant 'signed truncation check pattern'.
Roman Lebedev [Mon, 13 Aug 2018 21:54:37 +0000 (21:54 +0000)]
[InstCombine] Re-land: Optimize redundant 'signed truncation check pattern'.

Summary:
This comes with `Implicit Conversion Sanitizer - integer sign change` (D50250):
```
signed char test(unsigned int x) { return x; }
```
`clang++ -fsanitize=implicit-conversion -S -emit-llvm -o - /tmp/test.cpp -O3`
* Old: {F6904292}
* With this patch: {F6904294}

General pattern:
  X & Y

Where `Y` is checking that all the high bits (covered by a mask `4294967168`)
are uniform, i.e.  `%arg & 4294967168`  can be either  `4294967168`  or  `0`
Pattern can be one of:
  %t = add        i32 %arg,    128
  %r = icmp   ult i32 %t,      256
Or
  %t0 = shl       i32 %arg,    24
  %t1 = ashr      i32 %t0,     24
  %r  = icmp  eq  i32 %t1,     %arg
Or
  %t0 = trunc     i32 %arg  to i8
  %t1 = sext      i8  %t0   to i32
  %r  = icmp  eq  i32 %t1,     %arg
This pattern is a signed truncation check.

And `X` is checking that some bit in that same mask is zero.
I.e. can be one of:
  %r = icmp sgt i32   %arg,    -1
Or
  %t = and      i32   %arg,    2147483648
  %r = icmp eq  i32   %t,      0

Since we are checking that all the bits in that mask are the same,
and a particular bit is zero, what we are really checking is that all the
masked bits are zero.
So this should be transformed to:
  %r = icmp ult i32 %arg, 128

The transform itself ended up being rather horrible, even though i omitted some cases.
Surely there is some infrastructure that can help clean this up that i missed?

https://rise4fun.com/Alive/3Ou

The initial commit (rL339610)
was reverted, since the first assert was being triggered.
The @positive_with_extra_and test now has coverage for that case.

Reviewers: spatel, craig.topper

Reviewed By: spatel

Subscribers: RKSimon, erichkeane, vsk, llvm-commits

Differential Revision: https://reviews.llvm.org/D50465

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339621 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[NFC][InstCombine] Add a test for D50465 that used to assert
Roman Lebedev [Mon, 13 Aug 2018 21:49:33 +0000 (21:49 +0000)]
[NFC][InstCombine] Add a test for D50465 that used to assert

This is valid to fold, too.
https://rise4fun.com/Alive/0lz

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339619 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SimplifyLibCalls] don't drop fast-math-flags on trig reflection folds (retry r339608)
Sanjay Patel [Mon, 13 Aug 2018 21:49:19 +0000 (21:49 +0000)]
[SimplifyLibCalls] don't drop fast-math-flags on trig reflection folds (retry r339608)

Even though this code is below a function called optimizeFloatingPointLibCall(),
we apparently can't guarantee that we're dealing with FPMathOperators, so bail
out immediately if that's not true.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339618 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-objcopy] NFC: Fix minor formatting issues
Jordan Rupprecht [Mon, 13 Aug 2018 21:30:27 +0000 (21:30 +0000)]
[llvm-objcopy] NFC: Fix minor formatting issues

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339616 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRevert "[InstCombine] Optimize redundant 'signed truncation check pattern'."
Roman Lebedev [Mon, 13 Aug 2018 20:46:22 +0000 (20:46 +0000)]
Revert "[InstCombine] Optimize redundant 'signed truncation check pattern'."

At least one buildbot was able to actually trigger that assert
on the top of the function. Will investigate.

This reverts commit r339610.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339612 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] Optimize redundant 'signed truncation check pattern'.
Roman Lebedev [Mon, 13 Aug 2018 20:33:08 +0000 (20:33 +0000)]
[InstCombine] Optimize redundant 'signed truncation check pattern'.

Summary:
This comes with `Implicit Conversion Sanitizer - integer sign change` (D50250):
```
signed char test(unsigned int x) { return x; }
```
`clang++ -fsanitize=implicit-conversion -S -emit-llvm -o - /tmp/test.cpp -O3`
* Old: {F6904292}
* With this patch: {F6904294}

General pattern:
  X & Y

Where `Y` is checking that all the high bits (covered by a mask `4294967168`)
are uniform, i.e.  `%arg & 4294967168`  can be either  `4294967168`  or  `0`
Pattern can be one of:
  %t = add        i32 %arg,    128
  %r = icmp   ult i32 %t,      256
Or
  %t0 = shl       i32 %arg,    24
  %t1 = ashr      i32 %t0,     24
  %r  = icmp  eq  i32 %t1,     %arg
Or
  %t0 = trunc     i32 %arg  to i8
  %t1 = sext      i8  %t0   to i32
  %r  = icmp  eq  i32 %t1,     %arg
This pattern is a signed truncation check.

And `X` is checking that some bit in that same mask is zero.
I.e. can be one of:
  %r = icmp sgt i32   %arg,    -1
Or
  %t = and      i32   %arg,    2147483648
  %r = icmp eq  i32   %t,      0

Since we are checking that all the bits in that mask are the same,
and a particular bit is zero, what we are really checking is that all the
masked bits are zero.
So this should be transformed to:
  %r = icmp ult i32 %arg, 128

https://rise4fun.com/Alive/3Ou

Reviewers: spatel, craig.topper

Reviewed By: spatel

Subscribers: RKSimon, erichkeane, vsk, llvm-commits

Differential Revision: https://reviews.llvm.org/D50465

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339610 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agorevert r339608 - [SimplifyLibCalls] don't drop fast-math-flags on trig reflection...
Sanjay Patel [Mon, 13 Aug 2018 20:20:38 +0000 (20:20 +0000)]
revert r339608 - [SimplifyLibCalls] don't drop fast-math-flags on trig reflection folds

Can't set the builder flags without knowing this is an FPMathOperator. I'll add a test
for that and try again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339609 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SimplifyLibCalls] don't drop fast-math-flags on trig reflection folds
Sanjay Patel [Mon, 13 Aug 2018 20:14:27 +0000 (20:14 +0000)]
[SimplifyLibCalls] don't drop fast-math-flags on trig reflection folds

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339608 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoNFC: Add a test to LV showing that reduction is not possible when reduction var is...
Anna Thomas [Mon, 13 Aug 2018 19:55:25 +0000 (19:55 +0000)]
NFC: Add a test to LV showing that reduction is not possible when reduction var is reset in the loop

Added a test case to reduction showing where it's illegal to identify
vectorize a loop.
Resetting the reduction var during loop iterations disallows us from
widening the dependency cycle to VF, thereby making it illegal to
vectorize the loop.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339605 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SimplifyLibCalls] add reflection fold for -sin(-x) (PR38458)
Sanjay Patel [Mon, 13 Aug 2018 19:24:41 +0000 (19:24 +0000)]
[SimplifyLibCalls] add reflection fold for -sin(-x) (PR38458)

This is a very partial fix for the reported problem. I suspect
we do not get this fold in most motivating cases because most of
the time, the libcall would have been replaced by an intrinsic,
and that optimization is handled elsewhere...but maybe it should
be handled here?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339604 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine][NFC] Tests for 'signed truncation check' optimization
Roman Lebedev [Mon, 13 Aug 2018 18:51:09 +0000 (18:51 +0000)]
[InstCombine][NFC] Tests for 'signed truncation check' optimization

See D50465 for the actual opt itself.

Differential Revision: https://reviews.llvm.org/D50464

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339602 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[CodeGen] Fix assert in SelectionDAG::computeKnownBits
Scott Linder [Mon, 13 Aug 2018 18:44:21 +0000 (18:44 +0000)]
[CodeGen] Fix assert in SelectionDAG::computeKnownBits

Fix SelectionDAG::computeKnownBits asserting when handling EXTRACT_SUBVECTOR
when zero extending the demanded elements mask if it is already as long as the
source vector.

Differential Revision: https://reviews.llvm.org/D49574

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339600 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] add more tests for trig reflections; NFC (PR38458)
Sanjay Patel [Mon, 13 Aug 2018 18:34:32 +0000 (18:34 +0000)]
[InstCombine] add more tests for trig reflections; NFC (PR38458)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339598 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-mca] Propagate fatal llvm-mca errors from library classes to driver.
Matt Davis [Mon, 13 Aug 2018 18:11:48 +0000 (18:11 +0000)]
[llvm-mca] Propagate fatal llvm-mca errors from library classes to driver.

Summary:
This patch introduces error handling to propagate the errors from llvm-mca library classes (or what will become library classes) up to the driver.  This patch also introduces an enum to make clearer the intention of the return value for Stage::execute.

This supports PR38101.

Reviewers: andreadb, courbet, RKSimon

Reviewed By: andreadb

Subscribers: llvm-commits, tschuett, gbedwell

Differential Revision: https://reviews.llvm.org/D50561

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339594 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86][BtVer2] Use NoSchedPredicate to model default transitions in variant scheduling...
Andrea Di Biagio [Mon, 13 Aug 2018 17:52:39 +0000 (17:52 +0000)]
[X86][BtVer2] Use NoSchedPredicate to model default transitions in variant scheduling classes. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339589 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SimplifyLibCalls] reduce code for optimizeCos; NFCI
Sanjay Patel [Mon, 13 Aug 2018 17:40:49 +0000 (17:40 +0000)]
[SimplifyLibCalls] reduce code for optimizeCos; NFCI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339588 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAttempt to fix some MSVC build errors.
Erik Pilkington [Mon, 13 Aug 2018 17:39:19 +0000 (17:39 +0000)]
Attempt to fix some MSVC build errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339587 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ADT] Implemented unittests for ImmutableList
Kristof Umann [Mon, 13 Aug 2018 17:32:48 +0000 (17:32 +0000)]
[ADT] Implemented unittests for ImmutableList

Also fixed a typo that wasn't discovered as `create` was never instantiated.

Differential Revision: https://reviews.llvm.org/D50646

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339586 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] Limit simplifyAllocaArraySize constant folding to values that fit into...
Simon Pilgrim [Mon, 13 Aug 2018 16:50:20 +0000 (16:50 +0000)]
[InstCombine] Limit simplifyAllocaArraySize constant folding to values that fit into a uint64_t

Fixes OSS-Fuzz: https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=5223

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339584 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[itanium demangler] Add llvm::itaniumFindTypesInMangledName()
Erik Pilkington [Mon, 13 Aug 2018 16:37:47 +0000 (16:37 +0000)]
[itanium demangler] Add llvm::itaniumFindTypesInMangledName()

This function calls a callback whenever a <type> is parsed.

This is necessary to implement FindAlternateFunctionManglings in LLDB, which
uses a similar hack in FastDemangle. Once that function has been updated to use
this version, FastDemangle can finally be removed.

Differential revision: https://reviews.llvm.org/D50586

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339580 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] auto-generate full checks and add cos intrinsic test; NFC
Sanjay Patel [Mon, 13 Aug 2018 16:29:01 +0000 (16:29 +0000)]
[InstCombine] auto-generate full checks and add cos intrinsic test; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339579 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SLC] Expand simplification of pow() for vector types
Evandro Menezes [Mon, 13 Aug 2018 16:12:37 +0000 (16:12 +0000)]
[SLC] Expand simplification of pow() for vector types

Also consider vector constants when simplifying `pow()`.

Differential revision: https://reviews.llvm.org/D50035

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339578 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Tablegen] Replace uses of formatted_raw_ostream with raw_ostream in the predicate...
Andrea Di Biagio [Mon, 13 Aug 2018 15:13:35 +0000 (15:13 +0000)]
[Tablegen] Replace uses of formatted_raw_ostream with raw_ostream in the predicate expander. NFCI

This is a follow-up of r339552.

As pointed out by Craig in D50566, we don't need a formatted_raw_ostream to
indent strings. We can use instead raw_ostream::indent().

Internally, class PredicateExpander already keeps track of the current
indentation level. Also, the grammar for predicates is well parenthesized, and
therefore we don't need to use a formatted_raw_ostream to continuously track the
column number. Instead we can safely replace all the uses of
formatted_raw_ostream::PadToColumn() with uses of raw_ostream::indent().

By replacing formatted_raw_ostream with a simpler raw_ostream, we also avoid the
implicit check on the newline character on every print to stream.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339577 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Hexagon] Silence -Wuninitialized warning from GCC 5.4, NFC
Krzysztof Parzyszek [Mon, 13 Aug 2018 15:08:25 +0000 (15:08 +0000)]
[Hexagon] Silence -Wuninitialized warning from GCC 5.4, NFC

Patch by Kim Gräsman.

Differential Revision: https://reviews.llvm.org/D50623

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339576 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRevert "[Sparc] Add support for the cycle counter available in GR740"
Daniel Cederman [Mon, 13 Aug 2018 14:18:09 +0000 (14:18 +0000)]
Revert "[Sparc] Add support for the cycle counter available in GR740"

It breaks when using EXPENSIVE_CHECKS with the error message
"Bad machine code: Using an undefined physical register".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339570 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoCheck for tied operands
Sid Manning [Mon, 13 Aug 2018 14:01:25 +0000 (14:01 +0000)]
Check for tied operands

Differential Revision: https://reviews.llvm.org/D50592

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339567 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SystemZ] Increase the amount of inlining.
Jonas Paulsson [Mon, 13 Aug 2018 13:31:30 +0000 (13:31 +0000)]
[SystemZ]  Increase the amount of inlining.

Implement getInliningThresholdMultiplier() and have it return 3.

Review: Ulrich Weigand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339563 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Add tests showing missing div/rem 0, X -> 0 combines
Simon Pilgrim [Mon, 13 Aug 2018 13:29:54 +0000 (13:29 +0000)]
[X86] Add tests showing missing div/rem 0, X -> 0 combines

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339562 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[DAGCombiner] simplifyDivRem - add comment describing divide by undef/zero combine...
Simon Pilgrim [Mon, 13 Aug 2018 13:12:25 +0000 (13:12 +0000)]
[DAGCombiner] simplifyDivRem - add comment describing divide by undef/zero combine. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339561 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[CGP] Fix GEP issue with out of range APInt constant values not fitting in int64_t
Simon Pilgrim [Mon, 13 Aug 2018 12:10:09 +0000 (12:10 +0000)]
[CGP] Fix GEP issue with out of range APInt constant values not fitting in int64_t

Test case reduced from https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=7173

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339556 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Tablegen][SubtargetEmitter] Improve expansion of predicates of a variant scheduling...
Andrea Di Biagio [Mon, 13 Aug 2018 11:09:04 +0000 (11:09 +0000)]
[Tablegen][SubtargetEmitter] Improve expansion of predicates of a variant scheduling class.

This patch refactors the logic that expands predicates of a variant scheduling
class.

The idea is to improve the readability of the auto-generated code by removing
redundant parentheses around predicate expressions, and by removing redundant
if(true) statements.

This patch replaces the definition of NoSchedPred in TargetSchedule.td with an
instance of MCSchedPredicate. The new definition is sematically equivalent to
the previous one. The main difference is that now SubtargetEmitter knows that it
represents predicate "true".

Before this patch, we always generated an if (true) for the default transition
of a variant scheduling class.

Example (taken from AArch64GenSubtargetInfo.inc) :

```
if (SchedModel->getProcessorID() == 3) { // CycloneModel
  if ((TII->isScaledAddr(*MI)))
    return 927; // (WriteIS_WriteLD)_ReadBaseRS
  if ((true))
    return 928; // WriteLD_ReadDefault
}
```

Extra parentheses were also generated around the predicate expressions.

With this patch, we get the following auto-generated checks:

```
if (SchedModel->getProcessorID() == 3) { // CycloneModel
  if (TII->isScaledAddr(*MI))
    return 927; // (WriteIS_WriteLD)_ReadBaseRS
  return 928; // WriteLD_ReadDefault
}
```

The new auto-generated code behaves exactly the same as before. So, technically
this is a non functional change.

Differential revision: https://reviews.llvm.org/D50566

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339552 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Sparc] Add support for the cycle counter available in GR740
Daniel Cederman [Mon, 13 Aug 2018 10:49:48 +0000 (10:49 +0000)]
[Sparc] Add support for the cycle counter available in GR740

Summary: The GR740 provides an up cycle counter in the
registers ASR22 and ASR23. As these registers can not be
read together atomically we only use the value of ASR23
for llvm.readcyclecounter(). The ASR23 register holds the
32 LSBs of the up-counter.

Reviewers: jyknight, venkatra

Reviewed By: jyknight

Subscribers: fedor.sergeev, jrtc27, llvm-commits

Differential Revision: https://reviews.llvm.org/D48638

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339551 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRemove extra semicolon (fixes -Wpedantic warning). NFCI.
Simon Pilgrim [Mon, 13 Aug 2018 10:05:34 +0000 (10:05 +0000)]
Remove extra semicolon (fixes -Wpedantic warning). NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339549 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ARM] Added FP16 VREV Vector Instrinsic CodeGen support
Luke Geeson [Mon, 13 Aug 2018 08:37:41 +0000 (08:37 +0000)]
[ARM] Added FP16 VREV Vector Instrinsic CodeGen support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339546 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[GuardWidening] Widen very likely non-taken br instructions
Max Kazantsev [Mon, 13 Aug 2018 07:58:19 +0000 (07:58 +0000)]
[GuardWidening] Widen very likely non-taken br instructions

This is a second part of D49974 that handles widening of conditional branches that
have very likely `false` branch.

Differential Revision: https://reviews.llvm.org/D50040
Reviewed By: reames

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339537 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SelectionDAG] In PromoteFloatOp_BITCAST, insert a bitcast after the fp_to_fp16 in...
Craig Topper [Mon, 13 Aug 2018 06:53:49 +0000 (06:53 +0000)]
[SelectionDAG] In PromoteFloatOp_BITCAST, insert a bitcast after the fp_to_fp16 in case the result type isn't a scalar integer.

This is another variation of PR38533. In this case, the result type of the bitcast is legal and 16-bits wide, but not a scalar integer. So we need to emit the convert to i16 and then bitcast it to the true result type. This new bitcast will be further type legalized if necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339536 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SelectionDAG] In PromoteIntRes_BITCAST, when the input is TypePromoteFloat, make...
Craig Topper [Mon, 13 Aug 2018 06:53:47 +0000 (06:53 +0000)]
[SelectionDAG] In PromoteIntRes_BITCAST, when the input is TypePromoteFloat, make sure the output type is scalar. For vectors, use a store and load of temporary.

Previously if the result type was a vector, we emitted a FP_TO_FP16 with a vector result type which isn't valid.

This is basically the opposite case of the root cause of PR38533.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339535 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRestore correct x86_64 EH encodings in kernel code model
Lei Liu [Mon, 13 Aug 2018 06:06:53 +0000 (06:06 +0000)]
Restore correct x86_64 EH encodings in kernel code model

Fixes PR37524.

The exception handling encodings for x86_64 in kernel code model
has been changed with r309884.  Restore it to correct ones.  These
encodings include PersonalityEncoding, LSDAEncoding and
TTypeEncoding.

Differential Revision: https://reviews.llvm.org/D50490

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339534 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SelectionDAG] In PromoteFloatRes_BITCAST, insert a bitcast before the fp16_to_fp...
Craig Topper [Mon, 13 Aug 2018 05:26:49 +0000 (05:26 +0000)]
[SelectionDAG] In PromoteFloatRes_BITCAST, insert a bitcast before the fp16_to_fp in case the input type isn't an i16.

The bitcast can be further legalized as needed.

Fixes PR38533.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339533 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] Fix typo in comment. NFC
Craig Topper [Mon, 13 Aug 2018 00:54:23 +0000 (00:54 +0000)]
[InstCombine] Fix typo in comment. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339532 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] Replace call to haveNoCommonBitsSet in visitXor with just the special...
Craig Topper [Mon, 13 Aug 2018 00:38:27 +0000 (00:38 +0000)]
[InstCombine] Replace call to haveNoCommonBitsSet in visitXor with just the special case that doesn't use computeKnownBits.

Summary: computeKnownBits is expensive. The cases that would be detected by the computeKnownBits portion of haveNoCommonBitsSet were already handled by the earlier call to SimplifyDemandedInstructionBits.

Reviewers: spatel, lebedev.ri

Reviewed By: lebedev.ri

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D50604

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339531 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Add constant folding for AVX512 versions of scalar floating point to integer...
Craig Topper [Sun, 12 Aug 2018 22:09:54 +0000 (22:09 +0000)]
[X86] Add constant folding for AVX512 versions of scalar floating point to integer conversion intrinsics.

Summary:
We've supported constant folding for sse versions for many years. This patch adds support for the avx512 versions including unsigned with the default rounding mode. We could probably do more with other roundings modes and SAE in the future.

The test cases are largely based on the sse.ll test cases. But I did add some test cases to ensure the unsigned versions don't accept negative values. Also checked the bounds of f64->i32 conversions to make sure unsigned has a larger positive range than signed.

Reviewers: RKSimon, spatel, chandlerc

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D50553

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339529 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[globalisel] Remove dead code from GlobalISelEmitter
Daniel Sanders [Sun, 12 Aug 2018 21:49:42 +0000 (21:49 +0000)]
[globalisel] Remove dead code from GlobalISelEmitter

Summary: Found by GCC's -Wunused-function.

Patch by Kim Gräsman

Reviewers: ab, dsanders, llvm-commits

Reviewed By: dsanders

Subscribers: rovka, kristof.beyls

Differential Revision: https://reviews.llvm.org/D50611

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339528 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAMDGPU: Cleanup min/max legacy tests
Matt Arsenault [Sun, 12 Aug 2018 19:29:53 +0000 (19:29 +0000)]
AMDGPU: Cleanup min/max legacy tests

Also add some more tests in preparation for
a future patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339526 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoDAG: Check no-signed-zeros instead of unsafe-fp-math
Matt Arsenault [Sun, 12 Aug 2018 19:09:12 +0000 (19:09 +0000)]
DAG: Check no-signed-zeros instead of unsafe-fp-math

Addresses fixme, although this should still be checking individual
operand flags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339525 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[NFC] Fixed build, updated tests
David Bolvansky [Sun, 12 Aug 2018 18:32:53 +0000 (18:32 +0000)]
[NFC] Fixed build, updated tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339524 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[NFC] Renamed test file
David Bolvansky [Sun, 12 Aug 2018 17:43:27 +0000 (17:43 +0000)]
[NFC] Renamed test file

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339523 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Support][JSON][NFC] Silence GCC warning about broken strict aliasing rules
David Bolvansky [Sun, 12 Aug 2018 17:31:46 +0000 (17:31 +0000)]
[Support][JSON][NFC] Silence GCC warning about broken strict aliasing rules

Summary:
The as<T>() method would trigger the following warning on GCC <7:

   warning: dereferencing type-punned pointer will break
       strict-aliasing rules [-Wstrict-aliasing]

     return *reinterpret_cast<T *>(Union.buffer);
                                               ^

Union.buffer is guaranteed to be aligned to whatever types it contains,
and json::Value maintains the invariant that it only calls as<T>() for a
T it has previously placement-newed into Union.buffer. This should
follow the rules for strict aliasing.

Using two static_cast via void * instead of reinterpret_cast
silences the warning and presumably makes GCC understand that no
strict-aliasing violation is happening.

No functional change intended.

Patch by: kimgr (Kim Gräsman)

Reviewers: sammccall, xiangzhai, HaoLiu, llvm-commits, xbolva00

Reviewed By: sammccall, xbolva00

Subscribers: xbolva00

Differential Revision: https://reviews.llvm.org/D50608

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339521 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] Fold Select with binary op - non-commutative opcodes
David Bolvansky [Sun, 12 Aug 2018 17:30:07 +0000 (17:30 +0000)]
[InstCombine] Fold Select with binary op - non-commutative opcodes

Summary:
Basic version was merged - https://reviews.llvm.org/D49954

This adds support for FP & non-commutative opcodes

Precommited tests: https://reviews.llvm.org/rL338727

Reviewers: spatel, lebedev.ri

Reviewed By: spatel

Subscribers: jfb

Differential Revision: https://reviews.llvm.org/D50190

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339520 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] fix/enhance fadd/fsub factorization
Sanjay Patel [Sun, 12 Aug 2018 15:48:26 +0000 (15:48 +0000)]
[InstCombine] fix/enhance fadd/fsub factorization
  (X * Z) + (Y * Z) --> (X + Y) * Z
  (X * Z) - (Y * Z) --> (X - Y) * Z
  (X / Z) + (Y / Z) --> (X + Y) / Z
  (X / Z) - (Y / Z) --> (X - Y) / Z

The existing code that implemented these folds failed to
optimize vectors, and it transformed code with multiple
uses when it should not have.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339519 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] move/add tests for fadd/fsub factorization; NFC
Sanjay Patel [Sun, 12 Aug 2018 15:06:15 +0000 (15:06 +0000)]
[InstCombine] move/add tests for fadd/fsub factorization; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339518 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstSimplify] Guard against large shift amounts.
Benjamin Kramer [Sun, 12 Aug 2018 11:43:03 +0000 (11:43 +0000)]
[InstSimplify] Guard against large shift amounts.

These are always UB, but can happen for large integer inputs. Testing it
is very fragile as -simplifycfg will nuke the UB top-down.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339515 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAMDGPU: Check NSZ MI flag when folding omod
Matt Arsenault [Sun, 12 Aug 2018 08:44:25 +0000 (08:44 +0000)]
AMDGPU: Check NSZ MI flag when folding omod

I'm not sure the exact nsz flag combination that
is OK. I think as long as it's on either, this is OK.
For now just check it on the omod multiply.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339513 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAMDGPU: Use splat vectors for undefs when folding canonicalize
Matt Arsenault [Sun, 12 Aug 2018 08:42:54 +0000 (08:42 +0000)]
AMDGPU: Use splat vectors for undefs when folding canonicalize

If one of the elements is undef, use the canonicalized constant
from the other element instead of 0.

Splat vectors are more useful for other optimizations, such
as matching vector clamps. This was breaking on clamps
of half3 from the undef 4th component.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339512 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAMDGPU: Fix packing undef parts of build_vector
Matt Arsenault [Sun, 12 Aug 2018 08:42:46 +0000 (08:42 +0000)]
AMDGPU: Fix packing undef parts of build_vector

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339511 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[TargetLowering] Simplify one of the special cases in SimplifyDemandedBits for XOR...
Craig Topper [Sun, 12 Aug 2018 06:52:03 +0000 (06:52 +0000)]
[TargetLowering] Simplify one of the special cases in SimplifyDemandedBits for XOR. NFCI

We were checking for all bits being Known by checking Known.Zero|Known.One, but if all the bits are known then the value should be a Constant and we can just check for that instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339509 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[TargetLowering] Use APInt::isSubsetOf to simplify some code. NFC
Craig Topper [Sun, 12 Aug 2018 05:34:15 +0000 (05:34 +0000)]
[TargetLowering] Use APInt::isSubsetOf to simplify some code. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339508 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Remove unnecessary AddedComplexity line. NFC
Craig Topper [Sun, 12 Aug 2018 03:22:18 +0000 (03:22 +0000)]
[X86] Remove unnecessary AddedComplexity line. NFC

The use of the or_is_add predicate already gives enough of a complexity boost to get the patterns ordered properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339507 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Dominators] Remove the DeferredDominance class
Chijun Sima [Sat, 11 Aug 2018 08:12:07 +0000 (08:12 +0000)]
[Dominators] Remove the DeferredDominance class

Summary: After converting all existing passes to use the new DomTreeUpdater interface, there isn't any usage of the original DeferredDominance class. Thus, we can safely remove it from the codebase.

Reviewers: kuhar, brzycki, dmgreen, davide, grosser

Reviewed By: kuhar, brzycki

Subscribers: mgorny, llvm-commits

Differential Revision: https://reviews.llvm.org/D49747

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339502 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[UnJ] Improve explicit loop count checks
David Green [Sat, 11 Aug 2018 07:37:31 +0000 (07:37 +0000)]
[UnJ] Improve explicit loop count checks

Try to improve the computed counts when it has been explicitly set by a pragma
or command line option. This moves the code around, so that first call to
computeUnrollCount to get a sensible count and override that if explicit unroll
and jam counts are specified.

Also added some extra debug messages for when unroll and jamming is disabled.

Differential Revision: https://reviews.llvm.org/D50075

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339501 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[UnJ] Create a hasInvariantIterationCount function. NFC
David Green [Sat, 11 Aug 2018 06:57:28 +0000 (06:57 +0000)]
[UnJ] Create a hasInvariantIterationCount function. NFC

Pulled out a separate function for some code that calculates
if an inner loop iteration count is invariant to it's outer
loop.

Differential Revision: https://reviews.llvm.org/D50063

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339500 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Remove the AL/AX/EAX/RAX short immediate forms from the macro fusion shouldSche...
Craig Topper [Sat, 11 Aug 2018 06:42:51 +0000 (06:42 +0000)]
[X86] Remove the AL/AX/EAX/RAX short immediate forms from the macro fusion shouldScheduleAdjacent. NFC

These instructions are only created by the backend during MCInst lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339499 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Add the mem-reg form of CMP to the macro fusion shouldScheduleAdjacent.
Craig Topper [Sat, 11 Aug 2018 06:42:50 +0000 (06:42 +0000)]
[X86] Add the mem-reg form of CMP to the macro fusion shouldScheduleAdjacent.

Unlike the other arithmetic instructions the mem-reg form of compare is just a load and not a RMW operation. According to the Intel optimization manual, this form is also supported by macro fusion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339498 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Remove ADD8mi and ADDmr from the macro fusion shouldScheduleAdjacent.
Craig Topper [Sat, 11 Aug 2018 06:42:49 +0000 (06:42 +0000)]
[X86] Remove ADD8mi and ADDmr from the macro fusion shouldScheduleAdjacent.

The are RMW of memory operations. They aren't eligible for macro fusion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339497 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Change the MOV32ri64 pseudo instruction to def a GR64 directly instead of wrapp...
Craig Topper [Sat, 11 Aug 2018 05:33:00 +0000 (05:33 +0000)]
[X86] Change the MOV32ri64 pseudo instruction to def a GR64 directly instead of wrapping it in a SUBREG_TO_REG.

Now we switch to the subregister in expandPostRAPseudos where we already switched the opcode.

This simplifies a few isel patterns that used the pseudo directly. And magically seems to have improved our ability to CSE it in the undef-label.ll test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339496 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFix WebAssembly instruction printer after r339474
Richard Trieu [Sat, 11 Aug 2018 04:18:05 +0000 (04:18 +0000)]
Fix WebAssembly instruction printer after r339474

Treat the stack variants of control instructions the same as regular
instructions.  Otherwise, the vector ControlFlowStack will be the wrong
size and have out-of-bounds access.  This was detected by MemorySanitizer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339495 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[gold] Fix Tests cases on i686
Tom Stellard [Sat, 11 Aug 2018 01:08:34 +0000 (01:08 +0000)]
[gold] Fix Tests cases on i686

Reviewers: tejohnson

Reviewed By: tejohnson

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D50583

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339492 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAMDGPU/GlobalISel: Define instruction mapping for G_INSERT
Tom Stellard [Sat, 11 Aug 2018 00:51:54 +0000 (00:51 +0000)]
AMDGPU/GlobalISel: Define instruction mapping for G_INSERT

Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D49625

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339491 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRe-commit "[NFC] More ConstantMerge refactoring"
JF Bastien [Fri, 10 Aug 2018 22:41:09 +0000 (22:41 +0000)]
Re-commit "[NFC] More ConstantMerge refactoring"

My previous change moved some code upwards which caused an assert in debug mode
because the global value didn't necessarily have an initializer. Don't do that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339485 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[LICM] Hoist assumes out of loops
Philip Reames [Fri, 10 Aug 2018 22:21:56 +0000 (22:21 +0000)]
[LICM] Hoist assumes out of loops

If we have an assume which is known to execute and whose operand is invariant, we can lift that into the pre-header. So long as we don't change which paths the assume executes on, this is a legal transformation. It's likely to be a useful canonicalization as other transforms only look for dominating assumes.

Differential Revision: https://reviews.llvm.org/D50364

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339481 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRevert "[NFC] More ConstantMerge refactoring"
JF Bastien [Fri, 10 Aug 2018 22:10:20 +0000 (22:10 +0000)]
Revert "[NFC] More ConstantMerge refactoring"

Sanitizers seem unhappy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339480 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFix unused lambda capture warning from r339472.
Eli Friedman [Fri, 10 Aug 2018 22:03:25 +0000 (22:03 +0000)]
Fix unused lambda capture warning from r339472.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339479 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[NFC] More ConstantMerge refactoring
JF Bastien [Fri, 10 Aug 2018 21:58:00 +0000 (21:58 +0000)]
[NFC] More ConstantMerge refactoring

This makes my upcoming patch much easier to read.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339478 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[WebAssembly] Added default stack-only instruction mode for MC.
Wouter van Oortmerssen [Fri, 10 Aug 2018 21:32:47 +0000 (21:32 +0000)]
[WebAssembly] Added default stack-only instruction mode for MC.

Summary:
Moved Explicit Locals pass to last.
Made that pass obligatory.
Made it convert from register to stack based instructions, and removed the registers.
Fixes to related code that was expecting register based instructions.
Added the correct testing flag to all tests, depending on what the
format they were expecting so far.
Translated one test to stack format as example: reg-stackify-stack.ll

tested:
llvm-lit -v `find test -name WebAssembly`
unittests/MC/*

Reviewers: dschuff, sunfish

Subscribers: jfb, llvm-commits, aheejin, eraman, jgravelle-google, sbc100

Differential Revision: https://reviews.llvm.org/D50568

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339474 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ARM] Adjust AND immediates to make them cheaper to select.
Eli Friedman [Fri, 10 Aug 2018 21:21:53 +0000 (21:21 +0000)]
[ARM] Adjust AND immediates to make them cheaper to select.

LLVM normally prefers to minimize the number of bits set in an AND
immediate, but that doesn't always match the available ARM instructions.
In Thumb1 mode, prefer uxtb or uxth where possible; otherwise, prefer
a two-instruction sequence movs+ands or movs+bics.

Some potential improvements outlined in
ARMTargetLowering::targetShrinkDemandedConstant, but seems to work
pretty well already.

The ARMISelDAGToDAG fix ensures we don't generate an invalid UBFX
instruction due to a larger-than-expected mask. (It's orthogonal, in
some sense, but as far as I can tell it's either impossible or nearly
impossible to reproduce the bug without this change.)

According to my testing, this seems to consistently improve codesize by
a small amount by forming bic more often for ISD::AND with an immediate.

Differential Revision: https://reviews.llvm.org/D50030

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339472 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[MS Demangler] Support extern "C" functions.
Zachary Turner [Fri, 10 Aug 2018 21:09:05 +0000 (21:09 +0000)]
[MS Demangler] Support extern "C" functions.

There are two cases we need to support with extern "C"
functions.  The first is the case of a '9' indicating that
the function has no prototype.  This occurs when we mangle
a symbol inside of an extern "C" function, but not the
function itself.

The second case is when we have an overloaded extern "C"
functions.  In this case we emit $$J0 to indicate this.
This patch adds support for both of these cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339471 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] add tests for fsub factorization; NFC
Sanjay Patel [Fri, 10 Aug 2018 21:00:27 +0000 (21:00 +0000)]
[InstCombine] add tests for fsub factorization; NFC

The tests show that;
1. The fold doesn't fire for vectors, but it should.
2. The fold fires regardless of uses, but it shouldn't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339470 91177308-0d34-0410-b5e6-96231b3b80d8