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Bill Buzbee [Mon, 1 Dec 2014 19:10:14 +0000 (19:10 +0000)]
Merge "ART: x86 specific clearing higher bits when converting long to int"
Vladimir Marko [Mon, 1 Dec 2014 19:04:28 +0000 (19:04 +0000)]
Merge "Quick: Fix neg-long on ARM for overlapping regs."
Vladimir Marko [Mon, 1 Dec 2014 17:57:04 +0000 (17:57 +0000)]
Merge "Refactor handling of conditional branches with known result."
Vladimir Marko [Mon, 1 Dec 2014 17:56:41 +0000 (17:56 +0000)]
Merge "Quick: Use 16-bit conditional branch in Thumb2."
Vladimir Marko [Mon, 1 Dec 2014 17:56:27 +0000 (17:56 +0000)]
Merge "Quick: Use 16-bit Thumb2 PUSH/POP when possible."
Vladimir Marko [Mon, 1 Dec 2014 16:48:48 +0000 (16:48 +0000)]
Quick: Fix neg-long on ARM for overlapping regs.
Bug:
18569347
Change-Id: I764a4648b7ea5fd92f1ffbb9038b9d101b50d137
Nicolas Geoffray [Mon, 1 Dec 2014 14:52:01 +0000 (14:52 +0000)]
Merge "Remove type conversion nodes converting to the same type."
Nicolas Geoffray [Mon, 1 Dec 2014 14:16:20 +0000 (14:16 +0000)]
Remove type conversion nodes converting to the same type.
When optimizing, we ensure these conversions do not reach the
code generators. When not optimizing, we cannot get such situations.
Change-Id: I717247c957667675dc261183019c88efa3a38452
Nicolas Geoffray [Mon, 1 Dec 2014 12:29:09 +0000 (12:29 +0000)]
Merge "Opt Compiler: Arm64: Add support for more IRs plus various fixes."
Nicolas Geoffray [Mon, 1 Dec 2014 12:28:51 +0000 (12:28 +0000)]
Merge "Vixl: Update the VIXL interface to VIXL 1.7 and enable VIXL debug."
Nicolas Geoffray [Mon, 1 Dec 2014 12:04:49 +0000 (12:04 +0000)]
Merge "Fix insertion of parallel move when connecting siblings."
Nicolas Geoffray [Mon, 1 Dec 2014 09:50:04 +0000 (09:50 +0000)]
Fix insertion of parallel move when connecting siblings.
Also add a check that ensures parallel moves have been inserted
correctly.
This fixes tests:
org.apache.harmony.tests.java.util.BitSetTest#test_nextSetBitI
org.apache.harmony.tests.java.util.BitSetTest#test_31036_set
On host/x64.
Change-Id: I59d29aca393b5344bac933e2813ab409fea9d9b5
Nicolas Geoffray [Mon, 1 Dec 2014 10:40:12 +0000 (10:40 +0000)]
Merge "Don't walk the libcore tree when finding tests."
Nicolas Geoffray [Mon, 1 Dec 2014 10:12:15 +0000 (10:12 +0000)]
Don't walk the libcore tree when finding tests.
vogar will run tests twice if it is given, for example,
libcore.java.lang and libcore.java.lang.ref.
Also currently disable math tests until expectations/fixes
are in.
Change-Id: Iba2edad3ce0a6b27947ce6897d70abedf8d1e6b3
Nicolas Geoffray [Fri, 28 Nov 2014 16:27:01 +0000 (16:27 +0000)]
Merge "Print the right default for the compiler backend."
Nicolas Geoffray [Fri, 28 Nov 2014 16:22:11 +0000 (16:22 +0000)]
Print the right default for the compiler backend.
Change-Id: I7083c640af6e2af1c333d5551ba2391ab672954d
Nicolas Geoffray [Fri, 28 Nov 2014 16:04:38 +0000 (16:04 +0000)]
Merge "Don't use CanHoldArm in the code generator."
Nicolas Geoffray [Fri, 28 Nov 2014 15:00:02 +0000 (15:00 +0000)]
Don't use CanHoldArm in the code generator.
CanHoldArm was ARM32 specific. Instead use a virtual
Assembler::ShifterOperandCanHold that both thumb2 and arm32
implement.
Change-Id: I33794a93caf02ee5d78d32a8471d9fd6fe4f0a00
Nicolas Geoffray [Fri, 28 Nov 2014 15:54:54 +0000 (15:54 +0000)]
Merge "Add a script for running libcore tests."
Nicolas Geoffray [Fri, 28 Nov 2014 14:24:28 +0000 (14:24 +0000)]
Add a script for running libcore tests.
Script contains a list of packages that have no vogar failures,
that is, vogar finds the right test expectations.
Change-Id: Ie47bead6bb5457d055498570204187a54db45efa
Vladimir Marko [Fri, 28 Nov 2014 13:38:28 +0000 (13:38 +0000)]
Refactor handling of conditional branches with known result.
Detect IF_cc and IF_ccZ instructions with known results in
the basic block optimization phase (instead for the codegen
phase) and replace them with GOTO/NOP. Kill blocks that are
unreachable as a result.
Change-Id: I169c2fa6f1e8af685f4f3a7fe622f5da862ce329
Serban Constantinescu [Thu, 13 Nov 2014 14:05:07 +0000 (14:05 +0000)]
Opt Compiler: Arm64: Add support for more IRs plus various fixes.
Add support for more IRs and update others.
Change-Id: Iae1bef01dc3c0d238a46fbd2800e71c38288b1d2
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
Serban Constantinescu [Tue, 25 Nov 2014 20:05:46 +0000 (20:05 +0000)]
Vixl: Update the VIXL interface to VIXL 1.7 and enable VIXL debug.
This patch updates the interface to VIXL 1.7 and enables the debug version of
VIXL when ART is built in debug mode.
Change-Id: I443fb941bec3cffefba7038f93bb972e6b7d8db5
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
Nicolas Geoffray [Fri, 28 Nov 2014 11:26:24 +0000 (11:26 +0000)]
Merge "Fix a bug in the linear scan register allocator."
Nicolas Geoffray [Fri, 28 Nov 2014 11:07:27 +0000 (11:07 +0000)]
Merge "Fix bogus assumption for live registers at safe point."
Nicolas Geoffray [Fri, 28 Nov 2014 11:06:26 +0000 (11:06 +0000)]
Merge "Fix a bug in GVN."
Nicolas Geoffray [Thu, 27 Nov 2014 12:01:59 +0000 (12:01 +0000)]
Fix a bug in GVN.
When a predecessor block was killing instructions in a set, we were
not taking into account side effects of blocks between the dominator to
this predecessor.
Implementation now intersects the copied set of the dominator with
the predecessors to take these side effects into account.
Change-Id: If297439cc4e50cee91e9fffd028216a3e49e19ef
Roland Levillain [Fri, 28 Nov 2014 10:29:35 +0000 (10:29 +0000)]
Merge "Add support for long-to-float in the optimizing compiler."
Roland Levillain [Thu, 27 Nov 2014 18:31:21 +0000 (18:31 +0000)]
Add support for long-to-float in the optimizing compiler.
- Add support for the long-to-float Dex instruction in the
optimizing compiler.
- Have art::x86_64::X86_64Assembler::cvtsi2ss work with
64-bit operands.
- Generate x86, x86-64 and ARM (but not ARM64) code for
long to float HTypeConversion nodes.
- Add related tests to test/422-type-conversion.
Change-Id: Ic983cbeb1ae2051add40bc519a8f00a6196166c9
Roland Levillain [Thu, 27 Nov 2014 17:32:58 +0000 (17:32 +0000)]
Merge "Wrap long lines in the optimizing compiler."
Roland Levillain [Thu, 27 Nov 2014 17:15:16 +0000 (17:15 +0000)]
Wrap long lines in the optimizing compiler.
Change-Id: I5dee0c65e6652de574ae952b1f1dfc7355859e45
Roland Levillain [Thu, 27 Nov 2014 15:42:08 +0000 (15:42 +0000)]
Merge "Ensure opt. compiler doesn't get core & FP registers mixed up."
Roland Levillain [Thu, 27 Nov 2014 15:41:28 +0000 (15:41 +0000)]
Merge "Fix neg-float & neg-double for null values in opt. compiler."
Nicolas Geoffray [Thu, 27 Nov 2014 15:38:07 +0000 (15:38 +0000)]
Merge "Fix Move64 by using ParallelMoves."
Nicolas Geoffray [Thu, 27 Nov 2014 14:54:18 +0000 (14:54 +0000)]
Fix Move64 by using ParallelMoves.
Destination and source might overlap in a Move64, so we have to
use a parallel move resolver.
Change-Id: Ica6c72d91ab8e2e2ee4661b211ac1ee8f054b9ef
Roland Levillain [Thu, 27 Nov 2014 15:23:57 +0000 (15:23 +0000)]
Ensure opt. compiler doesn't get core & FP registers mixed up.
Replace Location::As<T>() with two method methods
(Location::AsRegister<T>() and Location::AsFpuRegister<T>())
checking the kind of the location (register).
Change-Id: I22b4abee1a124b684becd2dc1caf33652b911070
Roland Levillain [Thu, 27 Nov 2014 15:03:41 +0000 (15:03 +0000)]
Fix neg-float & neg-double for null values in opt. compiler.
- Implement float and double negation as an exclusive or
with a bit sign mask in x86 and x86-64 code generators.
- Enable requests of temporary FPU (double) registers during
register allocation.
- Update test cases in test/415-optimizing-arith-neg.
Change-Id: I9572c24b27c645ba698825e60cd5b3956b4895fa
Calin Juravle [Thu, 27 Nov 2014 13:13:34 +0000 (13:13 +0000)]
Merge "[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}"
Calin Juravle [Tue, 25 Nov 2014 20:56:51 +0000 (20:56 +0000)]
[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}
Adds:
- float comparison for arm, x86, x86_64 backends.
- ucomis{s,d} assembly to x86 and x86_64.
- vmstat assebmly for thumb2
- new assembly tests
Change-Id: Ie3e19d0c08b3b875cd0a4be4ee4e9c8a4a076290
Roland Levillain [Thu, 27 Nov 2014 12:30:22 +0000 (12:30 +0000)]
Merge "Add support for long-to-double in the optimizing compiler."
Vladimir Marko [Thu, 27 Nov 2014 12:26:18 +0000 (12:26 +0000)]
Merge "Optimizing: Use 16-bit Thumb2 PUSH/POP when possible."
Roland Levillain [Thu, 27 Nov 2014 12:06:00 +0000 (12:06 +0000)]
Add support for long-to-double in the optimizing compiler.
- Add support for the long-to-double Dex instruction in the
optimizing compiler.
- Enable requests of temporary FPU (double) registers during
code generation.
- Fix art::x86::X86Assembler::LoadLongConstant and extend
it to int64_t values.
- Have art::x86_64::X86_64Assembler::cvtsi2sd work with
64-bit operands.
- Generate x86, x86-64 and ARM (but not ARM64) code for
long to double HTypeConversion nodes.
- Add related tests to test/422-type-conversion.
Change-Id: Ie73d9e5e25bd2e15f585c371e8fc2dcb83438ccd
Yevgeny Rouban [Wed, 26 Nov 2014 12:11:54 +0000 (18:11 +0600)]
ART: x86 specific clearing higher bits when converting long to int
The following problem description is taken from
https://android-review.googlesource.com/107261
If destination and source of long-to-int is the same physical
register on 64-bit then we do not emit any instructions but
consider that destination is a 32-bit view of source register.
As a result high part contains garbage. If the destination is
used later as index to array access then this garbage is used
in computation of address because address is 64-bit. For all
other cases garbage is just ignored.
A generic solution (113023) for all hw platforms was suggested
but rejected later for the sake of HW specific solution:
https://android-review.googlesource.com/113023
https://android-review.googlesource.com/114436
This patch is a rework of patch 113023 to stick with x86_64
specific changes: for 64-bit target this patch forces generating
reg-to-reg copy if the src and dest are the same physical
registers. This makes the higher bits be zeroed by 32-bit move
instruction.
Change-Id: Id29af839506ff9319ffba08b2e86e240fef4dafd
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Signed-off-by: Yevgeny Rouban <yevgeny.y.rouban@intel.com>
Mathieu Chartier [Thu, 27 Nov 2014 00:06:57 +0000 (00:06 +0000)]
Merge "Trim reference tables when we trim the heap"
Mathieu Chartier [Wed, 26 Nov 2014 19:21:15 +0000 (11:21 -0800)]
Trim reference tables when we trim the heap
Before:
System server:
virtual shared shared private private
size RSS PSS clean dirty clean dirty # object
2200 300 229 0 80 0 220 77 /dev/ashmem/dalvik-indirect ref table (deleted)
Location:
1896 128 102 0 28 0 100 39 /dev/ashmem/dalvik-indirect ref table (deleted)
After:
virtual shared shared private private
size RSS PSS clean dirty clean dirty # object
System server:
2216 64 64 0 0 0 64 79 /dev/ashmem/dalvik-indirect ref table (deleted)
Location:
2120 48 48 0 0 0 48 67 /dev/ashmem/dalvik-indirect ref table (deleted)
No pause time regression measured in memalloc test.
(cherry picked from commit
84dc99d2fa67e5dff018685661cb2bff62132989)
Change-Id: I80d9bd3b98e888fa8f77d03df69f8479ed209986
Mathieu Chartier [Thu, 27 Nov 2014 00:06:30 +0000 (00:06 +0000)]
Merge "Add a way to change the IMT size"
Stephen Hines [Wed, 26 Nov 2014 22:32:34 +0000 (22:32 +0000)]
Merge "Add a missing SHARED_LOCKS_REQUIRED(mutator_lock_)."
Mathieu Chartier [Wed, 26 Nov 2014 02:36:01 +0000 (18:36 -0800)]
Add a way to change the IMT size
Useful for having smaller imts on memory constrainted devices.
Setting ART_IMT_SIZE=x will change the size of the IMT.
(cherry picked from commit
8ee96437f8cd24e1eb0b2adc6cef3346ed4b6a98)
Change-Id: Ia74946ffc57ad32de5a8d60be3412462f19f8076
Nicolas Geoffray [Wed, 26 Nov 2014 18:30:23 +0000 (18:30 +0000)]
Fix a bug in the linear scan register allocator.
Triggered by:
org.apache.harmony.tests.java.util.jar.JarFileTest#testGetJarEntry.
By miscompling:
okhttp.CacheControl#parse.
A move occuring just before the first instruction of a block
should not be handled by ConnectSplitSiblings, but by ConnectSiblings
instead.
Change-Id: I8ad409734809e6787bb7321563e1331e7a6906c0
Vladimir Marko [Wed, 26 Nov 2014 18:09:30 +0000 (18:09 +0000)]
Optimizing: Use 16-bit Thumb2 PUSH/POP when possible.
JNI compiler uses the same assembler but always pushes
and pops registers that require the 32-bit PUSH/POP.
Change-Id: I7e857ae799316586cd09d6547cf971ef439af147
Calin Juravle [Wed, 26 Nov 2014 19:01:33 +0000 (19:01 +0000)]
Merge "Revert "[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}""
Calin Juravle [Wed, 26 Nov 2014 19:01:09 +0000 (19:01 +0000)]
Revert "[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}"
Fails on arm due to missing vmrs op after vcmp. I revert this instead of pushing the fix because I don't understand yet why it compiles with run-test but not with dex2oat.
This reverts commit
fd861249f31ab360c12dd1ffb131d50f02b0bfc6.
Change-Id: Idc2d30f6a0f39ddd3596aa18a532ae90f8aaf62f
Andreas Gampe [Wed, 26 Nov 2014 17:52:32 +0000 (17:52 +0000)]
Merge "ART: Use Overwrite instead of Put"
Calin Juravle [Wed, 26 Nov 2014 17:03:53 +0000 (17:03 +0000)]
Merge "[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}"
Calin Juravle [Tue, 25 Nov 2014 20:56:51 +0000 (20:56 +0000)]
[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}
- adds float comparison for arm, x86, x86_64 backends.
- adds ucomis{s,d} assembly to x86 and x86_64.
Change-Id: I232d2b6e9ecf373beb5cc63698dd97a658ff9c83
Vladimir Marko [Wed, 26 Nov 2014 12:33:45 +0000 (12:33 +0000)]
Quick: Use 16-bit conditional branch in Thumb2.
We were using the 32-bit version because the compilation
time impact of having to change the instruction length and
reassemble instructions when the target is out of range was
too high. However, the assembly phase has been rewritten
since making that decision and the compile time impact is
now insignificant, so we prefer to save space.
Change-Id: Ib90f90d3f4e0c4e310267af272e3b16611026bbe
Vladimir Marko [Wed, 26 Nov 2014 15:42:32 +0000 (15:42 +0000)]
Quick: Use 16-bit Thumb2 PUSH/POP when possible.
Generate correct PUSH/POP in Gen{Entry,Exit}Sequence()
to avoid extra processing during insn fixup.
Change-Id: I396168e2a42faee6980d40779c7de9657531867b
Nicolas Geoffray [Wed, 26 Nov 2014 15:46:52 +0000 (15:46 +0000)]
Fix bogus assumption for live registers at safe point.
We did not take into account inactive intervals going
into active when computing live registers at a slow path
safe point. So we must ensure the safepoint interval is always
handled after all intervals starting at the same position have
been handled.
Change-Id: I05ea2161016a90b0ee3ba0b18cd54a8e46860f1e
Nicolas Geoffray [Wed, 26 Nov 2014 14:46:09 +0000 (14:46 +0000)]
Merge "Revert "[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}""
Nicolas Geoffray [Wed, 26 Nov 2014 14:45:52 +0000 (14:45 +0000)]
Revert "[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}"
Fails on x86_64 and target.
This reverts commit
cea28ec4b9e94ec942899acf1dbf20f8999b36b4.
Change-Id: I30c1d188c7ecfe765f137a307022ede84f15482c
Calin Juravle [Wed, 26 Nov 2014 12:04:39 +0000 (12:04 +0000)]
Merge "[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}"
Nicolas Geoffray [Wed, 26 Nov 2014 12:00:16 +0000 (12:00 +0000)]
Merge "Add ART_USE_OPTIMIZING_COMPILER flag."
Calin Juravle [Tue, 25 Nov 2014 20:56:51 +0000 (20:56 +0000)]
[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}
- adds float comparison for arm, x86, x86_64 backends.
- adds ucomis{s,d} assembly to x86 and x86_64.
Change-Id: Ie91e04bfb402025073054f3803a3a569e4705caa
Andreas Gampe [Wed, 26 Nov 2014 04:40:08 +0000 (20:40 -0800)]
ART: Use Overwrite instead of Put
Allow threads exiting twice when tracing.
Bug:
18469797
Change-Id: I88ce5ea8237e53a76ad68fd4b28a367f58e6d635
Stephen Hines [Wed, 26 Nov 2014 09:24:13 +0000 (01:24 -0800)]
Add a missing SHARED_LOCKS_REQUIRED(mutator_lock_).
This was caught by Clang 3.6 using -Wthread-safety-analysis.
Change-Id: If2f25331f111ba6c67570e5aece1fba38f714d05
Mathieu Chartier [Wed, 26 Nov 2014 00:03:31 +0000 (00:03 +0000)]
Merge "Move dexCacheStrings from ArtMethod to Class"
Mathieu Chartier [Tue, 25 Nov 2014 02:29:54 +0000 (18:29 -0800)]
Move dexCacheStrings from ArtMethod to Class
Adds one load for const strings which are not direct.
Saves >= 60KB of memory avg per app.
Image size: -350KB.
Bug:
17643507
Change-Id: I2d1a3253d9de09682be9bc6b420a29513d592cc8
(cherry picked from commit
f521f423b66e952f746885dd9f6cf8ef2788955d)
Nicolas Geoffray [Tue, 25 Nov 2014 23:42:00 +0000 (23:42 +0000)]
Add ART_USE_OPTIMIZING_COMPILER flag.
Change-Id: I86065aec5bfe59729c6a4064a3e54d5b523ca45c
Mathieu Chartier [Tue, 25 Nov 2014 23:31:24 +0000 (23:31 +0000)]
Merge "Fix oatwriter code deduping"
Mathieu Chartier [Tue, 25 Nov 2014 19:20:28 +0000 (11:20 -0800)]
Fix oatwriter code deduping
Now that the GC maps are part of the oat method header they need
to be checked in CodeOffsetsKeyComparator.
Bug:
18523556
Change-Id: I539a6e7216166342b22515c1e2cf831dad32e41e
(cherry picked from commit
4cdf4508903d13fd0f9fba5690aeac1b368db81b)
Andreas Gampe [Tue, 25 Nov 2014 21:30:20 +0000 (21:30 +0000)]
Merge "ART: Avoid recursive abort"
buzbee [Tue, 25 Nov 2014 20:09:03 +0000 (20:09 +0000)]
Merge "Quick compiler: handle embedded switch data"
buzbee [Tue, 25 Nov 2014 18:52:19 +0000 (10:52 -0800)]
Quick compiler: handle embedded switch data
Although switch data is generally placed at the end of a dex
file by dx, it can occur elsewhere (and does via obsfucators).
This CL fixes a parsing error related to embedded switch data by
ensuring valid dex instructions following the embedded data appear
in their own basic blocks.
AOSP b/80600
Change-Id: I91ead6b398386bcf168b1088c5bc13a53b18f26e
Bill Buzbee [Tue, 25 Nov 2014 16:28:31 +0000 (16:28 +0000)]
Merge "ART: GenLongArith has to clobber same operands for 2-op instr"
Bill Buzbee [Tue, 25 Nov 2014 16:28:19 +0000 (16:28 +0000)]
Merge "ART: Generate switch targets from successor blocks"
Vladimir Marko [Tue, 25 Nov 2014 11:44:56 +0000 (11:44 +0000)]
Merge "Skip null check in MarkGCCard() for known non-null values."
Nicolas Geoffray [Tue, 25 Nov 2014 11:19:37 +0000 (11:19 +0000)]
Merge "Fix tests now that dead phis are removed when building SSA."
Nicolas Geoffray [Tue, 25 Nov 2014 11:18:37 +0000 (11:18 +0000)]
Fix tests now that dead phis are removed when building SSA.
Change-Id: Ie795f5f1c7c44ec1a3ea2bac822b6255bfb8d45c
Nicolas Geoffray [Tue, 25 Nov 2014 10:33:31 +0000 (10:33 +0000)]
Merge "Fix a bug in the type analysis phase of optimizing."
Andreas Gampe [Tue, 25 Nov 2014 02:04:41 +0000 (02:04 +0000)]
Merge "ART: Fix inline dependency"
Andreas Gampe [Tue, 25 Nov 2014 02:03:01 +0000 (18:03 -0800)]
ART: Fix inline dependency
GetClassFromTypeIdx is defined in the -inl file.
Change-Id: Ib5dbcea08dccee43ff70cac2e45cdbf210cb490c
Nicolas Geoffray [Mon, 24 Nov 2014 15:28:45 +0000 (15:28 +0000)]
Fix a bug in the type analysis phase of optimizing.
Dex code can lead to the creation of a phi with one
float input and one integer input. Since the SSA builder trusts
the verifier, it assumes that the integer input must be converted
to float. However, when the register is not used afterwards, the
verifier hasn't ensured that. Therefore, the compiler must remove
the phi prior to doing type propagation.
Change-Id: Idcd51c4dccce827c59d1f2b253bc1c919bc07df5
Andreas Gampe [Mon, 24 Nov 2014 23:57:17 +0000 (23:57 +0000)]
Merge "ART: Fix unused variables and functions"
Andreas Gampe [Mon, 24 Nov 2014 22:29:46 +0000 (22:29 +0000)]
Merge "Revert "ART: Remove wrong DCHECK""
Andreas Gampe [Mon, 24 Nov 2014 22:23:53 +0000 (14:23 -0800)]
Revert "ART: Remove wrong DCHECK"
This reverts commit
5be30072c5a750617dc3f9380776d074f26d9f32.
The underlying computation was fixed in AOSP before.
Bug:
17772057
Bug:
17763227
Bug:
17762845
Andreas Gampe [Mon, 24 Nov 2014 21:42:22 +0000 (13:42 -0800)]
ART: Fix unused variables and functions
Change-Id: Icbab884d2dfd71656347368b424cb35cbf524051
Mathieu Chartier [Mon, 24 Nov 2014 19:57:50 +0000 (19:57 +0000)]
Merge "Delete ArtMethod gc_map_ field"
Vladimir Marko [Mon, 24 Nov 2014 19:45:41 +0000 (19:45 +0000)]
Skip null check in MarkGCCard() for known non-null values.
Use GVN's knowledge of non-null values to set a new MIR flag
for IPUT/SPUT/APUT to skip the value null check.
Change-Id: I97a8d1447acb530c9bbbf7b362add366d1486ee1
Vladimir Marko [Mon, 24 Nov 2014 19:09:57 +0000 (19:09 +0000)]
Merge "Further cleanup using dex_instruction_utils.h."
Calin Juravle [Mon, 24 Nov 2014 18:46:10 +0000 (18:46 +0000)]
Merge "Fix the list of arm64 broken optimizing tests."
Mathieu Chartier [Sat, 22 Nov 2014 00:51:29 +0000 (16:51 -0800)]
Delete ArtMethod gc_map_ field
Moved the gc_map field from OatMethod to OatQuickMethodHeader.
Deleted the ArtMethod gc_map_ field.
Bug:
17643507
Change-Id: Ifa0470c3e4c2f8a319744464d94c6838b76b3d48
(cherry picked from commit
807140048f82a2b87ee5bcf337f23b6a3d1d5269)
Calin Juravle [Mon, 24 Nov 2014 18:38:13 +0000 (18:38 +0000)]
Fix the list of arm64 broken optimizing tests.
Change-Id: I498c1dc0a32686f2b335a2b43ed31ac537f29029
Nicolas Geoffray [Mon, 24 Nov 2014 18:21:41 +0000 (18:21 +0000)]
Merge "Revert "Revert "Fix the computation of linear ordering."""
Nicolas Geoffray [Mon, 24 Nov 2014 17:47:10 +0000 (17:47 +0000)]
Revert "Revert "Fix the computation of linear ordering.""
PS2 fixes the obvious typos/wrong refactoring.
This reverts commit
e50fa5887b1342b845826197d81950e26753fc9c.
Change-Id: I22f81d63a12cf01aafd61535abc2399d936d49c2
Nicolas Geoffray [Mon, 24 Nov 2014 17:44:27 +0000 (17:44 +0000)]
Merge "Revert "Fix the computation of linear ordering.""
Nicolas Geoffray [Mon, 24 Nov 2014 17:44:15 +0000 (17:44 +0000)]
Revert "Fix the computation of linear ordering."
Build is broken.
This reverts commit
3054a90063d379ab8c9e5a42a7daf0d644b48b07.
Change-Id: I259bc2bd6a58e30391b8176f3db5fdb5c07e4d6d
Nicolas Geoffray [Mon, 24 Nov 2014 17:29:36 +0000 (17:29 +0000)]
Merge "Fix the computation of linear ordering."
Vladimir Marko [Mon, 24 Nov 2014 16:33:51 +0000 (16:33 +0000)]
Further cleanup using dex_instruction_utils.h.
Change-Id: I85aa9e7d744b37ee3d2531c50470cd3fa87dc864
Calin Juravle [Mon, 24 Nov 2014 16:37:16 +0000 (16:37 +0000)]
Merge "Fixed missing "//"."
Calin Juravle [Mon, 24 Nov 2014 16:36:44 +0000 (16:36 +0000)]
Fixed missing "//".
Change-Id: Ife5338d469e9db0b0ea37746dee11a40a52615f1