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Peter Maydell [Mon, 27 Sep 2021 14:03:42 +0000 (15:03 +0100)]
Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-09-25-v2' into staging
QAPI patches patches for 2021-09-25
# gpg: Signature made Mon 27 Sep 2021 13:44:23 BST
# gpg: using RSA key
354BC8B3D7EB2A6B68674E5F3870B400EB918653
# gpg: issuer "armbru@redhat.com"
# gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full]
# gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full]
# Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653
* remotes/armbru/tags/pull-qapi-2021-09-25-v2: (25 commits)
tests/qapi-schema: Make test-qapi.py -u work when files are absent
tests/qapi-schema: Use Python OSError instead of outmoded IOError
test-clone-visitor: Correct an accidental rename
tests/qapi-schema: Rename flat-union-* test cases to union-*
qapi: Drop simple unions
tests/qapi-schema: Purge simple unions from tests
tests/qapi-schema: Drop simple union __org.qemu_x-Union1
test-clone-visitor: Wean off __org.qemu_x-Union1
tests/qapi-schema: Rewrite simple union TestIfUnion to be flat
tests/qapi-schema: Simple union UserDefListUnion is now unused, drop
tests/qapi-schema: Wean off UserDefListUnion
test-clone-visitor: Wean off UserDefListUnion
test-qobject-output-visitor: Wean off UserDefListUnion
test-qobject-input-visitor: Wean off UserDefListUnion
tests/qapi-schema: Prepare for simple union UserDefListUnion removal
qapi: Convert simple union TransactionAction to flat one
qapi: Convert simple union ImageInfoSpecific to flat one
qapi: Convert simple union SocketAddressLegacy to flat one
qapi: Convert simple union ChardevBackend to flat one
qapi: Convert simple union MemoryDeviceInfo to flat one
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Mon, 27 Sep 2021 10:08:36 +0000 (11:08 +0100)]
Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.2-pull-request' into staging
Trivial patches pull request
20210927
# gpg: Signature made Mon 27 Sep 2021 10:52:10 BST
# gpg: using RSA key
CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg: issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* remotes/vivier2/tags/trivial-branch-for-6.2-pull-request:
multi-process: fix usage information
hmp: Drop a bogus sentence from set_password's documentation
hmp: Unbreak "change vnc"
hw/loader: Restrict PC_ROM_* definitions to hw/i386/pc
docs/nvdimm: Update nvdimm option value in machine example
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Dongli Zhang [Tue, 13 Jul 2021 00:47:18 +0000 (17:47 -0700)]
multi-process: fix usage information
From source code, the 'devid' of x-remote-object should be one of devices
in remote QEMU process.
Signed-off-by: Dongli Zhang <dongli.zhang@oracle.com>
Reviewed-by: Jagannathan Raman <jag.raman@oracle.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <
20210713004718.20381-1-dongli.zhang@oracle.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Markus Armbruster [Thu, 9 Sep 2021 08:12:19 +0000 (10:12 +0200)]
hmp: Drop a bogus sentence from set_password's documentation
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20210909081219.308065-3-armbru@redhat.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Markus Armbruster [Thu, 9 Sep 2021 08:12:18 +0000 (10:12 +0200)]
hmp: Unbreak "change vnc"
HMP command "change vnc" can take the password as argument, or prompt
for it:
(qemu) change vnc password 123
(qemu) change vnc password
Password: ***
(qemu)
This regressed in commit
cfb5387a1d "hmp: remove "change vnc TARGET"
command", v6.0.0.
(qemu) change vnc passwd 123
Password: ***
(qemu) change vnc passwd
(qemu)
The latter passes NULL to qmp_change_vnc_password(), which is a no-no.
Looks like it puts the display into "password required, but none set"
state.
The logic error is easy to miss in review, but testing should've
caught it.
Fix the obvious way.
Fixes:
cfb5387a1de2acda23fb5c97d2378b9e7ddf8025
Cc: qemu-stable@nongnu.org
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <
20210909081219.308065-2-armbru@redhat.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Philippe Mathieu-Daudé [Fri, 17 Sep 2021 18:59:49 +0000 (20:59 +0200)]
hw/loader: Restrict PC_ROM_* definitions to hw/i386/pc
The PC_ROM_* definitions are only used by the PC machine,
and are irrelevant to the other architectures / machines.
Reduce their scope by moving them to hw/i386/pc.c.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <
20210917185949.
2244956-1-philmd@redhat.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Pankaj Gupta [Thu, 23 Sep 2021 10:30:15 +0000 (12:30 +0200)]
docs/nvdimm: Update nvdimm option value in machine example
Update nvdimm option value in example command from "-machine pc,nvdimm"
to "-machine pc,nvdimm=on" as former complains with the below error:
"qemu-system-x86_64: -machine pc,nvdimm: Expected '=' after parameter 'nvdimm'"
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Pankaj Gupta <pankaj.gupta.linux@gmail.com>
Message-Id: <
20210923103015.135262-1-pankaj.gupta.linux@gmail.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Markus Armbruster [Wed, 22 Sep 2021 12:56:19 +0000 (14:56 +0200)]
tests/qapi-schema: Make test-qapi.py -u work when files are absent
test-qapi.py -u updates the expected files. Since it fails when they
are absent, users have to create them manually before they can use
test-qapi.py to fill in the contents, say for a new test. Silly.
Improve -u to create them.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <
20210922125619.670673-3-armbru@redhat.com>
Reviewed-by: John Snow <jsnow@redhat.com>
Markus Armbruster [Wed, 22 Sep 2021 12:56:18 +0000 (14:56 +0200)]
tests/qapi-schema: Use Python OSError instead of outmoded IOError
https://docs.python.org/3.6/library/exceptions.html has
Changed in version 3.3: EnvironmentError, IOError, WindowsError,
socket.error, select.error and mmap.error have been merged into
OSError, and the constructor may return a subclass.
and
The following exceptions are kept for compatibility with previous
versions; starting from Python 3.3, they are aliases of OSError.
exception EnvironmentError
exception IOError
exception WindowsError
Only available on Windows.
Switch to the preferred name.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <
20210922125619.670673-2-armbru@redhat.com>
Reviewed-by: John Snow <jsnow@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
[Details added to commit message]
Markus Armbruster [Fri, 17 Sep 2021 14:31:34 +0000 (16:31 +0200)]
test-clone-visitor: Correct an accidental rename
Commit
b359f4b203 "tests: Rename UserDefNativeListUnion to
UserDefListUnion" renamed test_clone_native_list() to
test_clone_list_union(). The function has nothing to do with unions.
Rename it to test_clone_list().
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <
20210917143134.412106-24-armbru@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Markus Armbruster [Fri, 17 Sep 2021 14:31:33 +0000 (16:31 +0200)]
tests/qapi-schema: Rename flat-union-* test cases to union-*
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <
20210917143134.412106-23-armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com
Markus Armbruster [Fri, 17 Sep 2021 14:31:32 +0000 (16:31 +0200)]
qapi: Drop simple unions
Simple unions predate flat unions. Having both complicates the QAPI
schema language and the QAPI generator. We haven't been using simple
unions in new code for a long time, because they are less flexible and
somewhat awkward on the wire.
The previous commits eliminated simple union from the tree. Now drop
them from the QAPI schema language entirely, and update mentions of
"flat union" to just "union".
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <
20210917143134.412106-22-armbru@redhat.com>
Markus Armbruster [Fri, 17 Sep 2021 14:31:31 +0000 (16:31 +0200)]
tests/qapi-schema: Purge simple unions from tests
Drop tests that are specifically about simple unions:
* SugaredUnion in doc-good: flat unions are covered by @Object.
* union-branch-case and union-clash-branches: branch naming for flat
unions is enforced for the tag enum instead, which is covered by
enum-member-case and enum-clash-member.
* union-empty: empty flat unions are covered by flat-union-empty.
Rewrite the remainder to use flat unions: args-union, bad-base,
flat-union-base-union, union-branch-invalid-dict, union-unknown.
Except drop union-optional-branch. because converting this one is not
worth the trouble; we don't explicitly check names beginning with '*'
in other places, either.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <
20210917143134.412106-21-armbru@redhat.com>
Markus Armbruster [Fri, 17 Sep 2021 14:31:30 +0000 (16:31 +0200)]
tests/qapi-schema: Drop simple union __org.qemu_x-Union1
Replace simple union __org.qemu_x-Union1 with flat union
__org.qemu_x-Union2, except drop it from __org.qemu_x-command, because
there it's only used to pull it into QMP. Now drop the unused
-Union1, and rename -Union2 to -Union.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <
20210917143134.412106-20-armbru@redhat.com>
Markus Armbruster [Fri, 17 Sep 2021 14:31:29 +0000 (16:31 +0200)]
test-clone-visitor: Wean off __org.qemu_x-Union1
test_clone_complex3() uses simple union __org.qemu_x-Union1 to cover
arrays. Use UserDefOneList instead. Unions are still covered by
test_clone_complex1().
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <
20210917143134.412106-19-armbru@redhat.com>
Markus Armbruster [Fri, 17 Sep 2021 14:31:28 +0000 (16:31 +0200)]
tests/qapi-schema: Rewrite simple union TestIfUnion to be flat
Simple unions predate flat unions. Having both complicates the QAPI
schema language and the QAPI generator. We haven't been using simple
unions in new code for a long time, because they are less flexible and
somewhat awkward on the wire.
To prepare for their removal, rewrite TestIfUnion to be flat.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <
20210917143134.412106-18-armbru@redhat.com>
Markus Armbruster [Fri, 17 Sep 2021 14:31:27 +0000 (16:31 +0200)]
tests/qapi-schema: Simple union UserDefListUnion is now unused, drop
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <
20210917143134.412106-17-armbru@redhat.com>
Markus Armbruster [Fri, 17 Sep 2021 14:31:26 +0000 (16:31 +0200)]
tests/qapi-schema: Wean off UserDefListUnion
Command boxed-union uses simple union UserDefListUnion to cover
unions. Use UserDefFlatUnion instead.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <
20210917143134.412106-16-armbru@redhat.com>
Markus Armbruster [Fri, 17 Sep 2021 14:31:25 +0000 (16:31 +0200)]
test-clone-visitor: Wean off UserDefListUnion
test_clone_complex1() uses simple union UserDefListUnion to cover
unions. Use UserDefFlatUnion instead. Arrays are still covered by
test_clone_complex3().
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <
20210917143134.412106-15-armbru@redhat.com>
Markus Armbruster [Fri, 17 Sep 2021 14:31:24 +0000 (16:31 +0200)]
test-qobject-output-visitor: Wean off UserDefListUnion
The test_visitor_out_list_union_FOO() use simple union
UserDefListUnion to cover lists of builtin types. Rewrite as
test_visitor_out_list_struct(), using struct ArrayStruct and a lot
less code.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <
20210917143134.412106-14-armbru@redhat.com>
Markus Armbruster [Fri, 17 Sep 2021 14:31:23 +0000 (16:31 +0200)]
test-qobject-input-visitor: Wean off UserDefListUnion
The test_visitor_in_list_union_FOO() use simple union UserDefListUnion
to cover lists of builtin types. Rewrite as
test_visitor_in_list_struct(), using struct ArrayStruct and a lot less
code.
test_visitor_in_fail_union_list() uses UserDefListUnion to cover
"variant members don't match the discriminator value". Cover that in
test_visitor_in_fail_union_flat() instead, and drop
test_visitor_in_fail_union_list(). Appropriating the former for this
purpose is okay, because it actually failed due to missing
discriminator, which is still covered by
test_visitor_in_fail_union_flat_no_discrim().
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <
20210917143134.412106-13-armbru@redhat.com>
Markus Armbruster [Fri, 17 Sep 2021 14:31:22 +0000 (16:31 +0200)]
tests/qapi-schema: Prepare for simple union UserDefListUnion removal
Simple unions predate flat unions. Having both complicates the QAPI
schema language and the QAPI generator. We haven't been using simple
unions in new code for a long time, because they are less flexible and
somewhat awkward on the wire.
To prepare for their removal, simple union UserDefListUnion has to go.
It is used to cover arrays. The next few commits will eliminate its
uses, and then it gets deleted. As a first step, provide struct
ArrayStruct for the tests to be rewritten.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <
20210917143134.412106-12-armbru@redhat.com>
Markus Armbruster [Fri, 17 Sep 2021 14:31:21 +0000 (16:31 +0200)]
qapi: Convert simple union TransactionAction to flat one
Simple unions predate flat unions. Having both complicates the QAPI
schema language and the QAPI generator. We haven't been using simple
unions in new code for a long time, because they are less flexible and
somewhat awkward on the wire.
To prepare for their removal, convert simple union TransactionAction
to an equivalent flat one. Adds some boilerplate to the schema, which
is a bit ugly, but a lot easier to maintain than the simple union
feature.
Cc: Kevin Wolf <kwolf@redhat.com>
Cc: Hanna Reitz <hreitz@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Acked-by: Hanna Reitz <hreitz@redhat.com>
Message-Id: <
20210917143134.412106-11-armbru@redhat.com>
Markus Armbruster [Fri, 17 Sep 2021 14:31:20 +0000 (16:31 +0200)]
qapi: Convert simple union ImageInfoSpecific to flat one
Simple unions predate flat unions. Having both complicates the QAPI
schema language and the QAPI generator. We haven't been using simple
unions in new code for a long time, because they are less flexible and
somewhat awkward on the wire.
To prepare for their removal, convert simple union ImageInfoSpecific
to an equivalent flat one. Adds some boilerplate to the schema, which
is a bit ugly, but a lot easier to maintain than the simple union
feature.
Implicit enum ImageInfoSpecificKind becomes explicit. It duplicates
part of enum BlockdevDriver. We could reuse BlockdevDriver instead.
Cc: Kevin Wolf <kwolf@redhat.com>
Cc: Hanna Reitz <hreitz@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Acked-by: Hanna Reitz <hreitz@redhat.com>
Message-Id: <
20210917143134.412106-10-armbru@redhat.com>
Markus Armbruster [Fri, 17 Sep 2021 14:31:19 +0000 (16:31 +0200)]
qapi: Convert simple union SocketAddressLegacy to flat one
Simple unions predate flat unions. Having both complicates the QAPI
schema language and the QAPI generator. We haven't been using simple
unions in new code for a long time, because they are less flexible and
somewhat awkward on the wire.
To prepare for their removal, convert simple union SocketAddressLegacy
to an equivalent flat one, with existing enum SocketAddressType
replacing implicit enum type SocketAddressLegacyKind. Adds some
boilerplate to the schema, which is a bit ugly, but a lot easier to
maintain than the simple union feature.
Cc: "Daniel P. Berrangé" <berrange@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <
20210917143134.412106-9-armbru@redhat.com>
Markus Armbruster [Fri, 17 Sep 2021 14:31:18 +0000 (16:31 +0200)]
qapi: Convert simple union ChardevBackend to flat one
Simple unions predate flat unions. Having both complicates the QAPI
schema language and the QAPI generator. We haven't been using simple
unions in new code for a long time, because they are less flexible and
somewhat awkward on the wire.
To prepare for their removal, convert simple union ChardevBackend to
an equivalent flat one. Adds some boilerplate to the schema, which is
a bit ugly, but a lot easier to maintain than the simple union
feature.
Cc: "Marc-André Lureau" <marcandre.lureau@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <
20210917143134.412106-8-armbru@redhat.com>
[Missing conditionals added]
Markus Armbruster [Fri, 17 Sep 2021 14:31:17 +0000 (16:31 +0200)]
qapi: Convert simple union MemoryDeviceInfo to flat one
Simple unions predate flat unions. Having both complicates the QAPI
schema language and the QAPI generator. We haven't been using simple
unions in new code for a long time, because they are less flexible and
somewhat awkward on the wire.
To prepare for their removal, convert simple union MemoryDeviceInfo to
an equivalent flat one. Adds some boilerplate to the schema, which is
a bit ugly, but a lot easier to maintain than the simple union
feature.
Cc: Eduardo Habkost <ehabkost@redhat.com>
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <
20210917143134.412106-7-armbru@redhat.com>
Markus Armbruster [Fri, 17 Sep 2021 14:31:16 +0000 (16:31 +0200)]
qapi: Convert simple union TpmTypeOptions to flat one
Simple unions predate flat unions. Having both complicates the QAPI
schema language and the QAPI generator. We haven't been using simple
unions in new code for a long time, because they are less flexible and
somewhat awkward on the wire.
To prepare for their removal, convert simple union TpmTypeOptions to
an equivalent flat one, with existing enum TpmType replacing implicit
enum TpmTypeOptionsKind. Adds some boilerplate to the schema, which
is a bit ugly, but a lot easier to maintain than the simple union
feature.
Cc: Stefan Berger <stefanb@linux.vnet.ibm.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Stefan Berger <stefanb@linux.ibm.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <
20210917143134.412106-6-armbru@redhat.com>
[Indentation tidied up]
Markus Armbruster [Fri, 17 Sep 2021 14:31:15 +0000 (16:31 +0200)]
qapi: Convert simple union InputEvent to flat one
Simple unions predate flat unions. Having both complicates the QAPI
schema language and the QAPI generator. We haven't been using simple
unions in new code for a long time, because they are less flexible and
somewhat awkward on the wire.
To prepare for their removal, convert simple union InputEvent to an
equivalent flat one. Adds some boilerplate to the schema, which is a
bit ugly, but a lot easier to maintain than the simple union feature.
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <
20210917143134.412106-5-armbru@redhat.com>
Markus Armbruster [Fri, 17 Sep 2021 14:31:14 +0000 (16:31 +0200)]
qapi: Convert simple union KeyValue to flat one
Simple unions predate flat unions. Having both complicates the QAPI
schema language and the QAPI generator. We haven't been using simple
unions in new code for a long time, because they are less flexible and
somewhat awkward on the wire.
To prepare for their removal, convert simple union KeyValue to an
equivalent flat one. Adds some boilerplate to the schema, which is a
bit ugly, but a lot easier to maintain than the simple union feature.
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <
20210917143134.412106-4-armbru@redhat.com>
Markus Armbruster [Fri, 17 Sep 2021 14:31:13 +0000 (16:31 +0200)]
qapi: Stop enforcing "type name should not end in 'Kind'
I'm about to convert simple unions to flat unions, then drop simple
union support. The conversion involves making the implict enum types
explicit. To reduce churn, I'd like to name them exactly like the
implicit types they replace. However, these names are reserved for
the generator's use. They won't be once simple unions are gone. Stop
enforcing this naming rule now rather than then.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <
20210917143134.412106-3-armbru@redhat.com>
Markus Armbruster [Fri, 17 Sep 2021 14:31:12 +0000 (16:31 +0200)]
qapi: Tidy up unusual line breaks
Break lines between members instead of within members.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <
20210917143134.412106-2-armbru@redhat.com>
Richard Henderson [Fri, 24 Sep 2021 17:21:18 +0000 (13:21 -0400)]
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-
20210921' into staging
Move cpu_signal_handler declaration.
Restrict cpu_handle_halt to sysemu.
Make do_unaligned_access noreturn.
Misc tcg/mips cleanup
Misc tcg/sparc cleanup
Misc tcg/riscv cleanup
# gpg: Signature made Tue 21 Sep 2021 10:47:29 PM EDT
# gpg: using RSA key
7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]
* remotes/rth/tags/pull-tcg-
20210921:
tcg/riscv: Remove add with zero on user-only memory access
hw/core: Make do_unaligned_access noreturn
tcg/sparc: Introduce tcg_out_mov_delay
tcg/sparc: Drop inline markers
tcg/mips: Drop special alignment for code_gen_buffer
tcg/mips: Unset TCG_TARGET_HAS_direct_jump
tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr
tcg/mips: Drop inline markers
accel/tcg: Restrict cpu_handle_halt() to sysemu
include/exec: Move cpu_signal_handler declaration
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Peter Maydell [Fri, 24 Sep 2021 14:05:12 +0000 (15:05 +0100)]
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-6.2-pull-request' into staging
Pull request linux-user
20210924
Clean up siginfo_t handling for arm, aarch64
# gpg: Signature made Fri 24 Sep 2021 14:56:12 BST
# gpg: using RSA key
CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg: issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* remotes/vivier2/tags/linux-user-for-6.2-pull-request:
linux-user/aarch64: Use force_sig_fault()
linux-user/arm: Use force_sig_fault()
linux-user: Provide new force_sig_fault() function
linux-user: Zero out target_siginfo_t in force_sig()
linux-user/arm: Use force_sig() to deliver fpa11 emulation SIGFPE
linux-user/arm: Set siginfo_t addr field for SIGTRAP signals
linux-user/aarch64: Set siginfo_t addr field for SIGTRAP signals
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Fri, 24 Sep 2021 09:28:13 +0000 (10:28 +0100)]
Merge remote-tracking branch 'remotes/nvme/tags/nvme-next-pull-request' into staging
hw/nvme updates
# gpg: Signature made Fri 24 Sep 2021 07:44:23 BST
# gpg: using RSA key
522833AA75E2DCE6A24766C04DE1AF316D4F0DE9
# gpg: Good signature from "Klaus Jensen <its@irrelevant.dk>" [unknown]
# gpg: aka "Klaus Jensen <k.jensen@samsung.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: DDCA 4D9C 9EF9 31CC 3468 4272 63D5 6FC5 E55D A838
# Subkey fingerprint: 5228 33AA 75E2 DCE6 A247 66C0 4DE1 AF31 6D4F 0DE9
* remotes/nvme/tags/nvme-next-pull-request:
hw/nvme: Return error for fused operations
hw/nvme: fix verification of select field in namespace attachment
hw/nvme: fix validation of ASQ and ACQ
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Pankaj Raghav [Wed, 15 Sep 2021 15:43:30 +0000 (17:43 +0200)]
hw/nvme: Return error for fused operations
Currently, FUSED operations are not supported by QEMU. As per the 1.4 SPEC,
controller should abort the command that requested a fused operation with
an INVALID FIELD error code if they are not supported.
Changes from v1:
Added FUSE flag check also to the admin cmd processing as the FUSED
operations are mentioned in the general SQE section in the SPEC.
Signed-off-by: Pankaj Raghav <p.raghav@samsung.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Naveen Nagar [Mon, 23 Aug 2021 11:03:33 +0000 (16:33 +0530)]
hw/nvme: fix verification of select field in namespace attachment
Fix is added to check for reserved value in select field for
namespace attachment
CC: Minwoo Im <minwoo.im.dev@gmail.com>
Signed-off-by: Naveen Nagar <naveen.n1@samsung.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Klaus Jensen [Mon, 23 Aug 2021 12:11:33 +0000 (14:11 +0200)]
hw/nvme: fix validation of ASQ and ACQ
Address 0x0 is a valid address. Fix the admin submission and completion
queue address validation to not error out on this.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Peter Maydell [Fri, 13 Aug 2021 13:18:09 +0000 (14:18 +0100)]
linux-user/aarch64: Use force_sig_fault()
Use the new force_sig_fault() function instead of setting up
a target_siginfo_t and calling queue_signal().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210813131809.28655-8-peter.maydell@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Peter Maydell [Fri, 13 Aug 2021 13:18:08 +0000 (14:18 +0100)]
linux-user/arm: Use force_sig_fault()
Use the new force_sig_fault() function instead of setting up
a target_siginfo_t and calling queue_signal().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210813131809.28655-7-peter.maydell@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Peter Maydell [Fri, 13 Aug 2021 13:18:07 +0000 (14:18 +0100)]
linux-user: Provide new force_sig_fault() function
In many places in the linux-user code we need to queue a signal for
the guest using the QEMU_SI_FAULT si_type. This requires that the
caller sets up and passes us a target_siginfo, including setting the
appropriate part of the _sifields union for the si_type. In a number
of places the code forgets to set the _sifields union field.
Provide a new force_sig_fault() function, which does the same thing
as the Linux kernel function of that name -- it takes the signal
number, the si_code value and the address to use in
_sifields._sigfault, and assembles the target_siginfo itself. This
makes the callsites simpler and means it's harder to forget to pass
in an address value.
We follow force_sig() and the kernel's force_sig_fault() in not
requiring the caller to pass in the CPU pointer but always acting
on the CPU of the current thread.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210813131809.28655-6-peter.maydell@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Peter Maydell [Fri, 13 Aug 2021 13:18:06 +0000 (14:18 +0100)]
linux-user: Zero out target_siginfo_t in force_sig()
The target_siginfo_t we populate in force_sig() will eventually
get copied onto the target's stack. Zero it out so that any extra
padding in the sifields union is consistently zero when the guest
sees it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210813131809.28655-5-peter.maydell@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Peter Maydell [Fri, 13 Aug 2021 13:18:05 +0000 (14:18 +0100)]
linux-user/arm: Use force_sig() to deliver fpa11 emulation SIGFPE
In the Arm target code, when the fpa11 emulation code tells us we
need to send the guest a SIGFPE, we do this with queue_signal(), but
we are using the wrong si_type, and we aren't setting the _sifields
union members corresponding to either the si_type we are using or the
si_type we should be using.
As the existing comment notes, the kernel code for this calls the old
send_sig() function to deliver the signal. This eventually results
in the kernel's signal handling code fabricating a siginfo_t with a
SI_KERNEL code and a zero pid and uid. For QEMU this means we need
to use QEMU_SI_KILL. We already have a function for that:
force_sig() sets up the whole target_siginfo_t the way we need it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210813131809.28655-4-peter.maydell@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Peter Maydell [Fri, 13 Aug 2021 13:18:04 +0000 (14:18 +0100)]
linux-user/arm: Set siginfo_t addr field for SIGTRAP signals
When generating a TRAP_BRKPT SIGTRAP, set the siginfo_t addr field
to the PC where the breakpoint/singlestep trap occurred; this is
what the kernel does for this signal for this architecture.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210813131809.28655-3-peter.maydell@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Peter Maydell [Fri, 13 Aug 2021 13:18:03 +0000 (14:18 +0100)]
linux-user/aarch64: Set siginfo_t addr field for SIGTRAP signals
When generating a TRAP_BRKPT SIGTRAP, set the siginfo_t addr field
to the PC where the breakpoint/singlestep trap occurred; this is
what the kernel does for this signal for this architecture.
Fixes: Coverity
1459154
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210813131809.28655-2-peter.maydell@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Richard Henderson [Thu, 5 Aug 2021 17:38:14 +0000 (07:38 -1000)]
tcg/riscv: Remove add with zero on user-only memory access
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 29 Jul 2021 20:45:10 +0000 (10:45 -1000)]
hw/core: Make do_unaligned_access noreturn
While we may have had some thought of allowing system-mode
to return from this hook, we have no guests that require this.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 4 Aug 2021 22:15:53 +0000 (01:15 +0300)]
tcg/sparc: Introduce tcg_out_mov_delay
This version of tcg_out_mov is emits a nop to fill the
delay slot if the move is not required.
The only current use, for INDEX_op_goto_ptr, will always
require the move but properly documents the delay slot.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 4 Aug 2021 22:09:41 +0000 (01:09 +0300)]
tcg/sparc: Drop inline markers
Let the compiler decide about inlining.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 6 Aug 2021 18:20:16 +0000 (08:20 -1000)]
tcg/mips: Drop special alignment for code_gen_buffer
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 6 Aug 2021 17:49:03 +0000 (07:49 -1000)]
tcg/mips: Unset TCG_TARGET_HAS_direct_jump
Only use indirect jumps. Finish weaning away from the
unique alignment requirements for code_gen_buffer.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 6 Aug 2021 18:03:45 +0000 (08:03 -1000)]
tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr
Weaning off of unique alignment requirements, so allow JAL
to not reach the target. TCG_TMP1 is always available for
use as a scratch because it is clobbered by the subroutine
being called.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 6 Aug 2021 17:04:00 +0000 (07:04 -1000)]
tcg/mips: Drop inline markers
Let the compiler decide about inlining.
Remove tcg_out_ext8s and tcg_out_ext16s as unused.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Philippe Mathieu-Daudé [Sun, 12 Sep 2021 17:27:02 +0000 (19:27 +0200)]
accel/tcg: Restrict cpu_handle_halt() to sysemu
Commit
372579427a5 ("tcg: enable thread-per-vCPU") added the following
comment describing EXCP_HALTED in qemu_tcg_cpu_thread_fn():
case EXCP_HALTED:
/* during start-up the vCPU is reset and the thread is
* kicked several times. If we don't ensure we go back
* to sleep in the halted state we won't cleanly
* start-up when the vCPU is enabled.
*
* cpu->halted should ensure we sleep in wait_io_event
*/
g_assert(cpu->halted);
break;
qemu_wait_io_event() is sysemu-specific, so we can restrict the
cpu_handle_halt() call in cpu_exec() to system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210912172731.789788-2-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 3 Aug 2021 15:31:43 +0000 (05:31 -1000)]
include/exec: Move cpu_signal_handler declaration
There is nothing target specific about this. The implementation
is host specific, but the declaration is 100% common.
Reviewed-By: Warner Losh <imp@bsdimp.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 21 Sep 2021 17:57:48 +0000 (10:57 -0700)]
Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-
20210921' into staging
Second RISC-V PR for QEMU 6.2
- ePMP CSR address updates
- Convert internal interrupts to use QEMU GPIO lines
- SiFive PWM support
- Support for RISC-V ACLINT
- SiFive PDMA fixes
- Update to u-boot instructions for sifive_u
- mstatus.SD bug fix for hypervisor extensions
- OpenTitan fix for USB dev address
# gpg: Signature made Mon 20 Sep 2021 11:52:26 PM PDT
# gpg: using RSA key
F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair23/tags/pull-riscv-to-apply-
20210921: (21 commits)
hw/riscv: opentitan: Correct the USB Dev address
target/riscv: csr: Rename HCOUNTEREN_CY and friends
target/riscv: Backup/restore mstatus.SD bit when virtual register swapped
docs/system/riscv: sifive_u: Update U-Boot instructions
hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer
hw/dma: sifive_pdma: allow non-multiple transaction size transactions
hw/dma: sifive_pdma: claim bit must be set before DMA transactions
hw/dma: sifive_pdma: reset Next* registers when Control.claim is set
hw/riscv: virt: Add optional ACLINT support to virt machine
hw/riscv: virt: Re-factor FDT generation
hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
hw/intc: Rename sifive_clint sources to riscv_aclint sources
sifive_u: Connect the SiFive PWM device
hw/timer: Add SiFive PWM support
hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines
hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines
hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines
hw/intc: sifive_clint: Use RISC-V CPU GPIO lines
target/riscv: Expose interrupt pending bits as GPIO lines
target/riscv: Fix satp write
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Peter Maydell [Tue, 21 Sep 2021 15:32:19 +0000 (16:32 +0100)]
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-
20210921' into staging
target-arm queue:
* Optimize codegen for MVE when predication not active
* hvf: Add Apple Silicon support
* hw/intc: Set GIC maintenance interrupt level to only 0 or 1
* Fix mishandling of MVE FPSCR.LTPSIZE reset for usermode emulator
* elf2dmp: Fix coverity nits
# gpg: Signature made Tue 21 Sep 2021 16:31:17 BST
# gpg: using RSA key
E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-
20210921: (27 commits)
target/arm: Optimize MVE 1op-immediate insns
target/arm: Optimize MVE VSLI and VSRI
target/arm: Optimize MVE VSHLL and VMOVL
target/arm: Optimize MVE VSHL, VSHR immediate forms
target/arm: Optimize MVE VMVN
target/arm: Optimize MVE VDUP
target/arm: Optimize MVE VNEG, VABS
target/arm: Optimize MVE arithmetic ops
target/arm: Optimize MVE logic ops
target/arm: Add TB flag for "MVE insns not predicated"
target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration
target/arm: Avoid goto_tb if we're trying to exit to the main loop
hvf: arm: Add rudimentary PMC support
arm: Add Hypervisor.framework build target
hvf: arm: Implement PSCI handling
hvf: arm: Implement -cpu host
arm/hvf: Add a WFI handler
hvf: Add Apple Silicon support
hvf: Introduce hvf_arch_init() callback
hvf: Add execute to dirty log permission bitmap
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Mon, 13 Sep 2021 09:54:40 +0000 (10:54 +0100)]
target/arm: Optimize MVE 1op-immediate insns
Optimize the MVE 1op-immediate insns (VORR, VBIC, VMOV) to
use TCG vector ops when possible.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210913095440.13462-13-peter.maydell@linaro.org
Peter Maydell [Mon, 13 Sep 2021 09:54:39 +0000 (10:54 +0100)]
target/arm: Optimize MVE VSLI and VSRI
Optimize the MVE shift-and-insert insns by using TCG
vector ops when possible.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210913095440.13462-12-peter.maydell@linaro.org
Peter Maydell [Mon, 13 Sep 2021 09:54:38 +0000 (10:54 +0100)]
target/arm: Optimize MVE VSHLL and VMOVL
Optimize the MVE VSHLL insns by using TCG vector ops when possible.
This includes the VMOVL insn, which we handle in mve.decode as "VSHLL
with zero shift count".
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210913095440.13462-11-peter.maydell@linaro.org
Peter Maydell [Mon, 13 Sep 2021 09:54:37 +0000 (10:54 +0100)]
target/arm: Optimize MVE VSHL, VSHR immediate forms
Optimize the MVE VSHL and VSHR immediate forms by using TCG vector
ops when possible.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210913095440.13462-10-peter.maydell@linaro.org
Peter Maydell [Mon, 13 Sep 2021 09:54:36 +0000 (10:54 +0100)]
target/arm: Optimize MVE VMVN
Optimize the MVE VMVN insn by using TCG vector ops when possible.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210913095440.13462-9-peter.maydell@linaro.org
Peter Maydell [Mon, 13 Sep 2021 09:54:35 +0000 (10:54 +0100)]
target/arm: Optimize MVE VDUP
Optimize the MVE VDUP insns by using TCG vector ops when possible.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210913095440.13462-8-peter.maydell@linaro.org
Peter Maydell [Mon, 13 Sep 2021 09:54:34 +0000 (10:54 +0100)]
target/arm: Optimize MVE VNEG, VABS
Optimize the MVE VNEG and VABS insns by using TCG
vector ops when possible.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210913095440.13462-7-peter.maydell@linaro.org
Peter Maydell [Mon, 13 Sep 2021 09:54:33 +0000 (10:54 +0100)]
target/arm: Optimize MVE arithmetic ops
Optimize MVE arithmetic ops when we have a TCG
vector operation we can use.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210913095440.13462-6-peter.maydell@linaro.org
Peter Maydell [Mon, 13 Sep 2021 09:54:32 +0000 (10:54 +0100)]
target/arm: Optimize MVE logic ops
When not predicating, implement the MVE bitwise logical insns
directly using TCG vector operations.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210913095440.13462-5-peter.maydell@linaro.org
Peter Maydell [Mon, 13 Sep 2021 09:54:31 +0000 (10:54 +0100)]
target/arm: Add TB flag for "MVE insns not predicated"
Our current codegen for MVE always calls out to helper functions,
because some byte lanes might be predicated. The common case is that
in fact there is no predication active and all lanes should be
updated together, so we can produce better code by detecting that and
using the TCG generic vector infrastructure.
Add a TB flag that is set when we can guarantee that there is no
active MVE predication, and a bool in the DisasContext. Subsequent
patches will use this flag to generate improved code for some
instructions.
In most cases when the predication state changes we simply end the TB
after that instruction. For the code called from vfp_access_check()
that handles lazy state preservation and creating a new FP context,
we can usually avoid having to try to end the TB because luckily the
new value of the flag following the register changes in those
sequences doesn't depend on any runtime decisions. We do have to end
the TB if the guest has enabled lazy FP state preservation but not
automatic state preservation, but this is an odd corner case that is
not going to be common in real-world code.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210913095440.13462-4-peter.maydell@linaro.org
Peter Maydell [Mon, 13 Sep 2021 09:54:30 +0000 (10:54 +0100)]
target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration
Architecturally, for an M-profile CPU with the LOB feature the
LTPSIZE field in FPDSCR is always constant 4. QEMU's implementation
enforces this everywhere, except that we don't check that it is true
in incoming migration data.
We're going to add come in gen_update_fp_context() which relies on
the "always 4" property. Since this is TCG-only, we don't actually
need to be robust to bogus incoming migration data, and the effect of
it being wrong would be wrong code generation rather than a QEMU
crash; but if it did ever happen somehow it would be very difficult
to track down the cause. Add a check so that we fail the inbound
migration if the FPDSCR.LTPSIZE value is incorrect.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210913095440.13462-3-peter.maydell@linaro.org
Peter Maydell [Mon, 13 Sep 2021 09:54:29 +0000 (10:54 +0100)]
target/arm: Avoid goto_tb if we're trying to exit to the main loop
Currently gen_jmp_tb() assumes that if it is called then the jump it
is handling is the only reason that we might be trying to end the TB,
so it will use goto_tb if it can. This is usually the case: mostly
"we did something that means we must end the TB" happens on a
non-branch instruction. However, there are cases where we decide
early in handling an instruction that we need to end the TB and
return to the main loop, and then the insn is a complex one that
involves gen_jmp_tb(). For instance, for M-profile FP instructions,
in gen_preserve_fp_state() which is called from vfp_access_check() we
want to force an exit to the main loop if lazy state preservation is
active and we are in icount mode.
Make gen_jmp_tb() look at the current value of is_jmp, and only use
goto_tb if the previous is_jmp was DISAS_NEXT or DISAS_TOO_MANY.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210913095440.13462-2-peter.maydell@linaro.org
Alexander Graf [Thu, 16 Sep 2021 15:54:03 +0000 (17:54 +0200)]
hvf: arm: Add rudimentary PMC support
We can expose cycle counters on the PMU easily. To be as compatible as
possible, let's do so, but make sure we don't expose any other architectural
counters that we can not model yet.
This allows OSs to work that require PMU support.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
20210916155404.86958-10-agraf@csgraf.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alexander Graf [Thu, 16 Sep 2021 15:54:02 +0000 (17:54 +0200)]
arm: Add Hypervisor.framework build target
Now that we have all logic in place that we need to handle Hypervisor.framework
on Apple Silicon systems, let's add CONFIG_HVF for aarch64 as well so that we
can build it.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>
Tested-by: Roman Bolshakov <r.bolshakov@yadro.com> (x86 only)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id:
20210916155404.86958-9-agraf@csgraf.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alexander Graf [Thu, 16 Sep 2021 15:54:01 +0000 (17:54 +0200)]
hvf: arm: Implement PSCI handling
We need to handle PSCI calls. Most of the TCG code works for us,
but we can simplify it to only handle aa64 mode and we need to
handle SUSPEND differently.
This patch takes the TCG code as template and duplicates it in HVF.
To tell the guest that we support PSCI 0.2 now, update the check in
arm_cpu_initfn() as well.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
20210916155404.86958-8-agraf@csgraf.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Mon, 20 Sep 2021 09:21:08 +0000 (10:21 +0100)]
hvf: arm: Implement -cpu host
Now that we have working system register sync, we push more target CPU
properties into the virtual machine. That might be useful in some
situations, but is not the typical case that users want.
So let's add a -cpu host option that allows them to explicitly pass all
CPU capabilities of their host CPU into the guest.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Acked-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
20210916155404.86958-7-agraf@csgraf.de
[PMM: drop unnecessary #include line from .h file]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Collingbourne [Thu, 16 Sep 2021 15:53:59 +0000 (17:53 +0200)]
arm/hvf: Add a WFI handler
Sleep on WFI until the VTIMER is due but allow ourselves to be woken
up on IPI.
In this implementation IPI is blocked on the CPU thread at startup and
pselect() is used to atomically unblock the signal and begin sleeping.
The signal is sent unconditionally so there's no need to worry about
races between actually sleeping and the "we think we're sleeping"
state. It may lead to an extra wakeup but that's better than missing
it entirely.
Signed-off-by: Peter Collingbourne <pcc@google.com>
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Acked-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-id:
20210916155404.86958-6-agraf@csgraf.de
[agraf: Remove unused 'set' variable, always advance PC on WFX trap,
support vm stop / continue operations and cntv offsets]
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Acked-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Tue, 21 Sep 2021 12:58:09 +0000 (13:58 +0100)]
Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-
20210920' into staging
Aspeed patches :
* MAC enablement fixes (Guenter)
* Watchdog and pca9552 fixes (Andrew)
* GPIO fixes (Joel)
* AST2600A3 SoC and DPS310 models (Joel)
* New Fuji BMC machine (Peter)
# gpg: Signature made Mon 20 Sep 2021 07:51:23 BST
# gpg: using RSA key
A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* remotes/legoater/tags/pull-aspeed-
20210920:
hw/arm/aspeed: Add Fuji machine type
hw/arm/aspeed: Allow machine to set UART default
hw/arm/aspeed: Initialize AST2600 UART clock selection registers
arm/aspeed: Add DPS310 to Witherspoon and Rainier
hw/misc: Add Infineon DPS310 sensor model
aspeed: Emulate the AST2600A3
arm/aspeed: rainier: Add i2c eeproms and muxes
misc/pca9552: Fix LED status register indexing in pca955x_get_led()
hw: aspeed_gpio: Clarify GPIO controller name
hw: aspeed_gpio: Simplify 1.8V defines
watchdog: aspeed: Fix sequential control writes
watchdog: aspeed: Sanitize control register values
hw: arm: aspeed: Enable mac0/1 instead of mac1/2 for g220a
hw: arm: aspeed: Enable eth0 interface for aspeed-ast2600-evb
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alistair Francis [Thu, 16 Sep 2021 04:37:38 +0000 (14:37 +1000)]
hw/riscv: opentitan: Correct the USB Dev address
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
d6cb4dfe75a2f536f217d7075b750ece3acb1535.
1631767043.git.alistair.francis@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Bin Meng [Wed, 15 Sep 2021 08:46:01 +0000 (16:46 +0800)]
target/riscv: csr: Rename HCOUNTEREN_CY and friends
The macro name HCOUNTEREN_CY suggests it is for CSR HCOUNTEREN, but
in fact it applies to M-mode and S-mode CSR too. Rename these macros
to have the COUNTEREN_ prefix.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id:
20210915084601.24304-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Tue, 14 Sep 2021 01:37:15 +0000 (09:37 +0800)]
target/riscv: Backup/restore mstatus.SD bit when virtual register swapped
When virtual registers are swapped, mstatus.SD bit should also be
backed up/restored. Otherwise, mstatus.SD bit will be incorrectly kept
across the world switches.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Vincent Chen <vincent.chen@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id:
20210914013717.881430-1-frank.chang@sifive.com
[ Changes by AF:
- Convert variable to a uint64_t to fix clang error
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Bin Meng [Sat, 11 Sep 2021 15:34:31 +0000 (23:34 +0800)]
docs/system/riscv: sifive_u: Update U-Boot instructions
In U-Boot v2021.07 release, there were 2 major changes for the
SiFive Unleashed board support:
- Board config name was changed from sifive_fu540_defconfig to
sifive_unleashed_defconfig
- The generic binman tool was used to generate the FIT image
(combination of U-Boot proper, DTB and OpenSBI firmware)
which make the existing U-Boot instructions out of date.
Update the doc with latest instructions.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id:
20210911153431.10362-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Sun, 12 Sep 2021 13:05:48 +0000 (21:05 +0800)]
hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer
Real PDMA doesn't set Control.error if there are 0 bytes to be
transferred. The DMA transfer is still success.
The following result is PDMA tested in U-Boot on Unmatched board:
=> mw.l 0x3000000 0x0 <= Disclaim channel 0
=> mw.l 0x3000000 0x1 <= Claim channel 0
=> mw.l 0x3000004 0x55000000 <= wsize = rsize = 5 (2^5 = 32 bytes)
=> mw.q 0x3000008 0x0 <= NextBytes = 0
=> mw.q 0x3000010 0x84000000 <= NextDestination = 0x84000000
=> mw.q 0x3000018 0x84001000 <= NextSource = 0x84001000
=> mw.l 0x84000000 0x87654321 <= Fill test data to dst
=> mw.l 0x84001000 0x12345678 <= Fill test data to src
=> md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents
84000000:
87654321 !Ce.
84001000:
12345678 xV4.
=> md.l 0x3000000 8 <= Dump PDMA status
03000000:
00000001 55000000 00000000 00000000 .......U........
03000010:
84000000 00000000 84001000 00000000 ................
=> mw.l 0x3000000 0x3 <= Set channel 0 run and claim bits
=> md.l 0x3000000 8 <= Dump PDMA status
03000000:
40000001 55000000 00000000 00000000 ...@...U........
03000010:
84000000 00000000 84001000 00000000 ................
=> md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents
84000000:
87654321 !Ce.
84001000:
12345678 xV4.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Tested-by: Max Hsu <max.hsu@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
20210912130553.179501-5-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Green Wan [Sun, 12 Sep 2021 13:05:47 +0000 (21:05 +0800)]
hw/dma: sifive_pdma: allow non-multiple transaction size transactions
Real PDMA is able to deal with non-multiple transaction size transactions.
The following result is PDMA tested in U-Boot on Unmatched board:
=> mw.l 0x3000000 0x0 <= Disclaim channel 0
=> mw.l 0x3000000 0x1 <= Claim channel 0
=> mw.l 0x3000004 0x11000000 <= wsize = rsize = 1 (2^1 = 2 bytes)
=> mw.q 0x3000008 0x3 <= NextBytes = 3
=> mw.q 0x3000010 0x84000000 <= NextDestination = 0x84000000
=> mw.q 0x3000018 0x84001000 <= NextSource = 0x84001000
=> mw.l 0x84000000 0x87654321 <= Fill test data to dst
=> mw.l 0x84001000 0x12345678 <= Fill test data to src
=> md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents
84000000:
87654321 !Ce.
84001000:
12345678 xV4.
=> md.l 0x3000000 8 <= Dump PDMA status
03000000:
00000001 11000000 00000003 00000000 ................
03000010:
84000000 00000000 84001000 00000000 ................
=> mw.l 0x3000000 0x3 <= Set channel 0 run and claim bits
=> md.l 0x3000000 8 <= Dump PDMA status
03000000:
40000001 11000000 00000003 00000000 ...@............
03000010:
84000000 00000000 84001000 00000000 ................
=> md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents
84000000:
87345678 xV4.
84001000:
12345678 xV4.
Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Tested-by: Max Hsu <max.hsu@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Message-id:
20210912130553.179501-4-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Sun, 12 Sep 2021 13:05:46 +0000 (21:05 +0800)]
hw/dma: sifive_pdma: claim bit must be set before DMA transactions
Real PDMA must have Control.claim bit to be set before
Control.run bit is set to start any DMA transactions.
Otherwise nothing will be transferred.
The following result is PDMA tested in U-Boot on Unmatched board:
=> mw.l 0x3000000 0x0 <= Disclaim channel 0
(Channel 0 is not claimed)
=> mw.l 0x3000004 0x55000000 <= wsize = rsize = 5 (2^5 = 32 bytes)
=> mw.q 0x3000008 0x2 <= NextBytes = 2
=> mw.q 0x3000010 0x84000000 <= NextDestination = 0x84000000
=> mw.q 0x3000018 0x84001000 <= NextSource = 0x84001000
=> mw.l 0x84000000 0x87654321 <= Fill test data to dst
=> mw.l 0x84001000 0x12345678 <= Fill test data to src
=> md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents
84000000:
87654321 !Ce.
84001000:
12345678 xV4.
=> md.l 0x3000000 8 <= Dump PDMA status
03000000:
00000000 55000000 00000002 00000000 .......U........
03000010:
84000000 00000000 84001000 00000000 ................
=> mw.l 0x3000000 0x3 <= Set channel 0 run and claim bits
=> md.l 0x3000000 8 <= Dump PDMA status
03000000:
00000001 66000000 00000000 00000000 .......f........
03000010:
00000000 00000000 00000000 00000000 ................
=> md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents
84000000:
87654321 !Ce.
84001000:
12345678 xV4.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Tested-by: Max Hsu <max.hsu@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
20210912130553.179501-3-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Sun, 12 Sep 2021 13:05:45 +0000 (21:05 +0800)]
hw/dma: sifive_pdma: reset Next* registers when Control.claim is set
Setting Control.claim clears all of the chanel's Next registers.
This is effective only when Control.claim is set from 0 to 1.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Tested-by: Max Hsu <max.hsu@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
20210912130553.179501-2-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anup Patel [Tue, 31 Aug 2021 11:06:03 +0000 (16:36 +0530)]
hw/riscv: virt: Add optional ACLINT support to virt machine
We extend virt machine to emulate ACLINT devices only when "aclint=on"
parameter is passed along with machine name in QEMU command-line.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
20210831110603.338681-5-anup.patel@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anup Patel [Tue, 31 Aug 2021 11:06:02 +0000 (16:36 +0530)]
hw/riscv: virt: Re-factor FDT generation
We re-factor and break the FDT generation into smaller functions
so that it is easier to modify FDT generation for different
configurations of virt machine.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
20210831110603.338681-4-anup.patel@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anup Patel [Tue, 31 Aug 2021 11:06:01 +0000 (16:36 +0530)]
hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
The RISC-V ACLINT is more modular and backward compatible with
original SiFive CLINT so instead of duplicating the original
SiFive CLINT implementation we upgrade the current SiFive CLINT
implementation to RISC-V ACLINT implementation.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
20210831110603.338681-3-anup.patel@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anup Patel [Tue, 31 Aug 2021 11:06:00 +0000 (16:36 +0530)]
hw/intc: Rename sifive_clint sources to riscv_aclint sources
We will be upgrading SiFive CLINT implementation into RISC-V ACLINT
implementation so let's first rename the sources.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
20210831110603.338681-2-anup.patel@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Alistair Francis [Thu, 9 Sep 2021 03:55:15 +0000 (13:55 +1000)]
sifive_u: Connect the SiFive PWM device
Connect the SiFive PWM device and expose it via the device tree.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
22f98648b4e012f78529a56f5ca60b0b27852a4d.
1631159656.git.alistair.francis@wdc.com
Alistair Francis [Thu, 9 Sep 2021 03:55:02 +0000 (13:55 +1000)]
hw/timer: Add SiFive PWM support
This is the initial commit of the SiFive PWM timer. This is used by
guest software as a timer and is included in the SiFive FU540 SoC.
Signed-off-by: Justin Restivo <jrestivo@draper.com>
Signed-off-by: Alexandra Clifford <aclifford@draper.com>
Signed-off-by: Amanda Strnad <astrnad@draper.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
9f70a210acbfaf0e1ea6ad311ab892ac69134d8b.
1631159656.git.alistair.francis@wdc.com
Alistair Francis [Mon, 30 Aug 2021 05:35:15 +0000 (15:35 +1000)]
hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines
Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the timer MIP bits.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
84d5b1d5783d2e79eee69a2f7ac480cc0c070db3.
1630301632.git.alistair.francis@wdc.com
Alistair Francis [Mon, 30 Aug 2021 05:35:02 +0000 (15:35 +1000)]
hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines
Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the external MIP bits.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
0364190bfa935058a845c0fa1ecf650328840ad5.
1630301632.git.alistair.francis@wdc.com
Alistair Francis [Mon, 30 Aug 2021 05:34:49 +0000 (15:34 +1000)]
hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines
Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the external MIP bits.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
0a76946981852f5bd15f0c37ab35b253371027a8.
1630301632.git.alistair.francis@wdc.com
Alistair Francis [Mon, 30 Aug 2021 05:34:36 +0000 (15:34 +1000)]
hw/intc: sifive_clint: Use RISC-V CPU GPIO lines
Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the timer and soft MIP bits.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-id:
946e1ef5e268b24084c7ddad84c146de62a56736.
1630301632.git.alistair.francis@wdc.com
Alistair Francis [Mon, 30 Aug 2021 05:34:20 +0000 (15:34 +1000)]
target/riscv: Expose interrupt pending bits as GPIO lines
Expose the 12 interrupt pending bits in MIP as GPIO lines.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
069d6162f0bc2f4a4f5a44e73f6442b11c703c53.
1630301632.git.alistair.francis@wdc.com
LIU Zhiwei [Wed, 1 Sep 2021 12:45:39 +0000 (20:45 +0800)]
target/riscv: Fix satp write
These variables should be target_ulong. If truncated to int,
the bool conditions they indicate will be wrong.
As satp is very important for Linux, this bug almost fails every boot.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id:
20210901124539.222868-1-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Alistair Francis [Thu, 2 Sep 2021 00:40:10 +0000 (10:40 +1000)]
target/riscv: Update the ePMP CSR address
Update the ePMP CSRs to match the 0.9.3 ePMP spec
https://github.com/riscv/riscv-tee/blob/
61455747230a26002d741f64879dd78cc9689323/Smepmp/Smepmp.pdf
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
28c908de60b9b04fa20e63d113885c98586053f3.
1630543194.git.alistair.francis@wdc.com
Peter Maydell [Mon, 20 Sep 2021 15:17:05 +0000 (16:17 +0100)]
Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging
# gpg: Signature made Fri 17 Sep 2021 09:17:32 BST
# gpg: using RSA key
EF04965B398D6211
# gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [marginal]
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg: It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211
* remotes/jasowang/tags/net-pull-request:
virtio-net: fix use after unmap/free for sg
ebpf: only include in system emulators
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Mon, 20 Sep 2021 13:20:03 +0000 (14:20 +0100)]
Merge remote-tracking branch 'remotes/jsnow-gitlab/tags/python-pull-request' into staging
Python Pull request
This fixes the check-python-tox job.
CI including optional jobs is all green:
https://gitlab.com/jsnow/qemu/-/pipelines/
372151147
# gpg: Signature made Thu 16 Sep 2021 23:05:35 BST
# gpg: using RSA key
F9B7ABDBBCACDF95BE76CBD07DEF8106AAFC390E
# gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>" [full]
# Primary key fingerprint: FAEB 9711 A12C F475 812F 18F2 88A9 064D 1835 61EB
# Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76 CBD0 7DEF 8106 AAFC 390E
* remotes/jsnow-gitlab/tags/python-pull-request:
python: pylint 2.11 support
python: Update for pylint 2.10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alexander Graf [Thu, 16 Sep 2021 15:53:58 +0000 (17:53 +0200)]
hvf: Add Apple Silicon support
With Apple Silicon available to the masses, it's a good time to add support
for driving its virtualization extensions from QEMU.
This patch adds all necessary architecture specific code to get basic VMs
working, including save/restore.
Known limitations:
- WFI handling is missing (follows in later patch)
- No watchpoint/breakpoint support
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
20210916155404.86958-5-agraf@csgraf.de
[PMM: added missing #include]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alexander Graf [Thu, 16 Sep 2021 15:53:57 +0000 (17:53 +0200)]
hvf: Introduce hvf_arch_init() callback
We will need to install a migration helper for the ARM hvf backend.
Let's introduce an arch callback for the overall hvf init chain to
do so.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
20210916155404.86958-4-agraf@csgraf.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>