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Heejin Ahn [Thu, 8 Mar 2018 04:05:37 +0000 (04:05 +0000)]
[WebAssembly] Add except_ref as a first-class type
Summary: Add except_ref as a first-class type, according to the [[https://github.com/WebAssembly/exception-handling/blob/master/proposals/Level-1.md | Level 1 exception handling proposal ]].
Reviewers: dschuff
Subscribers: jfb, sbc100, llvm-commits
Differential Revision: https://reviews.llvm.org/D43706
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326985
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Heejin Ahn [Thu, 8 Mar 2018 03:47:52 +0000 (03:47 +0000)]
[WebAssembly] Add IntrNoReturn property to throw/rethrow intrinsics
Reviewers: dschuff
Subscribers: jfb, sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D43740
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326984
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Daniel Sanders [Thu, 8 Mar 2018 02:36:25 +0000 (02:36 +0000)]
Support resetting STATISTIC() values using llvm::ResetStatistics()
Summary:
Most of the time, compiler statistics can be obtained using a process that
performs a single compilation and terminates such as llc. However, this isn't
always the case. JITs for example, perform multiple compilations over their
lifetime and STATISTIC() will record cumulative values across all of them.
Provide tools like this with the facilities needed to measure individual
compilations by allowing them to reset the STATISTIC() values back to zero using
llvm::ResetStatistics(). It's still the tools responsibility to ensure that they
perform compilations in such a way that the results are meaningful to their
intended use.
Reviewers: qcolombet, rtereshin, bogner, aditya_nandakumar
Reviewed By: bogner
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44181
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326981
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Fangrui Song [Thu, 8 Mar 2018 01:28:45 +0000 (01:28 +0000)]
Add attributes and fix some keywords in llvm-mode.el
Reviewers: rafael, echristo
Reviewed By: echristo
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44135
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326978
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Bob Haarman [Thu, 8 Mar 2018 01:13:10 +0000 (01:13 +0000)]
Revert "[LTO] Support filtering by hotness threshold"
This reverts commit
1f3bd185c53beb6aa68446974b7e80837abd6ef0 (r326107)
because it fails
ThinLTO/X86/diagnostic-handler-remarks-with-hotness.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326975
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Rafael Auler [Thu, 8 Mar 2018 00:46:53 +0000 (00:46 +0000)]
Reland "[DebugInfo] Support DWARF expressions in eh_frame"
Summary:
Original change was D43313 (r326932) and reverted by r326953 because it
broke an LLD test and a windows build. The LLD test was already fixed in
lld commit r326944 (thanks maskray). This is the original change with
the windows build fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326970
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Weiming Zhao [Thu, 8 Mar 2018 00:28:25 +0000 (00:28 +0000)]
[AArch64] Fix UB about shift amount exceeds data bit-width
Summary:
Fixes an UB caught by sanitizer. The shift amount might be larger than 32 so the operand should be 1ULL.
In this patch, we replace the original expression with existing API with uint64_t type.
Reviewers: eli.friedman, rengolin
Reviewed By: rengolin
Subscribers: rengolin, javed.absar, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D44234
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326969
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Craig Topper [Thu, 8 Mar 2018 00:21:17 +0000 (00:21 +0000)]
[X86] Fix some isel patterns that used aligned vector load instructions with unaligned predicates.
These patterns weren't checking the alignment of the load, but were using the aligned instructions. This will cause a GP fault if the data isn't aligned.
I believe these were introduced in r312450.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326967
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Rafael Espindola [Thu, 8 Mar 2018 00:17:13 +0000 (00:17 +0000)]
Delete code that is probably dead since r249303.
With r249303 the expression evaluation should expand variables that
are not in sections (and so don't have an atom).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326966
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Eugene Zemtsov [Thu, 8 Mar 2018 00:07:26 +0000 (00:07 +0000)]
Fix build broken by r326959
Adding Demangle to link time dependencies of Symbolize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326964
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Simon Pilgrim [Wed, 7 Mar 2018 23:56:42 +0000 (23:56 +0000)]
[X86][SSE] LowerBUILD_VECTORAsVariablePermute - reorder permute types. NFCI.
Reorder into 128/256/512 bit vector size groupings.
NFCI commit before some new features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326963
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Eugene Zemtsov [Wed, 7 Mar 2018 23:07:34 +0000 (23:07 +0000)]
Use itaniumDemangle in llvm-symbolizer
Currently on Windows (_MSC_VER) LLVMSymbolizer supports only Microsoft mangling.
This fix just explicitly uses itaniumDemangle when mangled name starts with _Z.
Differential Revision: https://reviews.llvm.org/D44192
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326959
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Sanjay Patel [Wed, 7 Mar 2018 22:43:08 +0000 (22:43 +0000)]
[TTI] add explanatory comments for getArithmeticInstrCost; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326956
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Evandro Menezes [Wed, 7 Mar 2018 22:35:32 +0000 (22:35 +0000)]
[AArch64] Adjust the cost of integer vector division
Since there is no instruction for integer vector division, factor in the
cost of singling out each element to be used with the scalar division
instruction.
Differential revision: https://reviews.llvm.org/D43974
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326955
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Rui Ueyama [Wed, 7 Mar 2018 22:29:48 +0000 (22:29 +0000)]
Revert r326932: [DebugInfo] Support DWARF expressions in eh_frame
This reverts commit rr326932 because it broke lld/test/ELF/eh-frame-hdr-augmentation.s.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326953
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Sebastian Pop [Wed, 7 Mar 2018 22:07:13 +0000 (22:07 +0000)]
[AArch64] add missing pattern for insert_subvector undef
The attached testcase started failing after the patch to define
isExtractSubvectorCheap with the following pattern mismatch:
ISEL: Starting pattern match
Initial Opcode index to 85068
Match failed at index 85076
LLVM ERROR: Cannot select: t47: v8i16 = insert_subvector undef:v8i16, t43, Constant:i64<0>
The code generated from llvm/lib/Target/AArch64/AArch64InstrInfo.td
def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
(INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
is in ninja/lib/Target/AArch64/AArch64GenDAGISel.inc
At the location of the error it is:
/* 85076*/ OPC_CheckChild2Type, MVT::i32,
And it failed to match the type of operand 2.
Adding another def-pat for i64 fixes the failed def-pat error:
def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i64 0)),
(INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326949
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Jake Ehrlich [Wed, 7 Mar 2018 20:33:02 +0000 (20:33 +0000)]
Revert "[llvm-objcopy] Add support for large indexes"
Not all build bots have unzip which I used in a test.
This reverts commit
0b1f26d39ea42dd3716b525fbc8c78d8c7bb4479.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326941
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Jake Ehrlich [Wed, 7 Mar 2018 19:59:15 +0000 (19:59 +0000)]
[llvm-objcopy] Add support for large indexes
Because of -ffunction-sections (and maybe other use cases I'm not aware of?) it
can occur that we need more than 0xfeff sections but ELF dosn't support that
many sections. To solve this problem SHN_XINDEX exists and with it come a whole
host of changes for section indexes everywhere. This change adds support for
those cases which should allow llvm-objcopy to copy binaries that have an
arbitrary number of sections.
Differential Revision: https://reviews.llvm.org/D42516
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326940
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Craig Topper [Wed, 7 Mar 2018 19:45:45 +0000 (19:45 +0000)]
[X86] Remove unused function argument. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326939
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Daniel Sanders [Wed, 7 Mar 2018 19:32:36 +0000 (19:32 +0000)]
Fix cmake's multi-config generators after r326738
LLVM_ENABLE_STATS isn't known at configure-time in these generators so we must
defer it to build-time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326936
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Rafael Auler [Wed, 7 Mar 2018 19:19:51 +0000 (19:19 +0000)]
[DebugInfo] Support DWARF expressions in eh_frame
This patch enhances DWARFDebugFrame with the capability of parsing and
printing DWARF expressions in CFI instructions. It also makes FDEs and
CIEs accessible to lib users, so they can process them in client tools
that rely on LLVM. To make it self-contained with a test case, it
teaches llvm-readobj to be able to dump EH frames and checks they are
correct in a unit test. The llvm-readobj code is Maksim Panchenko's work
(maksfb).
Reviewers: JDevlieghere, espindola
Reviewed By: JDevlieghere
Differential Revision: https://reviews.llvm.org/D43313
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326932
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Simon Pilgrim [Wed, 7 Mar 2018 19:14:05 +0000 (19:14 +0000)]
[X86][SSE] Regenerate float maxnum/minnum tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326930
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Zachary Turner [Wed, 7 Mar 2018 19:12:36 +0000 (19:12 +0000)]
Fix a bug regarding a mis-identified file type in pdbutil.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326929
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Zachary Turner [Wed, 7 Mar 2018 18:58:33 +0000 (18:58 +0000)]
Update a few switch statements to handle file_magic::pdb.
This fixes a couple of warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326927
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Roorda, Jan-Willem [Wed, 7 Mar 2018 18:53:36 +0000 (18:53 +0000)]
[Pipeliner] Fixed node order issue related to zero latency edges
Summary:
A desired property of the node order in Swing Modulo Scheduling is
that for nodes outside circuits the following holds: none of them is
scheduled after both a successor and a predecessor. We call
node orders that meet this property valid.
Although invalid node orders do not lead to the generation of incorrect
code, they can cause the pipeliner not being able to find a pipelined schedule
for arbitrary II. The reason is that after scheduling the successor and the
predecessor of a node, no room may be left to schedule the node itself.
For data flow graphs with 0-latency edges, the node ordering algorithm
of Swing Modulo Scheduling can generate such undesired invalid node orders.
This patch fixes that.
In the remainder of this commit message, I will give an example
demonstrating the issue, explain the fix, and explain how the the fix is tested.
Consider, as an example, the following data flow graph with all
edge latencies 0 and all edges pointing downward.
```
n0
/ \
n1 n3
\ /
n2
|
n4
```
Consider the implemented node order algorithm in top-down mode. In that mode,
the algorithm orders the nodes based on greatest Height and in case of equal
Height on lowest Movability. Finally, in case of equal Height and
Movability, given two nodes with an edge between them, the algorithm prefers
the source-node.
In the graph, for every node, the Height and Movability are equal to 0.
As will be explained below, the algorithm can generate the order n0, n1, n2, n3, n4.
So, node n3 is scheduled after its predecessor n0 and after its successor n2.
The reason that the algorithm can put node n2 in the order before node n3,
even though they have an edge between them in which node n3 is the source,
is the following: Suppose the algorithm has constructed the partial node
order n0, n1. Then, the nodes left to be ordered are nodes n2, n3, and n4. Suppose
that the while-loop in the implemented algorithm considers the nodes in
the order n4, n3, n2. The algorithm will start with node n4, and look for
more preferable nodes. First, node n4 will be compared with node n3. As the nodes
have equal Height and Movability and have no edge between them, the algorithm
will stick with node n4. Then node n4 is compared with node n2. Again the
Height and Movability are equal. But, this time, there is an edge between
the two nodes, and the algorithm will prefer the source node n2.
As there are no nodes left to compare, the algorithm will add node n2 to
the node order, yielding the partial node order n0, n1, n2. In this way node n2
arrives in the node-order before node n3.
To solve this, this patch introduces the ZeroLatencyHeight (ZLH) property
for nodes. It is defined as the maximum unweighted length of a path from the
given node to an arbitrary node in which each edge has latency 0.
So, ZLH(n0)=3, ZLH(n1)=ZLH(n3)=2, ZLH(n2)=1, and ZLH(n4)=0
In this patch, the preference for a greater ZeroLatencyHeight
is added in the top-down mode of the node ordering algorithm, after the
preference for a greater Height, and before the preference for a
lower Movability.
Therefore, the two allowed node-orders are n0, n1, n3, n2, n4 and n0, n3, n1, n2, n4.
Both of them are valid node orders.
In the same way, the bottom-up mode of the node ordering algorithm is adapted
by introducing the ZeroLatencyDepth property for nodes.
The patch is tested by adding extra checks to the following existing
lit-tests:
test/CodeGen/Hexagon/SUnit-boundary-prob.ll
test/CodeGen/Hexagon/frame-offset-overflow.ll
test/CodeGen/Hexagon/vect/vect-shuffle.ll
Before this patch, the pipeliner failed to pipeline the loops in these tests
due to invalid node-orders. After the patch, the pipeliner successfully
pipelines all these loops.
Reviewers: bcahoon
Reviewed By: bcahoon
Subscribers: Ayal, mgrang, llvm-commits
Differential Revision: https://reviews.llvm.org/D43620
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326925
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Zachary Turner [Wed, 7 Mar 2018 18:40:41 +0000 (18:40 +0000)]
Teach identify_file_magic to identify PDB files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326924
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Stefan Pintilie [Wed, 7 Mar 2018 18:27:10 +0000 (18:27 +0000)]
[PowerPC] Move test to correct location.
Test was added in r326906 to an incorrect location.
Moving the test to PPC CodeGen directory as the test is PPC specific.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326923
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Craig Topper [Wed, 7 Mar 2018 17:53:18 +0000 (17:53 +0000)]
[X86] Make the MUL->VPMADDWD work before op legalization on AVX1 targets. Simplify feature checks by using isTypeLegal.
The v8i32 conversion on AVX1 targets was only working after LowerMUL splits 256-bit vectors.
While I was there I've also made it so we don't have to check for AVX2 and BWI directly and instead just ask if the type is legal.
Differential Revision: https://reviews.llvm.org/D44190
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326917
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Craig Topper [Wed, 7 Mar 2018 17:53:16 +0000 (17:53 +0000)]
[Support] Stop passing StringRefs by const reference in some of the getHostCPUname implementations. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326916
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Krzysztof Parzyszek [Wed, 7 Mar 2018 17:27:18 +0000 (17:27 +0000)]
[Hexagon] Rewrite non-HVX unaligned loads as pairs of aligned ones
This is a follow-up to r325169, this time for all types, not just HVX
vector types.
Disable this by default, since it's not always safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326915
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Sanjay Patel [Wed, 7 Mar 2018 17:18:22 +0000 (17:18 +0000)]
[LangRef] fix formatting in FP descriptions; NFC
This is a clean-up step to reduce diffs ahead of real
changes to the FP semantics as discussed on llvm-dev:
http://lists.llvm.org/pipermail/llvm-dev/2018-February/121444.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326913
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Farhana Aleen [Wed, 7 Mar 2018 17:09:18 +0000 (17:09 +0000)]
[AMDGPU] Increased vector length for global/constant loads.
Summary: GCN ISA supports instructions that can read 16 consecutive dwords from memory through the scalar data cache;
loadstoreVectorizer should take advantage of the wider vector length and pack 16/8 elements of dwords/quadwords.
Author: FarhanaAleen
Reviewed By: rampitec
Subscribers: llvm-commits, AMDGPU
Differential Revision: https://reviews.llvm.org/D44179
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326910
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Justin Lebar [Wed, 7 Mar 2018 16:56:49 +0000 (16:56 +0000)]
Re-land: Teach CorrelatedValuePropagation to reduce the width of udiv/urem instructions.
Summary:
If the operands of a udiv/urem can be proved to fit within a smaller
power-of-two-sized type, reduce the width of the udiv/urem.
Backed out for failing an assert in clang bootstrap builds. Re-landing
with a fix for handling non-power-of-two inputs (e.g. udiv i24).
Original Differential Revision: https://reviews.llvm.org/D44102
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326908
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Farhana Aleen [Wed, 7 Mar 2018 16:55:27 +0000 (16:55 +0000)]
Revert "[AMDGPU] Widened vector length for global/constant address space."
This reverts commit
ce988cc100dc65e7c6c727aff31ceb99231cab03.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326907
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Stefan Pintilie [Wed, 7 Mar 2018 16:53:09 +0000 (16:53 +0000)]
[PowerPC] LSR tunings for PowerPC
The purpose of this patch is to have LSR generate better code on Power.
This is done by overriding isLSRCostLess.
Differential Revision: https://reviews.llvm.org/D40855
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326906
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Wei Mi [Wed, 7 Mar 2018 16:45:33 +0000 (16:45 +0000)]
[SampleFDO] Extend SampleProfReader to handle demangled names.
SampleProfReader assumes function names in the profile are all mangled names.
However, there are cases that few demangled names are somehow contained in
the profile (usually because of debug info problems), which may trigger parsing
error in SampleProfReader and cause the whole profile to be unusable. The patch
extends SampleProfReader to handle profiles with demangled names, so that those
profiles can still be useful.
Differential revision: https://reviews.llvm.org/D44161
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326905
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Farhana Aleen [Wed, 7 Mar 2018 16:29:05 +0000 (16:29 +0000)]
[AMDGPU] Widened vector length for global/constant address space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326904
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Jonas Devlieghere [Wed, 7 Mar 2018 16:28:53 +0000 (16:28 +0000)]
[dwarfdump] Only print CU relative offset in verbose mode
Instead of only printing the CU-relative offset in non-verbose mode, it
makes more sense to only printed the resolved address. In verbose mode
we still print both.
Differential revision: https://reviews.llvm.org/D44148
rdar://
33525475
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326903
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Alexander Kornienko [Wed, 7 Mar 2018 16:27:44 +0000 (16:27 +0000)]
Revert "Reapply "[DWARFv5] Emit file 0 to the line table.""
This reverts commit r326839.
r326839 breaks assembly file parsing:
$ cat q.c
void g() {}
$ clang -S q.c -g
$ clang -g -c q.s
q.s:9:2: error: file number already allocated
.file 1 "/tmp/test" "q.c"
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326902
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Justin Lebar [Wed, 7 Mar 2018 16:05:43 +0000 (16:05 +0000)]
Revert rL326898: "Teach CorrelatedValuePropagation to reduce the width of udiv/urem instructions."
Breaks bootstrap builds: clang built with this patch asserts while
building MCDwarf.cpp: Assertion `castIsValid(op, S, Ty) && "Invalid
cast!"' failed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326900
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Justin Lebar [Wed, 7 Mar 2018 15:11:13 +0000 (15:11 +0000)]
Teach CorrelatedValuePropagation to reduce the width of udiv/urem instructions.
Summary:
If the operands of a udiv/urem can be proved to fit within a smaller
power-of-two-sized type, reduce the width of the udiv/urem.
Reviewers: spatel, sanjoy
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D44102
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326898
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Simon Pilgrim [Wed, 7 Mar 2018 14:13:14 +0000 (14:13 +0000)]
[X86][X87] Add X87 fp80 conversion tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326897
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Simon Dardis [Wed, 7 Mar 2018 11:39:48 +0000 (11:39 +0000)]
[mips] Correct the definition of m(f|t)c(0|2)
These instructions are defined as taking a GPR register and a
coprocessor register for ISAs up to MIPS32. MIPS32 extended the
definition to allow a selector--a value from 0 to 32--to access
another register.
These instructions are now internally defined as being MIPS-I
instructions, but are rejected for pre-MIPS32 ISA's if they have
an explicit selector which is non-zero. This deviates slightly from
GAS's behaviour which rejects assembly instructions with an
explicit selector for pre-MIPS32 ISAs.
E.g:
mfc0 $4, $5, 0
is rejected by GAS for MIPS-I to MIPS-V but will be accepted
with this patch for MIPS-I to MIPS-V.
Reviewers: atanasyan
Differential Revision: https://reviews.llvm.org/D41662
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326890
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Sven van Haastregt [Wed, 7 Mar 2018 10:29:28 +0000 (10:29 +0000)]
[LoadStoreVectorizer] Differentiate between <1 x T> and T
The LoadStoreVectorizer thought that <1 x T> and T were the same types
when merging stores, leading to a crash later.
Patch by Erik Hogeman.
Differential Revision: https://reviews.llvm.org/D44014
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326884
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Sjoerd Meijer [Wed, 7 Mar 2018 09:10:44 +0000 (09:10 +0000)]
[ARM] Fix for PR36577
Don't PerformSHLSimplify if the given node is used by a node that also uses a
constant because we may get stuck in an infinite combine loop.
bugzilla: https://bugs.llvm.org/show_bug.cgi?id=36577
Patch by Sam Parker.
Differential Revision: https://reviews.llvm.org/D44097
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326882
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Jonas Paulsson [Wed, 7 Mar 2018 08:57:09 +0000 (08:57 +0000)]
[SystemZ] NFC refactoring in SystemZHazardRecognizer.
Use Reset() after emitting a call.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326881
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Jonas Paulsson [Wed, 7 Mar 2018 08:54:32 +0000 (08:54 +0000)]
[SystemZ] Improve getCurrCycleIdx() in SystemZHazardRecognizer.
getCurrCycleIdx() returns the decoder cycle index which the next candidate SU
will be placed on.
This patch improves this method by passing the candidate SU to it so that if
SU will begin a new group, the index of that group is returned instead.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326880
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Jonas Paulsson [Wed, 7 Mar 2018 08:45:09 +0000 (08:45 +0000)]
[SystemZ] NFC refactoring in SystemZHazardRecognizer.
Handle the not-taken branch in emitInstruction() where the TakenBranch
argument is available. This is cleaner than relying on EmitInstruction().
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326879
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Jonas Paulsson [Wed, 7 Mar 2018 08:39:00 +0000 (08:39 +0000)]
[SystemZ] Improved debug dumping during post-RA scheduling.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326878
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Clement Courbet [Wed, 7 Mar 2018 08:14:02 +0000 (08:14 +0000)]
[X86] Add IMUL scheduling info on sandybridge, fix it on >=haswell.
Summary:
Only IMUL16rri uses an extra P0156. IMUL32* and IMUL16rr only use
P1.
This was computed using https://github.com/google/EXEgesis/blob/master/exegesis/tools/compute_itineraries.cc
This can easily be validated by running perf on the following code:
```
int main(int argc, char**argv) {
int a = argc;
int b = argc;
int c = argc;
int d = argc;
for (int i = 0; i < LOOP_ITERATIONS; ++i) {
asm volatile(
R"(
.rept 10000
imull $0x2, %%edx, %%eax
imull $0x2, %%ecx, %%ebx
imull $0x2, %%eax, %%edx
imull $0x2, %%ebx, %%ecx
.endr
)"
: "+a"(a), "+b"(b), "+c"(c), "+d"(d)
:
:);
}
return a+b+c+d;
}
```
-> test.cc
perf stat -x, -e cycles --pfm-events=uops_executed_port:port_0:u,uops_executed_port:port_1:u,uops_executed_port:port_2:u,uops_executed_port:port_3:u,uops_executed_port:port_4:u,uops_executed_port:port_5:u,uops_executed_port:port_6:u,uops_executed_port:port_7:u test
Reviewers: craig.topper, RKSimon, gadi.haber
Subscribers: llvm-commits, gchatelet, chandlerc
Differential Revision: https://reviews.llvm.org/D43460
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326877
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Aaron Smith [Wed, 7 Mar 2018 02:23:08 +0000 (02:23 +0000)]
[llvm-pdbdump] Add guard for null pointers and remove unused code
Summary: This avoids crashing when a user tries to dump a pdb with the `-native` option.
Reviewers: zturner, llvm-commits, rnk
Reviewed By: zturner
Subscribers: mgrang
Differential Revision: https://reviews.llvm.org/D44117
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326863
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Evgeny Stupachenko [Wed, 7 Mar 2018 02:17:08 +0000 (02:17 +0000)]
Add early exit on reassociation of 0 expression.
Summary:
Before the patch a try to reassociate ((v * 16) * 0) * 1 fall into infinite loop
Reviewers: pankajchawla
Differential Revision: http://reviews.llvm.org/D41467
From: Evgeny Stupachenko <evstupac@gmail.com>
<evgeny.v.stupachenko@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326861
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Aaron Smith [Wed, 7 Mar 2018 00:33:09 +0000 (00:33 +0000)]
[DebugInfoPDB] Add DIA implementation for getSrcLineOnTypeDefn
Summary: This helps to determine the line number for a PDB type with definition
Reviewers: zturner, llvm-commits, rnk
Reviewed By: zturner
Subscribers: rengolin, JDevlieghere
Differential Revision: https://reviews.llvm.org/D44119
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326857
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Eugene Zelenko [Tue, 6 Mar 2018 23:06:13 +0000 (23:06 +0000)]
[Transforms] Add missing header for InstructionCombining.cpp, in order to export LLVMInitializeInstCombine as extern "C". Fixes PR35947.
Patch by Brenton Bostick.
Differential revision: https://reviews.llvm.org/D44140
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326843
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Craig Topper [Tue, 6 Mar 2018 22:45:31 +0000 (22:45 +0000)]
[X86] Fix a typo in Host.cpp that causes us to misidentify KNL, Silvermont, Goldmont and probably other CPUs for -march=native
I think most of the Intel Core CPUs and recent AMD CPUs are unaffected. All the CPUs that have a "subtype" should work. The ones that were broken are the ones that are a "type" with no subtypes.
Fixes PR36619.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326840
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Paul Robinson [Tue, 6 Mar 2018 22:37:45 +0000 (22:37 +0000)]
Reapply "[DWARFv5] Emit file 0 to the line table."
Fixes the bug found by asan. Also XFAIL the new test for Darwin,
which is stuck on DWARF v2, and fix up other tests so they stop
failing on Windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326839
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Simon Pilgrim [Tue, 6 Mar 2018 22:32:01 +0000 (22:32 +0000)]
[TargetLowering] Add vector BITCAST support to SimplifyDemandedVectorElts
Notably helps cleanup after legalization of vector types
Differential Revision: https://reviews.llvm.org/D43674
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326838
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Sebastian Pop [Tue, 6 Mar 2018 21:55:59 +0000 (21:55 +0000)]
DA: remove uses of GEP, only ask SCEV
It's been quite some time the Dependence Analysis (DA) is broken,
as it uses the GEP representation to "identify" multi-dimensional arrays.
It even wrongly detects multi-dimensional arrays in single nested loops:
from test/Analysis/DependenceAnalysis/Coupled.ll, example @couple6
;; for (long int i = 0; i < 50; i++) {
;; A[i][3*i - 6] = i;
;; *B++ = A[i][i];
DA used to detect two subscripts, which makes no sense in the LLVM IR
or in C/C++ semantics, as there are no guarantees as in Fortran of
subscripts not overlapping into a next array dimension:
maximum nesting levels = 1
SrcPtrSCEV = %A
DstPtrSCEV = %A
using GEPs
subscript 0
src = {0,+,1}<nuw><nsw><%for.body>
dst = {0,+,1}<nuw><nsw><%for.body>
class = 1
loops = {1}
subscript 1
src = {-6,+,3}<nsw><%for.body>
dst = {0,+,1}<nuw><nsw><%for.body>
class = 1
loops = {1}
Separable = {}
Coupled = {1}
With the current patch, DA will correctly work on only one dimension:
maximum nesting levels = 1
SrcSCEV = {(-2424 + %A)<nsw>,+,1212}<%for.body>
DstSCEV = {%A,+,404}<%for.body>
subscript 0
src = {(-2424 + %A)<nsw>,+,1212}<%for.body>
dst = {%A,+,404}<%for.body>
class = 1
loops = {1}
Separable = {0}
Coupled = {}
This change removes all uses of GEP from DA, and we now only rely
on the SCEV representation.
The patch does not turn on -da-delinearize by default, and so the DA analysis
will be more conservative in the case of multi-dimensional memory accesses in
nested loops.
I disabled some interchange tests, as the DA is not able to disambiguate
the dependence anymore. To make DA stronger, we may need to
compute a bound on the number of iterations based on the access functions
and array dimensions.
The patch cleans up all the CHECKs in test/Transforms/LoopInterchange/*.ll to
avoid checking for snippets of LLVM IR: this form of checking is very hard to
maintain. Instead, we now check for output of the pass that are more meaningful
than dozens of lines of LLVM IR. Some tests now require -debug messages and thus
only enabled with asserts.
Patch written by Sebastian Pop and Aditya Kumar.
Differential Revision: https://reviews.llvm.org/D35430
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326837
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Daniel Sanders [Tue, 6 Mar 2018 21:16:42 +0000 (21:16 +0000)]
PrintStatistics() and PrintStatisticsJSON() should take StatLock
These two functions iterate over the list of statistics but don't take the lock
that protects the iterators from being invalidated by
StatisticInfo::addStatistic().
So far, this hasn't been an issue since (in-tree at least) these functions are
called by the StatisticInfo destructor so addStatistic() shouldn't be called
anymore. However, we do expose them in the public API.
Note that this only protects against iterator invalidation and does not protect
against ordering issues caused by statistic updates that race with
PrintStatistics()/PrintStatisticsJSON().
Thanks to Roman Tereshin for spotting it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326834
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Craig Topper [Tue, 6 Mar 2018 19:44:52 +0000 (19:44 +0000)]
[TargetLowering] Rename DAGCombinerInfo::isAfterLegalizeVectorOps to DAGCombiner::isAfterLegalizeDAG since that's what it checks. NFC
The code checks Level == AfterLegalizeDAG which is the fourth and last of the possible DAG combine stages that we have.
There is a Level called AfterLegalVectorOps, but that's the third DAG combine and it doesn't always run.
A function called isAfterLegalVectorOps should imply it returns true in either of the DAG combines that runs after the legalize vector ops stage, but that's not what this function does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326832
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Aaron Smith [Tue, 6 Mar 2018 19:36:17 +0000 (19:36 +0000)]
[SymboleFilePDB] Put the test input back that my previous commit clobbered
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326831
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Krzysztof Parzyszek [Tue, 6 Mar 2018 19:15:58 +0000 (19:15 +0000)]
[Hexagon] Update more testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326830
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Krzysztof Parzyszek [Tue, 6 Mar 2018 19:07:21 +0000 (19:07 +0000)]
[Hexagon] Remove {{ *}} from testcases
The spaces in the instructions are now consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326829
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Sanjay Patel [Tue, 6 Mar 2018 19:01:18 +0000 (19:01 +0000)]
[InstCombine] simplify min/max canonicalization; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326828
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Craig Topper [Tue, 6 Mar 2018 18:56:33 +0000 (18:56 +0000)]
[X86] Reject registers that require a REX prefix in inline asm constraints in 32-bit mode
We don't currently reject r8-r15 or xmm8-32 or bpl/spl/sil/dil in 32-bit mode.
Differential Revision: https://reviews.llvm.org/D44031
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326826
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Stanislav Mekhanoshin [Tue, 6 Mar 2018 18:33:55 +0000 (18:33 +0000)]
[AMDGPU] Add default ISA version targets
In case if -mattr used to modify feature set bits in llvm-mc call
getIsaVersion can fail to identify specific ISA due to test mismatch.
Adding default fallback tests which will always correctly report at
least major version.
Differential Revision: https://reviews.llvm.org/D44163
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326825
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Aaron Smith [Tue, 6 Mar 2018 18:20:22 +0000 (18:20 +0000)]
[CodeView] Emit UdtSourceLine information for enums
Summary:
- Emit UdtSourceLine information for enums to match MSVC
- Add a method to add UDTSrcLine and call it for all Class/Struct/Union/Enum
- Update test cases to verify the changes
Reviewers: zturner, llvm-commits, rnk
Reviewed By: rnk
Differential Revision: https://reviews.llvm.org/D44116
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326824
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Sanjay Patel [Tue, 6 Mar 2018 18:19:42 +0000 (18:19 +0000)]
[PatternMatch] define m_Not using m_Xor and cst_pred_ty
Using cst_pred_ty in the definition allows us to match vectors with undef elements.
This is a continuation of an effort to make all pattern matchers allow undef elements in vectors:
rL325437
rL325466
D43792
Differential Revision: https://reviews.llvm.org/D44076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326823
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Rafael Espindola [Tue, 6 Mar 2018 17:19:23 +0000 (17:19 +0000)]
Refactor check for dllimport in the Verifier.
This avoids duplicated code and now also rejects dllimport aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326814
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Sanjay Patel [Tue, 6 Mar 2018 16:57:55 +0000 (16:57 +0000)]
[ValueTracking] move helpers for SelectPatterns from InstCombine to ValueTracking
Most of the folds based on SelectPatternResult belong in InstSimplify rather than
InstCombine, so the helper code should be available to other passes/analysis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326812
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Sebastian Pop [Tue, 6 Mar 2018 16:54:55 +0000 (16:54 +0000)]
[AArch64] define isExtractSubvectorCheap
Following the ARM-neon backend, define isExtractSubvectorCheap to return true
when extracting low and high part of a neon register.
The patch disables a test in llvm/test/CodeGen/AArch64/arm64-ext.ll This
testcase is fragile in the sense that it requires a BUILD_VECTOR to "survive"
all DAG transforms until ISelLowering. The testcase is supposed to check that
AArch64TargetLowering::ReconstructShuffle() works, and for that we need a
BUILD_VECTOR in ISelLowering. As we now transform the BUILD_VECTOR earlier into
an VEXT + vector_shuffle, we don't have the BUILD_VECTOR pattern when we get to
ISelLowering. As there is no way to disable the combiner to only exercise the
code in ISelLowering, the patch disables the testcase.
Differential revision: https://reviews.llvm.org/D43973
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326811
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Oliver Stannard [Tue, 6 Mar 2018 16:51:17 +0000 (16:51 +0000)]
[Asm] Fix another layering violation in assmebly macro dumping
AsmToken is in the MCParser library, so we can't use its dump function from
MCAsmMacro in the MC library. Instead, just print the string, which we don't
need the MCParser library for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326810
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Roorda, Jan-Willem [Tue, 6 Mar 2018 16:26:01 +0000 (16:26 +0000)]
[Pipeliner] Test commit: fixed spelling mistake in comments
Reviewers: bcahoon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44152
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326808
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Yaxun Liu [Tue, 6 Mar 2018 16:04:39 +0000 (16:04 +0000)]
[AMDGPU] Fix lowering OpenCL enqueue_kernel
One addrspacecast disappeared in clang emitted IR for
block invoke function due to adoption of the new
addr space mapping.
Differential Revision: https://reviews.llvm.org/D43785
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326806
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Oliver Stannard [Tue, 6 Mar 2018 15:32:34 +0000 (15:32 +0000)]
[ARM][Asm] Fix layering violation introduced by r326795
The MCAsmMacro::dump function is in the MCParser library, so can't be called
from the MC library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326804
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Simi Pallipurath [Tue, 6 Mar 2018 15:21:19 +0000 (15:21 +0000)]
[ARM]Decoding MSR with unpredictable destination register causes an assert
This patch handling:
Enable parsing of raw encodings of system registers .
Allows UNPREDICTABLE sysregs to be decoded to a raw number in the same way that disasslib does, rather than llvm crashing.
Disassemble msr/mrs with unpredictable sysregs as SoftFail.
Fix regression due to SoftFailing some encodings.
Patch by Chris Ryder
Differential revision:https://reviews.llvm.org/D43374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326803
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Simi Pallipurath [Tue, 6 Mar 2018 14:35:23 +0000 (14:35 +0000)]
test commit: fix typo in comment
This is a simple change to do the test commit and verify commit access.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326800
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Oliver Stannard [Tue, 6 Mar 2018 14:07:01 +0000 (14:07 +0000)]
[Asm] Add debug printing for assembler macros
This adds some debug printing (gated behind the "asm-macros" debug flag) which
can help tracing complicated assembly macros.
Differential revision: https://reviews.llvm.org/D43937
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326795
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Oliver Stannard [Tue, 6 Mar 2018 14:02:14 +0000 (14:02 +0000)]
[Asm] Refactor debug printing of AsmToken
* Move printing from llvm-mc to the AsmToken class, so that it can be used elsewhere.
* Add 5 cases which were missed: BigNum, Comment, HashDirective, Space and
BackSlash, and remove the default case so that -Wswitch will catch this error
in future.
This is almost NFC, except for the fact that llvm-mc can now print those 5
tokens in -as-lex mode.
Differential revision: https://reviews.llvm.org/D43936
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326794
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Florian Hahn [Tue, 6 Mar 2018 14:00:58 +0000 (14:00 +0000)]
[CallSiteSplitting] Do not crash when BB's terminator changes.
Change doCallSiteSplitting to iterate until we reach the terminator instruction.
tryToSplitCallSite can replace BB's terminator in case BB is a successor of
itself. Then IE will be invalidated and we also have to check the current
terminator.
Reviewers: junbuml, davidxl, davide, fhahn
Reviewed By: fhahn, junbuml
Differential Revision: https://reviews.llvm.org/D43824
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326793
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Nicolai Haehnle [Tue, 6 Mar 2018 13:49:16 +0000 (13:49 +0000)]
TableGen: Add !foldl operation
Change-Id: I63d67bf6e0b315e2d3360e47e3b62c9517f38987
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326790
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Nicolai Haehnle [Tue, 6 Mar 2018 13:49:06 +0000 (13:49 +0000)]
TableGen: Remove the ResolveFirst mechanism
Summary:
It is no longer used.
Change-Id: I1e47267d1975d43ad43acd6347f54e958e3b6c86
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D43757
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326789
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Nicolai Haehnle [Tue, 6 Mar 2018 13:49:01 +0000 (13:49 +0000)]
TableGen: Delay instantiating inline anonymous records
Summary:
Only instantiate anonymous records once all variable references in template
arguments have been resolved. This allows patterns like the new test case,
which in practice can appear in expressions like:
class IntrinsicTypeProfile<list<LLVMType> ty, int shift> {
list<LLVMType> types =
!listconcat(ty, [llvm_any_ty, LLVMMatchType<shift>]);
}
class FooIntrinsic<IntrinsicTypeProfile P, ...>
: Intrinsic<..., P.types, ...>;
Without this change, the anonymous LLVMMatchType instantiation would
never get resolved.
Another consequence of this change is that anonymous inline
instantiations are uniqued via the folding set of the newly introduced
VarDefInit.
Change-Id: I7a7041a20e297cf98c9109b28d85e64e176c932a
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D43756
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326788
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Nicolai Haehnle [Tue, 6 Mar 2018 13:48:54 +0000 (13:48 +0000)]
TableGen: Move getNewAnonymousName into RecordKeeper
Summary:
So that we will be able to generate new anonymous names more easily
outside the parser as well.
Change-Id: I28f396a7bdbc3ff0c665d466abbd3d31376e21b4
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D43755
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326787
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Nicolai Haehnle [Tue, 6 Mar 2018 13:48:47 +0000 (13:48 +0000)]
TableGen: Explicitly check whether a record has been resolved
Summary:
There are various places where resolving and constant folds can
get stuck, especially around casts. We don't always signal an
error for those, because in many cases they can legitimately
occur without being an error in the "untaken branch" of an !if.
Change-Id: I3befc0e4234c8e6cc61190504702918c9f29ce5c
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D43754
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326786
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Nicolai Haehnle [Tue, 6 Mar 2018 13:48:39 +0000 (13:48 +0000)]
TableGen: Allow !cast of records, cleanup conversion machinery
Summary:
Distinguish two relationships between types: is-a and convertible-to.
For example, a bit is not an int or vice versa, but they can be
converted into each other (with range checks that you can think of
as "dynamic": unlike other type checks, those range checks do not
happen during parsing, but only once the final values have been
established).
Actually converting initializers between types is subtle: even
when values of type A can be converted to type B (e.g. int into
string), it may not be possible to do so with a concrete initializer
(e.g., a VarInit that refers to a variable of type int cannot
be immediately converted to a string).
For this reason, distinguish between getCastTo and convertInitializerTo:
the latter implements the actual conversion when appropriate, while
the former will first try to do the actual conversion and fall back
to introducing a !cast operation so that the conversion will be
delayed until variable references have been resolved.
To make the approach of adding !cast operations to work, !cast needs
to fallback to convertInitializerTo when the special string <-> record
logic does not apply.
This enables casting records to a subclass, although that new
functionality is only truly useful together with !isa, which will be
added in a later change.
The test is removed because it uses !srl on a bit sequence,
which cannot really be supported consistently, but luckily
isn't used anywhere either.
Change-Id: I98168bf52649176654ed2ec61a29bdb29970cfe7
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D43753
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326785
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Nicolai Haehnle [Tue, 6 Mar 2018 13:48:30 +0000 (13:48 +0000)]
TableGen: Simplify BitsInit::resolveReferences
Summary:
No functional change intended. The removed code has a loop for
recursive resolving, which is superseded by the recursive
resolving done by the Resolver implementations.
Add a test case which was broken by an earlier version of this
change.
Change-Id: Ib208d037b77a8bbb725977f1388601fc984723d8
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D43655
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326784
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Nicolai Haehnle [Tue, 6 Mar 2018 13:48:20 +0000 (13:48 +0000)]
TableGen: Generalize record types to fix typeIsConvertibleTo et al.
Summary:
Allow RecordRecTy to represent the type "subclass of N superclasses",
where N may be zero. Furthermore, generate RecordRecTy instances only
with actual classes in the list.
Keeping track of multiple superclasses is required to resolve the type
of a list correctly in some cases. The old code relied on the incorrect
behavior of typeIsConvertibleTo, and an earlier version of this change
relied on a modified ordering of superclasses (it was committed in
r325884 and then reverted because unfortunately some of clang-tblgen's
backends depend on the ordering).
Previously, the DefInit for each Record would have a RecordRecTy of
that Record as its type. Now, all defs with the same superclasses will
share the same type.
This allows us to be more consistent about type checks involving records:
- typeIsConvertibleTo actually requires the LHS to be a subtype of the
RHS
- resolveTypes will return the least supertype of given record types in
all cases
- different record types in the two branches of an !if are handled
correctly
Add a test that used to be accepted without flagging the obvious type
error.
Change-Id: Ib366db1a4e6a079f1a0851e469b402cddae76714
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D43680
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326783
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Bjorn Pettersson [Tue, 6 Mar 2018 13:23:28 +0000 (13:23 +0000)]
Fixup for rL326769 (RegState::Debug is being truncated to a bool)
I obviously messed up arguments to MachineOperand::CreateReg
in rL326769. This should make it work as intended.
Thanks to RKSimon for spotting this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326780
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Florian Hahn [Tue, 6 Mar 2018 13:12:32 +0000 (13:12 +0000)]
[CloneFunction] Support BB == PredBB in DuplicateInstructionsInSplit.
In case PredBB == BB and StopAt == BB's terminator, StopAt != &*BI will
fail, because BB's terminator instruction gets replaced.
By using BB.getTerminator() we get the current terminator which we can use
to compare.
Reviewers: sanjoy, anna, reames
Reviewed By: anna
Differential Revision: https://reviews.llvm.org/D43822
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326779
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Dylan McKay [Tue, 6 Mar 2018 11:20:25 +0000 (11:20 +0000)]
[AVR] Remove the earlyclobber flag from LDDWRdYQ
Before I started maintaining the AVR backend, this instruction
never originally used to have an earlyclobber flag.
Some time afterwards (years ago), I must've added it back in, not realising that it
was left out for a reason.
This pseudo instrction exists solely to work around a long standing bug
in the register allocator.
Before this commit, the LDDWRdYQ pseudo was not actually working around
any bug. With the earlyclobber flag removed again, the LDDWRdYQ pseudo
now correctly works around PR13375 again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326774
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Bjorn Pettersson [Tue, 6 Mar 2018 08:47:07 +0000 (08:47 +0000)]
[DebugInfo] Discard invalid DBG_VALUE instructions in LiveDebugVariables
Summary:
This is a workaround for pr36417
https://bugs.llvm.org/show_bug.cgi?id=36417
LiveDebugVariables will now verify that the DBG_VALUE instructions
are sane (prior to register allocation) by asking LIS if a virtual
register used in the DBG_VALUE is live (or dead def) in the slot
index before the DBG_VALUE. If it isn't sane the DBG_VALUE is
discarded.
One pass that was identified as introducing non-sane DBG_VALUE
instructtons, when analysing pr36417, was the DAG->DAG Instruction
Selection. It sometimes inserts DBG_VALUE instructions referring to
a virtual register that is defined later in the same basic block.
So it is a use before def kind of problem. The DBG_VALUE is
typically inserted in the beginning of a basic block when this
happens. The problem can be seen in the test case
test/DebugInfo/X86/dbg-value-inlined-parameter.ll
Reviewers: aprantl, rnk, probinson
Reviewed By: aprantl
Subscribers: vsk, davide, alexcrichton, Ka-Ka, eraman, llvm-commits, JDevlieghere
Differential Revision: https://reviews.llvm.org/D43956
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326769
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Sam Clegg [Tue, 6 Mar 2018 07:13:10 +0000 (07:13 +0000)]
[WebAssebmly] Remove reloc ordering constraint
The MC layer doesn't currently emit relocations in offset
order for the entire code section so this check was causing
failures on the wasm waterfall.
Perhaps we can re-instate this check if we divide the relocations
per-function, or add extra ordering the MC object writer.
Differential Revision: https://reviews.llvm.org/D44136
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326765
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Martin Storsjo [Tue, 6 Mar 2018 06:00:13 +0000 (06:00 +0000)]
[X86] Handle EAX being live when calling chkstk for x86_64
EAX can turn out to be alive here, when shrink wrapping is done
(which is allowed when using dwarf exceptions, contrary to the
normal case with WinCFI).
This fixes PR36487.
Differential Revision: https://reviews.llvm.org/D43968
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326764
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Serge Pavlov [Tue, 6 Mar 2018 04:00:30 +0000 (04:00 +0000)]
Updated docs in CrashRecoveryContext.h
Differential Revision: https://reviews.llvm.org/D43200
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326763
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Paul Robinson [Tue, 6 Mar 2018 03:15:21 +0000 (03:15 +0000)]
Revert "[DWARFv5] Emit file 0 to the line table."
Caused an asan failure.
This reverts commit
d54883f081186cdcce74e6f98cfc0438579ec019.
aka r326758
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326762
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Xin Tong [Tue, 6 Mar 2018 02:24:02 +0000 (02:24 +0000)]
[MergeICmp] Simplify how BCECmpBlock instructions are blacklisted
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326761
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Xin Tong [Tue, 6 Mar 2018 02:04:57 +0000 (02:04 +0000)]
[MergeICmp] Fix printing. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326760
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Paul Robinson [Tue, 6 Mar 2018 01:59:56 +0000 (01:59 +0000)]
[DWARFv5] Emit file 0 to the line table.
DWARF v5 specifies that the root file (also given in the DW_AT_name
attribute of the compilation unit DIE) should be emitted explicitly to
the line table's list of files. This makes the line table more
independent of the .debug_info section.
Differential Revision: https://reviews.llvm.org/D44054
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326758
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Reid Kleckner [Mon, 5 Mar 2018 23:18:13 +0000 (23:18 +0000)]
Disable llvm-opt-fuzzer/exec-options.ll on Windows, it is too flaky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326752
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