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Mike Turquette [Tue, 30 Sep 2014 21:24:38 +0000 (14:24 -0700)]
doc/kernel-parameters.txt: clarify clk_ignore_unused
Refine the definition around clk_ignore_unused, which caused some
confusion recently on the linux-fbdev and linux-arm-kernel mailing
lists[0].
[0] http://lkml.kernel.org/r/<
20140929135358.GC30998@ulmo>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Mike Turquette [Tue, 30 Sep 2014 19:49:42 +0000 (12:49 -0700)]
Merge branch 'clk-pxa27x' into clk-next
Robert Jarzmik [Wed, 30 Jul 2014 20:51:04 +0000 (22:51 +0200)]
arm: pxa: Transition pxa27x to clk framework
Transition the PXA27x CPUs to the clock framework.
This transition still enables legacy platforms to run without device
tree as before, ie relying on platform data encoded in board specific
files.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Robert Jarzmik [Wed, 30 Jul 2014 20:51:03 +0000 (22:51 +0200)]
dts: add devicetree bindings for pxa27x clocks
Add the clock tree description for the PXA27x based boards.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Robert Jarzmik [Wed, 30 Jul 2014 20:51:02 +0000 (22:51 +0200)]
clk: add pxa27x clock drivers
Move pxa27x clock drivers from arch/arm/mach-pxa to driver/clk.
In the move :
- convert to new clock framework legacy clocks
- provide clocks as before for platform data based boards
- provide clocks through devicetree
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Robert Jarzmik [Wed, 30 Jul 2014 20:51:01 +0000 (22:51 +0200)]
arm: pxa: add clock pll selection bits
Add missing bits for CCCR and CCSR :
- CPLL and PPLL selection, either full speed or 13MHz
- CPSR masks
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Robert Jarzmik [Wed, 30 Jul 2014 20:51:00 +0000 (22:51 +0200)]
clk: dts: document pxa clock binding
Document the device-tree binding of Marvell PXA based SoCs.
PXA clocks are mostly fixed rate and fixed ratio clocks derived from an
external oscillator, and gated by a register set (CKEN or CKEN*).
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Robert Jarzmik [Wed, 30 Jul 2014 20:50:59 +0000 (22:50 +0200)]
clk: add pxa clocks infrastructure
Add a the common code used by all PXA variants.
This is the first step in the transition from architecture defined
clocks (in arch/arm/mach-pxa) towards clock framework. The goal is to
have the same features (and not all the features) of the existing
clocks, and enable the transition of PXA to device-tree.
All PXA rely on a "CKEN" type clock, which :
- has a gate (bit in CKEN register)
- is generated from a PLL, generally divided
- has an alternate low power clock
Each variant will specialize the CKEN clock :
- pxa25x have no low power clock
- pxa27x in low power use always the 13 MHz ring oscillator
- pxa3xx in low power have specific dividers for each clock
The device-tree provides a list of CLK_* (ex: CLK_USB or CLK_I2C) to get
a handle on the clock. While pxa-clock.h will describe all the clocks of
all the variants, each variant will only use a subset of it.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Mark Brown [Tue, 30 Sep 2014 17:16:22 +0000 (18:16 +0100)]
clk: gpio-gate: Ensure gpiod_ APIs are prototyped
The gpio-gate clock uses the gpiod_ APIs but does not directly include the
header for them causing build failures in some configurations including ARM
allnoconfig. Include the header directly.
Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Mike Turquette [Tue, 30 Sep 2014 06:43:12 +0000 (23:43 -0700)]
Merge tag 'for_3.18/samsung-clk' of git://git./linux/kernel/git/tfiga/samsung-clk into clk-next
Samsung clock patches for v3.18
1) non-critical fixes (without the need to push to stable)
fa0111be4ff3 clk: samsung: exynos4: remove duplicate div_core2 divider clock instantiation
b511593d7165 clk: samsung: exynos4: fix g3d clocks
c14254300131 clk: samsung: exynos4: add missing smmu_g2d clock and update comments
22842d244af3 clk: samsung: exynos5260: fix typo in clock name
e82ba578ccde clk: samsung: exynos3250: fix width field of mout_mmc0/1
59037b92f440 clk: samsung: exynos3250: fix width and shift of div_spi0_isp clock
5ce37f266650 clk: samsung: exynos3250: fix mout_cam_blk parent list
2) Clock driver extensions
07ccf02ba5c3 dt-bindings: clk: samsung: Document the DMC domain of Exynos3250 CMU
d0e73eaf1925 ARM: dts: exynos3250: Add CMU node for DMC domain clocks
e3c3f19bc618 clk: samsung: exynos3250: Register DMC clk provider
4676f0aab9dc clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocks
Mike Turquette [Tue, 30 Sep 2014 06:38:59 +0000 (23:38 -0700)]
Merge branch 'for-v3.18/ti-clk-driver' of github.com:t-kristo/linux-pm into clk-next
Peter Ujfalusi [Mon, 29 Sep 2014 08:10:33 +0000 (11:10 +0300)]
clk: ti: dra7-atl-clock: Mark the device as pm_runtime_irq_safe
It is safe to call the pm sync calls in interrupt context in this driver.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Behan Webster [Sat, 27 Sep 2014 00:31:48 +0000 (17:31 -0700)]
clk: ti: LLVMLinux: Move __init outside of type definition
As written, the __init for ti_clk_get_div_table is in the middle of the return
type.
The gcc documentation indicates that section attributes should be added to the
end of the function declaration:
extern void foobar (void) __attribute__ ((section ("bar")));
However gcc seems to be very permissive with where attributes can be placed.
clang on the other hand isn't so permissive, and fails if you put the section
definition in the middle of the return type:
drivers/clk/ti/divider.c:298:28: error: expected ';' after struct
static struct clk_div_table
^
;
drivers/clk/ti/divider.c:298:1: warning: 'static' ignored on this
declaration [-Wmissing-declarations]
static struct clk_div_table
^
drivers/clk/ti/divider.c:299:9: error: type specifier missing,
defaults to 'int' [-Werror,-Wimplicit-int]
__init *ti_clk_get_div_table(struct device_node *node)
~~~~~~ ^
drivers/clk/ti/divider.c:345:9: warning: incompatible pointer types
returning 'struct clk_div_table *' from a function with result type 'int *' [-Wincompatible-pointer-types]
return table;
^~~~~
drivers/clk/ti/divider.c:419:9: warning: incompatible pointer types
assigning to 'const struct clk_div_table *' from 'int *' [-Wincompatible-pointer-types]
*table = ti_clk_get_div_table(node);
^ ~~~~~~~~~~~~~~~~~~~~~~~~~~
3 warnings and 2 errors generated.
By convention, most of the kernel code puts section attributes between the
return type and function name. In the case where the return type is a pointer,
it's important to place the '*' on left of the __init.
This updated code works for both gcc and clang.
Signed-off-by: Behan Webster <behanw@converseincode.com>
Reviewed-by: Mark Charlebois <charlebm@gmail.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Sebastian Andrzej Siewior [Thu, 18 Sep 2014 14:33:27 +0000 (16:33 +0200)]
clk: ti: consider the fact that of_clk_get() might return an error
I "forgot" to update the dtb and the kernel crashed:
|Unable to handle kernel NULL pointer dereference at virtual address
0000002e
|PC is at __clk_get_flags+0x4/0xc
|LR is at ti_dt_clockdomains_setup+0x70/0xe8
because I did not have the clock nodes. of_clk_get() returns an error
pointer which is not checked here.
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tero Kristo [Fri, 12 Sep 2014 13:39:07 +0000 (16:39 +0300)]
clk: ti: dra7-atl-clock: fix a memory leak
of_clk_add_provider makes an internal copy of the parent_names property
while its called, thus it is no longer needed after this call and can
be freed.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tero Kristo [Fri, 12 Sep 2014 12:01:57 +0000 (15:01 +0300)]
clk: ti: change clock init to use generic of_clk_init
Previously, the TI clock driver initialized all the clocks hierarchically
under each separate clock provider node. Now, each clock that requires
IO access will instead check their parent node to find out which IO range
to use.
This patch allows the TI clock driver to use a few new features provided
by the generic of_clk_init, and also allows registration of clock nodes
outside the clock hierarchy (for example, any external clocks.)
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Jyri Sarha <jsarha@ti.com>
Cc: Stefan Assmann <sassmann@kpanic.de>
Acked-by: Tony Lindgren <tony@atomide.com>
Mike Turquette [Sun, 28 Sep 2014 17:47:15 +0000 (10:47 -0700)]
Merge tag 'hix5hd2-clock-for-3.18-v2' of git://github.com/hisilicon/linux-hisi into clk-next
Hisilicon HiX5HD2 clock updates for 3.18-v2
- Add I2C clocks
- Add watchdog clocks
- Add sd clocks
- Add complex clock implementation to support sata, usb and ethernet
Wei Yan [Thu, 7 Aug 2014 01:09:13 +0000 (09:09 +0800)]
clk: hix5hd2: add I2C clocks
hix5hd2 add I2C clocks (I2C0~i2C5)
Signed-off-by: Wei Yan <sledge.yanwei@huawei.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Guoxiong Yan [Tue, 17 Jun 2014 09:04:17 +0000 (17:04 +0800)]
clk: hix5hd2: add watchdog0 clocks
hix5hd2 add watchdog0 clocks
Signed-off-by: Guoxiong Yan <yanguoxiong@huawei.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Jiancheng Xue [Wed, 28 May 2014 03:35:32 +0000 (11:35 +0800)]
clk: hix5hd2: add sd clk
Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Zhangfei Gao [Tue, 13 May 2014 12:26:59 +0000 (20:26 +0800)]
clk: hix5hd2: add complex clk
Support clk of sata, usb and ethernet
Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Xiubo Li [Mon, 22 Sep 2014 05:52:11 +0000 (13:52 +0800)]
clk: use uninitialized_var instead setting 'flags' to 0 directly.
Setting 'flags' to zero will be certainly a misleading way to avoid
warning of 'flags' may be used uninitialized. uninitialized_var is
a correct way because the warning is a false possitive.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Mike Turquette [Sat, 27 Sep 2014 19:52:33 +0000 (12:52 -0700)]
Merge tag 'sunxi-clocks-for-3.18' of git://git./linux/kernel/git/mripard/linux into clk-next
Allwinner Clocks Additions for 3.18
The most important part of this serie is the addition of the phase API to
handle the MMC clocks in the Allwinner SoCs.
Apart from that, the A23 gained a new mbus driver, and there's a fix for a
incorrect divider table on the APB0 clock.
Mike Turquette [Sat, 27 Sep 2014 19:50:40 +0000 (12:50 -0700)]
Merge tag 'v3.18-rockchip-cpuclk' of git://git./linux/kernel/git/mmind/linux-rockchip into clk-next
CPU clock handling for Rockchip SoCs
Heiko Stuebner [Fri, 5 Sep 2014 09:25:03 +0000 (11:25 +0200)]
clk: rockchip: switch to using the new cpuclk type for armclk
This adds the necessary soc-specific divider values and switches the armclk
to use the newly introduced cpuclk type.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Heiko Stuebner [Thu, 4 Sep 2014 20:10:43 +0000 (22:10 +0200)]
clk: rockchip: add new clock-type for the cpuclk
When changing the armclk on Rockchip SoCs it is supposed to be reparented
to an alternate parent before changing the underlying pll and back after
the change. Additionally there exist clocks that are very tightly bound to
the armclk whose divider values are set according to the armclk rate.
Add a special clock-type to handle all that. The rate table and divider
values will be supplied from the soc-specific clock controllers.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
On a rk3288-board:
Tested-by: Doug Anderson <dianders@chromium.org>
Heiko Stuebner [Thu, 4 Sep 2014 19:43:17 +0000 (21:43 +0200)]
clk: rockchip: make tightly bound armclk child-clocks read-only
Rockchip SoCs contain clocks tightly bound to the armclk, where the best
rate / divider is supplied by the vendor after careful measuring.
Often this ideal rate may be greater than the current rate.
Therefore prevent the ccf from trying to set these dividers itself by
setting them to read-only.
In the case of the rk3066, this also includes the aclk_cpu, which makes it
necessary to also split its direct child-clocks (pclk_cpu, hclk_cpu, ...)
into individual definitions for rk3066 and rk3188.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Heiko Stuebner [Thu, 4 Sep 2014 19:24:45 +0000 (21:24 +0200)]
clk: rockchip: reparent aclk_cpu_pre to the gpll
aclk_cpu_pre on the rk3188 can either be sourced from the armclk or the gpll.
To reduce complexity on apll changes caused by cpufreq, reparent it always
to the gpll source.
If really necessary it could be reparented back on a per board level using
the assigned-clocks mechanism.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Jianqun [Mon, 1 Sep 2014 21:56:28 +0000 (23:56 +0200)]
clk: rockchip: fix rk3288 pll status register location
In RK3288, APLL lock status bit is in GRF_SOC_STATUS1,
but in RK3188, is GRFSOC_STATUS0.
Signed-off-by: Jianqun <jay.xu@rock-chips.com>
Also name the constant accordingly as GRF_SOC_STATUS1
to prevent confusion.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Heiko Stuebner [Mon, 1 Sep 2014 21:52:40 +0000 (23:52 +0200)]
clk: rockchip: fix rk3066 pll status register location
The register providing the pll lock status is at a different address on the
rk3066. The error became apparent while working on cpufreq support for
the rockchip SoCs.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Doug Anderson [Tue, 16 Sep 2014 04:07:57 +0000 (21:07 -0700)]
clk: rockchip: change pll rate without a clk-notifier
The Rockchip PLL code switches into slow mode (AKA bypass more AKA
24MHz mode) before actually changing the PLL. This keeps anyone from
using the PLL while it's changing. However, in all known Rockchip
SoCs nobody should ever see the 24MHz when changing the PLL supplying
the armclk because we should reparent children to an alternate
(faster than 24MHz) PLL.
One problem is that the code to switch to an alternate parent was
running in PRE_RATE_CHANGE. ...and the code to switch to slow mode
was _also_ running in PRE_RATE_CHANGE. That meant there was no real
guarantee that we would switch to an alternate parent before switching
to 24MHz mode.
Let's move the switch to "slow mode" straight into
rockchip_rk3066_pll_set_rate(). That means we're guaranteed that the
24MHz is really a last-resort.
Note that without this change on real systems we were the code to
switch to an alternate parent at 24MHz. In some older versions of
that code we'd appy a (temporary) / 5 to the 24MHz causing us to run
at 4.8MHz. That wasn't enough to service USB interrupts in some cases
and could lead to a system hang.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Heiko Stuebner [Sat, 27 Sep 2014 15:56:55 +0000 (17:56 +0200)]
Merge branch 'v3.18-next/armclkid' into v3.18-next/cpuclk
Heiko Stuebner [Fri, 5 Sep 2014 09:28:12 +0000 (11:28 +0200)]
clk: rockchip: add binding id for ARMCLK
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Chen-Yu Tsai [Tue, 16 Sep 2014 10:04:01 +0000 (18:04 +0800)]
clk: sunxi: Add sun8i MBUS clock support
The MBUS clock on sun8i is slightly different from the old mod0 clocks.
The divider is 3 bits wider, while also needing a divider table for the
higher 4 values, which all set the same divider.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Fri, 11 Jul 2014 16:43:18 +0000 (18:43 +0200)]
clk: sunxi: mod0: Introduce MMC proper phase handling
The MMC clock we thought we had until now are actually not one but three
different clocks.
The main one is unchanged, and will have three outputs:
- The clock fed into the MMC
- a sample and output clocks, to deal with when should we output/sample data
to/from the MMC bus
The phase control we had are actually controlling the two latter clocks, but
the main MMC one is unchanged.
We can adjust the phase with a 3 bits value, from 0 to 7, 0 meaning a 180 phase
shift, and the other values being the number of periods from the MMC parent
clock to outphase the clock of.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Maxime Ripard [Thu, 10 Jul 2014 21:56:11 +0000 (23:56 +0200)]
clk: sunxi: Move mbus to mod0 file
Move the MBUS clock to the module clocks file. It's pretty trivial, but still
requires to enable the clocks to make sure it won't get disabled.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Maxime Ripard [Thu, 10 Jul 2014 21:55:18 +0000 (23:55 +0200)]
clk: sunxi: Move mod0 clock to a file of its own
Since we know have the ability to declare factors clock outside of clk-sunxi,
create a new mod0 driver to deal with the mod0 clocks.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Maxime Ripard [Wed, 16 Jul 2014 21:45:48 +0000 (23:45 +0200)]
ARM: sunxi: dt: Switch to the new mbus compatible
Now that we have a compatible of its own for the mbus clock, switch to it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Maxime Ripard [Thu, 10 Jul 2014 21:53:40 +0000 (23:53 +0200)]
clk: sunxi: Introduce mbus compatible
Even though the mbus clock is a regular module clock, given its nature, it
needs to be enabled all the time.
Introduce a new compatible, to differentiate it from the other module clocks.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Maxime Ripard [Fri, 4 Jul 2014 20:24:52 +0000 (22:24 +0200)]
clk: sunxi: factors: Invert the probing logic
Until now, the factors clock probing was done directly by sunxi_init_clocks,
with the factors registration being called directly with the clocks data passed
as an argument.
This approch has shown its limits when we added more clocks, since we couldn't
really split code with such a logic in smaller files, and led to a huge file
having all the clocks.
Introduce an intermediate probing function, so that factor clocks will be able
to directly be called by CLK_OF_DECLARE, which will in turn ease the split into
several files.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Maxime Ripard [Mon, 14 Jul 2014 11:53:27 +0000 (13:53 +0200)]
clk: Add a function to retrieve phase
The current phase API doesn't look into the actual hardware to get the phase
value, but will rather get it from a variable only set by the set_phase
function.
This will cause issue when the client driver will never call the set_phase
function, where we can end up having a reported phase that will not match what
the hardware has been programmed to by the bootloader or what phase is
programmed out of reset.
Add a new get_phase function for the drivers to implement so that we can get
this value.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Maxime Ripard [Sat, 30 Aug 2014 19:18:00 +0000 (21:18 +0200)]
clk: Include of.h in clock-provider.h
CLK_OF_DECLARE relies on OF_DECLARE_1 that is defined in of.h. Fixes build
errors when one use CLK_OF_DECLARE but doesn't include of.h
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Mike Turquette [Wed, 19 Feb 2014 05:21:25 +0000 (21:21 -0800)]
clk: introduce clk_set_phase function & callback
A common operation for a clock signal generator is to shift the phase of
that signal. This patch introduces a new function to the clk.h API to
dynamically adjust the phase of a clock signal. Additionally this patch
introduces support for the new function in the common clock framework
via the .set_phase call back in struct clk_ops.
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Mike Turquette [Sat, 27 Sep 2014 00:04:08 +0000 (17:04 -0700)]
Merge tag 'clk-mvebu-3.18' of git://git.infradead.org/linux-mvebu into clk-next
clock changes for mvebu for v3.18
- correct timer drift caused by SSCG deviation
- fix typo in comment
Jyri Sarha [Fri, 5 Sep 2014 12:21:34 +0000 (15:21 +0300)]
clk: add gpio gated clock
The added gpio-gate-clock is a basic clock that can be enabled and
disabled trough a gpio output. The DT binding document for the clock
is also added. For EPROBE_DEFER handling the registering of the clock
has to be delayed until of_clk_get() call time.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Mike Turquette [Fri, 26 Sep 2014 23:10:57 +0000 (16:10 -0700)]
Merge tag 'qcom-clocks-for-3.18' of git://git./linux/kernel/git/galak/linux-qcom into clk-next
qcom clock changes for 3.18
Some fixes for the IPQ driver and some code consolidation
and refactoring.
Mike Turquette [Fri, 26 Sep 2014 23:09:39 +0000 (16:09 -0700)]
Merge tag 'tegra-clk-3.18' of git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-next
Tegra clk updates for 3.18
Mike Turquette [Tue, 9 Sep 2014 06:11:26 +0000 (23:11 -0700)]
asm-generic: COMMON_CLK defines __clk_{get,put}
If CONFIG_COMMON_CLK is selected then __clk_get and __clk_put are
defined in drivers/clk/clk.c and declared in include/linux/clkdev.h.
Sylwester's series[0] to properly support clk_{get,put} in the common
clock framework made changes to the asm-specific clkdev.h headers, but
not the asm-generic version. Tomeu's recent changes[1] to introduce a
provider/consumer split in the clock framework uncovered this problem,
causing the following build error on any architecture using the
asm-generic clkdev.h (e.g. x86 architecture and the ACPI LPSS driver):
In file included from drivers/acpi/acpi_lpss.c:15:0:
include/linux/clkdev.h:59:5: error: conflicting types for ‘__clk_get’
int __clk_get(struct clk_core *clk);
^
In file included from arch/x86/include/generated/asm/clkdev.h:1:0,
from include/linux/clkdev.h:15,
from drivers/acpi/acpi_lpss.c:15:
include/asm-generic/clkdev.h:20:19: note: previous definition of ‘__clk_get’ was here
static inline int __clk_get(struct clk *clk) { return 1; }
^
Fixed by only declarating __clk_get and __clk_put when
CONFIG_COMMON_CLK is set.
[0] http://lkml.kernel.org/r/<
1386177127-2894-5-git-send-email-s.nawrocki@samsung.com>
[1] http://lkml.kernel.org/r/<
1409758148-20104-1-git-send-email-tomeu.vizoso@collabora.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Kiran Padwal [Wed, 24 Sep 2014 09:45:29 +0000 (15:15 +0530)]
clk: Remove .owner field for driver
There is no need to init .owner field.
Based on the patch from Peter Griffin <peter.griffin@linaro.org>
"mmc: remove .owner field for drivers using module_platform_driver"
This patch removes the superflous .owner field for drivers which
use the module_platform_driver API, as this is overriden in
platform_driver_register anyway."
Signed-off-by: Kiran Padwal <kiran.padwal@smartplayin.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Mike Turquette [Thu, 25 Sep 2014 22:48:04 +0000 (15:48 -0700)]
Merge branch 'clk-next-rockchip' into clk-next
Kever Yang [Thu, 25 Sep 2014 07:48:47 +0000 (15:48 +0800)]
clk: rockchip: add clock node in PD_VIDEO
This patch add the clock node in PD_VIDEO
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Kever Yang [Thu, 25 Sep 2014 07:48:46 +0000 (15:48 +0800)]
clk: rockchip: use the clock id for nodes init
This patch use the new defined clock ID to initial the clock nodes.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Kever Yang [Wed, 24 Sep 2014 13:36:34 +0000 (21:36 +0800)]
clk: rockchip: add some needed clock binding id for rk3288
This patch add some clock binding id for different modules
that under development and going to send upstream.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Heiko Stübner [Wed, 24 Sep 2014 21:41:54 +0000 (23:41 +0200)]
clk: rockchip: add missing rk3288 npll rate table
The npll on rk3288 is exactly the same pll type as the other 4. Yet it
was missing the link to the rate table, making rate changes impossible.
Change that by setting the table.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Mark yao [Fri, 12 Sep 2014 09:24:46 +0000 (17:24 +0800)]
clk: rockchip: rk3288: fix softreset register count
The rk3288 actually has 12 softresets, so fix the register count.
Signed-off-by: Mark yao <mark.yao@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Mark yao [Fri, 12 Sep 2014 11:45:27 +0000 (19:45 +0800)]
clk: rockchip: rk3288: add reset indices for SOFTRST9-11
The patch add the rest of the indices of the additional reset
registers from the updated TRM.
Signed-off-by: Mark yao <mark.yao@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Thomas Abraham [Wed, 30 Jul 2014 07:55:32 +0000 (13:25 +0530)]
clk: samsung: exynos4: remove duplicate div_core2 divider clock instantiation
The 'div_core2' clock and the 'arm_clk' divider clocks are instances of
the same divider clock. So remove the 'arm_clk' clock instance.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
[tomasz.figa@gmail.com: Fixed remaining occurences of 'arm_clk'.]
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Stephen Boyd [Mon, 28 Apr 2014 22:59:16 +0000 (15:59 -0700)]
clk: qcom: Add support for banked MD RCGs
The banked MD RCGs in global clock control have a different
register layout than the ones implemented in multimedia clock
control. Add support for these types of clocks so we can change
the rates of the UBI32 clocks.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Mon, 28 Apr 2014 22:58:11 +0000 (15:58 -0700)]
clk: qcom: Add support for setting rates on PLLs
Some PLLs may require changing their rate at runtime. Add support
for these PLLs.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Thu, 4 Sep 2014 20:21:50 +0000 (13:21 -0700)]
clk: qcom: Consolidate frequency finding logic
There are two find_freq() functions in clk-rcg.c and clk-rcg2.c
that are almost exactly the same. Consolidate them into one
function to save on some code space.
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Andy Gross [Tue, 16 Sep 2014 21:04:12 +0000 (16:04 -0500)]
clk: qcom: Add IPQ8064 PLL required for USB
This patch adds the PLL0 that is required for the USB clocks to
work properly.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Fixes:
24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)"
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Marek Szyprowski [Mon, 22 Sep 2014 12:17:12 +0000 (14:17 +0200)]
clk: samsung: exynos4: fix g3d clocks
sclk_g3d clock doesn't have enable/disable bits, but the driver hijacked
g3d gate clock bits for this purpose and didn't provide real g3d clock
at all. This patch fixes this issue by adding proper definition for g3d
clock and removing incorrect access to GATE_IP_G3D register in sclk_g3d.
In addition CLK_SET_RATE_PARENT flag is dropped from sclk_g3d, because
it does not make any sense and most likely has been added by mistake.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
[tomasz.figa@gmail.com: Adjusted commit message.]
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Marek Szyprowski [Tue, 1 Jul 2014 08:10:05 +0000 (10:10 +0200)]
clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocks
This patch adds support for exporting mout_hdmi and mout_mixer to device
tree. Access to those clocks is required to correctly setup HDMI module
on Exynos 4210 and 4x12 SoCs.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
CC: Mike Turquette <mturquette@linaro.org>
CC: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Marek Szyprowski [Tue, 16 Sep 2014 11:54:31 +0000 (13:54 +0200)]
clk: samsung: exynos4: add missing smmu_g2d clock and update comments
This patch adds missing smmu_g2d clock implementation and updates
comment about Exynos4 clocks from 278-282 range. Those clocks are
available on all Exynos4 SoC series, so the misleading comment has been
removed.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Krzysztof Kozlowski [Tue, 2 Sep 2014 13:21:17 +0000 (15:21 +0200)]
dt-bindings: clk: samsung: Document the DMC domain of Exynos3250 CMU
Document the new compatible for clock in DMC (Dynamic Memory
Controller) domain of Exynos3250 Clock Management Unit (CMU).
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Krzysztof Kozlowski [Tue, 2 Sep 2014 13:21:16 +0000 (15:21 +0200)]
ARM: dts: exynos3250: Add CMU node for DMC domain clocks
Add CMU (Clock Management Unit) node for DMC (Dynamic Memory Controller)
domain clocks on Exynos3250.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Krzysztof Kozlowski [Tue, 2 Sep 2014 13:21:15 +0000 (15:21 +0200)]
clk: samsung: exynos3250: Register DMC clk provider
Add clock provider for clocks in DMC domain including EPLL and BPLL. The
DMC clocks are necessary for Exynos3 devfreq driver.
The DMC clock domain uses different address space (0x105C0000) than
standard clock domain (0x10030000 - 0x10050000). The difference is huge
enough to add new DT node for the clock provider, rather than extending
existing address space.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Chander Kashyap [Wed, 10 Sep 2014 05:56:05 +0000 (11:26 +0530)]
clk: samsung: exynos5260: fix typo in clock name
The parent name added in parent list as
mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p, is different
than the defined parent due to typo.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Chander Kashyap <k.chander@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Pankaj Dubey [Fri, 5 Sep 2014 11:54:41 +0000 (17:24 +0530)]
clk: samsung: exynos3250: fix width field of mout_mmc0/1
As per Exynos3250 user manual mmc0/1 mux selection has 4 bit wide.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Pankaj Dubey [Tue, 9 Sep 2014 11:54:57 +0000 (17:24 +0530)]
clk: samsung: exynos3250: fix width and shift of div_spi0_isp clock
Update shift and width field of div_spi0_isp clock as per Exynos3250
user manual.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Pankaj Dubey [Sat, 6 Sep 2014 13:03:33 +0000 (18:33 +0530)]
clk: samsung: exynos3250: fix mout_cam_blk parent list
As per user manual of Exynos3250 SRC_CAM can select
div_cam_blk_320 if it's value is 0xC, so placing
div_cam_blk_320 at proper index in parent list of mout_cam_blk.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Tomeu Vizoso [Wed, 17 Sep 2014 09:34:17 +0000 (11:34 +0200)]
clk: tegra: Make clock initialization more robust
Don't abort clock initialization if we cannot match an entry in
tegra_clk_init_table to a valid entry in the clk array.
Also log a corresponding error message.
This was discovered when testing a patch that removed the EMC clock from
tegra124_clks but left a mention in tegra_clk_init_table.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Mikko Perttunen [Fri, 11 Jul 2014 14:18:29 +0000 (17:18 +0300)]
clk: tegra124: Add PLL_M_UD and PLL_C_UD clocks
These clocks are used as parents for some EMC timings.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Mikko Perttunen [Fri, 11 Jul 2014 14:18:28 +0000 (17:18 +0300)]
ARM: tegra: Add PLL_M_UD and PLL_C_UD to tegra124-car binding header
Add these clocks to the binding header so that EMC timings that have
them as parent can refer to the clocks.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Mike Turquette [Wed, 17 Sep 2014 18:47:56 +0000 (11:47 -0700)]
Merge branch 'clk-fixes' into clk-next
Linus Torvalds [Mon, 15 Sep 2014 00:50:12 +0000 (17:50 -0700)]
Linux 3.17-rc5
Linus Torvalds [Mon, 15 Sep 2014 00:37:36 +0000 (17:37 -0700)]
Merge branch 'for-linus' of git://git./linux/kernel/git/viro/vfs
Pull vfs fixes from Al Viro:
"double iput() on failure exit in lustre, racy removal of spliced
dentries from ->s_anon in __d_materialise_dentry() plus a bunch of
assorted RCU pathwalk fixes"
The RCU pathwalk fixes end up fixing a couple of cases where we
incorrectly dropped out of RCU walking, due to incorrect initialization
and testing of the sequence locks in some corner cases. Since dropping
out of RCU walk mode forces the slow locked accesses, those corner cases
slowed down quite dramatically.
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs:
be careful with nd->inode in path_init() and follow_dotdot_rcu()
don't bugger nd->seq on set_root_rcu() from follow_dotdot_rcu()
fix bogus read_seqretry() checks introduced in
b37199e
move the call of __d_drop(anon) into __d_materialise_unique(dentry, anon)
[fix] lustre: d_make_root() does iput() on dentry allocation failure
Linus Torvalds [Mon, 15 Sep 2014 00:28:32 +0000 (17:28 -0700)]
vfs: avoid non-forwarding large load after small store in path lookup
The performance regression that Josef Bacik reported in the pathname
lookup (see commit
99d263d4c5b2 "vfs: fix bad hashing of dentries") made
me look at performance stability of the dcache code, just to verify that
the problem was actually fixed. That turned up a few other problems in
this area.
There are a few cases where we exit RCU lookup mode and go to the slow
serializing case when we shouldn't, Al has fixed those and they'll come
in with the next VFS pull.
But my performance verification also shows that link_path_walk() turns
out to have a very unfortunate 32-bit store of the length and hash of
the name we look up, followed by a 64-bit read of the combined hash_len
field. That screws up the processor store to load forwarding, causing
an unnecessary hickup in this critical routine.
It's caused by the ugly calling convention for the "hash_name()"
function, and easily fixed by just making hash_name() fill in the whole
'struct qstr' rather than passing it a pointer to just the hash value.
With that, the profile for this function looks much smoother.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Linus Torvalds [Sun, 14 Sep 2014 19:28:08 +0000 (12:28 -0700)]
Merge branch 'parisc-3.17-1' of git://git./linux/kernel/git/deller/parisc-linux
Pull parisc updates from Helge Deller:
"The most important patch is a new Light Weigth Syscall (LWS) for 8,
16, 32 and 64 bit atomic CAS operations which is required in order to
be able to implement the atomic gcc builtins on our platform.
Other than that, we wire up the seccomp, getrandom and memfd_create
syscalls, fixes a minor off-by-one bug and a wrong printk string"
* 'parisc-3.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
parisc: Implement new LWS CAS supporting 64 bit operations.
parisc: Wire up seccomp, getrandom and memfd_create syscalls
parisc: dino: fix %d confusingly prefixed with 0x in format string
parisc: sys_hpux: NUL terminator is one past the end
Al Viro [Sun, 14 Sep 2014 01:59:43 +0000 (21:59 -0400)]
be careful with nd->inode in path_init() and follow_dotdot_rcu()
in the former we simply check if dentry is still valid after picking
its ->d_inode; in the latter we fetch ->d_inode in the same places
where we fetch dentry and its ->d_seq, under the same checks.
Cc: stable@vger.kernel.org # 2.6.38+
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Al Viro [Sun, 14 Sep 2014 01:55:46 +0000 (21:55 -0400)]
don't bugger nd->seq on set_root_rcu() from follow_dotdot_rcu()
return the value instead, and have path_init() do the assignment. Broken by
"vfs: Fix absolute RCU path walk failures due to uninitialized seq number",
which was Cc-stable with 2.6.38+ as destination. This one should go where
it went.
To avoid dummy value returned in case when root is already set (it would do
no harm, actually, since the only caller that doesn't ignore the return value
is guaranteed to have nd->root *not* set, but it's more obvious that way),
lift the check into callers. And do the same to set_root(), to keep them
in sync.
Cc: stable@vger.kernel.org # 2.6.38+
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Linus Torvalds [Sun, 14 Sep 2014 17:54:12 +0000 (10:54 -0700)]
Merge tag 'ntb-3.17' of git://github.com/jonmason/ntb
Pull ntb driver bugfixes from Jon Mason:
"NTB driver fixes for queue spread and buffer alignment. Also, update
to MAINTAINERS to reflect new e-mail address"
* tag 'ntb-3.17' of git://github.com/jonmason/ntb:
ntb: Add alignment check to meet hardware requirement
MAINTAINERS: update NTB info
NTB: correct the spread of queues over mw's
Linus Torvalds [Sun, 14 Sep 2014 17:37:10 +0000 (10:37 -0700)]
Merge branch 'irq-urgent-for-linus' of git://git./linux/kernel/git/tip/tip
Pull ARM irq chip fixes from Thomas Gleixner:
"Another pile of ARM specific irq chip fixlets:
- off by one bugs in the crossbar driver
- missing annotations
- a bunch of "make it compile" updates
I pulled the lot today from Jason, but it has been in -next for at
least a week"
* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
irqchip: gic-v3: Declare rdist as __percpu pointer to __iomem pointer
irqchip: gic: Make gic_default_routable_irq_domain_ops static
irqchip: exynos-combiner: Fix compilation error on ARM64
irqchip: crossbar: Off by one bugs in init
irqchip: gic-v3: Tag all low level accessors __maybe_unused
irqchip: gic-v3: Only define gic_peek_irq() when building SMP
Thomas Gleixner [Sun, 14 Sep 2014 13:19:19 +0000 (15:19 +0200)]
Merge tag 'irqchip-urgent-3.17' of git://git.infradead.org/users/jcooper/linux into irq/urgent
irqchip fixes for v3.17 from Jason Cooper
- GIC/GICV3: Various fixlets
- crossbar: Fix off-by-one bug
- exynos-combiner: Fix arm64 build error
Dave Jiang [Thu, 28 Aug 2014 20:53:02 +0000 (13:53 -0700)]
ntb: Add alignment check to meet hardware requirement
The NTB translate register must have the value to be BAR size aligned.
This alignment check make sure that the DMA memory allocated has the
proper alignment. Another requirement for NTB to function properly with
memory window BAR size greater or equal to 4M is to use the CMA feature
in 3.16 kernel with the appropriate CONFIG_CMA_ALIGNMENT and
CONFIG_CMA_SIZE_MBYTES set.
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jon Mason <jdmason@kudzu.us>
Jon Mason [Thu, 19 Jun 2014 17:44:24 +0000 (10:44 -0700)]
MAINTAINERS: update NTB info
Update my contact info to my personal email address and add Dave Jiang.
Signed-off-by: Jon Mason <jon.mason@intel.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Jon Mason [Thu, 19 Jun 2014 17:11:13 +0000 (10:11 -0700)]
NTB: correct the spread of queues over mw's
The detection of an uneven number of queues on the given memory windows
was not correct. The mw_num is zero based and the mod should be
division to spread them evenly over the mw's.
Signed-off-by: Jon Mason <jon.mason@intel.com>
Al Viro [Sun, 14 Sep 2014 01:50:45 +0000 (21:50 -0400)]
fix bogus read_seqretry() checks introduced in
b37199e
read_seqretry() returns true on mismatch, not on match...
Cc: stable@vger.kernel.org # 3.15+
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Al Viro [Thu, 11 Sep 2014 22:55:50 +0000 (18:55 -0400)]
move the call of __d_drop(anon) into __d_materialise_unique(dentry, anon)
and lock the right list there
Cc: stable@vger.kernel.org
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Al Viro [Wed, 3 Sep 2014 17:11:09 +0000 (13:11 -0400)]
[fix] lustre: d_make_root() does iput() on dentry allocation failure
double-free is a bad thing
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Linus Torvalds [Sat, 13 Sep 2014 21:22:12 +0000 (14:22 -0700)]
Merge branches 'locking-urgent-for-linus' and 'timers-urgent-for-linus' of git://git./linux/kernel/git/tip/tip
Pull futex and timer fixes from Thomas Gleixner:
"A oneliner bugfix for the jinxed futex code:
- Drop hash bucket lock in the error exit path. I really could slap
myself for intruducing that bug while fixing all the other horror
in that code three month ago ...
and the timer department is not too proud about the following fixes:
- Deal with a long standing rounding bug in the timeval to jiffies
conversion. It's a real issue and this fix fell through the cracks
for quite some time.
- Another round of alarmtimer fixes. Finally this code gets used
more widely and the subtle issues hidden for quite some time are
noticed and fixed. Nothing really exciting, just the itty bitty
details which bite the serious users here and there"
* 'locking-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
futex: Unlock hb->lock in futex_wait_requeue_pi() error path
* 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
alarmtimer: Lock k_itimer during timer callback
alarmtimer: Do not signal SIGEV_NONE timers
alarmtimer: Return relative times in timer_gettime
jiffies: Fix timeval conversion to jiffies
Guy Martin [Fri, 12 Sep 2014 16:02:34 +0000 (18:02 +0200)]
parisc: Implement new LWS CAS supporting 64 bit operations.
The current LWS cas only works correctly for 32bit. The new LWS allows
for CAS operations of variable size.
Signed-off-by: Guy Martin <gmsoft@tuxicoman.be>
Cc: <stable@vger.kernel.org> # 3.13+
Signed-off-by: Helge Deller <deller@gmx.de>
Linus Torvalds [Sat, 13 Sep 2014 18:30:10 +0000 (11:30 -0700)]
vfs: fix bad hashing of dentries
Josef Bacik found a performance regression between 3.2 and 3.10 and
narrowed it down to commit
bfcfaa77bdf0 ("vfs: use 'unsigned long'
accesses for dcache name comparison and hashing"). He reports:
"The test case is essentially
for (i = 0; i <
1000000; i++)
mkdir("a$i");
On xfs on a fio card this goes at about 20k dir/sec with 3.2, and 12k
dir/sec with 3.10. This is because we spend waaaaay more time in
__d_lookup on 3.10 than in 3.2.
The new hashing function for strings is suboptimal for <
sizeof(unsigned long) string names (and hell even > sizeof(unsigned
long) string names that I've tested). I broke out the old hashing
function and the new one into a userspace helper to get real numbers
and this is what I'm getting:
Old hash table had
1000000 entries, 0 dupes, 0 max dupes
New hash table had 12628 entries, 987372 dupes, 900 max dupes
We had 11400 buckets with a p50 of 30 dupes, p90 of 240 dupes, p99 of 567 dupes for the new hash
My test does the hash, and then does the d_hash into a integer pointer
array the same size as the dentry hash table on my system, and then
just increments the value at the address we got to see how many
entries we overlap with.
As you can see the old hash function ended up with all 1 million
entries in their own bucket, whereas the new one they are only
distributed among ~12.5k buckets, which is why we're using so much
more CPU in __d_lookup".
The reason for this hash regression is two-fold:
- On 64-bit architectures the down-mixing of the original 64-bit
word-at-a-time hash into the final 32-bit hash value is very
simplistic and suboptimal, and just adds the two 32-bit parts
together.
In particular, because there is no bit shuffling and the mixing
boundary is also a byte boundary, similar character patterns in the
low and high word easily end up just canceling each other out.
- the old byte-at-a-time hash mixed each byte into the final hash as it
hashed the path component name, resulting in the low bits of the hash
generally being a good source of hash data. That is not true for the
word-at-a-time case, and the hash data is distributed among all the
bits.
The fix is the same in both cases: do a better job of mixing the bits up
and using as much of the hash data as possible. We already have the
"hash_32|64()" functions to do that.
Reported-by: Josef Bacik <jbacik@fb.com>
Cc: Al Viro <viro@zeniv.linux.org.uk>
Cc: Christoph Hellwig <hch@infradead.org>
Cc: Chris Mason <clm@fb.com>
Cc: linux-fsdevel@vger.kernel.org
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Linus Torvalds [Sat, 13 Sep 2014 18:24:03 +0000 (11:24 -0700)]
Make hash_64() use a 64-bit multiply when appropriate
The hash_64() function historically does the multiply by the
GOLDEN_RATIO_PRIME_64 number with explicit shifts and adds, because
unlike the 32-bit case, gcc seems unable to turn the constant multiply
into the more appropriate shift and adds when required.
However, that means that we generate those shifts and adds even when the
architecture has a fast multiplier, and could just do it better in
hardware.
Use the now-cleaned-up CONFIG_ARCH_HAS_FAST_MULTIPLIER (together with
"is it a 64-bit architecture") to decide whether to use an integer
multiply or the explicit sequence of shift/add instructions.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Linus Torvalds [Sat, 13 Sep 2014 18:14:53 +0000 (11:14 -0700)]
Make ARCH_HAS_FAST_MULTIPLIER a real config variable
It used to be an ad-hoc hack defined by the x86 version of
<asm/bitops.h> that enabled a couple of library routines to know whether
an integer multiply is faster than repeated shifts and additions.
This just makes it use the real Kconfig system instead, and makes x86
(which was the only architecture that did this) select the option.
NOTE! Even for x86, this really is kind of wrong. If we cared, we would
probably not enable this for builds optimized for netburst (P4), where
shifts-and-adds are generally faster than multiplies. This patch does
*not* change that kind of logic, though, it is purely a syntactic change
with no code changes.
This was triggered by the fact that we have other places that really
want to know "do I want to expand multiples by constants by hand or
not", particularly the hash generation code.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Linus Torvalds [Sat, 13 Sep 2014 17:04:10 +0000 (10:04 -0700)]
Merge tag 'dm-3.17-fix2' of git://git./linux/kernel/git/device-mapper/linux-dm
Pull device mapper fix from Mike Snitzer:
"Fix a race in the DM cache target that caused dirty blocks to be
marked as clean. This could cause no writeback to occur or spurious
dirty block counts"
* tag 'dm-3.17-fix2' of git://git.kernel.org/pub/scm/linux/kernel/git/device-mapper/linux-dm:
dm cache: fix race causing dirty blocks to be marked as clean
Linus Torvalds [Sat, 13 Sep 2014 16:39:55 +0000 (09:39 -0700)]
Merge branch 'for-linus' of git://git.kernel.dk/linux-block
Pull block fixes from Jens Axboe:
"A small collection of fixes for the current rc series. This contains:
- Two small blk-mq patches from Rob Elliott, cleaning up error case
at init time.
- A fix from Ming Lei, fixing SG merging for blk-mq where
QUEUE_FLAG_SG_NO_MERGE is the default.
- A dev_t minor lifetime fix from Keith, fixing an issue where a
minor might be reused before all references to it were gone.
- Fix from Alan Stern where an unbalanced queue bypass caused SCSI
some headaches when it does a series of add/del on devices without
fully registrering the queue.
- A fix from me for improving the scaling of tag depth in blk-mq if
we are short on memory"
* 'for-linus' of git://git.kernel.dk/linux-block:
blk-mq: scale depth and rq map appropriate if low on memory
Block: fix unbalanced bypass-disable in blk_register_queue
block: Fix dev_t minor allocation lifetime
blk-mq: cleanup after blk_mq_init_rq_map failures
blk-mq: pass along blk_mq_alloc_tag_set return values
blk-merge: fix blk_recount_segments
Chen-Yu Tsai [Sat, 6 Sep 2014 06:45:10 +0000 (14:45 +0800)]
clk: sunxi: add correct divider table for sun4i-apb0 clock
The sun4i-apb0 clock, as found on all platforms using it, is a
power-of-two-based divider clock, with a special divider of 2
for value 0.
This was causing the clock framework to incorrectly calculate
the clock rate for apb1 and related modules on sun6i and sun8i.
On sun[4/5/7]i, u-boot SPL configures the divider with value 1
for /2 divider, so no suprises there.
This patch adds a proper divider table for it, so the correct
clock rate can be calculated.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Linus Torvalds [Sat, 13 Sep 2014 00:45:27 +0000 (17:45 -0700)]
Merge tag 'stable/for-linus-3.17-b-rc4-arm-tag' of git://git./linux/kernel/git/xen/tip
Pull Xen ARM bugfix from Stefano Stabellini:
"The patches fix the "xen_add_mach_to_phys_entry: cannot add" bug that
has been affecting xen on arm and arm64 guests since 3.16. They
require a few hypervisor side changes that just went in xen-unstable.
A couple of days ago David sent out a pull request with a few other
Xen fixes (it is already in master). Sorry we didn't synchronized
better among us"
* tag 'stable/for-linus-3.17-b-rc4-arm-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip:
xen/arm: remove mach_to_phys rbtree
xen/arm: reimplement xen_dma_unmap_page & friends
xen/arm: introduce XENFEAT_grant_map_identity
Richard Larocque [Wed, 10 Sep 2014 01:31:05 +0000 (18:31 -0700)]
alarmtimer: Lock k_itimer during timer callback
Locks the k_itimer's it_lock member when handling the alarm timer's
expiry callback.
The regular posix timers defined in posix-timers.c have this lock held
during timout processing because their callbacks are routed through
posix_timer_fn(). The alarm timers follow a different path, so they
ought to grab the lock somewhere else.
Cc: stable@vger.kernel.org
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Prarit Bhargava <prarit@redhat.com>
Cc: Sharvil Nanavati <sharvil@google.com>
Signed-off-by: Richard Larocque <rlarocque@google.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>