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Matthew Gharrity [Wed, 20 Jul 2016 19:50:52 +0000 (19:50 +0000)]
Merge \\"Fix accidental pass-by-value\\" am:
27d99ed243
am:
3fa237bc32
Change-Id: I5eaec7a7a98f6179e0bdb0aae1449ebbb4121075
Matthew Gharrity [Wed, 20 Jul 2016 19:48:24 +0000 (19:48 +0000)]
Merge \"Fix accidental pass-by-value\"
am:
27d99ed243
Change-Id: Iab0f6c30f77a0764a11ce094d05a79e81d28685e
Treehugger Robot [Wed, 20 Jul 2016 19:42:28 +0000 (19:42 +0000)]
Merge "Fix accidental pass-by-value"
Richard Uhler [Wed, 20 Jul 2016 18:30:50 +0000 (18:30 +0000)]
Merge changes I328ea51d,I577c5d02 am:
6c81dfeaef
am:
f87c76d0dc
Change-Id: Id44ec9b26970ce22620975cbbdc4fa25204013cf
Richard Uhler [Wed, 20 Jul 2016 18:28:17 +0000 (18:28 +0000)]
Merge changes I328ea51d,I577c5d02
am:
6c81dfeaef
Change-Id: I18b7d076b1db11560f4ee4488a5c4f5f8093ffa5
Treehugger Robot [Wed, 20 Jul 2016 18:22:10 +0000 (18:22 +0000)]
Merge changes I328ea51d,I577c5d02
* changes:
Compute oat and odex filenames eagerly.
Make a static OatFileAssistant::DexLocationToOatFileName function.
Matthew Gharrity [Wed, 20 Jul 2016 17:13:45 +0000 (10:13 -0700)]
Fix accidental pass-by-value
Change-Id: I245111eabb43368875c1215ca4f3a1f1918492fe
Vladimir Marko [Wed, 20 Jul 2016 12:10:51 +0000 (12:10 +0000)]
Merge \\"ART: Change return types of field access entrypoints\\" am:
360b4b0137
am:
127d900ccc
Change-Id: Ibb1d4ae96a3c6514cdd6a1d1f77d6f9f66f8cee1
Andreas Gampe [Wed, 20 Jul 2016 12:07:24 +0000 (12:07 +0000)]
Merge \"ART: Change return types of field access entrypoints\"
am:
360b4b0137
Change-Id: I98f4f6ea89d48f5405da245c94ff7bddb0b5d588
Vladimir Marko [Wed, 20 Jul 2016 12:01:15 +0000 (12:01 +0000)]
Merge "ART: Change return types of field access entrypoints"
Nicolas Geoffray [Wed, 20 Jul 2016 11:02:47 +0000 (11:02 +0000)]
Merge \\"Fix test after rename.\\" am:
522da11a6c
am:
c8f60fd364
Change-Id: I445afbc70e5c0ba06f2d6687f1876e27e1a92d2e
Nicolas Geoffray [Wed, 20 Jul 2016 10:59:18 +0000 (10:59 +0000)]
Merge \"Fix test after rename.\"
am:
522da11a6c
Change-Id: Iefbef3b21a47951c736522079a780884308a4dc5
Nicolas Geoffray [Wed, 20 Jul 2016 10:53:11 +0000 (10:53 +0000)]
Merge "Fix test after rename."
Nicolas Geoffray [Wed, 20 Jul 2016 10:49:47 +0000 (11:49 +0100)]
Fix test after rename.
bug:
29964720
Change-Id: I37cebc40ca83597b159eefbc492e8cc105996306
Andreas Gampe [Wed, 20 Jul 2016 05:34:53 +0000 (22:34 -0700)]
ART: Change return types of field access entrypoints
Ensure that return types guarantee full-width data as the compiled
code and mterp expect by using size_t and ssize_t.
This fixes Clang no longer sign-/zero-extending small return types.
Bug:
30232671
Test: m ART_TEST_RUN_TEST_NDEBUG=true ART_TEST_INTERPRETER=true test-art-host-run-test
Change-Id: Ic505befc6c94e2dccbc8abf2b13d4c2d662e68d1
Nicolas Geoffray [Wed, 20 Jul 2016 10:38:47 +0000 (10:38 +0000)]
Merge \\"JIT: Don\\'t update the dex cache of another class loader.\\" am:
79e7324514
am:
7dfe12f613
Change-Id: I6675e34a34104df1b9909e994b245f696f00d0ed
Nicolas Geoffray [Wed, 20 Jul 2016 10:36:17 +0000 (10:36 +0000)]
Merge \"JIT: Don\'t update the dex cache of another class loader.\"
am:
79e7324514
Change-Id: Iebb37f437c9dfd2693e30b76d55eedc3754653c4
Nicolas Geoffray [Wed, 20 Jul 2016 10:30:09 +0000 (10:30 +0000)]
Merge "JIT: Don't update the dex cache of another class loader."
Vladimir Marko [Wed, 20 Jul 2016 09:31:12 +0000 (09:31 +0000)]
Merge \\"ARM: Change mem address mode for array accesses.\\" am:
c17e6d3f0d
am:
5ae90905ce
Change-Id: I3a2a756aff25f4c112f59cee9d19beeb32e6de59
Artem Serov [Wed, 20 Jul 2016 09:28:14 +0000 (09:28 +0000)]
Merge \"ARM: Change mem address mode for array accesses.\"
am:
c17e6d3f0d
Change-Id: I2d7b575279de5633edb5cfe22167fcfd7cdd8267
Vladimir Marko [Wed, 20 Jul 2016 09:20:55 +0000 (09:20 +0000)]
Merge "ARM: Change mem address mode for array accesses."
Artem Serov [Mon, 11 Jul 2016 13:02:34 +0000 (14:02 +0100)]
ARM: Change mem address mode for array accesses.
Switch from:
add IP, r[Array], r[Index], LSL #2
ldr r0, [IP, #12]
To:
add IP. r[Array], #12
ldr r0, [IP, r[Index], LSL #2]
These is a base for the future TryExtractArrayAccessAddress
optimization port to arm.
Test: aosp_shamu-userdebug boots and passes "m test-art-target".
Change-Id: I6ab01ba3271a8f79599ddd91a6b63cd1b37d2d67
Matthew Gharrity [Wed, 20 Jul 2016 00:22:38 +0000 (00:22 +0000)]
Merge \\"Refactor SSA deconstruction into its own class\\" am:
dc4f4d42aa
am:
2bb481b75c
Change-Id: Icefcb18977b0e343e2faa239aa3a927c7f7ad295
Matthew Gharrity [Wed, 20 Jul 2016 00:05:08 +0000 (00:05 +0000)]
Merge \"Refactor SSA deconstruction into its own class\"
am:
dc4f4d42aa
Change-Id: Ie844ec62bcea08ad24ac0a6682adbf632e4e69e3
Treehugger Robot [Wed, 20 Jul 2016 00:02:38 +0000 (00:02 +0000)]
Merge "Refactor SSA deconstruction into its own class"
Hiroshi Yamauchi [Tue, 19 Jul 2016 23:52:27 +0000 (23:52 +0000)]
Merge \\"Tune the GC ergnomics for the read barrier config.\\" am:
0331aa7274
am:
61b07eb778
Change-Id: Iaf4d2fa18aee0f25987410ffa68b4da2eb586853
Stephen Hines [Tue, 19 Jul 2016 23:50:52 +0000 (23:50 +0000)]
Merge \\"Disable warnings triggered in Clang r271374\\" am:
73e83ec579
am:
8748c04bca
Change-Id: I47c22d97cd2173ffa79b9979b12dd41edc50d01a
Hiroshi Yamauchi [Tue, 19 Jul 2016 23:44:05 +0000 (23:44 +0000)]
Merge \"Tune the GC ergnomics for the read barrier config.\"
am:
0331aa7274
Change-Id: Ib31f3c99bee9236746b8ac5eb5615bd794abeb29
Pirama Arumuga Nainar [Tue, 19 Jul 2016 23:40:18 +0000 (23:40 +0000)]
Merge \"Disable warnings triggered in Clang r271374\"
am:
73e83ec579
Change-Id: I7badac5ae194cda9411ea2856a30e4add8fc1ed8
Treehugger Robot [Tue, 19 Jul 2016 22:07:57 +0000 (22:07 +0000)]
Merge "Tune the GC ergnomics for the read barrier config."
Stephen Hines [Tue, 19 Jul 2016 22:02:31 +0000 (22:02 +0000)]
Merge "Disable warnings triggered in Clang r271374"
Matthew Gharrity [Mon, 18 Jul 2016 20:38:44 +0000 (13:38 -0700)]
Refactor SSA deconstruction into its own class
Test: m test-art-host
Change-Id: Ie82c2802f76f27512ef922ba583caeccf5675063
Pirama Arumuga Nainar [Tue, 28 Jun 2016 17:51:10 +0000 (10:51 -0700)]
Disable warnings triggered in Clang r271374
http://b/
28149048
http://b/
29823425
Disable -Wconstant-conversion and -Wundefined-var-template. The second
bug above tracks that these warnings get reenabled.
Test: Tested build, boot and common usage for Arm, Arm64, x86, x86_64,
Mips images in AOSP and internal branch.
Change-Id: Iea20cf6b5dbec3247b55cf8130f88202e786e367
Hiroshi Yamauchi [Tue, 19 Jul 2016 00:07:26 +0000 (17:07 -0700)]
Tune the GC ergnomics for the read barrier config.
Add 1.0 to the heap growth multiplier for the read barrier config, which
reduces the GC frequency down to roughly the same as CMS in one of the
jank tests.
Bug:
29517059
Bug:
12687968
Test: ART run-tests.
Change-Id: I1302a2f17e862f152d2f92bc06a65c9e6defcba0
Nicolas Geoffray [Tue, 19 Jul 2016 16:06:23 +0000 (17:06 +0100)]
JIT: Don't update the dex cache of another class loader.
This only works for properly delegating class loaders. But Java allows
non-delegating ones :(
bug:
29964720
Change-Id: I8b785e6cdfe9a2b77322521a02b8e59ec332ad83
test:612-jit-dex-cache
Richard Uhler [Tue, 19 Apr 2016 20:24:41 +0000 (13:24 -0700)]
Compute oat and odex filenames eagerly.
Because we almost always need both of them anyway, and they aren't
expensive to compute.
Test: oat file assistant tests.
Change-Id: I328ea51da6eb8700329f829a0458b02e12d1ee9e
Richard Uhler [Tue, 19 Apr 2016 20:08:04 +0000 (13:08 -0700)]
Make a static OatFileAssistant::DexLocationToOatFileName function.
So that you can figure out an oat file name without instantiating an
OatFileAssistant object.
Test: oat file assistant tests.
Change-Id: I577c5d02225f926086e9833d45b88d8a92db52fa
Vladimir Marko [Tue, 19 Jul 2016 12:45:38 +0000 (12:45 +0000)]
Merge \\"ARM: Fix shifted register offset mem address mode for load signed.\\" am:
bae13af2fc
am:
e743f45582
Change-Id: I342bc690d3eb3f3dfa52bb4b61e5139d736a9561
Artem Serov [Tue, 19 Jul 2016 12:42:42 +0000 (12:42 +0000)]
Merge \"ARM: Fix shifted register offset mem address mode for load signed.\"
am:
bae13af2fc
Change-Id: I0c647d242f865e8a67dce0ef17388e7113a2f6a7
Vladimir Marko [Tue, 19 Jul 2016 12:37:33 +0000 (12:37 +0000)]
Merge "ARM: Fix shifted register offset mem address mode for load signed."
Artem Serov [Mon, 11 Jul 2016 13:00:46 +0000 (14:00 +0100)]
ARM: Fix shifted register offset mem address mode for load signed.
For example 'ldrsh r0, [sp, r1, LSL #2]' previously
was assembled as 'ldrh'.
Test: New test in assembler_thumb2_test.cc .
Change-Id: I1d30724f0c2745b131876bffefdc0a780d76f6a1
Mathieu Chartier [Mon, 18 Jul 2016 23:06:21 +0000 (23:06 +0000)]
Merge \\"Do allocation fence before pushing on allocation stack\\" am:
2be946bbf9
am:
6631f8824f
Change-Id: Idf1eaacb7e46ed160d3f6852d7a8ca6aa756fc2c
Mathieu Chartier [Mon, 18 Jul 2016 23:04:22 +0000 (23:04 +0000)]
Merge \"Do allocation fence before pushing on allocation stack\"
am:
2be946bbf9
Change-Id: I9506c94419d6fcddeba63264fbc75c83ac1c4ffa
Treehugger Robot [Mon, 18 Jul 2016 22:53:44 +0000 (22:53 +0000)]
Merge "Do allocation fence before pushing on allocation stack"
Mathieu Chartier [Mon, 18 Jul 2016 18:11:45 +0000 (11:11 -0700)]
Do allocation fence before pushing on allocation stack
Heap::VisitObjects relies on having valid classes for objects in
the allocation stack. If the writes reorder, the thread calling
VisitObjects could see the free list pointer instead of the class
of the object. I believe this is causing crashes in VisitObjects.
Bug:
28790624
Test: Volantis booted
Change-Id: I0f2d4097de1ef3f5caf670ecc977d4d6837872ca
Matthew Gharrity [Mon, 18 Jul 2016 19:50:47 +0000 (19:50 +0000)]
Merge \\"Rename current register allocator implementation\\" am:
0c67ddaff8
am:
407e663d22
Change-Id: Icc223a8ce610b234e6540eaeebdd2fbe6edcb7df
Matthew Gharrity [Mon, 18 Jul 2016 19:47:48 +0000 (19:47 +0000)]
Merge \"Rename current register allocator implementation\"
am:
0c67ddaff8
Change-Id: I7adac5a5f5a9ba63fcb0097d94b31ede77597e98
Treehugger Robot [Mon, 18 Jul 2016 19:35:11 +0000 (19:35 +0000)]
Merge "Rename current register allocator implementation"
Andreas Gampe [Mon, 18 Jul 2016 19:01:13 +0000 (19:01 +0000)]
Merge \\"ART: Fix run-test script\\" am:
64a73d790d
am:
5af55b212d
Change-Id: Id048e0a30393b979e040b0df28603e8e8b2698f8
Andreas Gampe [Mon, 18 Jul 2016 18:57:44 +0000 (18:57 +0000)]
Merge \"ART: Fix run-test script\"
am:
64a73d790d
Change-Id: I9dd051ba4a63c536a1a45ac7a30bc80cd380f5ff
Treehugger Robot [Mon, 18 Jul 2016 18:49:56 +0000 (18:49 +0000)]
Merge "ART: Fix run-test script"
Andreas Gampe [Sat, 25 Jun 2016 05:30:29 +0000 (22:30 -0700)]
ART: Fix run-test script
Don't assume out is under BUILD_TOP.
Test: run-test with OUT_DIR_COMMON_BASE set
Change-Id: Iba408e807e6a15ff60de54d6d4d653814d4b11d0
Roland Levillain [Mon, 18 Jul 2016 15:48:59 +0000 (15:48 +0000)]
Merge \\"MIPS64: Highest/Lowest Bit Intrinsic Support\\" am:
4c489f48ef
am:
8ef385099a
Change-Id: I79e1d52b6a0af68f93296bf517fefeba64cd1b59
Chris Larsen [Mon, 18 Jul 2016 15:45:33 +0000 (15:45 +0000)]
Merge \"MIPS64: Highest/Lowest Bit Intrinsic Support\"
am:
4c489f48ef
Change-Id: Iab39b42ed59a14a8cd02b8a357bb404d65cdd09f
Roland Levillain [Mon, 18 Jul 2016 15:40:34 +0000 (15:40 +0000)]
Merge "MIPS64: Highest/Lowest Bit Intrinsic Support"
Roland Levillain [Mon, 18 Jul 2016 15:21:00 +0000 (15:21 +0000)]
Merge \\"Fix the build with respect to new VIXL.\\" am:
11502fb83b
am:
f34d34524e
Change-Id: I98d54c97b1c866c1828f84f72aa206f27db2b577
Roland Levillain [Mon, 18 Jul 2016 15:18:01 +0000 (15:18 +0000)]
Merge \"Fix the build with respect to new VIXL.\"
am:
11502fb83b
Change-Id: I592e4fa47a4c443fadb174a18d13d98f09fc4beb
Roland Levillain [Mon, 18 Jul 2016 15:07:19 +0000 (15:07 +0000)]
Merge "Fix the build with respect to new VIXL."
Roland Levillain [Mon, 18 Jul 2016 15:03:05 +0000 (16:03 +0100)]
Fix the build with respect to new VIXL.
Test: Build ART for ARM64.
Change-Id: I2a9ebf145c61db9f8ceec6616963bac3ad5a7eb9
Roland Levillain [Mon, 18 Jul 2016 14:36:01 +0000 (14:36 +0000)]
Merge \\"Fixes to build against new VIXL interface.\\" am:
5668e58daf
am:
4bc7404c60
Change-Id: I5d8df7a549efff6f3cfc963db7f67e700d0e87f0
Scott Wakeling [Mon, 18 Jul 2016 14:33:16 +0000 (14:33 +0000)]
Merge \"Fixes to build against new VIXL interface.\"
am:
5668e58daf
Change-Id: I588dd05f58c50d5d50d5dd12b1dbf9e83819968d
Roland Levillain [Mon, 18 Jul 2016 14:28:05 +0000 (14:28 +0000)]
Merge "Fixes to build against new VIXL interface."
Nicolas Geoffray [Mon, 18 Jul 2016 12:26:16 +0000 (12:26 +0000)]
Merge \\"Add a new control flow simplifier.\\" am:
24670a7aac
am:
edde16a482
Change-Id: Iabc6265d6740346966966467fe2edcf9f2249c85
Nicolas Geoffray [Mon, 18 Jul 2016 12:23:19 +0000 (12:23 +0000)]
Merge \"Add a new control flow simplifier.\"
am:
24670a7aac
Change-Id: Ic6ee515aaee1feabf30c874bedc20aa8670cbbb3
Nicolas Geoffray [Mon, 18 Jul 2016 12:16:46 +0000 (12:16 +0000)]
Merge "Add a new control flow simplifier."
Alexandre Rames [Mon, 18 Jul 2016 11:28:13 +0000 (11:28 +0000)]
Merge \\"ARM64: Improve code generated to spill/restore for slow paths.\\" am:
471c2270aa
am:
2f130700c9
Change-Id: I76b2cc087f05030c8993f4aeb31f922708267c39
Alexandre Rames [Mon, 18 Jul 2016 11:25:16 +0000 (11:25 +0000)]
Merge \"ARM64: Improve code generated to spill/restore for slow paths.\"
am:
471c2270aa
Change-Id: Ic804eca9bac139147a6df8ccab3dbc97f1eadf5d
Treehugger Robot [Mon, 18 Jul 2016 11:19:14 +0000 (11:19 +0000)]
Merge "ARM64: Improve code generated to spill/restore for slow paths."
Alexandre Rames [Fri, 15 Jul 2016 16:41:13 +0000 (17:41 +0100)]
ARM64: Improve code generated to spill/restore for slow paths.
Aligning the accesses allows generating better code.
Before:
add x16, sp, #0x44 (68)
stp x0, x1, [x16, #-16]
After:
stp x0, x1, [sp, #56]
Change-Id: I3e20ad3fa59d00aee4b4d14ea9d59c7cd546509e
Nicolas Geoffray [Fri, 15 Jul 2016 09:46:17 +0000 (10:46 +0100)]
Add a new control flow simplifier.
Run it in the dead code elimination phase, as it relates to
creating dead branches.
From 0.04 to 0.07% less code size framework/gms/docs/fb (70K saved on fb)
3%-5% runtime performance improvements on Richards/DeltaBlue/Ritz.
Compile-time is mixed, so in the noise (from 2% slower to 1% faster).
test:611-checker-simplify-if
Change-Id: Ife8b7882d57b5481f5ca9dc163beba655d7e78bf
Andreas Gampe [Sat, 16 Jul 2016 04:54:57 +0000 (04:54 +0000)]
Merge \\"ART: Replace ScopedFd with FdFile\\" am:
173f435e56
am:
b1057359e6
Change-Id: I18c779bde7247cde666d372af63a1c97a9486615
Andreas Gampe [Sat, 16 Jul 2016 04:51:29 +0000 (04:51 +0000)]
Merge \"ART: Replace ScopedFd with FdFile\"
am:
173f435e56
Change-Id: Ibcd5c857690db1374dfa4bf2920e78569bcd876d
Treehugger Robot [Sat, 16 Jul 2016 04:46:46 +0000 (04:46 +0000)]
Merge "ART: Replace ScopedFd with FdFile"
Andreas Gampe [Sat, 16 Jul 2016 00:17:34 +0000 (17:17 -0700)]
ART: Replace ScopedFd with FdFile
FdFile can now be used like ScopedFd. Remove ScopedFd.
Bug:
21192156
Test: m test-art-host
Test: m test-art-target (shamu)
Change-Id: I32115fa8b2b8bb5aa5d1886eae63522f80ce836b
Matthew Gharrity [Thu, 14 Jul 2016 21:08:16 +0000 (14:08 -0700)]
Rename current register allocator implementation
This will allow a cleaner commit in an upcoming
refactoring of register allocation.
Test: m test-art-host
Change-Id: If420c97b088b3c934411ff83373e024003120746
Serdjuk, Nikolay Y [Fri, 15 Jul 2016 16:48:37 +0000 (16:48 +0000)]
Merge \\"ART: disassembler_x86 doesn\\'t recognize NOPs\\" am:
161c866ca7
am:
da75a752b2
Change-Id: I493a85b5a6d661f052616d8507632b6561f6f3bc
Serdjuk, Nikolay Y [Fri, 15 Jul 2016 16:45:09 +0000 (16:45 +0000)]
Merge \"ART: disassembler_x86 doesn\'t recognize NOPs\"
am:
161c866ca7
Change-Id: I5b43d2844e64a74104bd916307b843165a4a12d3
Treehugger Robot [Fri, 15 Jul 2016 16:40:28 +0000 (16:40 +0000)]
Merge "ART: disassembler_x86 doesn't recognize NOPs"
Scott Wakeling [Fri, 24 Jun 2016 15:19:36 +0000 (16:19 +0100)]
Fixes to build against new VIXL interface.
- Fix namespace usage and use of deprecated functions.
- Link all dependants to new libvixl-arm64 target for now.
Change-Id: Iee6f299784fd663fc2a759f3ee816fdbc511e509
Andreas Gampe [Fri, 15 Jul 2016 00:58:12 +0000 (00:58 +0000)]
Merge changes from topic \\'cherry_pinner\\' am:
edec0eb18d
am:
c03ec97cad
Change-Id: I18ad89dec50e4d9f91ce1c8df965c986a0bb0c31
Andreas Gampe [Fri, 15 Jul 2016 00:54:54 +0000 (00:54 +0000)]
Merge changes from topic \'cherry_pinner\'
am:
edec0eb18d
Change-Id: Ie07251a8addccdfbfa642b586bc05ed2cfac1b07
Andreas Gampe [Fri, 15 Jul 2016 00:45:22 +0000 (00:45 +0000)]
Merge changes from topic 'cherry_pinner'
* changes:
ART: Fix build break
Add API for getting location of odex or oat file
Andreas Gampe [Thu, 14 Jul 2016 23:50:52 +0000 (16:50 -0700)]
ART: Fix build break
Build break introduced by mismatch from merges.
Bug:
28251566
(cherry picked from commit
a472e4fd6260740af230bab7be5740d8c7bac360)
Test: m test-art-host
Change-Id: I83a333dd7394af630c5a79153d4838eb3a910714
Philip Cuadra [Tue, 12 Jul 2016 23:37:40 +0000 (16:37 -0700)]
Add API for getting location of odex or oat file
Add an API for getting the file path of odex or oat file given a dex
path.
Bug
28251566
(cherry picked from commit
b4827ace453b9280060a826e8f22cc8c9b6edb7d)
Change-Id: Ibebaa20f15d8135b25d9eb5927b7979801ebf0b2
Mathieu Chartier [Thu, 14 Jul 2016 21:19:25 +0000 (21:19 +0000)]
Merge \\"Revert \\"Revert \\"Dump more dex file data in oatdump\\"\\"\\" am:
05d9a647a6
am:
9c26f22584
Change-Id: If4cbcba0fe9853d787eadaf731abcb5f96984f51
Mathieu Chartier [Thu, 14 Jul 2016 21:16:25 +0000 (21:16 +0000)]
Merge \"Revert \"Revert \"Dump more dex file data in oatdump\"\"\"
am:
05d9a647a6
Change-Id: Id0e8315df8d934d1ac652c8baa520ba58d2db19d
Treehugger Robot [Thu, 14 Jul 2016 21:09:55 +0000 (21:09 +0000)]
Merge "Revert "Revert "Dump more dex file data in oatdump"""
Mathieu Chartier [Thu, 14 Jul 2016 17:10:44 +0000 (10:10 -0700)]
Revert "Revert "Dump more dex file data in oatdump""
Delete runtime to fix leak before callin exit.
Bug:
29462018
This reverts commit
9c05578dd2306231437bd290c0f70abc2bb3b6d8.
Change-Id: Ica23ba0f2d07496d0e4a3288329945f612ac3b20
xueliang.zhong [Thu, 14 Jul 2016 19:52:50 +0000 (19:52 +0000)]
Merge \\"Integer.bitCount and Long.bitCount intrinsics for ARM\\" am:
f18f3cb337
am:
bc76799ba9
Change-Id: Ie63a98345ac7be6f2a4bd3f001c2b884487ade90
xueliang.zhong [Thu, 14 Jul 2016 19:49:51 +0000 (19:49 +0000)]
Merge \"Integer.bitCount and Long.bitCount intrinsics for ARM\"
am:
f18f3cb337
Change-Id: I920dbbe308feb3999966fb9f9fa7e1f6cf1d1fa1
Treehugger Robot [Thu, 14 Jul 2016 19:44:38 +0000 (19:44 +0000)]
Merge "Integer.bitCount and Long.bitCount intrinsics for ARM"
Andreas Gampe [Thu, 14 Jul 2016 18:58:13 +0000 (18:58 +0000)]
Merge \\"ART: Add FdFile constructors\\" am:
2fce5cf079
am:
0c2edd89b6
Change-Id: Ie1b78347e3d64b95c0f2ddae97b530cf1f5dd1e9
Andreas Gampe [Thu, 14 Jul 2016 18:55:19 +0000 (18:55 +0000)]
Merge \"ART: Add FdFile constructors\"
am:
2fce5cf079
Change-Id: Iba1dd0dbe494aa365dc0b6a4727a34721f2bd1d8
Treehugger Robot [Thu, 14 Jul 2016 18:48:03 +0000 (18:48 +0000)]
Merge "ART: Add FdFile constructors"
xueliang.zhong [Tue, 5 Jul 2016 14:28:19 +0000 (15:28 +0100)]
Integer.bitCount and Long.bitCount intrinsics for ARM
Change-Id: I4ed3e779415be026c7d090b61a3e356b37c418e5
Roland Levillain [Thu, 14 Jul 2016 09:41:58 +0000 (09:41 +0000)]
Merge \\"Introduce more compact ReadBarrierMark slow-paths.\\" am:
2c30a37342
am:
333b9e1f3b
Change-Id: Ie71cb6cd05a6590137b35cd3dd4761e5704ca107
Nicolas Geoffray [Thu, 14 Jul 2016 09:41:55 +0000 (09:41 +0000)]
Merge \\"Revert \\"Dump more dex file data in oatdump\\"\\" am:
7598736db0
am:
da9d11c5c3
Change-Id: I49eb03f31456e8a542aeaf6b7f67f35247b0d7b7
Roland Levillain [Thu, 14 Jul 2016 09:37:56 +0000 (09:37 +0000)]
Merge \"Introduce more compact ReadBarrierMark slow-paths.\"
am:
2c30a37342
Change-Id: I2101a1ca0c37c53499bb1bb75a6acb6e6b921c11
Nicolas Geoffray [Thu, 14 Jul 2016 09:37:35 +0000 (09:37 +0000)]
Merge \"Revert \"Dump more dex file data in oatdump\"\"
am:
7598736db0
Change-Id: I2d2efa7dbbd64d28d5ed80dc00940ca1e284e39d
Roland Levillain [Thu, 14 Jul 2016 09:32:34 +0000 (09:32 +0000)]
Merge "Introduce more compact ReadBarrierMark slow-paths."
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