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Hal Finkel [Mon, 31 Mar 2014 17:48:16 +0000 (17:48 +0000)]
[PowerPC] Don't ever expand BUILD_VECTOR of v2i64 with shuffles
If we have two unique values for a v2i64 build vector, this will always result
in two vector loads if we expand using shuffles. Only one is necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205231
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Hal Finkel [Mon, 31 Mar 2014 17:48:10 +0000 (17:48 +0000)]
Add a TLI hook to control when BUILD_VECTOR might be expanded using shuffles
There are two general methods for expanding a BUILD_VECTOR node:
1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
them together.
2. Build the vector on the stack and then load it.
Currently, we use a fixed heuristic: If there are only one or two unique
defined values, then we attempt an expansion in terms of SCALAR_TO_VECTOR and
vector shuffles (provided that the required shuffle mask is legal). Otherwise,
always expand via the stack. Even when SCALAR_TO_VECTOR is not legal, this
can still be a good idea depending on what tricks the target can play when
lowering the resulting shuffle. If the target can't do anything special,
however, and if SCALAR_TO_VECTOR is expanded via the stack, this heuristic
leads to sub-optimal code (two stack loads instead of one).
Because only the target knows whether the SCALAR_TO_VECTORs and shuffles for a
build vector of a particular type are likely to be optimial, this adds a new
TLI function: shouldExpandBuildVectorWithShuffles which takes the vector type
and the count of unique defined values. If this function returns true, then
method (1) will be used, subject to the constraint that all of the necessary
shuffles are legal (as determined by isShuffleMaskLegal). If this function
returns false, then method (2) is always used.
This commit does not enhance the current code to support expanding a
build_vector with more than two unique values using shuffles, but I'll commit
an implementation of the more-general case shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205230
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Daniel Sanders [Mon, 31 Mar 2014 17:43:46 +0000 (17:43 +0000)]
[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205229
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Paul Robinson [Mon, 31 Mar 2014 17:43:35 +0000 (17:43 +0000)]
Disable each MachineFunctionPass for 'optnone' functions, unless that
pass normally runs at optimization level None, or is part of the
register allocation pipeline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205228
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Yaron Keren [Mon, 31 Mar 2014 17:34:15 +0000 (17:34 +0000)]
Two updated tests for MinGW 32 and 64 exception handling code generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205227
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Hal Finkel [Mon, 31 Mar 2014 17:02:10 +0000 (17:02 +0000)]
[PowerPC] Correct P7 dispatch unit allocation for vector instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205222
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Tom Roeder [Mon, 31 Mar 2014 16:59:13 +0000 (16:59 +0000)]
This patch fixes LTO's RecordStreamer so that it records symbols in the MCExpr
part of an asm .symver directive as being used. This prevents referenced
functions from being internalized and deleted.
Without the patch to LTOModule.cpp, the test case will produce the error:
LLVM ERROR: A @@ version cannot be undefined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205221
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Saleem Abdulrasool [Mon, 31 Mar 2014 16:34:41 +0000 (16:34 +0000)]
Support: generalise object type handling for Windows
This generalises the object file type parsing to all Windows environments. This
is used by cygwin as well as MSVC environments for MCJIT. This also makes the
triple more similar to Chandler's suggestion of a separate field for the object
file format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205219
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Eli Bendersky [Mon, 31 Mar 2014 16:11:57 +0000 (16:11 +0000)]
PR19099 - revert r203483
Now that r205212 was committed, r203483 is no longer necessary; it was a
temporary workaround that only handled a small number of the problematic cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205216
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Christian Pirker [Mon, 31 Mar 2014 16:06:39 +0000 (16:06 +0000)]
ARM: change parameter names of the ELFARMAsmBackend constructor
I removed the underscore at the beginning of the parameter name,
because of a comment from Tim.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205215
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Robert Khasanov [Mon, 31 Mar 2014 16:01:38 +0000 (16:01 +0000)]
Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205214
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Daniel Sanders [Mon, 31 Mar 2014 15:58:58 +0000 (15:58 +0000)]
[mips] Fix use of uninitialized value reported by the sanitizer-x86_64-linux-bootstrap buildbot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205213
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Eli Bendersky [Mon, 31 Mar 2014 15:56:26 +0000 (15:56 +0000)]
Fix for PR19099 - NVPTX produces invalid symbol names.
This is a more thorough fix for the issue than r203483. An IR pass will run
before NVPTX codegen to make sure there are no invalid symbol names that can't
be consumed by the ptxas assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205212
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Tim Northover [Mon, 31 Mar 2014 15:46:46 +0000 (15:46 +0000)]
ARM64: add extra patterns for scalar shifts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205209
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Tim Northover [Mon, 31 Mar 2014 15:46:42 +0000 (15:46 +0000)]
ARM64: add extra scalar neg pattern & tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205208
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Tim Northover [Mon, 31 Mar 2014 15:46:38 +0000 (15:46 +0000)]
ARM64: add patterns for scalar sqdmlal & sqdmlsl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205207
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Tim Northover [Mon, 31 Mar 2014 15:46:34 +0000 (15:46 +0000)]
ARM64: add more patterns for commuted fmsub operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205206
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Tim Northover [Mon, 31 Mar 2014 15:46:30 +0000 (15:46 +0000)]
ARM64: shuffle patterns around for fmin/fmax & add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205205
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Tim Northover [Mon, 31 Mar 2014 15:46:26 +0000 (15:46 +0000)]
ARM64: add more scalar patterns for usqadd & suqadd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205204
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Tim Northover [Mon, 31 Mar 2014 15:46:22 +0000 (15:46 +0000)]
ARM64: add more scalar patterns for reciprocal ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205203
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Tim Northover [Mon, 31 Mar 2014 15:46:17 +0000 (15:46 +0000)]
ARM64: add i64 scalar pattern for @llvm.arm64.abs
This will be used by the Clang front-end code for vabsd_s64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205202
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Daniel Sanders [Mon, 31 Mar 2014 15:15:02 +0000 (15:15 +0000)]
[mips] Implement missing relocations in the integrated assembler.
%got_hi, %got_lo, %call_hi, %call_lo, %higher, and %highest are now recognised
by MipsAsmParser::getVariantKind().
To prevent future issues with missing entries in this StringSwitch, I've added
an assertion to the default case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205200
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Daniel Sanders [Mon, 31 Mar 2014 14:47:41 +0000 (14:47 +0000)]
[mips] Remove R_MIPS_GOT which isn't used and shares the same number as R_MIPS_GOT16
Unlike my previous commit, don't try to remove the corresponding VK_Mips_GOT yet
even though it shares the same assembly text since that is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205196
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Daniel Sanders [Mon, 31 Mar 2014 14:34:36 +0000 (14:34 +0000)]
Revert r205194 - [mips] Removed R_MIPS_GOT. It's identical to R_MIPS_GOT16.
There's a couple additional bits I missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205195
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Daniel Sanders [Mon, 31 Mar 2014 14:30:05 +0000 (14:30 +0000)]
[mips] Removed R_MIPS_GOT. It's identical to R_MIPS_GOT16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205194
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Rafael Espindola [Mon, 31 Mar 2014 14:15:07 +0000 (14:15 +0000)]
Capitalize the D in parseDirectiveGpDWord.
DWord seems to be the canonical way to camel case dword in llvm.
Thanks to Daniel Sander for noticing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205191
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Dmitri Gribenko [Mon, 31 Mar 2014 14:14:13 +0000 (14:14 +0000)]
Remove unused private typedef
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205190
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Tom Stellard [Mon, 31 Mar 2014 14:01:56 +0000 (14:01 +0000)]
R600/SI: Implement SIInstrInfo::isTriviallyRematerializable()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205188
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Tom Stellard [Mon, 31 Mar 2014 14:01:55 +0000 (14:01 +0000)]
R600/SI: Lower i64 SELECT by bitcasting to a vector type
This allows allows us to replace ISD::EXTRACT_ELEMENT, which is lowered
using shifts, with ISD::EXTRACT_VECTOR_ELT, which is a no-op.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205187
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Tom Stellard [Mon, 31 Mar 2014 14:01:52 +0000 (14:01 +0000)]
R600/SI: Return the correct index for VGPRs in getHWRegIndex()
The register index is stored in the low 8-bits of the encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205186
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Zoran Jovanovic [Mon, 31 Mar 2014 14:00:10 +0000 (14:00 +0000)]
Fixed issue with microMIPS JAL instruction.
Differential Revision: http://llvm-reviews.chandlerc.com/D3200
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205185
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NAKAMURA Takumi [Mon, 31 Mar 2014 13:30:02 +0000 (13:30 +0000)]
llvm/test/MC/Mips/mips64r2/valid-xfail.s: This REQUIRES asserts. Seems it doesn't fail with -Asserts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205182
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Daniel Sanders [Mon, 31 Mar 2014 12:13:12 +0000 (12:13 +0000)]
[mips] Added a full set of instruction test cases for all ISA's (but not ASE's).
Summary:
Where those ISA's are not currently supported, the test is run with the smallest
superset of that ISA.
Some instructions are valid but don't pass yet. These have been placed in the
valid-xfail.s's which will XPASS if _any_ instruction starts working.
The valid.s's do not verify the encoding yet. There are also no tests checking that instructions from neighbouring ISA's are not accepted.
Reviewers: matheusalmeida
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3214
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205180
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Hal Finkel [Mon, 31 Mar 2014 11:43:19 +0000 (11:43 +0000)]
Look at shuffles of build_vectors in DAGCombiner::visitEXTRACT_VECTOR_ELT
When the loop vectorizer vectorizes code that uses the loop induction variable,
we often end up with IR like this:
%b1 = insertelement <2 x i32> undef, i32 %v, i32 0
%b2 = shufflevector <2 x i32> %b1, <2 x i32> undef, <2 x i32> zeroinitializer
%i = add <2 x i32> %b2, <i32 2, i32 3>
If the add in this example is not legal (as is the case on PPC with VSX), it
will be scalarized, and we'll end up with a number of extract_vector_elt nodes
with the vector shuffle as the input operand, and that vector shuffle is fed by
one or more build_vector nodes. By the time that vector operations are
expanded, visitEXTRACT_VECTOR_ELT will not create new extract_vector_elt by
looking through the vector shuffle (to make sure that no illegal operations are
created), and so the extract_vector_elt -> vector shuffle -> build_vector is
never simplified to an operand of the build vector.
By looking at build_vectors through a shuffle we fix this particular situation,
preventing a vector from being built, only to be deconstructed again (for the
scalarized add) -- an expensive proposition when this all needs to be done via
the stack. We probably want a more comprehensive fix here where we look back
recursively through any shuffles to any build_vectors or scalar_to_vectors,
etc. but that can come later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205179
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Daniel Sanders [Mon, 31 Mar 2014 11:00:04 +0000 (11:00 +0000)]
[mips] Check emitted code for llvm.bswap.i32 on MIPS16/MIPS64 and llvm.bswap.i64 on MIPS16.
While reviewing r204163, I noticed that the MIPS16 test only checked for a .ent
directive and didn't actually check the code emitted. Fixed this and added a
check for llvm.bswap.i32 on MIPS64 at the same time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205177
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Tim Northover [Mon, 31 Mar 2014 10:21:36 +0000 (10:21 +0000)]
ARM64: fix a couple of signed/unsigned comparison warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205174
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Daniel Sanders [Mon, 31 Mar 2014 09:44:05 +0000 (09:44 +0000)]
[yaml2obj] Add support for ELF e_flags.
Summary:
The FileHeader mapping now accepts an optional Flags sequence that accepts
the EF_<arch>_<flag> constants. When not given, Flags defaults to zero.
Reviewers: atanasyan
Reviewed By: atanasyan
CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D3213
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205173
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Alexey Samsonov [Mon, 31 Mar 2014 07:59:33 +0000 (07:59 +0000)]
Try to fix MSan bootstrap bot: make ARM64Disassembler::getInstruction() always initialize Size argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205171
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Yaron Keren [Mon, 31 Mar 2014 07:59:14 +0000 (07:59 +0000)]
Correct OS conditionals following r204977 and r204978.
Previously, MinGW OS was Triple::MinGW and Cygwin was Triple::Cygwin
and now it is Triple::Win32 with Environment being GNU or Cygwin.
So,
TheTriple.getOS() == Triple::Win32
is replaced by
TheTriple.isWindowsMSVCEnvironment()
and
(TheTriple.getOS() == Triple::MinGW32 || TheTriple.getOS() == Triple::Cygwin)
is replaced by
TheTriple.isOSCygMing()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205170
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Craig Topper [Mon, 31 Mar 2014 06:53:13 +0000 (06:53 +0000)]
[C++11] Mark more classes in the X86 target as 'final'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205166
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Craig Topper [Mon, 31 Mar 2014 06:22:15 +0000 (06:22 +0000)]
Mark a couple of the X86 target classes as final. Allows the compiler to de-virtualize some internal calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205165
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NAKAMURA Takumi [Mon, 31 Mar 2014 01:10:26 +0000 (01:10 +0000)]
ARM64CollectLOH.cpp: Tweak \param. [-Wdocumentation]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205162
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Chandler Carruth [Mon, 31 Mar 2014 00:02:10 +0000 (00:02 +0000)]
[ARM64] Fix materialization of an fp128 zero immediate. There currently
is not a pattern to lower this with clever instructions that zero the
register, so restrict the zero immediate legality special case to f64
and f32 (the only two sizes which fmov seems to directly support). Fixes
backend errors when building code such as libxml.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205161
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Adam Nemet [Sun, 30 Mar 2014 18:07:13 +0000 (18:07 +0000)]
[X86] Adjust cost of FP_TO_UINT v8f32->v8i32
There is no direct AVX instruction to convert to unsigned. I have some ideas
how we may be able to do this with three vector instructions but the current
backend just bails on this to get it scalarized.
See the comment why we need to adjust the cost returned by BasicTTI.
The test is a bit roundabout (and checks assembly rather than bit code) because
I'd like it to work even if at some point we could vectorize this conversion.
Fixes <rdar://problem/
16371920>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205159
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Stepan Dyatkovskiy [Sun, 30 Mar 2014 17:09:54 +0000 (17:09 +0000)]
PR18929:
According to ARM assembler language hash symbol is optional before immediates.
For example, see here for more details:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0473j/dom1359731154529.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205157
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Hal Finkel [Sun, 30 Mar 2014 15:10:18 +0000 (15:10 +0000)]
Make use of previously generated stores in SelectionDAGLegalize::ExpandExtractFromVectorThroughStack
When expanding EXTRACT_VECTOR_ELT and EXTRACT_SUBVECTOR using
SelectionDAGLegalize::ExpandExtractFromVectorThroughStack, we store the entire
vector and then load the piece we want. This is fine in isolation, but
generating a new store (and corresponding stack slot) for each extraction ends
up producing code of poor quality. When we scalarize a vector operation (using
SelectionDAG::UnrollVectorOp for example) we generate one EXTRACT_VECTOR_ELT
for each element in the vector. This used to generate one stored copy of the
vector for each element in the vector. Now we search the uses of the vector for
a suitable store before generating a new one, which results in much more
efficient scalarization code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205153
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NAKAMURA Takumi [Sun, 30 Mar 2014 14:04:00 +0000 (14:04 +0000)]
llvm/test/MC/ELF/nocompression.s: Loosen an expression to match "llvm-mc.EXE".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205148
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Hal Finkel [Sun, 30 Mar 2014 13:22:59 +0000 (13:22 +0000)]
[PowerPC] Handle VSX v2i64 SIGN_EXTEND_INREG
sitofp from v2i32 to v2f64 ends up generating a SIGN_EXTEND_INREG v2i64 node
(and similarly for v2i16 and v2i8). Even though there are no sign-extension (or
algebraic shifts) for v2i64 types, we can handle v2i32 sign extensions by
converting two and from v2i64. The small trick necessary here is to shift the
i32 elements into the right lanes before the i32 -> f64 step. This is because
of the big Endian nature of the system, we need the i32 portion in the high
word of the i64 elements.
For v2i16 and v2i8 we can do the same, but we first use the default Altivec
shift-based expansion from v2i16 or v2i8 to v2i32 (by casting to v4i32) and
then apply the above procedure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205146
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Chandler Carruth [Sun, 30 Mar 2014 12:07:07 +0000 (12:07 +0000)]
[Allocator] Lift the slab size and size threshold into template
parameters rather than runtime parameters.
There is only one user of these parameters and they are compile time for
that user. Making these compile time seems to better reflect their
intended usage as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205143
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Chandler Carruth [Sun, 30 Mar 2014 11:36:32 +0000 (11:36 +0000)]
[Allocator] Simplify unittests by using the default size parameters in
more places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205141
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Chandler Carruth [Sun, 30 Mar 2014 11:36:29 +0000 (11:36 +0000)]
[Allocator] Stop forward-declaring BumpPtrAllocator in a few places.
This is a necessary step to lifting some of its configuration into
template parameters rather than runtime parameters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205140
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Chandler Carruth [Sun, 30 Mar 2014 11:20:25 +0000 (11:20 +0000)]
Don't mark the declarations of the TSan annotation functions as weak.
That causes references to them to be weak references which can collapse
to null if no definition is provided. We call these functions
unconditionally, so a definition *must* be provided. Make the
definitions provided in the .cpp file weak by re-declaring them as weak
just prior to defining them. This should keep compilers which cannot
attach the weak attribute to the definition happy while actually
resolving the symbols correctly during the link.
You might ask yourself upon reading this commit log: how did *any* of
this work before? Well, fun story. It turns out we have some code in
Support (BumpPtrAllocator) which both uses virtual dispatch and has
out-of-line vtables used by that virtual dispatch. If you move the
virtual dispatch into its header in *just* the right way, the optimizer
gets to devirtualize, and remove all references to the vtable. Then the
sad part: the references to this one vtable were the only strong symbol
uses in the support library for llvm-tblgen AFAICT. At least, after
doing something just like this, these symbols stopped getting their weak
definition and random calls to them would segfault instead.
Yay software.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205137
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Chandler Carruth [Sun, 30 Mar 2014 09:08:07 +0000 (09:08 +0000)]
[ARM64] Fix a heap-use-after-free spotted by ASan.
StringRef::lower() returns a std::string. Better yet, we can now stop
thinking about what it returns and write 'auto'. It does the right
thing. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205135
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Tim Northover [Sun, 30 Mar 2014 08:30:28 +0000 (08:30 +0000)]
ARM64: uncopy/paste helper function
It was doing functional but highly suspect operations on bools due to
the more limited shifting operands supported by memory instructions.
Should fix some MSVC warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205134
91177308-0d34-0410-b5e6-
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Tim Northover [Sun, 30 Mar 2014 07:35:48 +0000 (07:35 +0000)]
ARM64: remove unused variables
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205133
91177308-0d34-0410-b5e6-
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Tim Northover [Sun, 30 Mar 2014 07:25:23 +0000 (07:25 +0000)]
ARM64: remove -m32/-m64 mapping with ARM.
This is causing the ARM build-bots to fail since they only include
the ARM backend and can't create an ARM64 target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205132
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Tim Northover [Sun, 30 Mar 2014 07:25:18 +0000 (07:25 +0000)]
ARM64: override all the things.
Actually, mostly only those in the top-level directory that already
had a "virtual" attached. But it's the thought that counts and it's
been a long day.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205131
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Saleem Abdulrasool [Sun, 30 Mar 2014 07:19:31 +0000 (07:19 +0000)]
Support: correct Windows normalisation
If the environment is unknown and no object file is provided, then assume an
"MSVC" environment, otherwise, set the environment to the object file format.
In the case that we have a known environment but a non-native file format for
Windows (COFF) which is used for MCJIT, then append the custom file format to
the triple as an additional component.
This fixes the MCJIT tests on Windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205130
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NAKAMURA Takumi [Sun, 30 Mar 2014 05:01:17 +0000 (05:01 +0000)]
Suppress llvm/test/CodeGen/ARM64 for targeting pecoff. ARM64 is unaware of that.
FIXME: Could we support them?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205126
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NAKAMURA Takumi [Sun, 30 Mar 2014 05:01:04 +0000 (05:01 +0000)]
llvm/test/Transforms/LoopStrengthReduce/ARM64/lsr-*.ll: Add explicit triple arm64-unknown for targeting pecoff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205125
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NAKAMURA Takumi [Sun, 30 Mar 2014 04:35:00 +0000 (04:35 +0000)]
X86Subtarget.h: isTargetWindows() should tell whether he is targeting msvc.
FYI, !isWindowsGNUEnvironment() is insufficient. It missed cygwin.
FIXME: The name "isTargetWindows" should be fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205124
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Lang Hames [Sun, 30 Mar 2014 04:27:33 +0000 (04:27 +0000)]
[MC] Remove an unused (and broken) variant of the setupForSymbolicDisassembly
method in MCDisassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205123
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Lang Hames [Sun, 30 Mar 2014 03:47:00 +0000 (03:47 +0000)]
[PBQP] Move invalid graph nodeId/edgeId methods into base class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205122
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Rafael Espindola [Sun, 30 Mar 2014 03:26:17 +0000 (03:26 +0000)]
Add a missing break.
Patch by Tobias Güntner.
I tried to write a test, but the only difference is the Changed value that
gets returned. It can be tested with "opt -debug-pass=Executions -functionattrs,
but that doesn't seem worth it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205121
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Saleem Abdulrasool [Sun, 30 Mar 2014 03:22:37 +0000 (03:22 +0000)]
Support: normalize the default triple on Unix
This will fix cross-compiling buildbots (e.g. cygwin). This is in the same vein
as SVN r205070. Apply this to fix the cross-compiling scenario, even though the
preferred solution is to update the build system to normalize the embedded
triple rather than perform this at runtime every time. This is meant to tide us
over until that approach is fleshed out and applied.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205120
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Rafael Espindola [Sun, 30 Mar 2014 02:33:01 +0000 (02:33 +0000)]
Remove dead declarations.
Patch by Tobias Güntner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205119
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Benjamin Kramer [Sat, 29 Mar 2014 20:16:23 +0000 (20:16 +0000)]
Remove outdated comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205117
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Dmitri Gribenko [Sat, 29 Mar 2014 19:40:32 +0000 (19:40 +0000)]
Fix a few -Wdocumentation warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205116
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Benjamin Kramer [Sat, 29 Mar 2014 19:21:20 +0000 (19:21 +0000)]
Detemplatize LOHDirective.
The ARM64 backend uses it only as a container to keep an MCLOHType and
Arguments around so give it its own little copy. The other functionality
isn't used and we had a crazy method specialization hack in place to
keep it working. Unfortunately that was incompatible with MSVC.
Also range-ify a couple of loops while at it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205114
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Benjamin Kramer [Sat, 29 Mar 2014 18:00:49 +0000 (18:00 +0000)]
ARM64: Remove unused helper function, make others static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205112
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Benjamin Kramer [Sat, 29 Mar 2014 17:17:15 +0000 (17:17 +0000)]
tblgen: Twinify PrintFatalError.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205110
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Tim Northover [Sat, 29 Mar 2014 16:59:27 +0000 (16:59 +0000)]
TableGen: don't save a StringRef to a local std::string.
This caused a failure in some Windows builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205109
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Benjamin Kramer [Sat, 29 Mar 2014 16:54:29 +0000 (16:54 +0000)]
Avoid storing Twines.
While there nested ifs into a helper function. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205108
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Hal Finkel [Sat, 29 Mar 2014 16:04:40 +0000 (16:04 +0000)]
[PowerPC] Handle v2i64 comparisons
v2i64 is a legal type under VSX, however we don't have native vector
comparisons. We can handle eq/ne by casting it to an Altivec type, but
everything else must be expanded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205106
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Tim Northover [Sat, 29 Mar 2014 15:35:57 +0000 (15:35 +0000)]
ARM64: format register strings without creating a local Twine.
It was causing horrible failures on some build-bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205105
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Logan Chien [Sat, 29 Mar 2014 15:10:22 +0000 (15:10 +0000)]
llvm-mc: Fix build breakage caused by r205050.
When LLVM is not built with zlib, nocompression.s will test
for the error message. But this test case will cause breakage
because the exit code is non-zero. This commit fix this issue
by adding "not" to the command.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205102
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Hal Finkel [Sat, 29 Mar 2014 13:20:31 +0000 (13:20 +0000)]
[PowerPC] VSX instruction latency corrections
The vector divide and sqrt instructions have high latencies, and the scalar
comparisons are like all of the others. On the P7, permutations take an extra
cycle over purely-simple vector ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205096
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Stepan Dyatkovskiy [Sat, 29 Mar 2014 13:12:40 +0000 (13:12 +0000)]
Recommitted fix for PR18931, with extended tests set.
Issue subject: Crash using integrated assembler with immediate arithmetic
Fix description:
Expressions like 'cmp r0, #(l1 - l2) >> 3' could not be evaluated on asm parsing stage,
since it is impossible to resolve labels on this stage. In the end of stage we still have
expression (MCExpr).
Then, when we want to encode it, we expect it to be an immediate, but it still an expression.
Patch introduces a Fixup (MCFixup instance), that is processed after main encoding stage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205094
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Tim Northover [Sat, 29 Mar 2014 11:51:49 +0000 (11:51 +0000)]
ARM64: use 64-bit constant even on 32-bit machines
Another existing bot failure so no tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205093
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Tim Northover [Sat, 29 Mar 2014 11:47:07 +0000 (11:47 +0000)]
ARM64: change format specifier to work on 32-bit targets
Existing tests were failing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205092
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Chandler Carruth [Sat, 29 Mar 2014 11:07:40 +0000 (11:07 +0000)]
[ARM64] Fix 'assert("...")' to be 'assert(0 && "...")'. Otherwise, it is
no assert at all. ;] Some of these should probably be switched to
llvm_unreachable, but I didn't want to perturb the behavior in this
patch.
Found by -Wstring-conversion, which I'll try to turn on in CMake builds
at least as it is finding useful things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205091
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Tim Northover [Sat, 29 Mar 2014 10:18:08 +0000 (10:18 +0000)]
ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.
Everything will be easier with the target in-tree though, hence this
commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090
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Tim Northover [Sat, 29 Mar 2014 09:03:22 +0000 (09:03 +0000)]
TableGen: avoid dereferencing nullptr variable
ARM64 ended up reaching odder parts of TableGen alias generation than
current backends and caused a segfault.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205089
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Tim Northover [Sat, 29 Mar 2014 09:03:18 +0000 (09:03 +0000)]
CodeGen: add sensible defaults for the ISD::FROUND operation
Some exotic types didn't know how to handle FROUND, which ARM64 uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205088
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Tim Northover [Sat, 29 Mar 2014 09:03:13 +0000 (09:03 +0000)]
MC-exceptions: add support for compact-unwind without .eh_frame
ARM64 has compact-unwind information, but doesn't necessarily want to
emit .eh_frame directives as well. This teaches MC about such a
situation so that it will skip .eh_frame info when compact unwind has
been successfully produced.
For functions incompatible with compact unwind, the normal information
is still written.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205087
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Tim Northover [Sat, 29 Mar 2014 08:22:29 +0000 (08:22 +0000)]
CodeGenPrep: wrangle IR to exploit AArch64 tbz/tbnz inst.
Given IR like:
%bit = and %val, #imm-with-1-bit-set
%tst = icmp %bit, 0
br i1 %tst, label %true, label %false
some targets can emit just a single instruction (tbz/tbnz in the
AArch64 case). However, with ISel acting at the basic-block level, all
three instructions need to be together for this to be possible.
This adds another transformation to CodeGenPrep to expose these
opportunities, if targets opt in via the hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205086
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Tim Northover [Sat, 29 Mar 2014 08:22:20 +0000 (08:22 +0000)]
MC: add a RefKind field to MCValue
This is principally to allow neater mapping of fixups to relocations
in ARM64 ELF. Without this, there isn't enough information available
to GetRelocType, leading to many more fixup_arm64_... enumerators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205085
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Tim Northover [Sat, 29 Mar 2014 07:34:53 +0000 (07:34 +0000)]
MachO: Add linker-optimisation hint framework to MC.
Another part of the ARM64 backend (so tests will be following soon).
This is currently used by the linker to relax adrp/ldr pairs into nops
where possible, though could well be more broadly applicable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205084
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Tim Northover [Sat, 29 Mar 2014 07:33:24 +0000 (07:33 +0000)]
MachO: actually set linker-private prefix at MC level.
This was accidentally omitted from r205081.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205083
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Tim Northover [Sat, 29 Mar 2014 07:05:06 +0000 (07:05 +0000)]
MachO: allow each section to have a linker-private symbol
The upcoming ARM64 backend doesn't have section-relative relocations,
so we give each section its own symbol to provide this functionality.
Of course, it doesn't need to appear in the final executable, so
linker-private is the best kind for this purpose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205081
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Tim Northover [Sat, 29 Mar 2014 07:04:59 +0000 (07:04 +0000)]
Make GetCPISymbol a virtual method.
ARM64 for iOS is going to want to emit these symbols in a
linker-private style for efficiency, but other targets probably don't
want that behaviour.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205080
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Tim Northover [Sat, 29 Mar 2014 07:04:54 +0000 (07:04 +0000)]
Intrinsics: add LLVMHalfElementsVectorType constraint
This is like the LLVMMatchType, except the verifier checks that the
second argument is a vector with the same base type and half the
number of elements.
This will be used by the ARM64 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205079
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Rafael Espindola [Sat, 29 Mar 2014 06:26:49 +0000 (06:26 +0000)]
Completely rewrite ELFObjectWriter::RecordRelocation.
I started trying to fix a small issue, but this code has seen a small fix too
many.
The old code was fairly convoluted. Some of the issues it had:
* It failed to check if a symbol difference was in the some section when
converting a relocation to pcrel.
* It failed to check if the relocation was already pcrel.
* The pcrel value computation was wrong in some cases (relocation-pc.s)
* It was missing quiet a few cases where it should not convert symbol
relocations to section relocations, leaving the backends to patch it up.
* It would not propagate the fact that it had changed a relocation to pcrel,
requiring a quiet nasty work around in ARM.
* It was missing comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205076
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Hal Finkel [Sat, 29 Mar 2014 05:29:01 +0000 (05:29 +0000)]
[PowerPC] Add subregister classes for f64 VSX values
We had stored both f64 values and v2f64, etc. values in the VSX registers. This
worked, but was suboptimal because we would always spill 16-byte values even
through we almost always had scalar 8-byte values. This resulted in an
increase in stack-size use, extra memory bandwidth, etc. To fix this, I've
added 64-bit subregisters of the Altivec registers, and combined those with the
existing scalar floating-point registers to form a class of VSX scalar
floating-point registers. The ABI code has also been enhanced to use this
register class and some other necessary improvements have been made.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205075
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Saleem Abdulrasool [Sat, 29 Mar 2014 01:08:53 +0000 (01:08 +0000)]
Windows: canonicalise the default windows triple
Canonicalise the default triple that is used on Windows. This should hopefully
fix the MSVC buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205070
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Akira Hatanaka [Fri, 28 Mar 2014 23:28:07 +0000 (23:28 +0000)]
[x86] Fix printing of register operands with q modifier.
Emit 32-bit register names instead of 64-bit register names if the target does
not have 64-bit general purpose registers.
<rdar://problem/
14653996>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205067
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David Blaikie [Fri, 28 Mar 2014 21:48:31 +0000 (21:48 +0000)]
Debug Compression: Avoid compression debug_frame for now
Turns out debug_frame does use multiple fragments, so it doesn't
compress correctly with the current approach. Disable compressing it for
now while I figure out what's the best solution for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205059
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David Majnemer [Fri, 28 Mar 2014 21:40:47 +0000 (21:40 +0000)]
X86: Disable IsLegalToCallImmediateAddr for Win32
WinCOFF cannot form PC relative relocations to support absolute
MCValues. We should reenable this once WinCOFF supports emission of
IMAGE_REL_I386_REL32 relocations.
This fixes PR19272.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205058
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David Blaikie [Fri, 28 Mar 2014 21:00:25 +0000 (21:00 +0000)]
Add missing include (for r205050)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205053
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David Blaikie [Fri, 28 Mar 2014 20:45:24 +0000 (20:45 +0000)]
llvm-mc: error when -compress-debug-sections is requested and zlib is not linked
This is a bit of a stab in the dark, since I have zlib on my machine.
Just going to bounce it off the bots & see if it sticks.
Do we have some convention for negative REQUIRES: checks? Or do I just
need to add a feature like I've done here?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205050
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