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Veerabadhran Gopalakrishnan [Thu, 1 Apr 2021 13:38:39 +0000 (19:08 +0530)]
drm/amdgpu: enabled VCN3.0 CG for BEIGE GOBY
Enable VCN CG for BEIGE GOBY
Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 19 Mar 2021 06:48:28 +0000 (14:48 +0800)]
drm/amdgpu: enable ih CG for beige_goby
Enable ih clock gating for beige_goby.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 19 Mar 2021 06:44:55 +0000 (14:44 +0800)]
drm/amdgpu: enable hdp CG and LS for beige_goby
Enable hdp MGCG and LS for beige_goby.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 19 Mar 2021 06:37:57 +0000 (14:37 +0800)]
drm/amdgpu: enable mc CG and LS for beige_goby
Enable mc CG and LS for beige_goby.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 19 Mar 2021 06:29:28 +0000 (14:29 +0800)]
drm/amdgpu: enable athub/mmhub PG for beige_goby
Enable athub/mmhub power gating for beige_goby.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 19 Mar 2021 06:15:28 +0000 (14:15 +0800)]
drm/amdgpu: support athub cg setting for beige_goby
Enable athub cg for beige_goby.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 19 Mar 2021 06:05:34 +0000 (14:05 +0800)]
drm/amdgpu: enable GFX clock gating for beige_goby
Enable GFX MGCG, CGCG and 3DCG for beige_goby.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Wed, 17 Mar 2021 09:11:53 +0000 (17:11 +0800)]
drm/amd/pm: use macro to get pptable members
Use macro to get the pptable members for different pptable structures.
v2: abstract the table operations especially get the table members
to simplify cover the two different pptable structures.
v3: move pptable operations related structures and functions into ppt.c
v4: use macro to simplify the operation to get pptable members
v5: fix parameter reference error and add dump pptable support for
beige_goby
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Evan Quan <Evan.Quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Wed, 17 Mar 2021 09:08:07 +0000 (17:08 +0800)]
drm/amd/pm: update smu11 driver interface header for beige_goby
Use new struct name to identify beige_goby pptable
due to extra added fields.
v2: squash in updates (Alex)
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Evan Quan <Evan.Quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Fri, 12 Mar 2021 03:26:58 +0000 (11:26 +0800)]
drm/amd/pm: add mode1 support for beige_goby
Add mode1 reset as the default reset method for beige_goby
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Tue, 16 Mar 2021 02:42:34 +0000 (10:42 +0800)]
drm/amd/amdgpu: update golden_setting_10_3_5 for beige_goby
add mmCGTT_SPI_{RA0/RA1}_CLK_CTRL setting
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Veerabadhran Gopalakrishnan [Wed, 10 Mar 2021 19:39:11 +0000 (01:09 +0530)]
drm/amdgpu: Enable VCN for Beige Goby
Enabled VCN support for Beige Goby chip
Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sat, 6 Mar 2021 14:31:42 +0000 (22:31 +0800)]
drm/amdgpu: add gc_10_3_5 golden setting for beige_goby
execute gc_10_3_5 golden registers one-time initialization
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 16 Dec 2020 15:17:20 +0000 (10:17 -0500)]
drm/amdgpu: add mmhub client support for beige goby
For decoding GPUVM page faults.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Tue, 10 Nov 2020 08:02:22 +0000 (16:02 +0800)]
drm/amd/amdgpu: add psp support for beige_goby
add general PSP support for beige_goby
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Tue, 3 Nov 2020 03:37:23 +0000 (11:37 +0800)]
drm/amd/amdgpu: add smu support for beige_goby
Use soft-pptable for beige_goby
v2: fix format
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Wed, 21 Oct 2020 10:18:40 +0000 (18:18 +0800)]
drm/amdkfd: add kfd2kgd funcs for beige_goby kfd support
Add the function pointer.
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Wed, 21 Oct 2020 10:15:36 +0000 (18:15 +0800)]
drm/amdkfd: support beige_goby KFD
Add KFD support for beige_goby
v2: fix asic name typo
v3: squash in updates (Alex)
v4: squash in needs_atomics fix (Alex)
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Wed, 14 Oct 2020 07:51:23 +0000 (15:51 +0800)]
drm/amd/amdgpu: Use IP discovery table for beige goby
Rather than gpu info firmware.
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Tue, 27 Oct 2020 08:59:42 +0000 (16:59 +0800)]
drm/amd/amdgpu: support cp_fw_write_wait for beige_goby
Same as dimgrey_cavefish to support WAIT_REG_MEM packet.
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Tue, 13 Oct 2020 09:43:07 +0000 (17:43 +0800)]
drm/amd/amdgpu: add virtual display support for beige_goby
Add virtual ip block for beige_goby
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Tue, 13 Oct 2020 09:35:21 +0000 (17:35 +0800)]
drm/amd/amdgpu: configure beige_goby gfx according to gfx 10.3's definition
The gfx version of beige_goby is 10.3,
identical to sienna_cichlid,
follow the way of sienna_cichlid
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Tue, 13 Oct 2020 09:08:07 +0000 (17:08 +0800)]
drm/amd/amdgpu: add sdma ip block for beige_goby
Enable sdma block for beige_goby, same as sienna_cichlid
v2: share the same setting of sdma instance num with vangogh
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Suggested-by: Alexander Deucher <Alexander.Deucher@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Tue, 13 Oct 2020 09:04:01 +0000 (17:04 +0800)]
drm/amd/amdgpu: add gfx ip block for beige_goby
Enable gfx block for beige_goby, same as dimgrey_cavefish
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Tue, 13 Oct 2020 08:58:01 +0000 (16:58 +0800)]
drm/amd/amdgpu: add ih ip block for beige_goby
Enable ih block for beige_goby, same as dimgrey_cavefish
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Tue, 13 Oct 2020 08:51:08 +0000 (16:51 +0800)]
drm/amd/amdgpu: add gmc ip block for beige_goby
Enable gmc block for beige_goby, same as sienna_cichlid
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Tue, 13 Oct 2020 08:46:21 +0000 (16:46 +0800)]
drm/amd/amdgpu: add common ip block for beige_goby
Same as dimgrey_cavefish
v2: fix comments typo
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Tue, 13 Oct 2020 08:42:02 +0000 (16:42 +0800)]
drm/amd/amdgpu: add mmhub support for beige_goby
Same as dimgrey_cavefish
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Tue, 13 Oct 2020 08:32:42 +0000 (16:32 +0800)]
drm/amd/amdgpu: initialize IP offset for beige_goby
Add ip offset definition for beige_goby and initialize it
v2: squash in fixes (Alex)
V3: fix permissions on file (Alex)
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Tue, 13 Oct 2020 08:09:55 +0000 (16:09 +0800)]
drm/amd/amdgpu: add common support for beige_goby
Add external id and set clock gating for beige_goby
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Tue, 13 Oct 2020 07:46:16 +0000 (15:46 +0800)]
drm/amd/amdgpu: add gmc support for beige_goby
Same as dimgrey_cavefish
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Tue, 13 Oct 2020 06:48:37 +0000 (14:48 +0800)]
drm/amd/amdgpu: add support for beige_goby firmware
Add support for beige_goby cp/rlc firmware
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Tue, 13 Oct 2020 06:42:25 +0000 (14:42 +0800)]
drm/amd/amdgpu: set asic family and ip blocks for beige_goby
Same as navi series
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Tue, 13 Oct 2020 06:38:49 +0000 (14:38 +0800)]
drm/amd/amdgpu: set fw load type for beige_goby
Use direct load for beige_goby
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Tue, 13 Oct 2020 06:30:32 +0000 (14:30 +0800)]
drm/amd/amdgpu: add beige_goby asic type
Add chip type for beige_goby
v2: fix enum count (Alex)
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Sun, 9 May 2021 19:17:58 +0000 (15:17 -0400)]
drm/amd/display: 3.2.136
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Sun, 9 May 2021 01:09:49 +0000 (21:09 -0400)]
drm/amd/display: [FW Promotion] Release 0.0.66
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wyatt Wood [Thu, 6 May 2021 20:11:16 +0000 (16:11 -0400)]
drm/amd/display: Refactor and add visual confirm for HW Flip Queue
[Why]
Visual confirm will indicate if driver is programming
the surface address.
Refactor is required because much of the visual confirm
logic is buried deep in the mpcc files.
In addition, visual confirm is not updated during fast updates.
[How]
In order to have visual confirm for driver flips, visual confirm
needs to be updated on every frame, including fast updates.
Add a new hw sequencer interface update_visual_confirm_color,
and a new mpc function pointer set_bg_color.
v2: drop unused variable (Alex)
Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nikola Cornij [Fri, 7 May 2021 02:46:52 +0000 (22:46 -0400)]
drm/amd/display: Use the correct max downscaling value for DCN3.x family
[why]
As per spec, DCN3.x can do 6:1 downscaling and DCN2.x can do 4:1. The
max downscaling limit value for DCN2.x is 250, which means it's
calculated as 1000 / 4 = 250. For DCN3.x this then gives 1000 / 6 = 167.
[how]
Set maximum downscaling limit to 167 for DCN3.x
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wayne Lin [Wed, 28 Apr 2021 10:04:44 +0000 (18:04 +0800)]
drm/amd/display: Avoid get/put vblank when stream disabled
[Why]
amdgpu_dm_crtc_set_crc_source() will call
amdgpu_dm_crtc_configure_crc_source() to enable/disable CRC
generation. However, configuration will be deferred to stream enabled.
If stream is not enabled, current flow will still try to get/put vblank
refcount.
[How]
Return EINVAL to skip actions on vblank refcount when stream is not
enabled.
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Reviewed-by: Chao-kai Wang <Stylon.Wang@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Zhan Liu [Wed, 5 May 2021 21:44:46 +0000 (17:44 -0400)]
drm/amd/display: Correct DPCD revision for eDP v1.4
[Why]
eDP version and DPCD revision are different. Per VESA
spec, "The DPCD revision for eDP v1.4 is 13h".
SUPPORTED_LINK_RATES is valid since eDP v1.4 (DPCD_REV_13).
[How]
Correct DPCD_REV for eDP v1.4.
Signed-off-by: Zhan Liu <zhan.liu@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 29 Apr 2021 20:32:47 +0000 (16:32 -0400)]
drm/amd/display: Add Overflow check to skip MALL
[Why]
In some small modes (<200pixels) the stutter period is really big and will cause
overflow. In these cases we shouldnt try to enable MALL as it will exceeds range
of hysteresis timer (this can be seen in some IGT tests where the
plane size is small)
[How]
Compare the stutter_period with the frame time and if we will overflow
there is no point in trying to enable MALL (and see the ASSERT) so we
early exist in this case
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wayne Lin [Tue, 27 Apr 2021 04:00:40 +0000 (12:00 +0800)]
drm/amd/display: Refactor suspend/resume of Secure display
[Why]
Once set ROI and do suspend/resume, current flow will not enable
OTG_CRC_CTL again due to we'll defer crc configuration when stream
is enabled.
[How]
Remove current suspend/resume function and have logic implemented into
amdgpu_dm_atomic_commit_tail()
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Reviewed-by: Chao-kai Wang <Stylon.Wang@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wenjing Liu [Mon, 3 May 2021 22:42:28 +0000 (18:42 -0400)]
drm/amd/display: consider channel coding in configure lttpr mode
[why]
Some lttpr configuration steps are exclusive to 8b/10b channel
coding mode. We need to take channel conding into account.
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Acked-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wenjing Liu [Mon, 3 May 2021 21:32:05 +0000 (17:32 -0400)]
drm/amd/display: rename perform_link_training_int function
[why]
The function's name doesn't represent what it actaully does.
The function implements necessary steps for our hardware to
transition from link training mode back to video idle mode.
Therefore, rename the function as dp_transition_to_video_idle
so everyone can understand it.
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wenjing Liu [Mon, 3 May 2021 21:05:40 +0000 (17:05 -0400)]
drm/amd/display: decide link training settings based on channel coding
[how]
Rename initialize_training_settings to decide_training_settings.
Call get link encoding format and decide training settings
based on current channel coding.
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wenjing Liu [Mon, 3 May 2021 18:51:27 +0000 (14:51 -0400)]
drm/amd/display: determine dp link encoding format from link settings
[how]
Implement a function that determines link encoding format
based on the link settings passed in.
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chris Park [Tue, 4 May 2021 20:20:55 +0000 (16:20 -0400)]
drm/amd/display: Disconnect non-DP with no EDID
[Why]
Active DP dongles return no EDID when dongle
is connected, but VGA display is taken out.
Current driver behavior does not remove the
active display when this happens, and this is
a gap between dongle DTP and dongle behavior.
[How]
For active DP dongles and non-DP scenario,
disconnect sink on detection when no EDID
is read due to timeout.
Signed-off-by: Chris Park <Chris.Park@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
George Shen [Tue, 4 May 2021 19:31:37 +0000 (15:31 -0400)]
drm/amd/display: Minor refactor of DP PHY test automation
[Why]
Improve readability and maintainability of code.
[How]
Refactor test pattern size calculation out of function
call parameter and store value in variable.
Signed-off-by: George Shen <george.shen@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rodrigo Siqueira [Tue, 4 May 2021 14:09:25 +0000 (10:09 -0400)]
drm/amd/display: Document set RECOUT operation
During the investigation on how to add visual confirmation on top of the
planes used by DCN, it becomes evident that the lack of information in
the code makes this work unnecessarily complicated. This commit
introduces a set of documentation related to the RECOUT operation in
order to make it easy for developers to navigate this set of functions.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rodrigo Siqueira [Thu, 15 Apr 2021 14:22:03 +0000 (10:22 -0400)]
drm/amd/display: Add kernel-doc to some hubp functions
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rodrigo Siqueira [Thu, 15 Apr 2021 13:57:19 +0000 (09:57 -0400)]
drm/amd/display: Remove legacy comments
To improve the code readability, this commit removes a set of commented
and not used functions for a long time. Notice that now we have the
amdgpu_dm_dtn_log, which prints all the relevant information that we
need.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rodrigo Siqueira [Thu, 15 Apr 2021 13:32:57 +0000 (09:32 -0400)]
drm/amd/display: Add documentation for power gate plane
This commit introduces kernel documentation to some essential functions
related to power gate control over planes. It also adds a macro to make
one part of the code easy to understand.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wyatt Wood [Tue, 19 Jan 2021 22:05:05 +0000 (17:05 -0500)]
drm/amd/display: Add get_current_time interface to dmub_srv
[Why]
Need to get current DMUB time.
[How]
Add get_current_time interface to dmub_srv.
v2: drop whitespace changes (Alex)
Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hugo Hu [Wed, 21 Apr 2021 06:23:44 +0000 (14:23 +0800)]
drm/amd/display: treat memory as a single-channel for asymmetric memory V3
Previous patch caused crash and had been reverted. This patch
addresses the issue without regression.
[Why]
1. Driver use umachannelnumber to calculate watermarks for stutter.
In asymmetric memory config, the actual bandwidth is less than
dual-channel. The bandwidth should be the same as single-channel.
2. We found single rank dimm need additional delay time for stutter.
[How]
Get information from each DIMM. Treat memory config as a single-channel
for asymmetric memory in bandwidth calculating.
Add additional delay time for single rank dimm.
Signed-off-by: Hugo Hu <hugo.hu@amd.com>
Reviewed-by: Sung Lee <Sung.Lee@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lijo Lazar [Thu, 13 May 2021 08:21:23 +0000 (16:21 +0800)]
drm/amd/pm: Reset max GFX clock after disabling determinism
When determinism mode is disabled on aldebaran, max GFX clock will
be reset to default max frequency value.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lijo Lazar [Thu, 13 May 2021 07:51:18 +0000 (15:51 +0800)]
drm/amd/pm: Fix showing incorrect frequencies on aldebaran
v1: Use the current and custom pstate frequencies to track the current and
user-set min/max values in manual and determinism mode. Previously, only
actual_* value was used to track the currrent and user requested value.
The value will get reassigned whenever user requests a new value with
pp_od_clk_voltage node. Hence it will show incorrect values when user
requests an invalid value or tries a partial request without committing
the values. Separating out to custom and current variable fixes such
issues.
v2: Remove redundant if-else check
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lijo Lazar [Thu, 13 May 2021 06:42:17 +0000 (14:42 +0800)]
drm/amd/pm: Add custom/current freq to pstates
Add custom member for user requested custom frequency, level mask
or min/max frequencies. Add curr member to keep track of the current
active values.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Clements [Mon, 17 May 2021 08:36:26 +0000 (16:36 +0800)]
drm/amdgpu: Conditionally reset RAS counters on boot
Only clear RAS error counters if perestent EDC harvesting is not supported
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Changfeng [Fri, 14 May 2021 07:28:25 +0000 (15:28 +0800)]
drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid compute hang
There is problem with 3DCGCG firmware and it will cause compute test
hang on picasso/raven1. It needs to disable 3DCGCG in driver to avoid
compute hang.
Signed-off-by: Changfeng <Changfeng.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Peng Ju Zhou [Wed, 28 Apr 2021 08:22:27 +0000 (16:22 +0800)]
drm/amdgpu: Refine the error report when flush tlb.
there are 2 hubs to flush in the gmc, to make it easier
to debug when hub flush failed, refine the logs.
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Peng Ju Zhou [Fri, 23 Apr 2021 05:36:18 +0000 (13:36 +0800)]
drm/amdgpu: Skip the program of GRBM_CAM* in SRIOV
KMD should not the program these registers,
so skip them in the SRIOV environment.
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yi Li [Fri, 14 May 2021 06:40:39 +0000 (14:40 +0800)]
drm/amdgpu: Fix GPU TLB update error when PAGE_SIZE > AMDGPU_PAGE_SIZE
When PAGE_SIZE is larger than AMDGPU_PAGE_SIZE, the number of GPU TLB
entries which need to update in amdgpu_map_buffer() should be multiplied
by AMDGPU_GPU_PAGES_IN_CPU_PAGE (PAGE_SIZE / AMDGPU_PAGE_SIZE).
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Yi Li <liyi@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Philip Yang [Thu, 13 May 2021 16:30:48 +0000 (12:30 -0400)]
drm/amdkfd: heavy-weight flush TLB after unmap
Need do a heavy-weight TLB flush to make sure we have no more dirty data
in the cache for the unmapped pages.
Define enum TLB_FLUSH_TYPE, add flush_type parameter to
amdgpu_amdkfd_flush_gpu_tlb_pasid.
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Philip Yang [Thu, 13 May 2021 16:16:01 +0000 (12:16 -0400)]
Revert "drm/amdkfd: flush TLB after updating GPU page table"
This reverts commit
1704ac8e439e3dcf97431e268bd64fde1874d807.
After "drm/amdgpu: flush TLB if valid PDE turns into PTE" is checked
in, this workaround is not needed.
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiawei Gu [Thu, 13 May 2021 06:17:58 +0000 (14:17 +0800)]
drm/amdgpu: Fill adev->unique_id with data from PF2VF msg
Initialize unique_id from PF2VF under virtualization.
V2: skip smu_get_unique_id() under virtualization
Signed-off-by: Jiawei Gu <Jiawei.Gu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Philip Yang [Wed, 12 May 2021 12:02:46 +0000 (08:02 -0400)]
drm/amdgpu: flush TLB if valid PDE turns into PTE
Mapping huge page, 2MB aligned address with 2MB size, uses PDE0 as PTE.
If previously valid PDE0, PDE0.V=1 and PDE0.P=0 turns into PTE, this
requires TLB flush, otherwise page table walker will not read updated
PDE0.
Change page table update mapping to return table_freed flag to indicate
the previously valid PDE may have turned into a PTE if page table is
freed.
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 12 May 2021 08:36:43 +0000 (10:36 +0200)]
drm/radeon: use the dummy page for GART if needed
Imported BOs don't have a pagelist any more.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Fixes:
0575ff3d33cd ("drm/radeon: stop using pages with drm_prime_sg_to_page_addr_arrays v2")
Christian König [Tue, 27 Apr 2021 09:40:40 +0000 (11:40 +0200)]
drm/amdgpu: move struct amdgpu_vram_reservation into vram mgr
Not used outside of that file.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Tested-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 27 Apr 2021 09:36:10 +0000 (11:36 +0200)]
drm/amdgpu: check contiguous flags instead of mm_node
Drop the last user of drm_mm_node.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Tested-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 27 Apr 2021 09:17:59 +0000 (11:17 +0200)]
drm/amdgpu: set the contiguous flag if possible
This avoids reallocating scanout BOs on first pin in a lot of cases.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Tested-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 27 Apr 2021 08:29:10 +0000 (10:29 +0200)]
drm/amdgpu: use cursor functions in amdgpu_bo_in_cpu_visible_vram
One of the last remaining uses of drm_mm_node.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Tested-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 22 Mar 2021 12:33:05 +0000 (13:33 +0100)]
drm/amdgpu: re-apply "use the new cursor in the VM code" v2
Now that we found the underlying problem we can re-apply this patch.
This reverts commit
6b44b667e24cf89603ebdaa31b939c034d425162.
v2: rebase on KFD changes
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Tested-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 13 May 2021 15:55:49 +0000 (23:55 +0800)]
drm/amdgpu: query boot config cap before issue psp cmd
Only send boot_config cmd to ASICs that support dynamic
boot config. Otherwise, the boot_config cmd will fail.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 13 May 2021 15:06:57 +0000 (23:06 +0800)]
drm/amdgpu: add helper function to query dynamic boot config cap
Check firmware flags to determine whether dynmaic
boot config is supported or not.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 13 May 2021 14:17:07 +0000 (22:17 +0800)]
drm/amdgpu: switch to cached fw flags for mem training cap
Check cached firmware_flags to determin whether
two stage mem training is supported or not.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 13 May 2021 14:02:29 +0000 (22:02 +0800)]
drm/amdgpu: switch to cached fw flags for sram ecc cap
Check cached firmware_flags to determine whether
sram ecc is supported or not.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 13 May 2021 13:56:50 +0000 (21:56 +0800)]
drm/amdgpu: switch to cached fw flags for gpu virt cap
Check cached firmware_flags to determine if gpu
virtualization is supported in vbios
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 13 May 2021 13:46:24 +0000 (21:46 +0800)]
drm/amdgpu: add atomfirmware helper function to query fw cap
Fimware capability was changed from 16 bits to 32 bits
for atomfirmware. add helper funciton to query firmware
capability and cache the value at early stage.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bokun Zhang [Thu, 13 May 2021 05:17:54 +0000 (01:17 -0400)]
drm/amdgpu: Complete multimedia bandwidth interface
- Update SRIOV PF2VF header with latest revision
- Extend existing function in amdgpu_virt.c to read MM bandwidth config
from PF2VF message
- Add SRIOV Sienna Cichlid codec array and update the bandwidth with
PF2VF message
v2: squash in removal of unused variable (Alex)
Signed-off-by: Bokun Zhang <bokun.zhang@amd.com>
Reviewed-by: Monk liu <monk.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Mon, 10 May 2021 22:50:11 +0000 (18:50 -0400)]
drm/amdgpu: Albebaran: MTYPE_NC for coarse-grain remote memory
MTYPE UC was used for a specific use case that ended up not being
implemented. Use NC for better performance for coarse-grained memory where
cache coherence during shader execution is not required.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Oak Zeng <Oak.Zeng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Mon, 10 May 2021 22:37:56 +0000 (18:37 -0400)]
drm/amdgpu: Arcturus: MTYPE_NC for coarse-grain remote memory
MTYPE UC was used for a specific use case that ended up not being
implemented. Use NC for better performance for coarse-grained memory where
cache coherence during shader execution is not required.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Oak Zeng <Oak.Zeng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jinzhou Su [Wed, 12 May 2021 01:48:13 +0000 (09:48 +0800)]
drm/amdgpu: Add compile flag for securedisplay
Add compile flag CONFIG_DEBUG_FS to clear the warning:
unused variable 'amdgpu_securedisplay_debugfs_ops'
Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dennis Li [Tue, 11 May 2021 07:35:49 +0000 (15:35 +0800)]
drm/amdkfd: refine the poison data consumption handling
The user applications maybe register the KFD_EVENT_TYPE_HW_EXCEPTION and
KFD_EVENT_TYPE_MEMORY events, driver could notify them when poison data
consumed. Beside that, some applications maybe register SIGBUS signal
hander. These applications will handle poison data by themselves, exit
or re-create context to re-dispatch works.
Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kai-Heng Feng [Fri, 30 Apr 2021 04:56:56 +0000 (12:56 +0800)]
drm/radeon/dpm: Disable sclk switching on Oland when two 4K 60Hz monitors are connected
Screen flickers rapidly when two 4K 60Hz monitors are in use. This issue
doesn't happen when one monitor is 4K 60Hz (pixelclock 594MHz) and
another one is 4K 30Hz (pixelclock 297MHz).
The issue is gone after setting "power_dpm_force_performance_level" to
"high". Following the indication, we found that the issue occurs when
sclk is too low.
So resolve the issue by disabling sclk switching when there are two
monitors requires high pixelclock (> 297MHz).
v2:
- Only apply the fix to Oland.
Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Philip Yang [Wed, 5 May 2021 14:32:27 +0000 (10:32 -0400)]
drm/amdkfd: new range accessible by all GPUs
If xnack is on, new range is created to recover retry vm fault or
created by SVM API calls, set all GPUs have access to the range.
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lijo Lazar [Tue, 11 May 2021 12:20:14 +0000 (20:20 +0800)]
drm/amd/pm: Update aldebaran pmfw interface
Update aldebaran driver-PMFW interface to version 0x07
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roy Sun [Fri, 11 Dec 2020 05:00:03 +0000 (13:00 +0800)]
drm/amd/amdgpu: Cancel the hrtimer in sw_fini
Move the process of cancelling hrtimer to sw_fini
Signed-off-by: Roy Sun <Roy.Sun@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Tue, 11 May 2021 03:00:41 +0000 (11:00 +0800)]
drm/amd/pm: enable ASPM by default
Since ASPM function has been stable, we don't need to add the modprobe
parameter and we can enable ASPM by default.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Fri, 7 May 2021 05:56:46 +0000 (13:56 +0800)]
drm/amdgpu: update the method for harvest IP for specific SKU
Update the method of disabling VCN IP for specific SKU for navi1x ASIC,
it will judge whether should add the related IP at the function of
amdgpu_device_ip_block_add().
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun GAO [Thu, 29 Apr 2021 06:08:13 +0000 (14:08 +0800)]
drm/amdgpu: add judgement when add ip blocks (v2)
Judgement whether to add an sw ip according to the harvest info.
v2: fix indentation (Alex)
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dennis Li [Sat, 8 May 2021 09:10:24 +0000 (17:10 +0800)]
drm/amdgpu: add synchronization among waves in the same threadgroup
It is possible that the previous waves have exited before others are
created, so the other waves maybe reuse pyhsical resouces left by
previous ones. Therefore add barrier instruction to synchronize waves within
the same threadgroup.
Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 23 Apr 2021 20:43:18 +0000 (16:43 -0400)]
drm/amdgpu/display: fix dal_allocation documentation
Add missing structure elements.
Fixes:
0dd79532340568 ("drm/amdgpu/display: Implement functions to let DC allocate GPU memory")
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 7 May 2021 20:33:28 +0000 (16:33 -0400)]
drm/amdgpu/display: fix build when CONFIG_DRM_AMD_DC_DCN is not defined
Fixes:
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c: In function ‘amdgpu_dm_initialize_drm_device’:
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3726:7: error: implicit declaration of function ‘register_outbox_irq_handlers’; did you mean ‘register_hpd_handlers’? [-Werror=implicit-function-declaration]
3726 | if (register_outbox_irq_handlers(dm->adev)) {
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
| register_hpd_handlers
Fixes:
81927e2808be ("drm/amd/display: Support for DMUB AUX")
Reviewed-by: Jude Shih <shenshih@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Jude Shish <Jude.Shih@amd.com>
Alex Deucher [Fri, 7 May 2021 20:29:33 +0000 (16:29 -0400)]
drm/amdgpu/display: fix warning when CONFIG_DRM_AMD_DC_DCN is not defined
Fixes:
At top level:
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:633:13: warning: ‘dm_dmub_outbox1_low_irq’ defined but not used [-Wunused-function]
633 | static void dm_dmub_outbox1_low_irq(void *interrupt_params)
| ^~~~~~~~~~~~~~~~~~~~~~~
Fixes:
81927e2808be ("drm/amd/display: Support for DMUB AUX")
Reviewed-by: Jude Shih <shenshih@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Jude Shih <Jude.Shih@amd.com>
Alex Deucher [Fri, 7 May 2021 20:16:49 +0000 (16:16 -0400)]
drm/amdgpu/display: remove an old DCN3 guard
The DCN3 guards were dropped a while ago, this one must have
snuck in in a merge or something.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Zhen Lei [Mon, 10 May 2021 12:23:38 +0000 (20:23 +0800)]
drm/amdgpu: Delete two unneeded bool conversions
The result of an expression consisting of a single relational operator is
already of the bool type and does not need to be evaluated explicitly.
No functional change.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Zhen Lei [Mon, 10 May 2021 12:16:21 +0000 (20:16 +0800)]
drm/amd/display: Delete several unneeded bool conversions
The result of an expression consisting of a single relational operator is
already of the bool type and does not need to be evaluated explicitly.
No functional change.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
David Ward [Mon, 10 May 2021 09:30:39 +0000 (05:30 -0400)]
drm/amd/display: Initialize attribute for hdcp_srm sysfs file
It is stored in dynamically allocated memory, so sysfs_bin_attr_init() must
be called to initialize it. (Note: "initialization" only sets the .attr.key
member in this struct; it does not change the value of any other members.)
Otherwise, when CONFIG_DEBUG_LOCK_ALLOC=y this message appears during boot:
BUG: key
ffff9248900cd148 has not been registered!
Fixes:
9037246bb2da ("drm/amd/display: Add sysfs interface for set/get srm")
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1586
Reported-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>
Signed-off-by: David Ward <david.ward@gatech.edu>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Gustavo A. R. Silva [Mon, 10 May 2021 20:46:18 +0000 (15:46 -0500)]
drm/amd/pm: Fix out-of-bounds bug
Create new structure SISLANDS_SMC_SWSTATE_SINGLE, as initialState.levels
and ACPIState.levels are never actually used as flexible arrays. Those
arrays can be used as simple objects of type
SISLANDS_SMC_HW_PERFORMANCE_LEVEL, instead.
Currently, the code fails because flexible array _levels_ in
struct SISLANDS_SMC_SWSTATE doesn't allow for code that accesses
the first element of initialState.levels and ACPIState.levels
arrays:
drivers/gpu/drm/amd/pm/powerplay/si_dpm.c:
4820: table->initialState.levels[0].mclk.vDLL_CNTL =
4821: cpu_to_be32(si_pi->clock_registers.dll_cntl);
...
5021: table->ACPIState.levels[0].mclk.vDLL_CNTL =
5022: cpu_to_be32(dll_cntl);
because such element cannot be accessed without previously allocating
enough dynamic memory for it to exist (which never actually happens).
So, there is an out-of-bounds bug in this case.
That's why struct SISLANDS_SMC_SWSTATE should only be used as type
for object driverState and new struct SISLANDS_SMC_SWSTATE_SINGLE is
created as type for objects initialState, ACPIState and ULVState.
Also, with the change from one-element array to flexible-array member
in commit
0e1aa13ca3ff ("drm/amd/pm: Replace one-element array with
flexible-array in struct SISLANDS_SMC_SWSTATE"), the size of
dpmLevels in struct SISLANDS_SMC_STATETABLE should be fixed to be
SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE instead of
SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1.
Fixes:
0e1aa13ca3ff ("drm/amd/pm: Replace one-element array with flexible-array in struct SISLANDS_SMC_SWSTATE")
Cc: stable@vger.kernel.org
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>