OSDN Git Service
Ahmed Bougacha [Tue, 19 Jul 2016 19:47:06 +0000 (19:47 +0000)]
[GlobalISel] Simplify more RegClassOrRegBank is+get. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276011
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David Majnemer [Tue, 19 Jul 2016 18:50:26 +0000 (18:50 +0000)]
[FunctionAttrs] Correct the safety analysis for inference of 'returned'
We skipped over ReturnInsts which didn't return an argument which would
lead us to incorrectly conclude that an argument returned by another
ReturnInst was 'returned'.
This reverts commit r275756.
This fixes PR28610.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276008
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Davide Italiano [Tue, 19 Jul 2016 18:31:07 +0000 (18:31 +0000)]
[SCCP] Improve assert messages. NFCI.
I've been hitting those already while working on SCCP and I think
it's be useful to provide a more explanatory diagnostic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276007
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Kostya Serebryany [Tue, 19 Jul 2016 18:29:06 +0000 (18:29 +0000)]
[libFuzzer] properly intercept memmem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276006
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Chad Rosier [Tue, 19 Jul 2016 18:11:11 +0000 (18:11 +0000)]
[DSE] Add additional debug output. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276005
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David Majnemer [Tue, 19 Jul 2016 17:52:41 +0000 (17:52 +0000)]
Add a testcase for r275581
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276002
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David Majnemer [Tue, 19 Jul 2016 17:50:30 +0000 (17:50 +0000)]
[RegionInfo] Some cleanups
- Use unique_ptr instead of managing a container of new'd pointers.
- Use range based for loops.
No functional change is intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276001
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David Majnemer [Tue, 19 Jul 2016 17:50:27 +0000 (17:50 +0000)]
[RegionPass] Some minor cleanups
No functional change is intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276000
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David Majnemer [Tue, 19 Jul 2016 17:50:24 +0000 (17:50 +0000)]
[LoopPass] Some minor cleanups
No functional change is intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275999
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Aaron Ballman [Tue, 19 Jul 2016 17:46:55 +0000 (17:46 +0000)]
This code block breaks the docs build (lab.llvm.org:8011/builders/llvm-sphinx-docs/builds/11920/steps/docs-llvm-html/logs/stdio), but I cannot see anything immediately wrong with it and cannot reproduce the diagnostic locally. Setting the code highlighting to none instead of nasm to hopefully get the bot stumbling back towards green.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275998
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Sanjay Patel [Tue, 19 Jul 2016 17:07:35 +0000 (17:07 +0000)]
add tests related to PR28466
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275995
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Simon Pilgrim [Tue, 19 Jul 2016 17:04:28 +0000 (17:04 +0000)]
[X86][AVX512] Added AVX512 subvector broadcast tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275994
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Simon Pilgrim [Tue, 19 Jul 2016 16:52:05 +0000 (16:52 +0000)]
[X86][AVX] Fixed typo in test names
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275992
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Chad Rosier [Tue, 19 Jul 2016 16:50:57 +0000 (16:50 +0000)]
[DSE] Add additional debug output. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275991
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Sanjay Patel [Tue, 19 Jul 2016 16:49:55 +0000 (16:49 +0000)]
add missing test for simplifySelectBitTest()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275990
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Tobias Grosser [Tue, 19 Jul 2016 16:39:17 +0000 (16:39 +0000)]
[InstCombine] Enable cast-folding in logic(cast(icmp), cast(icmp))
Summary:
Currently, InstCombine is already able to fold expressions of the form `logic(cast(A), cast(B))` to the simpler form `cast(logic(A, B))`, where logic designates one of `and`/`or`/`xor`. This transformation is implemented in `foldCastedBitwiseLogic()` in InstCombineAndOrXor.cpp. However, this optimization will not be performed if both `A` and `B` are `icmp` instructions. The decision to preclude casts of `icmp` instructions originates in r48715 in combination with r261707, and can be best understood by the title of the former one:
> Transform (zext (or (icmp), (icmp))) to (or (zext (cimp), (zext icmp))) if at least one of the (zext icmp) can be transformed to eliminate an icmp.
Apparently, it introduced a transformation that is a reverse of the transformation that is done in `foldCastedBitwiseLogic()`. Its purpose is to expose pairs of `zext icmp` that would subsequently be optimized by `transformZExtICmp()` in InstCombineCasts.cpp. Therefore, in order to avoid an endless loop of switching back and forth between these two transformations, the one in `foldCastedBitwiseLogic()` has been restricted to exclude `icmp` instructions which is mirrored in the responsible check:
`if ((!isa<ICmpInst>(Cast0Src) || !isa<ICmpInst>(Cast1Src)) && ...`
This check seems to sort out more cases than necessary because:
- the reverse transformation is obviously done for `or` instructions only
- and also not every `zext icmp` pair is necessarily the result of this reverse transformation
Therefore we now remove this check and replace it by a more finegrained one in `shouldOptimizeCast()` that now rejects only those `logic(zext(icmp), zext(icmp))` that would be able to be optimized by `transformZExtICmp()`, which also avoids the mentioned endless loop. That means we are now able to also simplify expressions of the form `logic(cast(icmp), cast(icmp))` to `cast(logic(icmp, icmp))` (`cast` being an arbitrary `CastInst`).
As an example, consider the following IR snippet
```
%1 = icmp sgt i64 %a, %b
%2 = zext i1 %1 to i8
%3 = icmp slt i64 %a, %c
%4 = zext i1 %3 to i8
%5 = and i8 %2, %4
```
which would now be transformed to
```
%1 = icmp sgt i64 %a, %b
%2 = icmp slt i64 %a, %c
%3 = and i1 %1, %2
%4 = zext i1 %3 to i8
```
This issue became apparent when experimenting with the programming language Julia, which makes use of LLVM. Currently, Julia lowers its `Bool` datatype to LLVM's `i8` (also see https://github.com/JuliaLang/julia/pull/17225). In fact, the above IR example is the lowered form of the Julia snippet `(a > b) & (a < c)`. Like shown above, this may introduce `zext` operations, casting between `i1` and `i8`, which could for example hinder ScalarEvolution and Polly on certain code.
Reviewers: grosser, vtjnash, majnemer
Subscribers: majnemer, llvm-commits
Differential Revision: https://reviews.llvm.org/D22511
Contributed-by: Matthias Reisinger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275989
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Matt Arsenault [Tue, 19 Jul 2016 16:27:56 +0000 (16:27 +0000)]
AMDGPU: Only use legal inline immediates with kill pseudo
Only if the value is negative or positive is what matters,
so use a constant that doesn't require an instruction to
materialize.
These should really just emit the write exec directly,
but for stick with the kill pseudo-terminator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275988
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Simon Pilgrim [Tue, 19 Jul 2016 15:07:43 +0000 (15:07 +0000)]
[X86][SSE] Reimplement SSE fp2si conversion intrinsics instead of using generic IR
D20859 and D20860 attempted to replace the SSE (V)CVTTPS2DQ and VCVTTPD2DQ truncating conversions with generic IR instead.
It turns out that the behaviour of these intrinsics is different enough from generic IR that this will cause problems, INF/NAN/out of range values are guaranteed to result in a 0x80000000 value - which plays havoc with constant folding which converts them to either zero or UNDEF. This is also an issue with the scalar implementations (which were already generic IR and what I was trying to match).
This patch changes both scalar and packed versions back to using x86-specific builtins.
It also deals with the other scalar conversion cases that are runtime rounding mode dependent and can have similar issues with constant folding.
A companion clang patch is at D22105
Differential Revision: https://reviews.llvm.org/D22106
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275981
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Sam Parker [Tue, 19 Jul 2016 14:44:05 +0000 (14:44 +0000)]
[ARM] Refactor Thumb2 Mul and Mla instr descs
Recommitting after r274347 was reverted. This patch introduces some
classes to refactor the 3 and 4 register Thumb2 multiplication
instruction descriptions, plus improved tests for some of those
instructions.
Differential Revision: https://reviews.llvm.org/D21929
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275979
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Pankaj Gode [Tue, 19 Jul 2016 14:30:21 +0000 (14:30 +0000)]
[AArch64] PredictableSelectIsExpensive for Vulcan.
Adding PredictableSelectIsExpensive for Vulcan
Differential Revision: https://reviews.llvm.org/D22448
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275978
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Peter Smith [Tue, 19 Jul 2016 14:15:33 +0000 (14:15 +0000)]
Add support for tlsldm assembler operator to ARM target
The standard local dynamic model for TLS on ARM systems needs two
relocations:
- R_ARM_TLS_LDM32 (module idx)
- R_ARM_TLS_LDO32 (offset of object from origin of module TLS block)
In GNU style assembler we use symbol(tlsldm) and symbol(tlsldo) to
produce these relocations.
llvm-mc for ARM supports symbol(tlsldo) but does not support symbol(tlsldm).
This patch wires up the existing symbol(tlsldm) to R_ARM_TLS_LDM32.
TLS for ARM is defined in Addenda to, and Errata in, the ABI for the
ARM Architecture
Differential Revision: https://reviews.llvm.org/D22461
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275977
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Simon Pilgrim [Tue, 19 Jul 2016 14:12:45 +0000 (14:12 +0000)]
[AARCH64] Fix linu triple typo
As promised in D22191
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275976
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Simon Pilgrim [Tue, 19 Jul 2016 13:35:11 +0000 (13:35 +0000)]
[AARCH64] Enable AARCH64 lit tests on windows dev machines
As discussed on PR27654, this patch fixes the triples of a lot of aarch64 tests and enables lit tests on windows
This will hopefully help stop cases where windows developers break the aarch64 target
Differential Revision: https://reviews.llvm.org/D22191
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275973
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Simon Pilgrim [Tue, 19 Jul 2016 12:26:51 +0000 (12:26 +0000)]
Get rid of VS2015 operator precedence warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275971
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Daniel Sanders [Tue, 19 Jul 2016 10:58:06 +0000 (10:58 +0000)]
[mips][ias] R_MIPS_GOT_(PAGE|OFST) do not need symbols
Reviewers: sdardis
Subscribers: dsanders, llvm-commits, sdardis
Differential Revision: https://reviews.llvm.org/D22458
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275968
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Daniel Sanders [Tue, 19 Jul 2016 10:49:03 +0000 (10:49 +0000)]
[mips] Correct label prefixes for N32 and N64.
Summary:
N32 and N64 follow the standard ELF conventions (.L) whereas O32 uses its own
($).
This fixes the majority of object differences between -fintegrated-as and
-fno-integrated-as.
Reviewers: sdardis
Subscribers: dsanders, sdardis, llvm-commits
Differential Revision: https://reviews.llvm.org/D22412
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275967
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Daniel Sanders [Tue, 19 Jul 2016 10:22:19 +0000 (10:22 +0000)]
[mips] Recognise the triple used by Debian stretch for mips64el.
Summary:
The triple used for this distribution is mips64el-linux-gnuabi64.
Reviewers: sdardis
Subscribers: sdardis, llvm-commits
Differential Revision: https://reviews.llvm.org/D22406
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275966
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Tobias Grosser [Tue, 19 Jul 2016 09:06:08 +0000 (09:06 +0000)]
[InstCombine] Minor cleanup of cast simplification code [NFC]
Summary:
This patch cleans up parts of InstCombine to raise its compliance with the LLVM coding standards and to increase its readability. The changes and according rationale are summarized in the following:
- Rename `ShouldOptimizeCast()` to `shouldOptimizeCast()` since functions should start with a lower case letter.
- Move `shouldOptimizeCast()` from InstCombineCasts.cpp to InstCombineAndOrXor.cpp since it's only used there.
- Simplify interface of `shouldOptimizeCast()`.
- Minor code style adaptions in `shouldOptimizeCast()`.
- Remove the documentation on the function definition of `shouldOptimizeCast()` since it just repeats the documentation on its declaration. Also enhance the documentation on its declaration with more information describing its intended use and make it doxygen-compliant.
- Change a comment in `foldCastedBitwiseLogic()` from `fold (logic (cast A), (cast B)) -> (cast (logic A, B))` to `fold logic(cast(A), cast(B)) -> cast(logic(A, B))` since the surrounding comments use this format.
- Remove comment `Only do this if the casts both really cause code to be generated.` in `foldCastedBitwiseLogic()` since it just repeats parts of the documentation of `shouldOptimizeCast()` and does not help to improve readability.
- Simplify the interface of `isEliminableCastPair()`.
- Removed the documentation on the function definition of `isEliminableCastPair()` which only contained obvious statements about its implementation. Instead added more general doxygen-compliant documentation to its declaration.
- Renamed parameter `DoXform` of `transformZExtIcmp()` to `DoTransform` to make its intention clearer.
- Moved documentation of `transformZExtIcmp()` from its definition to its declaration and made it doxygen-compliant.
Reviewers: vtjnash, grosser
Subscribers: majnemer, llvm-commits
Differential Revision: https://reviews.llvm.org/D22449
Contributed-by: Matthias Reisinger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275964
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Tobias Grosser [Tue, 19 Jul 2016 09:01:46 +0000 (09:01 +0000)]
Style: drop some unnecessary ';' [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275963
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Elena Demikhovsky [Tue, 19 Jul 2016 07:14:21 +0000 (07:14 +0000)]
AVX-512: Fixed BT instruction selection.
The following condition expression ( a >> n) & 1 is converted to "bt a, n" instruction. It works on all intel targets.
But on AVX-512 it was broken because the expression is modified to (truncate (a >>n) to i1).
I added the new sequence (truncate (a >>n) to i1) to the BT pattern.
Differential Revision: https://reviews.llvm.org/D22354
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275950
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Craig Topper [Tue, 19 Jul 2016 02:00:38 +0000 (02:00 +0000)]
[AVX512] Give priority to EVEX encoded PSHUFB over the VEX versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275942
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Craig Topper [Tue, 19 Jul 2016 02:00:35 +0000 (02:00 +0000)]
[X86] Remove superfluous parameter from a multiclass. All instantiations passed the same value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275941
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George Burgess IV [Tue, 19 Jul 2016 01:29:15 +0000 (01:29 +0000)]
[MemorySSA] Update to the new shiny walker.
This patch updates MemorySSA's use-optimizing walker to be more
accurate and, in some cases, faster.
Essentially, this changed our core walking algorithm from a
cache-as-you-go DFS to an iteratively expanded DFS, with all of the
caching happening at the end. Said expansion happens when we hit a Phi,
P; we'll try to do the smallest amount of work possible to see if
optimizing above that Phi is legal in the first place. If so, we'll
expand the search to see if we can optimize to the next phi, etc.
An iteratively expanded DFS lets us potentially quit earlier (because we
don't assume that we can optimize above all phis) than our old walker.
Additionally, because we don't cache as we go, we can now optimize above
loops.
As an added bonus, this patch adds a ton of verification (if
EXPENSIVE_CHECKS are enabled), so finding bugs is easier.
Differential Revision: https://reviews.llvm.org/D21777
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275940
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Craig Topper [Tue, 19 Jul 2016 01:26:19 +0000 (01:26 +0000)]
[X86] Rename VINSERTzrr to use a capital Z to match other instructions. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275939
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Vedant Kumar [Tue, 19 Jul 2016 01:17:20 +0000 (01:17 +0000)]
Retry: [llvm-profdata] Speed up merging by using a thread pool
Add a "-j" option to llvm-profdata to control the number of threads used.
Auto-detect NumThreads when it isn't specified, and avoid spawning threads when
they wouldn't be beneficial.
I tested this patch using a raw profile produced by clang (147MB). Here is the
time taken to merge 4 copies together on my laptop:
No thread pool: 112.87s user 5.92s system 97% cpu 2:01.08 total
With 2 threads: 134.99s user 26.54s system 164% cpu 1:33.31 total
Changes since the initial commit:
- When handling odd-length inputs, call ThreadPool::wait() before merging the
last profile. Should fix a race/off-by-one (see r275937).
Differential Revision: https://reviews.llvm.org/D22438
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275938
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Vedant Kumar [Tue, 19 Jul 2016 00:57:09 +0000 (00:57 +0000)]
Revert "[llvm-profdata] Speed up merging by using a thread pool"
This reverts commit r275921. It broke the ppc64be bot:
http://lab.llvm.org:8011/builders/clang-ppc64be-linux-multistage/builds/3537
I'm not sure why it broke, but based on the output, it looks like an
off-by-one (one profile left un-merged).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275937
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Wei Mi [Tue, 19 Jul 2016 00:50:43 +0000 (00:50 +0000)]
Recommit the patch "Use uniforms set to populate VecValuesToIgnore".
For instructions in uniform set, they will not have vector versions so
add them to VecValuesToIgnore.
For induction vars, those only used in uniform instructions or consecutive
ptrs instructions have already been added to VecValuesToIgnore above. For
those induction vars which are only used in uniform instructions or
non-consecutive/non-gather scatter ptr instructions, the related phi and
update will also be added into VecValuesToIgnore set.
The change will make the vector RegUsages estimation less conservative.
Differential Revision: https://reviews.llvm.org/D20474
The recommit fixed the testcase global_alias.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275936
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Matt Arsenault [Tue, 19 Jul 2016 00:35:22 +0000 (00:35 +0000)]
AMDGPU/SI: Fix SI scheduler refcount issue
Without this fix, releaseSuccessors when InOrOutBlock is
false could release SUs outside the schedule BasicBlock.
Patch by Axel Davy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275935
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Matt Arsenault [Tue, 19 Jul 2016 00:35:03 +0000 (00:35 +0000)]
AMDGPU: Expand register indexing pseudos in custom inserter
This is to help moveSILowerControlFlow to before regalloc.
There are a couple of tradeoffs with this. The complete CFG
is visible to more passes, the loop body avoids an extra copy of m0,
vcc isn't required, and immediate offsets can be shrunk into s_movk_i32.
The disadvantage is the register allocator doesn't understand that
the single lane's vector is dead within the loop body, so an extra
register is used to outlive the loop block when expanding the
VGPR -> m0 loop. This also now results in worse waitcnt insertion
before the loop instead of after for pending operations at the point
of the indexing, but that should be fixed by future improvements to
cross block waitcnt insertion.
v_movreld_b32's operands are now modeled more correctly since vdst
is not a true output. This is kind of a hack to treat vdst as a
use operand. Extra checking is required in the verifier since
I can't seem to get tablegen to emit an implicit operand for a
virtual register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275934
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Lang Hames [Tue, 19 Jul 2016 00:25:52 +0000 (00:25 +0000)]
[Kaleidoscope][BuildingAJIT] More work on the text for Chapter 3.
Add an overview of stubs and compile callbacks before the discussion of the
source changes.
-- This line, and those below, will be ignored--
M docs/tutorial/BuildingAJIT3.rst
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275933
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Sanjoy Das [Tue, 19 Jul 2016 00:23:54 +0000 (00:23 +0000)]
[LoopReroll] Reroll loops with unordered atomic memory accesses
Reviewers: hfinkel, jfb, reames
Subscribers: mcrosier, mzolotukhin, llvm-commits
Differential Revision: https://reviews.llvm.org/D22385
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275932
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Matt Arsenault [Mon, 18 Jul 2016 23:20:46 +0000 (23:20 +0000)]
TableGen: Allow custom register operand decoder method
This is for a situation where the encoding for a register may be
different depending on the specific operand. For some instructions,
we want to apply additional restrictions beyond the encoding's
constraints.
In AMDGPU some operands are VSrc_32, using the VS_32 pseudo register
class which accept VGPRs, SGPRs, or immediates in the encoding.
Some specific instructions with the same encoding operand do not want
to allow immediates or SGPRs, but the encoding format is different
in this case than a regular VGPR_32 operand.
This allows specifying the encoding should be treated the same
without introducing yet another dummy register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275929
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Matt Arsenault [Mon, 18 Jul 2016 23:09:51 +0000 (23:09 +0000)]
AMDGPU: Fix test name and broken CHECK-LABEL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275928
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Vedant Kumar [Mon, 18 Jul 2016 22:50:10 +0000 (22:50 +0000)]
[utils] Generate html reports with the code coverage utility script
Instead of extracting raw coverage mappings into an artifact directory,
actually generate useful html reports for a given list of binaries with
symbol demangling turned on.
No tests, but this is actively being used to drive the (still nascent)
coverage bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275927
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Matt Arsenault [Mon, 18 Jul 2016 22:12:46 +0000 (22:12 +0000)]
Fix -Wreturn-type with gcc 4.8 and libc++
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275922
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Vedant Kumar [Mon, 18 Jul 2016 22:02:39 +0000 (22:02 +0000)]
[llvm-profdata] Speed up merging by using a thread pool
Add a "-j" option to llvm-profdata to control the number of threads
used. Auto-detect NumThreads when it isn't specified, and avoid spawning
threads when they wouldn't be beneficial.
I tested this patch using a raw profile produced by clang (147MB). Here is the
time taken to merge 4 copies together on my laptop:
No thread pool: 112.87s user 5.92s system 97% cpu 2:01.08 total
With 2 threads: 134.99s user 26.54s system 164% cpu 1:33.31 total
Differential Revision: https://reviews.llvm.org/D22438
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275921
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Artem Belevich [Mon, 18 Jul 2016 21:58:48 +0000 (21:58 +0000)]
[NVPTX] Make sure we adjust alignment at all call sites
.. including calls from kernel functions that were
ignored by mistake before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275920
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Dehao Chen [Mon, 18 Jul 2016 21:41:50 +0000 (21:41 +0000)]
[PM] Convert Loop Strength Reduce pass to new PM
Summary: Convert Loop String Reduce pass to new PM
Reviewers: davidxl, silvas
Subscribers: junbuml, sanjoy, mzolotukhin, llvm-commits
Differential Revision: https://reviews.llvm.org/D22468
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275919
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Mehdi Amini [Mon, 18 Jul 2016 21:29:24 +0000 (21:29 +0000)]
Update doxygen description for `WriteBitcodeToFile()` API (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275917
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Teresa Johnson [Mon, 18 Jul 2016 21:22:24 +0000 (21:22 +0000)]
[PM] Port FunctionImport Pass to new PM
Summary: Port FunctionImport Pass to new PM.
Reviewers: mehdi_amini, davide
Subscribers: davidxl, llvm-commits
Differential Revision: https://reviews.llvm.org/D22475
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275916
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Wei Mi [Mon, 18 Jul 2016 21:14:43 +0000 (21:14 +0000)]
Revert rL275912.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275915
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Wei Mi [Mon, 18 Jul 2016 20:59:53 +0000 (20:59 +0000)]
Use uniforms set to populate VecValuesToIgnore.
For instructions in uniform set, they will not have vector versions so
add them to VecValuesToIgnore.
For induction vars, those only used in uniform instructions or consecutive
ptrs instructions have already been added to VecValuesToIgnore above. For
those induction vars which are only used in uniform instructions or
non-consecutive/non-gather scatter ptr instructions, the related phi and
update will also be added into VecValuesToIgnore set.
The change will make the vector RegUsages estimation less conservative.
Differential Revision: https://reviews.llvm.org/D20474
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275912
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Sanjay Patel [Mon, 18 Jul 2016 20:56:53 +0000 (20:56 +0000)]
refactor SimplifySelectInst; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275911
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Justin Lebar [Mon, 18 Jul 2016 20:40:35 +0000 (20:40 +0000)]
Write isUInt using template specializations to work around an incorrect MSVC warning.
Summary:
Per D22441, MSVC warns on our old implementation of isUInt<64>. It sees
uint64_t(1) << 64 and doesn't realize that it's not going to be
executed. Writing as a template specialization is ugly, but prevents
the warning.
Reviewers: RKSimon
Subscribers: majnemer, llvm-commits
Differential Revision: https://reviews.llvm.org/D22472
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275909
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Sanjay Patel [Mon, 18 Jul 2016 20:37:51 +0000 (20:37 +0000)]
add tests for missed sext transform
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275908
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Hans Wennborg [Mon, 18 Jul 2016 20:26:46 +0000 (20:26 +0000)]
build_llvm_package.bat: update version to 4.0.0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275903
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Sanjay Patel [Mon, 18 Jul 2016 20:06:51 +0000 (20:06 +0000)]
auto-generate checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275899
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Hans Wennborg [Mon, 18 Jul 2016 20:06:27 +0000 (20:06 +0000)]
Revert r273099 "If the revision number starts with r, drop it. It will get added back"
This doesn't seem to work with Bash:
$ /work/llvm/utils/release/merge.sh --proj llvm --rev r275870
/work/llvm/utils/release/merge.sh: line 34: ${$1#r}: bad substitution
I get the same error with and without a leading 'r'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275898
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Artem Belevich [Mon, 18 Jul 2016 19:54:56 +0000 (19:54 +0000)]
[NVPTX] Force minimum alignment of 4 for byval arguments of device-side functions.
Taking address of a byval variable in PTX is legal, but currently runs
into miscompilation by ptxas on sm_50+ (NVIDIA issue
1789042).
Work around the issue by enforcing minimum alignment on byval arguments
of device functions.
The change is a no-op on SASS level for sm_3x where ptxas already aligns
local copy by at least 4.
Differential Revision: https://reviews.llvm.org/D22428
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275893
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Michael Zolotukhin [Mon, 18 Jul 2016 19:44:19 +0000 (19:44 +0000)]
[LoopSimplify] Update LCSSA after separating nested loops.
Summary:
Usually LCSSA survives this transformation, but in some cases (see
attached test) it doesn't: values from the original loop after
separating might be used from the outer loop. Before the transformation
it was the same loop, so LCSSA phis were not required.
This fixes PR28272.
Reviewers: sanjoy, hfinkel, chandlerc
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D21665
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275891
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Vitaly Buka [Mon, 18 Jul 2016 19:44:01 +0000 (19:44 +0000)]
Revert "[ARM] Skip inline asm memory operands in DAGToDAGISel"
Breaks asan, see https://reviews.llvm.org/D22103
This reverts commit r275776.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275890
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Vitaly Buka [Mon, 18 Jul 2016 19:43:58 +0000 (19:43 +0000)]
Revert "[ARM] Update test to use CHECK-LABEL. NFCI."
Breaks asan, see https://reviews.llvm.org/D22103
This reverts commit r275777.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275889
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Nirav Dave [Mon, 18 Jul 2016 19:35:21 +0000 (19:35 +0000)]
[MC] Separate non-parsing operations from conditional chains. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275888
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David Majnemer [Mon, 18 Jul 2016 19:14:14 +0000 (19:14 +0000)]
[GVNHoist] Remove a home-grown version of replaceUsesOfWith
replaceUsesOfWith will, on average, consider fewer values when trying
to do the replacement.
No functional change is intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275884
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Michael Zolotukhin [Mon, 18 Jul 2016 19:05:08 +0000 (19:05 +0000)]
[LCSSA] Post-process PHI-nodes created by SSAUpdate when constructing LCSSA form.
Summary:
SSAUpdate might insert PHI-nodes inside loops, which can break LCSSA
form unless we fix it up.
This fixes PR28424.
Reviewers: sanjoy, chandlerc, hfinkel
Subscribers: uabelho, llvm-commits
Differential Revision: http://reviews.llvm.org/D21997
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275883
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Matt Arsenault [Mon, 18 Jul 2016 19:00:07 +0000 (19:00 +0000)]
AMDGPU: Remove pointless dyn_cast_or_null
This is already casted above so non-null
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275881
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Reid Kleckner [Mon, 18 Jul 2016 18:53:50 +0000 (18:53 +0000)]
Fix -Wmicrosoft-enum-value in GVNHoist.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275879
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Simon Pilgrim [Mon, 18 Jul 2016 18:53:15 +0000 (18:53 +0000)]
[X86][SSE] Regenerate extraction from promotion test
Added tests for SSE2 as well as SSE41
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275878
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Simon Pilgrim [Mon, 18 Jul 2016 18:44:01 +0000 (18:44 +0000)]
[X86][SSE] Regenerate extraction+store memop tests
Added tests for SSE2 as well as SSE41+AVX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275876
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Simon Pilgrim [Mon, 18 Jul 2016 18:42:33 +0000 (18:42 +0000)]
[X86][SSE] Regenerate truncate+extension memop tests
Added tests for SSE2 as well as SSE41
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275875
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Matt Arsenault [Mon, 18 Jul 2016 18:40:51 +0000 (18:40 +0000)]
AMDGPU: Fix missing switch case warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275873
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Simon Pilgrim [Mon, 18 Jul 2016 18:38:51 +0000 (18:38 +0000)]
Regenerate test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275872
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Matt Arsenault [Mon, 18 Jul 2016 18:35:05 +0000 (18:35 +0000)]
AMDGPU: Add intrinsic for s_flbit_i32/v_ffbh_i32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275871
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Matt Arsenault [Mon, 18 Jul 2016 18:34:59 +0000 (18:34 +0000)]
AMDGPU/R600: Replace barrier intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275870
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Matt Arsenault [Mon, 18 Jul 2016 18:34:53 +0000 (18:34 +0000)]
AMDGPU: Remove dead check in AMDGPUPromoteAlloca
This is currently only called with GEP users. A direct
alloca would only happen with current typed pointers
for arrays which are a perverse case.
Also fix crashes on 0 x and 1 x arrays.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275869
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Matt Arsenault [Mon, 18 Jul 2016 18:34:48 +0000 (18:34 +0000)]
AMDGPU: Remove dead code and redundant check
Non intrinsic calls aren't really handled, and this
IntrinsicInst dyn_cast checks for the function for us.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275868
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Teresa Johnson [Mon, 18 Jul 2016 18:31:50 +0000 (18:31 +0000)]
[ThinLTO] Address review comments from PGO indirect call promotion (NFC)
Address a couple of post-commit review comments from r275707.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275867
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Tim Northover [Mon, 18 Jul 2016 18:28:52 +0000 (18:28 +0000)]
CodeGenPrep: use correct function to determine Global's alignment.
Elsewhere (particularly computeKnownBits) we assume that a global will be
aligned to the value returned by Value::getPointerAlignment. This is used to
boost the alignment on memcpy/memset, so any target-specific request can only
increase that value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275866
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Vedant Kumar [Mon, 18 Jul 2016 18:02:54 +0000 (18:02 +0000)]
[llvm-cov] Re-write a very opaque comment (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275843
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Hans Wennborg [Mon, 18 Jul 2016 18:02:23 +0000 (18:02 +0000)]
Trunk release notes now refer to 4.0.0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275842
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Vedant Kumar [Mon, 18 Jul 2016 17:53:16 +0000 (17:53 +0000)]
[llvm-cov] Place anchors around line numbers in html reports
Based on a suggestion by Harlan Haskins!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275840
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Vedant Kumar [Mon, 18 Jul 2016 17:53:12 +0000 (17:53 +0000)]
[llvm-cov] Clean up error reporting (NFC)
Use CodeCoverageTool::{error,warning} everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275837
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Hans Wennborg [Mon, 18 Jul 2016 17:51:04 +0000 (17:51 +0000)]
Bump the trunk version to 4.0.0svn.
Differential Revision: https://reviews.llvm.org/D21821
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275827
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Krzysztof Parzyszek [Mon, 18 Jul 2016 17:36:46 +0000 (17:36 +0000)]
[Hexagon] Handle returning small structures by value
This is not compliant with the official ABI, but allows experimentation
with calling conventions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275825
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Krzysztof Parzyszek [Mon, 18 Jul 2016 17:34:49 +0000 (17:34 +0000)]
[Hexagon] Revert r275822: mistake in commit message
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275824
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Simon Pilgrim [Mon, 18 Jul 2016 17:32:59 +0000 (17:32 +0000)]
[X86][AVX] Add target shuffle decode support for VBROADCAST
Currently we only decode broadcasts from a vector of the same size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275823
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Krzysztof Parzyszek [Mon, 18 Jul 2016 17:30:41 +0000 (17:30 +0000)]
[Hexagon] Handle returning small structures by value
This is compliant with the official ABI, but allows experimentation with
calling conventions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275822
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Chih-Hung Hsieh [Mon, 18 Jul 2016 17:20:09 +0000 (17:20 +0000)]
[X86] Accept SELECT op code for x86-64 fp128 type
DAGTypeLegalizer::CanSkipSoftenFloatOperand should allow
SELECT op code for x86_64 fp128 type for MME targets,
so SoftenFloatOperand does not abort on SELECT op code.
Differential Revision: http://reviews.llvm.org/D21758
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275818
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David Majnemer [Mon, 18 Jul 2016 17:03:09 +0000 (17:03 +0000)]
[MathExtras] Fix UB in minIntN
We negated a value with a signed type which invited problems when that
value was the most negative signed number. Use an unsigned type
for the value instead. It will compute the same twos complement
result without the UB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275815
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Adam Nemet [Mon, 18 Jul 2016 16:37:32 +0000 (16:37 +0000)]
[LoopDist] This test does not require ASSERTS
Only its counterpart, diagnostics-with-hotness-lazy-BFI.ll, which
invokes opt with -debug-only=.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275812
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Adam Nemet [Mon, 18 Jul 2016 16:29:27 +0000 (16:29 +0000)]
[LoopDist] Port to new PM
Summary:
The direct motivation for the port is to ensure that the OptRemarkEmitter
tests work with the new PM.
This remains a function pass because we not only create multiple loops
but could also version the original loop.
In the test I need to invoke opt
with -passes='require<aa>,loop-distribute'. LoopDistribute does not
directly depend on AA however LAA does. LAA uses getCachedResult so
I *think* we need manually pull in 'aa'.
Reviewers: davidxl, silvas
Subscribers: sanjoy, llvm-commits, mzolotukhin
Differential Revision: https://reviews.llvm.org/D22437
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275811
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Adam Nemet [Mon, 18 Jul 2016 16:29:21 +0000 (16:29 +0000)]
[OptRemarkEmitter] Port to new PM
Summary:
The main goal is to able to start using the new OptRemarkEmitter
analysis from the LoopVectorizer. Since the vectorizer was recently
converted to the new PM, it makes sense to convert this analysis as
well.
This pass is currently tested through the LoopDistribution pass, so I am
also porting LoopDistribution to get coverage for this analysis with the
new PM.
Reviewers: davidxl, silvas
Subscribers: llvm-commits, mzolotukhin
Differential Revision: https://reviews.llvm.org/D22436
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275810
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Adam Nemet [Mon, 18 Jul 2016 16:29:17 +0000 (16:29 +0000)]
Sort include headers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275809
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Simon Pilgrim [Mon, 18 Jul 2016 16:17:34 +0000 (16:17 +0000)]
[X86][AVX2] Added tests that demonstrate duplicate broadcasts
We don't yet decode broadcasts as a target shuffle
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275808
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Krzysztof Parzyszek [Mon, 18 Jul 2016 16:15:15 +0000 (16:15 +0000)]
[Hexagon] Misc changes to HexagonMachineScheduler, NFC
- Remove duplicated code.
- Convert loop to range-for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275806
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Krzysztof Parzyszek [Mon, 18 Jul 2016 16:05:27 +0000 (16:05 +0000)]
[Hexagon] Enable .cur formation in MISched for Hexagon V60
Schedule a load and its use in the same packet in MISched. Previously,
isResourceAvailable was returning false for dependences in the same
packet, which prevented MISched from packetizing a load and its use in
the same packet for v60.
Patch by Ikhlas Ajbar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275804
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Alexander Kornienko [Mon, 18 Jul 2016 15:51:31 +0000 (15:51 +0000)]
Revert "r275571 [DSE]Enhance shorthening MemIntrinsic based on OverlapIntervals"
Causes https://llvm.org/bugs/show_bug.cgi?id=28588
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275801
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Krzysztof Parzyszek [Mon, 18 Jul 2016 15:47:25 +0000 (15:47 +0000)]
[Hexagon] Add verbose debugging mode to Hexagon MI Scheduler
Patch by Sergei Larin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275799
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Nemanja Ivanovic [Mon, 18 Jul 2016 15:30:00 +0000 (15:30 +0000)]
[PowerPC] Remove redundant direct moves when extracting integers and converting to FP
This patch corresponds to review:
https://reviews.llvm.org/D21354
We use direct moves for extracting integer elements from vectors. We also use
direct moves when converting integers to FP. When these operations are chained,
we get a direct move out of a VSR followed by a direct move back into a VSR.
These are redundant - all we need to do is line up the element and convert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275796
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Nirav Dave [Mon, 18 Jul 2016 15:24:03 +0000 (15:24 +0000)]
[MC] Cleanup Error Handling in AsmParser
Add parseToken and compatriot functions to stitch error checks in
straight linear code. As part of this fix some erronous handling of
directives where the EndOfStatement token either was not checked or
Lexed on termination.
Reviewers: rnk, majnemer
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D22312
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275795
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