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Brian Paul [Sat, 3 Dec 2011 17:04:19 +0000 (10:04 -0700)]
mesa: remove dead swrast and state tracker accum buffer code
Brian Paul [Sat, 3 Dec 2011 17:04:18 +0000 (10:04 -0700)]
mesa: rewrite accum buffer support
Implemented in terms of renderbuffer mapping/unmapping and format
packing/unpacking functions.
The swrast and state tracker code for implementing accumulation are
unused and will be removed in the next commit.
v2: don't use memcpy() in _mesa_clear_accum_buffer()
v3: don't allocate MAX_WIDTH arrays, be more careful with mapping flags
Reviewed-by: Eric Anholt <eric@anholt.net>
Brian Paul [Sat, 3 Dec 2011 17:04:18 +0000 (10:04 -0700)]
mesa: new format_pack.c code
This code packs colors, Z, stencil, etc. in the various mesa pixel
formats. Will be used for things like glDrawPixels, glTexImage,
glAccum, etc.
Brian Paul [Sat, 3 Dec 2011 17:04:18 +0000 (10:04 -0700)]
mesa: remove the ctx->Driver.IsTextureResident() hook
No driver implemented this and we always returned "True" for residence
queries.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Brian Paul [Sat, 3 Dec 2011 17:04:18 +0000 (10:04 -0700)]
mesa: remove TextureMemCpy driver hook
There's probably no reason to use a special version of memcpy() anymore.
Henri Verbeet [Sat, 3 Dec 2011 12:10:57 +0000 (13:10 +0100)]
st/mesa: Use util_blit_pixels_writemask() for depth blits as well in st_copy_texsubimage().
This has no piglit regressions on r600g and softpipe.
Signed-off-by: Henri Verbeet <hverbeet@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Thomas Hellstrom [Wed, 7 Dec 2011 19:11:23 +0000 (20:11 +0100)]
st/xa: Update xa_yuv_planar_blit semantics
Change and document the interpretation of the color conversion matrix
in order to make the function more versatile and to simplify the
generated shader.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
Paul Berry [Tue, 29 Nov 2011 22:51:03 +0000 (14:51 -0800)]
i965 gen6: Implement pass-through GS for transform feedback.
In Gen6, transform feedback is accomplished by having the geometry
shader send vertex data to the data port using "Streamed Vertex Buffer
Write" messages, while simultaneously passing vertices through to the
rest of the graphics pipeline (if rendering is enabled).
This patch adds a geometry shader program that simply passes vertices
through to the rest of the graphics pipeline. The rest of transform
feedback functionality will be added in future patches.
To make the new geometry shader easier to test, I've added an
environment variable "INTEL_FORCE_GS". If this environment variable
is enabled, then the pass-through geometry shader will always be used,
regardless of whether transform feedback is in effect.
On my Sandy Bridge laptop, I'm able to enable INTEL_FORCE_GS with no
Piglit regressions.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Eric Anholt <eric@anholt.net>
Paul Berry [Fri, 2 Dec 2011 22:38:52 +0000 (14:38 -0800)]
i965: Clean up misleading defines for DWORD 2 of URB_WRITE header.
R02_PRIM_END and R02_PRIM_START don't actually refer to bits in DWORD
2 of R0 (as the name, and comments in the code, would seem to
indicate). Actually they refer to bits in DWORD 2 of the header for
URB_WRITE messages.
This patch renames the defines to reflect what they actually mean. It
also addes a define URB_WRITE_PRIM_TYPE_SHIFT, which previously was
just hardcoded in .c files.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Paul Berry [Tue, 29 Nov 2011 22:54:02 +0000 (14:54 -0800)]
i965 gs: Clean up dodgy register re-use, at the cost of a few MOVs.
Prior to this patch, in the Gen4 and Gen5 GS, we used GRF 0 (called
"R0" in the code) as a staging area to prepare the message header for
the FF_SYNC and URB_WRITE messages. This cleverly avoided an
unnecessary MOV operation (since the initial value of GRF 0 contains
data that needs to be included in the message header), but it made the
code confusing, since GRF 0 could no longer be relied upon to contain
its initial value once the GS started preparing its first message.
This patch avoids confusion by using a separate register ("header") as
the staging area, at the cost of one MOV instruction.
Worse yet, prior to this patch, the GS would completely overwrite the
contents of GRF 0 with the writeback data it received from a completed
FF_SYNC or URB_WRITE message. It did this because DWORD 0 of the
writeback data contains the new URB handle, and that neds to be
included in DWORD 0 of the next URB_WRITE message header. However,
that caused the rest of the message header to be corrupted either with
undefined data or zeros. Astonishingly, this did not produce any
known failures (probably by dumb luck). However, it seems really
dodgy--corrupting FFTID in particular seems likely to cause GPU hangs.
This patch avoids the corruption by storing the writeback data in a
temporary register and then copying just DWORD 0 to the header for the
next message. This costs one extra MOV instruction per message sent,
except for the final message.
Also, this patch moves the logic for overriding DWORD 2 of the header
(which contains PrimType, PrimStart, PrimEnd, and some other data that
we don't care about yet). This logic is now in the function
brw_gs_overwrite_header_dw2() rather than in brw_gs_emit_vue(). This
saves one MOV instruction in brw_gs_quads() and brw_gs_quad_strip(),
and paves the way for the Gen6 GS, which will need more complex logic
to override DWORD 2 of the header.
Finally, the function brw_gs_alloc_regs() contained a benign bug: it
neglected to increment the register counter when allocating space for
the "temp" register. This turned out not to have any effect because
the temp register wasn't used on Gen4 and Gen5, the only hardware
models (so far) to require a GS program. Now, all the registers
allocated by brw_gs_alloc_regs() are actually used, and properly
accounted for.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Paul Berry [Wed, 7 Dec 2011 17:56:42 +0000 (09:56 -0800)]
i965 gen6: Allocate URB space for GS
When the GS is not in use, the entire URB space is available for the
VS. When the GS is in use, we split the URB space 50/50.
The 50/50 split is probably not optimal--we'll probably want tune this
for performance in a future patch. For example, in most situations,
it's probably worth allocating more than 50% of the space to the VS,
since VS space is used for vertex caching. But for now this is good
enough.
Based on previous work by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Tue, 15 Nov 2011 03:13:27 +0000 (19:13 -0800)]
i965: Set the maximum number of GS URB entries on Sandybridge.
We never filled this in before because we didn't care.
I'm skeptical these are correct; my sources indicate that both the VS
and GS # of entries are 256 on both GT1 and GT2.
I'm also loathe to change it and break stuff.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Paul Berry [Fri, 25 Nov 2011 05:41:07 +0000 (21:41 -0800)]
i965: Only convert if/else to conditional adds prior to Gen6.
Normally when outputting instructions in SPF (single program flow)
mode, we convert IF and ELSE instructions to conditional ADD
instructions applied to the IP register. On platforms prior to Gen6,
flow control instructions cause an implied thread switch, so this is a
significant savings.
However, according to the SandyBridge PRM (Volume 4 part 2, p79):
[Errata DevSNB{WA}] - When SPF is ON, IP may not be updated by
non-flow control instructions.
So we have to disable this optimization on Gen6.
On later platforms, there is no significant benefit to converting flow
control instructions to ADDs, so for the sake of consistency, this
patch disables the optimization on later platforms too.
The reason we never noticed this problem before is that so far we
haven't needed to use SPF mode on Gen6. However, later patches in
this series will introduce a Gen6 GS program which uses SPF mode.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Paul Berry [Tue, 22 Nov 2011 18:30:36 +0000 (10:30 -0800)]
i965 gs: Remove unnecessary mapping of key->primitive.
Previously, GS generation code contained a lookup table that mapped
primitive types POLYGON, TRISTRIP, and TRIFAN to TRILIST, mapped
LINESTRIP to LINELIST, and left all other primitives unchanged. This
was silly, because we never generate a GS program for those primitive
types anyhow.
This patch removes the unnecessary lookup table.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Paul Berry [Tue, 22 Nov 2011 19:53:46 +0000 (11:53 -0800)]
mesa: Track changes to transform feedback state.
This patch adds a new bit to the ctx->NewState bitfield,
_NEW_TRANSFORM_FEEDBACK, to track state changes that affect
ctx->TransformFeedback. This bit can be used by driver back-ends to
avoid expensive recomputations when transform feedback state has not
been modified.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Aaron Plattner [Tue, 6 Dec 2011 18:20:30 +0000 (10:20 -0800)]
glx: Fix indirect fallback when a non-Mesa GLX extension is present.
When driCreateScreen calls driConvertConfigs to try to convert the
configs for swrast, it fails and returns NULL. Instead of checking,
it just clobbers psc->base.configs. Then, when the application asks
for the FBconfigs, there aren't any.
Instead, make the caller responsible for freeing the old modes lists
if both calls to driConvertConfigs succeed.
Without the second fix, glxinfo fails unless you run it with
LIBGL_ALWAYS_INDIRECT:
$ glxinfo
name of display: :0.0
Error: couldn't find RGB GLX visual or fbconfig
$ LIBGL_ALWAYS_INDIRECT=1 glxinfo
name of display: :0.0
display: :0 screen: 0
direct rendering: No (LIBGL_ALWAYS_INDIRECT set)
server glx vendor string: NVIDIA Corporation
server glx version string: 1.4
[...]
Signed-off-by: Aaron Plattner <aplattner@nvidia.com>
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
Anuj Phogat [Tue, 6 Dec 2011 19:11:03 +0000 (11:11 -0800)]
glsl: Fix samplerCubeShadow support in shader compiler
This patch fixes the samplerCubeShadow support in GLSL shader compiler.
shader compiler was picking the 'r' texture coordinate for shadow comparison
when the expected behaviour is to use 'q' texture coordinate in case of cube
shadow maps.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Wed, 7 Dec 2011 20:34:28 +0000 (12:34 -0800)]
i965: Set Ivybridge's is_array SURFACE_STATE bit.
Fixes piglit tests fbo-array, fbo-depth-array, fbo-generatemipmap-array,
and array-texture, as well as the array variants of my new textureSize
and texelFetch tests.
Not a candidate for 7.11 because EXT_texture_array wasn't supported.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Wed, 7 Dec 2011 10:21:37 +0000 (02:21 -0800)]
i965: Return BRW_DEPTHBUFFER_D32_FLOAT as the null-depthbuffer format.
Fixes many crashes on Ivybridge due to upload_sf_state calling
brw_depthbuffer_format without an actual depth buffer. This was a
recent regression on master.
+3992 piglits on Ivybridge.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Eric Anholt [Wed, 30 Nov 2011 16:41:52 +0000 (08:41 -0800)]
intel: Update comment about how depth/stencil miptrees are handled.
This evolved over several commits, and I also wanted to document some
new information about how we handle formats.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Eric Anholt [Wed, 30 Nov 2011 16:31:53 +0000 (08:31 -0800)]
intel: Rely on miptree mapping for all renderbuffer maps.
Now that all RBs have miptrees, and miptree mapping covered these last
two code paths, consistently use them.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Eric Anholt [Wed, 30 Nov 2011 15:36:26 +0000 (07:36 -0800)]
intel: Add support for LLC-cached reads of X-tiled miptrees using a blit.
This mimics the MapRenderbuffer code, and should improve the
performance of glGetTexImage().
v2: Fix broken error handling.
Eric Anholt [Wed, 30 Nov 2011 15:18:42 +0000 (07:18 -0800)]
intel: Handle MapRenderbuffer of fake packed depth/stencil using miptree maps.
This gets the same performance win as the miptree maps did, and
removes a pile of code duplication.
Eric Anholt [Wed, 30 Nov 2011 16:27:53 +0000 (08:27 -0800)]
intel: Track miptrees for fake packed depth/stencil renderbuffers.
Right now the fake packed d/s RBs are creating two sub-renderbuffers
with their own storage, and the hardware setup and the mapping code
have been explicitly referencing them. By setting miptrees on them,
we'll be able to make our renderbuffer code for fake packed
depth/stencil more consistent with all our other renderbuffers.
The interesting new behavior here is that there is now a mt with a
non-depthstencil format (X8Z24) that has a stencil_mt field
associated. This looks like it should be safe, and we'll need to be
able to do this for floating point depth/stencil as well.
Eric Anholt [Wed, 30 Nov 2011 15:03:03 +0000 (07:03 -0800)]
intel: Make the fake packed depth/stencil mappings use a cached temporary.
Before, we had an uncached read of S8 to untile, then a RMW (so
uncached penalty) of the packed S8Z24 to store the value, then the
consumer would uncached read that once per pixel. If data was written
to the map, we would then have to uncached read the written data back
out and do the scatter to the tiled S8 buffer (also uncached access
penalties, since WC couldn't actually combine). So 3 or 5 uncached
accesses per pixel in the ROI (and we we were ignoring the ROI, so it
was the whole image).
Now we get an uncached read of S8 to untile, and an uncached read of
Z. The consumer gets to do cached accesses. Then if data was
written, we do streaming Z writes (WC success), and scattered S8
tiling writes (uncached penalty). So 2 or 3 uncached accesses per
pixel in the ROI.
This should be a performance win, to the extent that anybody is doing
software accesses of packed depth/stencil buffers.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Eric Anholt [Wed, 30 Nov 2011 14:47:27 +0000 (06:47 -0800)]
intel: Make intel_region_map return void *.
We don't gripe about void * arithmetic for our driver, and this
prevents silly casting when assigning the result of mapping to
non-byte types.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Eric Anholt [Tue, 29 Nov 2011 00:08:46 +0000 (16:08 -0800)]
intel: Move separate-stencil s8 mapping logic to intel_miptree_map.
We're going to want to reuse this logic in mapping of fake packed
miptrees wrapping separate depth/stencil miptrees.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Eric Anholt [Mon, 28 Nov 2011 23:49:01 +0000 (15:49 -0800)]
intel: Move the gtt-particular texture mapping logic to a helper function.
This code will be incrementally moving to a model like intel_fbo.c's
renderbuffer mapping with helper functions, as I move that code here.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Eric Anholt [Mon, 28 Nov 2011 19:02:59 +0000 (11:02 -0800)]
intel: Make mapping of texture slices track the region of interest.
This will be used for things like packed depth/stencil temporaries and
making LLC-cached temporary mappings using blits.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Eric Anholt [Mon, 28 Nov 2011 19:17:11 +0000 (11:17 -0800)]
intel: Move the teximage mapping logic to a miptree level/slice mapping.
This will let us share teximage mapping logic with renderbuffer
mapping, which has an intel_mipmap_tree but not a gl_texture_image.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Eric Anholt [Wed, 30 Nov 2011 16:52:54 +0000 (08:52 -0800)]
intel: Only prefer separate stencil when we can do HiZ.
This required is_hiz_depth_format to start returning true on S8_Z24 as
well, since that's the format we have here. The two previous callers
are only calling it on non-depthstencil formats.
This avoids us needing to have HiZ working on a new Z format
immediately upon exposing the format (particularly painful for
Z32_FLOAT_X24S8, which means all the fake packed depth/stencil paths).
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Thomas Hellstrom [Tue, 6 Dec 2011 09:16:13 +0000 (10:16 +0100)]
st/dri: Use depth instead of bpp when communicating formats with the X server v3
Some hardware can't reinterpret the format of hardware buffers and thus
the X server needs to know the format when the buffer is created.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Michel Daenzer <michel@daenzer.net>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
Kenneth Graunke [Wed, 23 Nov 2011 12:13:23 +0000 (04:13 -0800)]
i965: Set SURFACE_STATE vertical alignment bit on Ivybridge.
See intel_vertical_texture_alignment_unit() in intel_tex_layout.c;
certain surface types require setting this to VALIGN_4.
Analogous to commit
dd0e46c4102976b7d317104ecd1bb565ac34613a on Gen6.
Fixes piglit test fbo-generatemipmap-formats with the
GL_ARB_depth_texture and GL_EXT_packed_depth_stencil arguments.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Patrice Mandin [Tue, 6 Dec 2011 20:42:31 +0000 (21:42 +0100)]
nouveau/nvfx: Add more unsupported PIPE_CAP values
Signed-off-by: Patrice Mandin <patmandin@gmail.com>
Dave Airlie [Tue, 6 Dec 2011 16:09:51 +0000 (16:09 +0000)]
radeon: add original r100 to the always tiled depth list.
According to Alex, he thinks r100 is also covered.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Fabio Pedretti [Tue, 6 Dec 2011 15:44:07 +0000 (08:44 -0700)]
vega: remove unused vars
Signed-off-by: Brian Paul <brianp@vmware.com>
Fabio Pedretti [Tue, 6 Dec 2011 15:42:54 +0000 (08:42 -0700)]
osmesa: remove unused bpc variable
Signed-off-by: Brian Paul <brianp@vmware.com>
Dave Airlie [Tue, 6 Dec 2011 14:25:01 +0000 (14:25 +0000)]
radeon/r200: add RV200 detiling + add an always tiled flag
passes readpix sanity on the M7.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 6 Dec 2011 14:08:07 +0000 (14:08 +0000)]
r200: add Z16 depth detiling.
This passes readPixSanity with z16 visuals.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 6 Dec 2011 14:03:55 +0000 (14:03 +0000)]
r200: handle Z24 depth buffers correctly
The same detiling pattern applies to X8_Z24 as well.
Signed-off-by: Dave Airlie <Airlied@redhat.com>
Vadim Girlin [Fri, 2 Dec 2011 09:44:29 +0000 (13:44 +0400)]
r600g: check shaders presence in r600_draw_vbo
This patch should prevent the crashes when some shaders are absent,
see https://bugs.freedesktop.org/show_bug.cgi?id=43341
Note this is a candidate for the stable branch.
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dave Airlie [Tue, 6 Dec 2011 09:45:49 +0000 (09:45 +0000)]
r200: fix cb microtile setup
We shouldn't see this in buffers from the DDX but just in case.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 6 Dec 2011 09:44:37 +0000 (09:44 +0000)]
r200: enable tiling flags on blitter setup.
The r200 blitter also didn't set the correct tiling flags.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Anuj Phogat [Wed, 30 Nov 2011 19:39:57 +0000 (11:39 -0800)]
swrast: Add depth cube map support.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Anuj Phogat [Thu, 24 Nov 2011 00:14:43 +0000 (16:14 -0800)]
mesa: Allow glTexImage2D with a depth component cube map.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Mon, 5 Dec 2011 19:44:03 +0000 (11:44 -0800)]
i965: Fix incorrect comment about single program flow on Ironlake.
The code forces single program flow to be enabled on Ironlake, or
equivalently, disables multiple program flow. The comment was reversed.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Jerome Glisse [Mon, 5 Dec 2011 23:42:38 +0000 (18:42 -0500)]
r600g: fix error path and use util_slab_free
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Jerome Glisse [Mon, 5 Dec 2011 23:40:53 +0000 (18:40 -0500)]
gallium/radeon: fix indentation
Indentation cleanup, to keep consistency.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Dave Airlie [Mon, 5 Dec 2011 19:15:52 +0000 (19:15 +0000)]
radeon/r200: drop old span depth/stencil code.
This is no longer used with the new renderbuffer code.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Dec 2011 19:15:04 +0000 (19:15 +0000)]
radeon/r200: add draw/stencil buffer detiling
This moves the detiling to the fbo mapping, r200 depth is always tiled,
and we can't detile it with the blitter.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Dec 2011 16:51:03 +0000 (16:51 +0000)]
radeon: fix warnings
Dave Airlie [Mon, 5 Dec 2011 16:25:27 +0000 (16:25 +0000)]
radeon: use mesa renderbuffer accessors for depth for now.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Dec 2011 15:41:24 +0000 (15:41 +0000)]
radeon: add some tiling support for r100.
This sets up the tiling flags on the blitter.
Fixes some piglit tests with tiling enabled.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 11 Nov 2011 16:13:06 +0000 (16:13 +0000)]
radeon: texture/renderbuffer overhaul.
This could have been split up better, but the driver is just broken now,
so bisecting the brokenness is going to be painful no matter what.
This adds renderbuffer mapping/unmapping along with texture image allocation.
It drops all the old texture upload paths, some of which could possible be
reimplemented with the blitter later.
It also redoes the span code paths to use its own set of image mapping handlers,
along with removing the tiling decode paths for the color buffers, since
we now hope to use the blitter for this.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 11 Nov 2011 16:06:43 +0000 (16:06 +0000)]
radeon: set texture bits to always emit.
I think there is a missing state update or flush somewhere, and every
so often PP_CNTL goes to the kernel with a texture enabled but no texture.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 11 Nov 2011 15:55:30 +0000 (15:55 +0000)]
radeon: update flush according to glXMakeCurrent man page
This also copies code from intel driver to do this.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 11 Nov 2011 15:28:31 +0000 (15:28 +0000)]
radeon: drop border check
now that we strip borders off earlier.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 11 Nov 2011 15:25:43 +0000 (15:25 +0000)]
radeon: add a bit more debugging to the blit debug code.
For debugging blits it helps if we printed out the offsets as well.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Eric Anholt [Mon, 28 Nov 2011 00:26:19 +0000 (16:26 -0800)]
mesa: Reject glDrawPixels(integer format).
When folding GL_EXT_texture_integer into the core, a new (and very
sensible) restriction was added.
Reviewed-by: Brian Paul <brianp@vmware.com>
Brian Paul [Sat, 3 Dec 2011 16:31:43 +0000 (09:31 -0700)]
util: add casts in fprintf() calls to silence warnings
And wrap to 80 columns.
Mathias Fröhlich [Fri, 2 Dec 2011 07:08:07 +0000 (08:08 +0100)]
mesa: Use VERT_{ATTRIB,BIT}* for ARB input validation.
For validating ARB program inputs replace hard
coded bitfield and attribute number with the appropriate
VERT_{ATTRIB,BIT}* variant.
This should fix:
https://bugs.freedesktop.org/show_bug.cgi?id=43407
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Chia-I Wu [Sat, 3 Dec 2011 03:04:34 +0000 (11:04 +0800)]
egl_glx: fix eglDestroyContext
Wrong pointers are passed to glXDestroyContext.
Spotted by Brian Paul.
Stuart Abercrombie [Fri, 2 Dec 2011 19:29:38 +0000 (11:29 -0800)]
i965: Fix emit of a MOV with bad destination channel on gen6 math in FPs.
Previously a zero writemask would result in dst_chan == -1, meaning an
unnecessary MOV with the destination register dictated by undefined
memory contents would be emitted before returning. This caused
intermittent GPU hangs, e.g. with glean/texCombine.
Reviewed-by: Eric Anholt <eric@anholt.net>
Eric Anholt [Thu, 1 Dec 2011 22:52:44 +0000 (14:52 -0800)]
mesa: Fix assertions for block size handling in glCompressedTexSubImage2D.
Anything of less than (bw, bh) size is possible when you consider
rectangular textures, and this code is (now) safe for those. Even for
power-of-two textures, width could be 4 for FXT1 while not being
aligned to block size.
Fixes piglit compressedteximage GL_COMPRESSED_RGB_FXT1_3DFX
Reviewed-by: Brian Paul <brianp@vmware.com>
Eric Anholt [Thu, 1 Dec 2011 22:35:18 +0000 (14:35 -0800)]
mesa: Fix glCompressedTexSubImage (and non-Sub) for height == 2 or 1.
Generally this code works with width and height aligned to compressed
blocks, but at the 2x2 and 1x1 levels of a square texture (or height <
bh in general), we were skipping uploading our single row of blocks.
Fixes piglit compressedteximage GL_COMPRESSED_RGBA_S3TC_DXT5_EXT.
Reviewed-by: Brian Paul <brianp@vmware.com>
Eric Anholt [Wed, 30 Nov 2011 20:04:14 +0000 (12:04 -0800)]
mesa: Fix glCompressedTexImage when dstRowStride != srcRowStride.
Since the MapTextureImage changes on Intel, nwn had corruption in the
scrollbar at the load game menu, and corrupted ground textures in the
starting zone. Heroes of Newerth's intro screen was also thoroughly
garbled. A new piglit test "compressedteximage" was created to
regression test this.
The issue was this code now seeing dstRowStride aligned to hardware
requirements instead of a temporary buffer that gets uploaded to
hardware later. The existing code was just trying to memcpy
srcRowStride * height / bh, while the glCompressedTexSubImage2D()
storage code nearby did the correct walking by blockheight rows at a
time. Just reuse the subimage upload instead of duplicating that
logic.
v2: Update comment at the top of the function (suggestion by Joel
Forsberg)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41451
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
Marcin Slusarz [Fri, 11 Nov 2011 19:45:08 +0000 (20:45 +0100)]
nv50/nvc0: fix crash when channel allocation fails
Brian Paul [Thu, 1 Dec 2011 23:37:49 +0000 (16:37 -0700)]
mesa: add casts to fix unpack_SIGNED_GR1616()
We were passing unsigned values to the macro before.
Brian Paul [Thu, 1 Dec 2011 23:37:49 +0000 (16:37 -0700)]
mesa: remove unreachable code in _mesa_unpack_color_span_ubyte()
We checked if srcType == GL_UNSIGNED_BYTE earlier so there was no
way to reach this code. This was left-over code from the GLchan
removal work.
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Brian Paul [Thu, 1 Dec 2011 23:37:49 +0000 (16:37 -0700)]
vbo: remove unreachable _mesa_error() call
If mode is not GL_POINT/LINE/FILL we'll have already reported the
error earlier in the function and returned so we can never get here.
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Brian Paul [Thu, 1 Dec 2011 23:37:49 +0000 (16:37 -0700)]
mesa: move _mesa_error() call in compressedteximage()
We shouldn't call _mesa_error() if the target is a proxy texture.
Errors are handled later in the function.
Fixes a Coverity warning.
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Brian Paul [Thu, 1 Dec 2011 23:37:49 +0000 (16:37 -0700)]
mesa: fix potential mem leak in generate_mipmap_compressed()
Fixes a coverity warning.
Reviewed-by: Vinson Lee <vlee@vmware.com>
Brian Paul [Thu, 1 Dec 2011 23:37:49 +0000 (16:37 -0700)]
glsl: return visit_stop in ir_validate::visit_enter() to silence warning
Brian Paul [Thu, 1 Dec 2011 17:47:31 +0000 (10:47 -0700)]
mesa: fix some minor texstore comments
For the texsubimage commands, we're not mapping the whole image/region.
Brian Paul [Thu, 1 Dec 2011 03:35:02 +0000 (20:35 -0700)]
mesa: rename MESA_FORMAT_RG88_REV to MESA_FORMAT_RG88
R is in the high byte, G in the low byte.
Brian Paul [Thu, 1 Dec 2011 03:35:02 +0000 (20:35 -0700)]
mesa: rename MESA_FORMAT_RG88 to MESA_FORMAT_GR88
To better reflect the component ordering and be consistent with other
format names.
Brian Paul [Thu, 1 Dec 2011 03:35:02 +0000 (20:35 -0700)]
mesa: fix unpacking of RG88_REV texels
R should be in the high byte and G in the low byte for this format.
Kenneth Graunke [Tue, 15 Nov 2011 03:49:54 +0000 (19:49 -0800)]
i965: Make gen6_resolve_implied_move a no-op for MRF sources.
Attempting to move an MRF to a MRF is not only pointless, it will fail
because MRFs are read-only, resulting in garbage in your register.
If we already set up a MRF source, there's nothing to resolve anyway.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Mathias Fröhlich [Thu, 1 Dec 2011 17:31:06 +0000 (18:31 +0100)]
mesa: Renumber the tnl attributes to match VERT_ATTRIB*.
Also renumber the tnl modules vertex attributes to match
the renumbered VERT_ATTRIB_* values.
This should fix
https://bugs.freedesktop.org/show_bug.cgi?id=43353
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>
Tested-by: Vinson Lee <vlee@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Mathias Fröhlich [Thu, 1 Dec 2011 17:29:18 +0000 (18:29 +0100)]
mesa: Extend BITSET64_*_RANGE to work on arbitrary ranges.
The BITSET64_{TEST,SET,CLEAR}_RANGE macros only work on ranges
wither in the lower 32 or in the upper 32 bits of the bitset.
This change extends these macros to work on arbitrary ranges
possibly crossing the bitset word boundary.
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>
Reviewed-by: Brian Paul <brianp@vmware.com>
Stéphane Marchesin [Thu, 10 Nov 2011 00:46:24 +0000 (16:46 -0800)]
i915g: Implement GL_STREAM_* for textures by using untiled textures.
Stéphane Marchesin [Fri, 2 Dec 2011 02:09:18 +0000 (18:09 -0800)]
i915g: Add unsupported PIPE_SHADER_CAP_OUTPUT_READ to silence warnings.
Chia-I Wu [Wed, 30 Nov 2011 04:29:54 +0000 (12:29 +0800)]
docs: list GL_OES_compressed_ETC1_RGB8_texture in 7.12 release notes
Reviewed-by: Brian Paul <brianp@vmware.com>
Chia-I Wu [Tue, 29 Nov 2011 04:49:36 +0000 (12:49 +0800)]
st/mesa: add support for GL_OES_compressed_ETC1_RGB8_texture
Have st/mesa recognize MESA_FORMAT_ETC1_RGB8 then we are good to advertise the
extension.
Reviewed-by: Brian Paul <brianp@vmware.com>
Chia-I Wu [Mon, 28 Nov 2011 16:10:37 +0000 (00:10 +0800)]
gallium: add PIPE_FORMAT_ETC1_RGB8
The format is defined by GL_OES_compressed_ETC1_RGB8_texture.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Chia-I Wu [Mon, 28 Nov 2011 08:57:02 +0000 (16:57 +0800)]
mesa: add support for GL_OES_compressed_ETC1_RGB8_texture
Add support for GL_OES_compressed_ETC1_RGB8_texture to core mesa. There is no
driver support yet.
Unlike desktop GL compressed texture formats, GLES compressed texture formats
usually can only be used with glCompressedTexImage2D. All other gl*Tex*Image*
functions are updated to check for that.
Reviewed-by: Brian Paul <brianp@vmware.com>
Chia-I Wu [Mon, 28 Nov 2011 15:55:31 +0000 (23:55 +0800)]
mesa: add ETC1 decoding routines
The format is defined by GL_OES_compressed_ETC1_RGB8_texture. These routines
will be used in the following commit.
Reviewed-by: Brian Paul <brianp@vmware.com>
Chia-I Wu [Mon, 28 Nov 2011 08:41:10 +0000 (16:41 +0800)]
glapi: regenerate files for GL_OES_compressed_ETC1_RGB8_texture
Reviewed-by: Brian Paul <brianp@vmware.com>
Chia-I Wu [Mon, 28 Nov 2011 08:40:52 +0000 (16:40 +0800)]
glapi: add GL_OES_compressed_ETC1_RGB8_texture for GLES
Reviewed-by: Brian Paul <brianp@vmware.com>
Mathias Fröhlich [Thu, 1 Dec 2011 19:48:10 +0000 (20:48 +0100)]
swrast: Fix signed/unsigned problems with negative strides.
In swrast_map_renderbuffer negative strides lead to
render buffer map pointers that are off by 2^32.
Make sure that intermediate negative values are not
converted to an unsigned.
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>
Reviewed-by: Brian Paul <brianp@vmware.com>
Vinson Lee [Wed, 30 Nov 2011 23:32:16 +0000 (15:32 -0800)]
u_vbuf: Silence uninitialized variable warnings.
Fixes these GCC warnings.
u_vbuf.c: In function ‘u_vbuf_draw_begin’:
u_vbuf.c:839:20: warning: ‘max_index’ may be used uninitialized in this function [-Wuninitialized]
u_vbuf.c:838:20: warning: ‘min_index’ may be used uninitialized in this function [-Wuninitialized]
Signed-off-by: Vinson Lee <vlee@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Alex Deucher [Thu, 1 Dec 2011 00:34:15 +0000 (19:34 -0500)]
r600g: add some new pci ids
Note: this is a candidate for the stable branches.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Brian Paul [Thu, 1 Dec 2011 03:35:02 +0000 (20:35 -0700)]
mesa: fix unpack_ARGB1555_REV()
We weren't doing the necessary byte swap.
v2: use same arithmetic as unpack_ARGB1555() to be consistent.
Reviewed-by: Michel Dänzer <michel@daenzer.net>
Brian Paul [Thu, 1 Dec 2011 03:35:02 +0000 (20:35 -0700)]
mesa: fix indentation in attrib.c
Eric Anholt [Wed, 23 Nov 2011 18:20:12 +0000 (10:20 -0800)]
i965/fs: Fix regression in fbo-alphatest-nocolor.
In the refactor for handling user-defined out params, we failed to set
up the new color output tracking when there was no color drawbuffer in
place but alpha testing was on. Just always set up at least one when
handling gl_FragColor, since we won't make use of its value unless we
need to.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=42806
Eric Anholt [Wed, 23 Nov 2011 18:13:39 +0000 (10:13 -0800)]
i965/fs: Make register file enum 0 be the undefined register file.
In
6d874d0ee18b3694c49e0206fa519bd8b746ec24, I checked whether a
register that had been stored was BAD_FILE (as opposed to a legitimate
GRF), but actually the unset register was ARF NULL because it had been
memset to 0. Finding BAD_FILE for unset values in debugging was my
intention with that file, so make it the case more often by
rearranging the enum. There was only one place we relied on the magic
enum register_file to hardware register file correspondance anyway.
Eric Anholt [Wed, 23 Nov 2011 18:01:39 +0000 (10:01 -0800)]
i965: Don't perform the precompile on fragment shaders by default.
It is useful to have this option for shader-db, and it was also good
at the time where we were rejecting shaders due to various internal
limits we hadn't supported yet. However, at this point the precompile
step takes extra time (since not all NOS is known at link time) and
spews misleading debug in the common case of debugging a real app.
This is left in place for VS, where we still have a couple of codegen
failure paths that result in link failure through precompile. Those
need to be fixed.
shader-db can still get at the debug info it wants using
"shader_precompile=true" driconf option. Long term, we can probably
build a good-enough app for shader-db to trigger real codegen.
Kai Wasserbäch [Tue, 29 Nov 2011 21:36:02 +0000 (22:36 +0100)]
gallium/failover: Remove the deprecated module.
Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Signed-off-by: José Fonseca <jfonseca@vmware.com>
Brian Paul [Wed, 30 Nov 2011 14:09:46 +0000 (07:09 -0700)]
st/mesa: fix indentation
Brian Paul [Tue, 29 Nov 2011 14:44:20 +0000 (07:44 -0700)]
mesa: use _mesa_is_bufferobj() in update_array()