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Alexander Richardson [Mon, 25 Jun 2018 16:49:20 +0000 (16:49 +0000)]
Add Triple::isMIPS()/isMIPS32()/isMIPS64(). NFC
There are quite a few if statements that enumerate all these cases. It gets
even worse in our fork of LLVM where we also have a Triple::cheri (which
is mips64 + CHERI instructions) and we had to update all if statements that
check for Triple::mips64 to also handle Triple::cheri. This patch helps to
reduce our diff to upstream and should also make some checks more readable.
Reviewed By: atanasyan
Differential Revision: https://reviews.llvm.org/D48548
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335493
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Matt Arsenault [Mon, 25 Jun 2018 16:17:48 +0000 (16:17 +0000)]
AMDGPU/GlobalISel: Add support for llvm.amdgcn.kernarg.segment.ptr
Note a normal select test is not currently possible because this
relies on input registers tracked in SIMachineFunctionInfo which
are not currently serializable in MIR, but this does work end-to-end
from the IR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335490
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Matt Arsenault [Mon, 25 Jun 2018 16:05:55 +0000 (16:05 +0000)]
StackSlotColoring: Decide colors per stack ID
I thought I fixed this in r308673, but that fix was
very broken. The assumption that any frame index can be used
in place of another was more widespread than I realized.
Even when stack slot sharing was disabled, this was still
replacing frame index uses with a different ID with a different
stack slot.
Really fix this by doing the coloring per-stack ID, so all of
the coloring logically done in a separate namespace. This is a lot
simpler than trying to figure out how to change the color if
the stack ID is different.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335488
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Matt Arsenault [Mon, 25 Jun 2018 15:42:20 +0000 (15:42 +0000)]
AMDGPU: Remove commented out code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335486
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Matt Arsenault [Mon, 25 Jun 2018 15:42:12 +0000 (15:42 +0000)]
AMDGPU/GlobalISel: Fix G_IMPLICIT_DEF for pointers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335485
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Wei Mi [Mon, 25 Jun 2018 15:40:31 +0000 (15:40 +0000)]
[SampleFDO] Add an option to turn on/off warning about samples unused.
If a function has sample to use, but cannot use them because of no debug
information, currently a warning will be issued to inform the missing
opportunity.
This warning assumes the binary generating the profile and the binary using
the profile are similar enough. It is not always the case. Sometimes even
if the binaries are not quite similar, we may still get some benefit by
using sampleFDO. In those cases, we may still want to apply sampleFDO but
not want to see a lot of such warnings pop up.
The patch adds an option for the warning.
Differential Revision: https://reviews.llvm.org/D48510
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335484
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David Green [Mon, 25 Jun 2018 15:13:26 +0000 (15:13 +0000)]
[DA] Delinearise AddRecs if we can prove they don't wrap
We can prove that some delinearized subscripts do not wrap around to become
negative by the fact that they are from inbound geps of load/store locations.
This helps improve the delinearisation in cases where we can't prove that they
are non-negative from SCEV alone.
Differential Revision: https://reviews.llvm.org/D48481
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335481
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Matt Arsenault [Mon, 25 Jun 2018 14:29:04 +0000 (14:29 +0000)]
AMDGPU: Respect align argument parameter
This should avoid relying on the pointee type
to get the alignment, particularly since pointee
types are supposed to be removed at some point.
Also fixes not getting the alignment for unsized types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335478
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Artur Pilipenko [Mon, 25 Jun 2018 13:51:11 +0000 (13:51 +0000)]
SafepointIRVerifier should ignore dead blocks and dead edges
Not only should SafepointIRVerifier ignore unreachable blocks (as suggested in https://reviews.llvm.org/D47011) but it also has to ignore dead blocks.
In @test2 (see the new tests):
br i1 true, label %right, label %left
left:
...
right:
...
merge:
%val = phi i8 addrspace(1)* [ ..., %left ], [ ..., %right ]
use %val
both left and right branches are reachable.
If they collide then SafepointIRVerifier reports an error.
Because of the foldable branch condition GVN finds the left branch dead and removes the phi node entry that merges values from right and left. Then the use comes from the right branch. This results in no collision.
So, SafepointIRVerifier ends up in different results depending on either GVN is run or not.
To solve this issue this patch adds Dead Block detection to SafepointIRVerifier which can ignore dead blocks while validating IR. The Dead Block detection algorithm is taken from GVN but modified to not split critical edges. That is needed to keep CFG unchanged by SafepointIRVerifier.
Patch by Yevgeny Rouban.
Reviewed By: anna, apilipenko, DaniilSuchkov
Differential Revision: https://reviews.llvm.org/D47441
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335473
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Krzysztof Parzyszek [Mon, 25 Jun 2018 13:46:41 +0000 (13:46 +0000)]
Improve handling of COPY instructions with identical value numbers
Testcases provided by Tim Renouf.
Differential Revision: https://reviews.llvm.org/D48102
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335472
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Clement Courbet [Mon, 25 Jun 2018 13:44:27 +0000 (13:44 +0000)]
[llvm-exegesis][NFC] Remove unnecessary member variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335470
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Sanjay Patel [Mon, 25 Jun 2018 13:40:54 +0000 (13:40 +0000)]
[IR] avoid -Wdocumentation spew about HTML tags
There's probably a better solution, but adding spaces
in the IR vector examples sidesteps the problem without
uglifying the plain text.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335468
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Clement Courbet [Mon, 25 Jun 2018 13:39:50 +0000 (13:39 +0000)]
[llvm-exegesis] Fix warning in r22752: Initialize IsSnippetSetupComplete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335467
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Clement Courbet [Mon, 25 Jun 2018 13:12:02 +0000 (13:12 +0000)]
[llvm-exegesis] Generate snippet setup code.
Summary:
This ensures that the snippet always sees the same values for registers,
making measurements reproducible.
This will also allow exploring different values.
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48542
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335465
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Artur Pilipenko [Mon, 25 Jun 2018 12:58:13 +0000 (12:58 +0000)]
Revert change 335077 "[InlineSpiller] Fix a crash due to lack of forward progress from remat specifically for STATEPOINT"
This change caused widespread assertion failures in our downstream testing:
lib/CodeGen/LiveInterval.cpp:409: bool llvm::LiveRange::overlapsFrom(const llvm::LiveRange&, llvm::LiveRange::const_iterator) const: Assertion `!empty() && "empty range"' failed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335462
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Artur Pilipenko [Mon, 25 Jun 2018 12:55:58 +0000 (12:55 +0000)]
Revert change 335091.
It adds extra test for the change 335077, which is also to be reverted as it causes test failures in downstream testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335461
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Simon Pilgrim [Mon, 25 Jun 2018 11:46:24 +0000 (11:46 +0000)]
Use APInt[] bit access to avoid "32-bit shift implicitly converted to 64 bits" MSVC warning (again). NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335457
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Clement Courbet [Mon, 25 Jun 2018 11:44:29 +0000 (11:44 +0000)]
[llvm-exegesis][NFC] Simplify BenchmarkRunner ctor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335456
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Simon Pilgrim [Mon, 25 Jun 2018 11:38:27 +0000 (11:38 +0000)]
Use APInt[] bit access to avoid "32-bit shift implicitly converted to 64 bits" MSVC warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335454
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Clement Courbet [Mon, 25 Jun 2018 11:22:23 +0000 (11:22 +0000)]
[llvm-exegesis][NFC] clang-format
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335452
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Simon Pilgrim [Mon, 25 Jun 2018 11:19:05 +0000 (11:19 +0000)]
Fix -Wparentheses gcc warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335451
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Clement Courbet [Mon, 25 Jun 2018 11:12:30 +0000 (11:12 +0000)]
[llvm-exegesis][NFC] Fix `Operand` class comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335450
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Craig Topper [Mon, 25 Jun 2018 06:05:37 +0000 (06:05 +0000)]
[X86] Block commuting operand 1 of FMA*_Int instructions in findThreeSrcCommutedOpIndices. Remove uncommutable returns from getThreeSrcCommuteCase/getFMA3OpcodeToCommuteOperands.
We should be blocking the operand while we are in the routine that tries to find commutable operand indices. Doing it later means we might have missed out on another valid set of operands we could have commuted.
The intrinsic case was the only case that could really prevent commuting in getFMA3OpcodeToCommuteOperands. All the other cases in getThreeSrcCommuteCase were not reachable conditions as they were protected by findThreeSrcCommutedOpIndices.
With that abort case pushed earlier, we can remove all the abort checks and replace with asserts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335446
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George Burgess IV [Mon, 25 Jun 2018 05:30:36 +0000 (05:30 +0000)]
[MSSA] Add domination number verifier; NFC
It's easy for domination numbers to get out-of-date, and this is no more
costly than any of the other verifiers we already have, so it seems nice
to have.
A stage3 build with this Works On My Machine, so this hasn't caught any
bugs... yet. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335444
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Zachary Turner [Mon, 25 Jun 2018 04:38:03 +0000 (04:38 +0000)]
One more build fix for non MSVC compilers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335443
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Zachary Turner [Mon, 25 Jun 2018 04:35:35 +0000 (04:35 +0000)]
Try to fix build error on non MSVC compilers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335442
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Zachary Turner [Mon, 25 Jun 2018 03:13:27 +0000 (03:13 +0000)]
Fix CRLF line endings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335441
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Zachary Turner [Mon, 25 Jun 2018 03:13:09 +0000 (03:13 +0000)]
Add a TaskQueue that can serialize work on a ThreadPool.
We have ThreadPool, which can execute work asynchronously on N
background threads, but sometimes you need to make sure the work
is executed asynchronously but also serially. That is, if task
B is enqueued after task A, then task B should not begin until
task A has completed. This patch adds such a class.
Differential Revision: https://reviews.llvm.org/D48240
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335440
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Heejin Ahn [Mon, 25 Jun 2018 01:20:21 +0000 (01:20 +0000)]
[WebAssembly] Add WebAssemblyException information analysis
Summary:
A WebAssemblyException object contains BBs that belong to a 'catch' part
of the try-catch-end structure. Because CFGSort requires all the BBs
within a catch part to be sorted together as it does for loops, this
pass calculates the nesting structure of catch part of exceptions in a
function. Now this assumes the use of Windows EH instructions.
Reviewers: dschuff, majnemer
Subscribers: jfb, mgorny, sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D44134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335439
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Heejin Ahn [Mon, 25 Jun 2018 01:07:11 +0000 (01:07 +0000)]
[WebAssembly] Add WebAssemblyLateEHPrepare pass
Summary:
Add WebAssemblyLateEHPrepare pass that does several small jobs for
exception handling. This runs before CFGSort, and is different from
WasmEHPrepare pass that runs before ISel, even though the names are
similar.
Reviewers: dschuff, majnemer
Subscribers: sbc100, jgravelle-google, sunfish, mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D46803
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335438
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Craig Topper [Mon, 25 Jun 2018 01:01:47 +0000 (01:01 +0000)]
[X86] Simplify some code by using isOneConstant. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335437
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Craig Topper [Mon, 25 Jun 2018 00:21:53 +0000 (00:21 +0000)]
[X86] Remove the changes to combineScalarToVector made in r335037.
They appear to be untested other than the test case for p37879.ll and I believe we should be using SimplifyDemandedElts here to handle these cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335436
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Craig Topper [Mon, 25 Jun 2018 00:05:09 +0000 (00:05 +0000)]
[X86] Reduce the number of patterns needed for masked scalar ceil/floor isel.
The scalar to vector on the mask register should not be part of the patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335435
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Brad Smith [Sun, 24 Jun 2018 15:44:47 +0000 (15:44 +0000)]
[mips][ias] Enable IAS by default for OpenBSD / FreeBSD mips64/mips64el.
Reviewers: atanasyan
Differential Review: https://reviews.llvm.org/D31557
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335434
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Sanjay Patel [Sun, 24 Jun 2018 14:37:30 +0000 (14:37 +0000)]
[DAGCombiner] eliminate setcc bool math when input is low-bit of some value
This patch has the same motivating example as D48466:
define void @foo(i64 %x, i32 %c.0282.in, i32 %d.0280, i32* %ptr0, i32* %ptr1) {
%c.0282 = and i32 %c.0282.in,
268435455
%a16 = lshr i64 32508, %x
%a17 = and i64 %a16, 1
%tobool = icmp eq i64 %a17, 0
%. = select i1 %tobool, i32 1, i32 2
%.286 = select i1 %tobool, i32 27, i32 26
%shr97 = lshr i32 %c.0282, %.
%shl98 = shl i32 %c.0282.in, %.286
%or99 = or i32 %shr97, %shl98
%shr100 = lshr i32 %d.0280, %.
%shl101 = shl i32 %d.0280, %.286
%or102 = or i32 %shr100, %shl101
store i32 %or99, i32* %ptr0
store i32 %or102, i32* %ptr1
ret void
}
...but I'm trying to kill the setcc bool math sooner rather than later.
By matching a larger pattern that includes both the low-bit mask and the trailing add/sub,
we can create a universally good fold because we always eliminate the condition code
intermediate value.
Here are Alive proofs for these (currently instcombine folds the 'add' variants, but
misses the 'sub' patterns):
https://rise4fun.com/Alive/Gsyp
Name: sub of zext cmp mask
%a = and i8 %x, 1
%c = icmp eq i8 %a, 0
%z = zext i1 %c to i32
%r = sub i32 C1, %z
=>
%optional_cast = zext i8 %a to i32
%r = add i32 %optional_cast, C1-1
Name: add of zext cmp mask
%a = and i32 %x, 1
%c = icmp eq i32 %a, 0
%z = zext i1 %c to i8
%r = add i8 %z, C1
=>
%optional_cast = trunc i32 %a to i8
%r = sub i8 C1+1, %optional_cast
All of the tests look like improvements or neutral to me. But it is possible that x86
test+set+bitop is better than what we now show here. I suspect we could do better by
adding another fold for the 'sub' variants.
We start with select-of-constant in IR in the larger motivating test, so that's why I
included tests with selects. Proofs for those variants:
https://rise4fun.com/Alive/Bx1
Name: true const is bigger
Pre: C2 == (C1 + 1)
%a = and i8 %x, 1
%c = icmp eq i8 %a, 0
%r = select i1 %c, i64 C2, i64 C1
=>
%z = zext i8 %a to i64
%r = sub i64 C2, %z
Name: false const is bigger
Pre: C2 == (C1 + 1)
%a = and i8 %x, 1
%c = icmp eq i8 %a, 0
%r = select i1 %c, i64 C1, i64 C2
=>
%z = zext i8 %a to i64
%r = add i64 C1, %z
Differential Revision: https://reviews.llvm.org/D48466
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335433
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Craig Topper [Sun, 24 Jun 2018 06:56:49 +0000 (06:56 +0000)]
[X86] Regroup some isel patterns. NFC
For some reason the 64-bit patterns were separated from their 8/16/32-bit friends, but only for add/sub/mul. For and/or/xor they were together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335429
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Craig Topper [Sun, 24 Jun 2018 06:29:50 +0000 (06:29 +0000)]
[X86] Rename VFPCLASSSS and VFPCLASSSD internal instruction names to include a Z to match other EVEX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335428
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Zachary Turner [Sun, 24 Jun 2018 01:48:25 +0000 (01:48 +0000)]
Also forward declare BitScanReverse.
With the removal of intrin.h in an earlier patch, the intrinsics
that we were actually using were manually re-declared, however
several of them were missed leading to compilation failures with
MSVC. Fix those.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335427
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Brad Smith [Sat, 23 Jun 2018 22:02:59 +0000 (22:02 +0000)]
Add OpenBSD support to the Threading code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335426
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Brad Smith [Sat, 23 Jun 2018 21:43:27 +0000 (21:43 +0000)]
[CMake] Do not use --gc-sections on OpenBSD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335425
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Brad Smith [Sat, 23 Jun 2018 21:26:44 +0000 (21:26 +0000)]
[CMake] Support building shared library for OpenBSD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335424
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Jonas Devlieghere [Sat, 23 Jun 2018 19:04:10 +0000 (19:04 +0000)]
[llc] Fix sanitizer failure.
Store the string on the stack rather than just the StringRef.
Fix sanitizer bots:
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/19948
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap-msan/builds/5500
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335423
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Duncan P. N. Exon Smith [Sat, 23 Jun 2018 18:39:44 +0000 (18:39 +0000)]
ADT: Use EBO to shrink SmallVector size 1
SmallVectorStorage is empty when its size is 1; use inheritance so that
the empty base class optimization kicks in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335421
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Jonas Devlieghere [Sat, 23 Jun 2018 16:51:10 +0000 (16:51 +0000)]
[llc] Use WithColor for printing errors/warnings
Use the WithColor helper from support to print errors and warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335418
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Jonas Devlieghere [Sat, 23 Jun 2018 16:50:09 +0000 (16:50 +0000)]
[llvm-config] Use WithColor for printing errors.
Use the WithColor helper from support to print errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335417
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Jonas Devlieghere [Sat, 23 Jun 2018 16:49:07 +0000 (16:49 +0000)]
[llvm-mt] Use WithColor for printing errors.
Use the WithColor helper from support to print errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335416
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Jonas Devlieghere [Sat, 23 Jun 2018 16:48:03 +0000 (16:48 +0000)]
[TableGen] Use WithColor for printing errors/warnings
Use the WithColor helper from support to print errors and warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335415
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Craig Topper [Sat, 23 Jun 2018 06:15:04 +0000 (06:15 +0000)]
[X86] Make %eiz usage in 64-bit mode, force a 0x67 address size prefix. Fix some test CHECK lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335414
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Craig Topper [Sat, 23 Jun 2018 06:03:48 +0000 (06:03 +0000)]
[X86] Teach disassembler to use %eip instead of %rip when 0x67 prefix is used on a rip-relative address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335413
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Craig Topper [Sat, 23 Jun 2018 05:53:00 +0000 (05:53 +0000)]
[X86][AsmParser] Improve base/index register checks.
-Ensure EIP isn't used with an index reigster.
-Ensure EIP isn't used as index register.
-Ensure base register isn't a vector register.
-Ensure eiz/riz usage matches the size of their base register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335412
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Stanislav Mekhanoshin [Sat, 23 Jun 2018 04:01:28 +0000 (04:01 +0000)]
Fix invariant fdiv hoisting in LICM
FDiv is replaced with multiplication by reciprocal and invariant
reciprocal is hoisted out of the loop, while multiplication remains
even if invariant.
Switch checks for all invariant operands and only invariant
denominator to fix the issue.
Differential Revision: https://reviews.llvm.org/D48447
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335411
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Reid Kleckner [Sat, 23 Jun 2018 03:05:39 +0000 (03:05 +0000)]
[AMDGPU] Update includes for intrinsic changes :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335409
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Lang Hames [Sat, 23 Jun 2018 02:22:10 +0000 (02:22 +0000)]
[ORC] Fix formatting and list pending queries in VSO::dump.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335408
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Reid Kleckner [Sat, 23 Jun 2018 02:02:38 +0000 (02:02 +0000)]
[IR] Split Intrinsics.inc into enums and implementations
Implements PR34259
Intrinsics.h is a very popular header. Most LLVM TUs care about things
like dbg_value, but they don't care how they are implemented. After I
split these out, IntrinsicImpl.inc is 1.7 MB, so this saves each LLVM TU
from scanning 1.7 MB of source that gets pre-processed away.
It also means we can modify intrinsic properties without triggering a
full rebuild, but that's probably less of a win.
I think the next best thing to do would be to split out the target
intrinsics into their own header. Very, very few TUs care about
target-specific intrinsics. It's very hard to split up the target
independent intrinsics like llvm.expect, assume, and dbg.value, though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335407
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Reid Kleckner [Sat, 23 Jun 2018 01:19:49 +0000 (01:19 +0000)]
Avoid including intrin.h from MathExtras.h
This is repeatably worth 0.3s compile time on MathExtras.cpp. This is a
very popular header, and it basically pulls all Intel intrinsics into
every LLVM TU. Let's not do that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335406
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Fangrui Song [Sat, 23 Jun 2018 00:15:33 +0000 (00:15 +0000)]
[ELF] Change isSectionData to exclude SHF_EXECINSTR
Summary:
This affects what sections are displayed as "DATA" in llvm-objdump.
The other user llvm-size is unaffected.
Before, a "TEXT" section is also "DATA", which seems weird.
The sh_flags condition matches that of bfd's SEC_DATA but the sh_type
condition uses (== SHF_PROGBITS) instead of bfd's (!= SHT_NOBITS).
bfd's SEC_DATA is not appealing as so many sections will be shown as DATA.
Reviewers: jyknight, Bigcheese
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D48472
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335405
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Craig Topper [Sat, 23 Jun 2018 00:03:20 +0000 (00:03 +0000)]
[X86][AsmParser] Rework that allows (%dx) to be used in place of %dx with in/out instructions.
Previously, to support (%dx) we left a wide open hole in our 16-bit memory address checking. This let this address value be used with any instruction without error in the parser. It would later fail in the encoder with an assertion failure on debug builds and who knows what on release builds.
This patch passes the mnemonic down to the memory operand parsing function so we can allow the (%dx) form only on specific instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335403
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Reid Kleckner [Fri, 22 Jun 2018 23:53:22 +0000 (23:53 +0000)]
[RuntimeDyld] Implement the ELF PIC large code model relocations
Prerequisite for https://reviews.llvm.org/D47211 which improves our ELF
large PIC codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335402
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Eli Friedman [Fri, 22 Jun 2018 22:58:55 +0000 (22:58 +0000)]
[LoopReroll] Rewrite induction variable rewriting.
This gets rid of a bunch of weird special cases; instead, just use SCEV
rewriting for everything. In addition to being simpler, this fixes a
bug where we would use the wrong stride in certain edge cases.
The one bit I'm not quite sure about is the trip count handling,
specifically the FIXME about overflow. In general, I think we need to
widen the exit condition, but that's probably not profitable if the new
type isn't legal, so we probably need a check somewhere. That said, I
don't think I'm making the existing problem any worse.
As a followup to this, a bunch of IV-related code in root-finding could
be cleaned up; with SCEV-based rewriting, there isn't any reason to
assume a loop will have exactly one or two PHI nodes.
Differential Revision: https://reviews.llvm.org/D45191
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335400
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George Burgess IV [Fri, 22 Jun 2018 22:34:07 +0000 (22:34 +0000)]
[MSSA] Remove incorrect comment + `auto`ify dyn_cast results; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335399
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Craig Topper [Fri, 22 Jun 2018 22:28:39 +0000 (22:28 +0000)]
[X86][AsmParser] Keep track of whether an explicit scale was specified while parsing an address in Intel syntax. Use it for improved error checking.
This allows us to check these:
-16-bit addressing doesn't support scale so we should error if we find one there.
-Multiplying ESP/RSP by a scale even if the scale is 1 should be an error because ESP/RSP can't be an index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335398
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Fangrui Song [Fri, 22 Jun 2018 22:20:10 +0000 (22:20 +0000)]
[llvm-size] Make global variables static
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335397
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Sanjay Patel [Fri, 22 Jun 2018 22:07:26 +0000 (22:07 +0000)]
[x86] add more tests for bit hacking opportunities with setcc; NFC
Missed cases where the input and output are the same size in rL335391.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335396
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Sanjay Patel [Fri, 22 Jun 2018 22:06:33 +0000 (22:06 +0000)]
[PowerPC] add more tests for bit hacking opportunities with setcc; NFC
Missed cases where the input and output are the same size in rL335390.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335395
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Craig Topper [Fri, 22 Jun 2018 21:57:24 +0000 (21:57 +0000)]
[X86][AsmParser] In Intel syntax make sure we support ESP/RSP being the second register in memory expressions like [EAX+ESP].
By default, the second register gets assigned to the index register slot. But ESP can't be an index register so we need to swap it with the other register.
There's still a slight bug that we allow [EAX+ESP*1]. The existence of the multiply even though its with 1 should force ESP to the index register and trigger an error, but it doesn't currently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335394
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Matt Davis [Fri, 22 Jun 2018 21:35:26 +0000 (21:35 +0000)]
[llvm-mca] Remove unnecessary include and forward decl in RCU. NFC.
The DispatchUnit is no longer a dependency of RCU, so this patch removes a
stale include and forward decl. This patch also cleans up some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335392
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Sanjay Patel [Fri, 22 Jun 2018 21:16:54 +0000 (21:16 +0000)]
[x86] add tests for bit hacking opportunities with setcc; NFC
We likely gave up on folding some select-of-constants patterns in
IR with rL331486, and we need to recover those in the DAG.
The tests without select are based on our current DAGCombiner
optimizations for select-of-constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335391
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Sanjay Patel [Fri, 22 Jun 2018 21:16:29 +0000 (21:16 +0000)]
[PowerPC] add tests for bit hacking opportunities with setcc; NFC
We likely gave up on folding some select-of-constants patterns in
IR with rL331486, and we need to recover those in the DAG.
The tests without select are based on our current DAGCombiner
optimizations for select-of-constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335390
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Craig Topper [Fri, 22 Jun 2018 21:09:31 +0000 (21:09 +0000)]
[X86] Add test cases showing missed select simplifcation for MCU when icmp is in a slightly different form.
These test cases show that the "(select (and (x , 0x1) == 0), y, (z ^ y) ) -> (-(and (x , 0x1)) & z ) ^ y" doesn't work if the select condition is changed to (and (x, 0x1) != 1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335389
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Aditya Nandakumar [Fri, 22 Jun 2018 20:58:51 +0000 (20:58 +0000)]
[GISel]: Add G_ADDRSPACE_CAST Opcode
Added IRTranslator support for addrspacecast.
https://reviews.llvm.org/D48469
reviewed by: volkan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335388
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Fangrui Song [Fri, 22 Jun 2018 20:29:42 +0000 (20:29 +0000)]
[gdb] Use Latin-1 to decode StringRef
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335387
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Tobias Edler von Koch [Fri, 22 Jun 2018 20:23:21 +0000 (20:23 +0000)]
Re-land "[LTO] Enable module summary emission by default for regular LTO"
Since we are now producing a summary also for regular LTO builds, we
need to run the NameAnonGlobals pass in those cases as well (the
summary cannot handle anonymous globals).
See https://reviews.llvm.org/D34156 for details on the original change.
This reverts commit
6c9ee4a4a438a8059aacc809b2dd57128fccd6b3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335385
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Craig Topper [Fri, 22 Jun 2018 20:20:38 +0000 (20:20 +0000)]
[X86] Don't accept (%si,%bp) 16-bit address expressions.
The second register is the index register and should only be %si or %di if used with a base register. And in that case the base register should be %bp or %bx.
This makes us compatible with gas.
We do still need to support both orders with Intel syntax which uses [bp+si] and [si+bp]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335384
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Craig Topper [Fri, 22 Jun 2018 19:42:21 +0000 (19:42 +0000)]
[X86][AsmParser] Allow (%bp,%si) and (%bp,%di) to be encoded without using a zero displacement.
(%bp) can't be encoded without a displacement. The encoding is instead used for displacement alone. So a 1 byte displacement of 0 must be used. But if there is an index register we can encode without a displacement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335379
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Konstantin Zhuravlyov [Fri, 22 Jun 2018 19:23:18 +0000 (19:23 +0000)]
AMDHSA: Put old assembler docs back
Until we switch to code object v3 by default.
Follow up for https://reviews.llvm.org/D47736.
Differential Revision: https://reviews.llvm.org/D48497
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335378
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Simon Pilgrim [Fri, 22 Jun 2018 18:31:57 +0000 (18:31 +0000)]
[X86][SSE] Add sdiv by (nonuniform) minus one tests (PR37119)
Test cases from D45806
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335376
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Craig Topper [Fri, 22 Jun 2018 17:50:40 +0000 (17:50 +0000)]
[X86][AsmParser] Check for invalid 16-bit base register in Intel syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335373
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Craig Topper [Fri, 22 Jun 2018 17:15:58 +0000 (17:15 +0000)]
[X86] Don't allow ESP/RSP to be used as an index register in assembly.
Fixes PR37892
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335370
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Alina Sbirlea [Fri, 22 Jun 2018 17:14:35 +0000 (17:14 +0000)]
[LoopUnswitch]Fix comparison for DomTree updates.
Summary:
In LoopUnswitch when replacing a branch Parent -> Succ with a conditional
branch Parent -> True & Parent->False, the DomTree updates should insert an edge for
each of True/False if True/False are different than Succ, and delete Parent->Succ edge
if both are different. The comparison with Succ appears to be incorect,
it's comparing with Parent instead.
There is no test failing either before or after this change, but it seems to me this is
the right way to do the update.
Reviewers: chandlerc, kuhar
Subscribers: sanjoy, jlebar, llvm-commits
Differential Revision: https://reviews.llvm.org/D48457
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335369
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Andrea Di Biagio [Fri, 22 Jun 2018 17:03:40 +0000 (17:03 +0000)]
[llvm-mca] Remove redundant call. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335368
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Easwaran Raman [Fri, 22 Jun 2018 17:01:13 +0000 (17:01 +0000)]
[X86] Add a test to show missed opportunity to generate vfnmadd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335367
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Krzysztof Parzyszek [Fri, 22 Jun 2018 16:38:38 +0000 (16:38 +0000)]
Initialize LiveRegs once in BranchFolder::mergeCommonTails
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335365
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Simon Pilgrim [Fri, 22 Jun 2018 16:37:34 +0000 (16:37 +0000)]
[SLPVectorizer] Support alternate opcodes in tryToVectorizeList
Enable tryToVectorizeList to support InstructionsState alternate opcode patterns at a root (build vector etc.) as well as further down the vectorization tree.
NOTE: This patch reduces some of the debug reporting if there are opcode mismatches - I can try to add it back if it proves a problem. But it could get rather messy trying to provide equivalent verbose debug strings via getSameOpcode etc.
Differential Revision: https://reviews.llvm.org/D48488
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335364
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Andrea Di Biagio [Fri, 22 Jun 2018 16:37:05 +0000 (16:37 +0000)]
[llvm-mca] Set the operand ID for implicit register reads/writes. NFC
Also, move the definition of InstRef at the end of Instruction.h to avoid a
forward declaration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335363
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Matt Davis [Fri, 22 Jun 2018 16:17:26 +0000 (16:17 +0000)]
[llvm-mca] Introduce a sequential container of Stages
Summary:
Remove explicit stages and introduce a list of stages.
A pipeline should be composed of an arbitrary list of stages, and not any
predefined list of stages in the Backend. The Backend should not know of any
particular stage, rather it should only be concerned that it has a list of
stages, and that those stages will fulfill the contract of what it means to be
a Stage (namely pre/post/execute a given instruction).
For now, we leave the original set of stages defined in the Backend ctor;
however, I imagine these will be moved out at a later time.
This patch makes an adjustment to the semantics of Stage::isReady.
Specifically, what the Backend really needs to know is if a Stage has
unfinished work. With that said, it is more appropriately renamed
Stage::hasWorkToComplete(). This change will clean up the check in
Backend::run(), allowing us to query each stage to see if there is unfinished
work, regardless of what subclass a stage might be. I feel that this change
simplifies the semantics too, but that's a subjective statement.
Given how RetireStage and ExecuteStage handle data in their preExecute(), I've
had to change the order of Retire and Execute in our stage list. Retire must
complete any of its preExecute actions before ExecuteStage's preExecute can
take control. This is mainly because both stages utilize the RCU. In the
meantime, I want to see if I can adjust that or remove that coupling.
Reviewers: andreadb, RKSimon, courbet
Reviewed By: andreadb
Subscribers: tschuett, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D46907
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335361
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Simon Pilgrim [Fri, 22 Jun 2018 16:10:26 +0000 (16:10 +0000)]
[SLPVectorizer] reorderAltShuffleOperands should just take InstructionsState. NFCI.
All calls were extracting the InstructionsState Opcode/AltOpcode values so we might as well pass it directly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335359
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Paul Robinson [Fri, 22 Jun 2018 15:19:45 +0000 (15:19 +0000)]
Fix test again, try to keep all targets happy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335356
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Paul Robinson [Fri, 22 Jun 2018 15:07:26 +0000 (15:07 +0000)]
Fix test, nop is not always 1 byte
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335353
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Paul Robinson [Fri, 22 Jun 2018 14:16:11 +0000 (14:16 +0000)]
[DWARFv5] Allow ".loc 0" to refer to the root file.
DWARF v5 explicitly represents file #0 in the line table. Prior
versions did not, so ".loc 0" is still an error in those cases.
Differential Revision: https://reviews.llvm.org/D48452
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335350
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Simon Pilgrim [Fri, 22 Jun 2018 14:04:06 +0000 (14:04 +0000)]
[SLPVectorizer] Relax alternate opcodes to accept any BinaryOperator pair
SLP currently only accepts (F)Add/(F)Sub alternate counterpart ops to be merged into an alternate shuffle.
This patch relaxes this to accept any pair of BinaryOperator opcodes instead, assuming the target's cost model accepts the vectorization+shuffle.
Differential Revision: https://reviews.llvm.org/D48477
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335349
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Simon Pilgrim [Fri, 22 Jun 2018 13:53:58 +0000 (13:53 +0000)]
[SLPVectorizer][X86] Add alternate opcode tests for simple build vector cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335348
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Sanjay Patel [Fri, 22 Jun 2018 13:44:42 +0000 (13:44 +0000)]
[InstCombine] add shuffle+binops test from PR37806; NFC
This one shows another pattern that we'll need to match
in some cases, but the current ordering of folds allows
us to match this as 2 binops before simplification takes
place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335347
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Sanjay Patel [Fri, 22 Jun 2018 13:19:25 +0000 (13:19 +0000)]
[InstCombine] add tests for shuffle-with-different-binops; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335345
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Sanjay Patel [Fri, 22 Jun 2018 12:46:16 +0000 (12:46 +0000)]
[InstCombine] rearrange shuffle-of-binops logic; NFC
The commutative matcher makes things more complicated
here, and I'm planning an enhancement where this
form is more readable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335343
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Simon Pilgrim [Fri, 22 Jun 2018 12:41:48 +0000 (12:41 +0000)]
[X86] Regenerate tests to include fma comments
Noticed in the review of D48467
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335342
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Gabor Buella [Fri, 22 Jun 2018 12:01:43 +0000 (12:01 +0000)]
[X86] Add notes to a few intrinsics
This a change corresponding to the clang change in
https://reviews.llvm.org/D45616
Reviewers: craig.topper, uriel.k, RKSimon, andrew.w.kaylor, spatel, scanon, efriedma
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D48280
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335340
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George Rimar [Fri, 22 Jun 2018 10:53:47 +0000 (10:53 +0000)]
Recommit r335333 "[MC] - Add .stack_size sections into groups and link them with .text"
With compilation fix.
Original commit message:
D39788 added a '.stack-size' section containing metadata on function stack sizes
to output ELF files behind the new -stack-size-section flag.
This change does following two things on top:
1) Imagine the case when there are -ffunction-sections flag given and there are text sections in COMDATs.
The patch adds a '.stack-size' section into corresponding COMDAT group, so that linker will be able to
eliminate them fast during resolving the COMDATs.
2) Patch sets a SHF_LINK_ORDER flag and links '.stack-size' with the corresponding .text.
With that linker will be able to do -gc-sections on dead stack sizes sections.
Differential revision: https://reviews.llvm.org/D46874
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335336
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Simon Pilgrim [Fri, 22 Jun 2018 10:48:02 +0000 (10:48 +0000)]
[IR] Use Instruction::isBinaryOp helper instead of raw enum range tests. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335335
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George Rimar [Fri, 22 Jun 2018 10:27:33 +0000 (10:27 +0000)]
Revert r335332 "[MC] - Add .stack_size sections into groups and link them with .text"
It broke bots.
http://lab.llvm.org:8011/builders/clang-ppc64le-linux-lnt/builds/12891
http://lab.llvm.org:8011/builders/clang-cmake-x86_64-sde-avx512-linux/builds/9443
http://lab.llvm.org:8011/builders/lldb-x86_64-ubuntu-14.04-buildserver/builds/25551
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335333
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George Rimar [Fri, 22 Jun 2018 10:10:53 +0000 (10:10 +0000)]
[MC] - Add .stack_size sections into groups and link them with .text
D39788 added a '.stack-size' section containing metadata on function stack sizes
to output ELF files behind the new -stack-size-section flag.
This change does following two things on top:
1) Imagine the case when there are -ffunction-sections flag given and there are text sections in COMDATs.
The patch adds a '.stack-size' section into corresponding COMDAT group, so that linker will be able to
eliminate them fast during resolving the COMDATs.
2) Patch sets a SHF_LINK_ORDER flag and links '.stack-size' with the corresponding .text.
With that linker will be able to do -gc-sections on dead stack sizes sections.
Differential revision: https://reviews.llvm.org/D46874
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335332
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