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Karol Herbst [Tue, 9 Jan 2018 02:22:00 +0000 (03:22 +0100)]
nv50/ir/nir: add loadFrom and storeTo helpler
v8: don't require C++11 features
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Karol Herbst [Mon, 11 Dec 2017 17:01:29 +0000 (18:01 +0100)]
nv50/ir/nir: run assignSlots
v2: add support for geometry shaders
set idx
add some missing mappings
fix for 64bit inputs/outputs
fix up some FP color output index messup
parse centroid flag
v3: fix arrays in outputs as well
fix input/ouput size calculation for tessellation shaders
v4: add getSlotAddress helper
fix for 64 bit typed inputs
v5: change getSlotAddress interface for easier use
fix sample inputs
fix slot counting for mat
v7: fix driver_location of images
v8: don't require C++11 features
v9: convert to C++ style comments
support VERT_ATTRIB_POINT_SIZE
add more error checking to slots
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Karol Herbst [Mon, 18 Dec 2017 02:57:06 +0000 (03:57 +0100)]
nv50/ir/nir: add nir type helper functions
v4: treat imul as unsigned
v5: remove pointless !!
v7: inot is unsigned as well
v8: don't require C++11 features
v9: convert to C++ style comments
improve formatting
print error in all cases where codegen doesn't support a given type
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Pierre Moreau <pierre.morrow@free.fr>
Karol Herbst [Tue, 12 Dec 2017 20:01:28 +0000 (21:01 +0100)]
nv50/ir/nir: track defs and provide easy access functions
v2: add helper function for indirects
v4: add new getIndirect overload for easier use
v5: use getSSA for ssa values
we can just create the values for unassigned registers in getSrc
v6: always create at least 32 bit values
v8: don't require C++11 features
v9: include unordered_map on supported stdlibs
replace '(*it).' with 'it->'
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Karol Herbst [Sun, 10 Dec 2017 19:39:23 +0000 (20:39 +0100)]
nv50/ir/nir: run some passes to make the conversion easier
v2: add constant_folding
v6: print non final NIR only for verbose debugging
v8: add passes we will need for OpenCL compute shaders
v9: move type_size into anonymous namespace
convert to C++ style comments
lower bools to int32
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Pierre Moreau <pierre.morrow@free.fr>
Karol Herbst [Tue, 10 Apr 2018 14:41:01 +0000 (16:41 +0200)]
nouveau: fix nir and TGSI shader cache collision
v9: rename variable to driver_flags
use constants for shader cache flags
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <pierre.morrow@free.fr>
Karol Herbst [Sun, 10 Dec 2017 14:06:45 +0000 (15:06 +0100)]
nouveau: add support for nir
not all those nir options are actually required, it just made the work a
little easier.
v2: fix asserts
parse compute shaders
don't lower bitfield_insert
v3: fix memory leak
v4: don't lower fmod32
v5: set lower_all_io_to_temps to false
fix memory leak because we take over ownership of the nir shader
merge: use the lowering helper
v6: include TGSI debug header for proper assert call
add nv50 support
v7: fix Automake build
v8: free shader only for the set shader type
v9: check for IR type inside get_compiler_options
squash "nouveau: add env var to make nir default"
fix memory leak when creating compute shaders
use debug_get_bool_option as it is available in non debug builds
return failure if unsupported IR is encountered
don't lower fpow in nir
lower int 64 divmod inside nir to prevent crashes
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <pierre.morrow@free.fr>
Karol Herbst [Wed, 3 Jan 2018 14:31:15 +0000 (15:31 +0100)]
nv50/ir: add lowering helper
if we start supporting multiple input IRs we might want to move lowering code
into a common place and keep the initial translation simplier.
This will also allows us to react on ISA changes more easily.
v5: also handle SAT
v6: rename type variables
fixed lowering of NEG
add lowering of NOT
v8: don't require C++11 features
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <pierre.morrow@free.fr>
Karol Herbst [Tue, 2 Jan 2018 18:02:30 +0000 (19:02 +0100)]
nv50/ir: move common converter code in base class
v2: remove TGSI related bits
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <pierre.morrow@free.fr>
Karol Herbst [Fri, 15 Dec 2017 19:04:59 +0000 (20:04 +0100)]
nvc0: print the shader type when dumping headers
this makes debugging the shader header a little easier
Acked-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Bas Nieuwenhuizen [Sat, 16 Mar 2019 21:58:38 +0000 (22:58 +0100)]
radeonsi: Remove implicit const cast.
Fixes:
b9e02fe138e "gallium: add pipe_grid_info::last_block"
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Bas Nieuwenhuizen [Tue, 12 Mar 2019 23:15:09 +0000 (00:15 +0100)]
gitlab-ci: Build turnip.
No autotools build to care about.
The half baked turnips param is kind of ugly, but felt like a waste
defining more variables for it now.
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Bas Nieuwenhuizen [Tue, 12 Mar 2019 23:38:02 +0000 (00:38 +0100)]
turnip: Deconflict vk_format_table regeneration
Avoids
src/freedreno/vulkan/meson.build:42:0: ERROR: Tried to create target "vk_format_table.c", but a target of that name already exists.
when building both radv and turnip.
Fixes:
26380b3a9f8 "turnip: Add driver skeleton (v2)"
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Bas Nieuwenhuizen [Tue, 12 Mar 2019 23:07:02 +0000 (00:07 +0100)]
turnip: Fix GCC compiles.
Apparently GCC does not consider static const variables to be
integer constants, and hence the array size and the static assert
result in compile failures.
Fixes:
4b9f967cd1a "turnip: add a more complete format table"
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Jason Ekstrand [Thu, 14 Mar 2019 17:58:16 +0000 (12:58 -0500)]
intel/nir: Lower array-deref-of-vector UBO and SSBO loads
This fixes a serious performance issue with DXVK:
https://github.com/doitsujin/dxvk/issues/937
This was caused by a recent change that to improve performance on RADV
which back-fired on ANV and killed performance for some apps:
https://github.com/doitsujin/dxvk/commit/
e5a06d3f4a103a54cd4eb51970fedee405d1d698
Throwing in this bit of lowering lets us come along and CSE those UBO
loads (or copy-prop for SSBO load) and get one load where we previously
would have gotten several.
VkPipeline-db results on Kaby Lake:
total instructions in shared programs:
5115361 ->
5073185 (-0.82%)
instructions in affected programs:
1754333 ->
1712157 (-2.40%)
helped: 5331
HURT: 63
total cycles in shared programs:
2544501169 ->
2481144545 (-2.49%)
cycles in affected programs:
2531058653 ->
2467702029 (-2.50%)
helped: 9202
HURT: 4323
total loops in shared programs: 3340 -> 3331 (-0.27%)
loops in affected programs: 9 -> 0
helped: 9
HURT: 0
total spills in shared programs: 3246 -> 3053 (-5.95%)
spills in affected programs: 384 -> 191 (-50.26%)
helped: 10
HURT: 5
total fills in shared programs: 4626 -> 4452 (-3.76%)
fills in affected programs: 439 -> 265 (-39.64%)
helped: 10
HURT: 5
All of the shaders with hurt spilling were in Rise of the Tomb Raider
which also had shaders solidly helped in the spilling department. Not
shown in those results (because I've not had success dumping the
shaders) is Witcher 3 where this reduces spilling and improves over-all
perf by around 20-25%. There were no shader-db changes. Apparently,
this just isn't a pattern that happens in OpenGL.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Cc: "19.0" mesa-stable@lists.freedesktop.org
Jason Ekstrand [Mon, 11 Mar 2019 23:47:39 +0000 (18:47 -0500)]
nir: Add a new pass to lower array dereferences on vectors
This pass was originally written for lowering TCS output reads and
writes but it is also applicable just about anything including UBOs,
SSBOs, and shared variables.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Mon, 11 Mar 2019 23:58:24 +0000 (18:58 -0500)]
nir/builder: Add a vector extract helper
This one's a tiny bit better than what we had in spirv_to_nir because it
emits a binary tree rather than a linear walk. It also doesn't leave
around unneeded bcsel instructions for a constant index and returns an
undef for constant OOB access.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Gert Wollny [Fri, 15 Mar 2019 09:31:26 +0000 (10:31 +0100)]
softpipe: Enable PIPE_CAP_MIXED_COLORBUFFER_FORMATS
It seems softpipe actually supports this. This change enables the
following piglits as passing without regressions in the gpu test set:
gl-3.1-mixed-int-float-fbo
gl-3.1-mixed-int-float-fbo int_second
fbo-blending-format-quirks
Changes for deqp:
dEQP-GLES2.functional.fbo.completeness.attachment_combinations.rbo_tex_none_none QualityWarning -> Pass
dEQP-GLES2.functional.fbo.completeness.attachment_combinations.rbo_tex_none_rbo QualityWarning -> Pass
dEQP-GLES2.functional.fbo.completeness.attachment_combinations.rbo_tex_none_tex QualityWarning -> Pass
dEQP-GLES2.functional.fbo.completeness.attachment_combinations.rbo_tex_rbo_none QualityWarning -> Pass
dEQP-GLES2.functional.fbo.completeness.attachment_combinations.rbo_tex_tex_none QualityWarning -> Pass
dEQP-GLES2.functional.fbo.completeness.attachment_combinations.tex_rbo_none_none QualityWarning -> Pass
dEQP-GLES2.functional.fbo.completeness.attachment_combinations.tex_rbo_none_rbo QualityWarning -> Pass
dEQP-GLES2.functional.fbo.completeness.attachment_combinations.tex_rbo_none_tex QualityWarning -> Pass
dEQP-GLES2.functional.fbo.completeness.attachment_combinations.tex_rbo_rbo_none QualityWarning -> Pass
dEQP-GLES2.functional.fbo.completeness.attachment_combinations.tex_rbo_tex_none QualityWarning -> Pass
dEQP-GLES3.functional.fbo.completeness.samples.rbo0_rbo0_tex Fail -> Pass
dEQP-GLES3.functional.fbo.completeness.samples.rbo0_tex_none Fail -> Pass
dEQP-GLES3.functional.fbo.completeness.samples.rbo1_rbo1_rbo1 Fail -> Pass
dEQP-GLES3.functional.fragment_out.random.* NotSupported -> Pass
dEQP-GLES31.functional.shaders.builtin_functions.common.frexp.*_fragment Fail -> Pass
dEQP-GLES31.functional.shaders.builtin_functions.common.frexp.*_vertex Fail -> Pass
dEQP-GLES31.functional.shaders.builtin_functions.precision.frexp.*_fragment.* Fail -> Pass
dEQP-GLES31.functional.shaders.builtin_functions.precision.frexp.*_vertex.* Fail -> Pass
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Rob Clark [Tue, 26 Feb 2019 19:46:45 +0000 (14:46 -0500)]
freedreno/ir3/cp: fix ldib bug
Something that we didn't hit earlier because of the extra shr.b
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
James Zhu [Wed, 6 Mar 2019 17:36:37 +0000 (12:36 -0500)]
gallium/auxiliary/vl: Change weave compute shader implementation
Use 2D_ARRARY instead of RECT to fetch texels for weave compute
shader.
Problem 2,3: Fixed interpolation issue with weave de-interlace
Fixes:
9364d66cb7f7 (Add video compositor compute shader render)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109646
Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Tested-by: Bruno Milreu <bmilreu@gmail.com>
James Zhu [Wed, 6 Mar 2019 17:29:09 +0000 (12:29 -0500)]
gallium/auxiliary/vl: Change grid setting
Using draw area for grid setting instead of destination
buffer size.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Tested-by: Bruno Milreu <bmilreu@gmail.com>
James Zhu [Wed, 6 Mar 2019 17:01:07 +0000 (12:01 -0500)]
gallium/auxiliary/vl: Increase shader_params size
Increase shader_params size to pass sampler data to
compute shader during weave de-interlace.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Tested-by: Bruno Milreu <bmilreu@gmail.com>
Marek Olšák [Wed, 27 Feb 2019 22:19:55 +0000 (17:19 -0500)]
omx: add a compute path in enc_LoadImage_common
Acked-by: Leo Liu <leo.liu@amd.com>
Marek Olšák [Wed, 27 Feb 2019 22:19:54 +0000 (17:19 -0500)]
omx: clean up enc_LoadImage_common
- add *pipe
- add documentation
Acked-by: Leo Liu <leo.liu@amd.com>
Marek Olšák [Wed, 27 Feb 2019 22:19:53 +0000 (17:19 -0500)]
gallium: add pipe_grid_info::last_block
The OpenMAX state tracker will use this.
RadeonSI is adapted to use pipe_grid_info::last_block instead of its
internal state.
Acked-by: Leo Liu <leo.liu@amd.com>
Alejandro Piñeiro [Thu, 14 Mar 2019 10:02:52 +0000 (11:02 +0100)]
nir/xfb: move varyings info out of nir_xfb_info
When varyings was added we moved to use to dynamycally allocated
pointers, instead of allocating just one block for everything. That
breaks some assumptions of some vulkan drivers (like anv), that make
serialization and copying easier. And at the same time, varyings are
not needed for vulkan.
So this commit moves them out. Although it seems a little an overkill,
fixing the anv side would require a similar, or more, changes, so in
the end it is about to decide where do we want to put our effort.
v2: (from Jason review)
* Don't use a temp variable on the _create methods, just return
result of rzalloc_size
* Wrap some lines too long.
Fixes:
cf0b2ad486c9 ("nir/xfb: adding varyings on nir_xfb_info and gather_info")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Samuel Pitoiset [Fri, 15 Mar 2019 09:36:00 +0000 (10:36 +0100)]
radv: always load 3 channels for formats that need to be shuffled
This fixes a rendering issue with Hellblade and DXVK.
Fixes:
a66b186bebf ("radv: use typed buffer loads for vertex input fetches")
Reported-by: Philip Rebohle <philip.rebohle@tu-dortmund.de>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Mathias Fröhlich [Thu, 14 Mar 2019 04:58:43 +0000 (05:58 +0100)]
mesa: Add assert to _mesa_primitive_restart_index.
Make sure the inde_size parameter is meant to be in bytes.
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Mathias Fröhlich [Fri, 1 Mar 2019 08:27:54 +0000 (09:27 +0100)]
vbo: Fix GL_PRIMITIVE_RESTART_FIXED_INDEX in display list compiles.
The maximum value primitive restart index is different for each index data
type. Use the appropriate fixed restart index value.
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Mathias Fröhlich [Fri, 1 Mar 2019 08:27:54 +0000 (09:27 +0100)]
vbo: Fix basevertex handling in display list compiles.
The standard requires that the primitive restart comparison happens before
the basevertex value is added. Do this now, drop a reference to the standard
why this happens at this place.
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Mathias Fröhlich [Fri, 1 Mar 2019 08:27:54 +0000 (09:27 +0100)]
mesa: Use mapping tools in debug prints.
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Mathias Fröhlich [Fri, 1 Mar 2019 08:27:53 +0000 (09:27 +0100)]
mesa: Remove _ae_{,un}map_vbos and dependencies.
Since mapping and unmapping the buffer objects in a VAO is handled
directly from the VAO, this part of the _NEW_ARRAY state is no longer
used. So remove this part of array element state.
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Mathias Fröhlich [Fri, 1 Mar 2019 08:27:53 +0000 (09:27 +0100)]
mesa: Replace _ae_{,un}map_vbos with _mesa_vao_{,un}map_arrays
Due to the use of bitmaps, the _mesa_vao_{,un}map_arrays functions
should provide comparable runtime efficienty to the currently used
_ae_{,un}map_vbos functions. So use this functions and enable
further cleanup.
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Mathias Fröhlich [Fri, 1 Mar 2019 08:27:53 +0000 (09:27 +0100)]
mesa: Use _mesa_array_element in dlist save.
Make use of the newly factored out _mesa_array_element function
in display list compilation. For now that duplicates out the
primitive restart logic. But that turns out to need a fix in
display list handling anyhow.
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Mathias Fröhlich [Fri, 1 Mar 2019 08:27:53 +0000 (09:27 +0100)]
mesa: Factor out _mesa_array_element.
The factored out function handles emitting the vertex attributes
at the given index. The now public accessible function gets used
in the following patches.
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Mathias Fröhlich [Fri, 1 Mar 2019 08:27:53 +0000 (09:27 +0100)]
mesa: Implement helper functions to map and unmap a VAO.
Provide a set of functions that maps or unmaps all VBOs held
in a VAO. The functions will be used in the following patches.
v2: Update comments.
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Jason Ekstrand [Sun, 10 Mar 2019 13:57:51 +0000 (08:57 -0500)]
st/mesa: Let NIR lower UBO and SSBO access when we have it
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Sat, 9 Mar 2019 15:08:44 +0000 (09:08 -0600)]
i965: Stop setting LowerBuferInterfaceBlocks
Instead, we do UBO and SSBO deref lowering in NIR after we've given it a
chance to optimize SSBO access:
Shader-db results on Kaby Lake:
total instructions in shared programs:
15235775 ->
15235484 (<.01%)
instructions in affected programs: 14992 -> 14701 (-1.94%)
helped: 19
HURT: 20
total cycles in shared programs:
339220331 ->
339027307 (-0.06%)
cycles in affected programs:
79831981 ->
79638957 (-0.24%)
helped: 540
HURT: 602
total loops in shared programs: 4402 -> 4348 (-1.23%)
loops in affected programs: 186 -> 132 (-29.03%)
helped: 27
HURT: 0
total spills in shared programs: 23261 -> 23234 (-0.12%)
spills in affected programs: 38 -> 11 (-71.05%)
helped: 1
HURT: 0
total fills in shared programs: 31442 -> 31371 (-0.23%)
fills in affected programs: 98 -> 27 (-72.45%)
helped: 1
HURT: 0
LOST: 12
GAINED: 12
Most of the help and hurt in instruction counts was just churn caused by
re-ordering of optimizations and the fact that the NIR deref lowering
code is emitting slightly different instructions. Nothing was hurt by
more than three instructions and most things weren't helped by more than
four. The primary exception to this is one Car Chase shader:
shaders/non-free/gfxbench4/carchase/341.shader_test CS SIMD32: 1144 -> 821 (-28.23%)
There is also one compute shader in Manhattan 3.1 and a fragment shader
in the UE4 Shooter Game demo that now get a loop partially unrolled.
Those showed up in the results as hurt instructions but were manually
removed to get the results above.
The lost/gained was a dozen Car Chase shaders that went from SIMD8 to
SIMD16 thanks to improved register pressure:
shaders/non-free/gfxbench4/carchase/366.shader_test CS
shaders/non-free/gfxbench4/carchase/368.shader_test CS
shaders/non-free/gfxbench4/carchase/370.shader_test CS
shaders/non-free/gfxbench4/carchase/372.shader_test CS
shaders/non-free/gfxbench4/carchase/376.shader_test CS
shaders/non-free/gfxbench4/carchase/378.shader_test CS
shaders/non-free/gfxbench4/carchase/380.shader_test CS
shaders/non-free/gfxbench4/carchase/382.shader_test CS
shaders/non-free/gfxbench4/carchase/384.shader_test CS
shaders/non-free/gfxbench4/carchase/388.shader_test CS
shaders/non-free/gfxbench4/carchase/4.shader_test CS
shaders/non-free/gfxbench4/carchase/6.shader_test CS
Given how much it appeared to be improved, I ran Car Chase on my laptop.
Unfortunately, I wasn't able to see any measurable improvement. It
might be helped by 1-2% but it's in the noise. It does render correctly
as far as I can tell so the improvement is legitimate.
All of the loops that got delete were in dolphin uber shaders. I've had
no opportunity to test them for correctness or performance.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Sat, 9 Mar 2019 16:12:46 +0000 (10:12 -0600)]
glsl/nir: Add a pass to lower UBO and SSBO access
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Thu, 14 Mar 2019 17:00:04 +0000 (12:00 -0500)]
glsl/nir: Handle unlowered SSBO atomic and array_length intrinsics
We didn't have any of these before because all NIR consumers always
called lower_ubo_references. Soon, we want to pass the derefs straight
through to NIR so we need to handle these intrinsics directly.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Sat, 9 Mar 2019 15:40:09 +0000 (09:40 -0600)]
glsl/nir: Set explicit types on UBO/SSBO variables
We want to be able to use variables and derefs for UBO/SSBO access in
NIR. In order to do this, the rest of NIR needs to know the type layout
information.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Mon, 11 Mar 2019 19:53:31 +0000 (14:53 -0500)]
glsl: Don't lower vector derefs for SSBOs, UBOs, and shared
All of these are backed by some sort of memory so if you have multiple
threads writing to different components of the same vector at the same
time, the load-vec-store pattern that GLSL IR emits won't work. This
shouldn't affect any drivers today as they all call GLSL IR lowering
which lowers access to these variables to index+offset intrinsics before
we get to this point. However, NIR will start handling the derefs
itself and won't want the lowering.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Sun, 10 Mar 2019 13:35:00 +0000 (08:35 -0500)]
nir/lower_io: Add a new buffer_array_length intrinsic and lowering
Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Sat, 9 Mar 2019 16:10:37 +0000 (10:10 -0600)]
nir: Rename nir_address_format_vk_index_offset to not be vk
It's just a 32-bit index and offset. We're going to want to use it in
GL as well so stop talking about Vulkan.
Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Sun, 10 Mar 2019 22:41:02 +0000 (17:41 -0500)]
nir/deref: Consider COHERENT decorated var derefs as aliasing
If we get to two deref_var paths with different variables, we usually
know they don't alias. However, if both of the paths are marked
coherent, we don't have to worry about it.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Sat, 9 Mar 2019 15:06:27 +0000 (09:06 -0600)]
compiler/types: Add helpers to get explicit types for standard layouts
We also need to modify the current size/align helpers to not blow up
when they encounter an explicitly laid out type. Previously we
considered using the size/align helpers mutually exclusive with standard
layouts but now we just assert that they match.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Mon, 11 Mar 2019 02:43:37 +0000 (21:43 -0500)]
compiler/types: Add a C wrapper to get full struct field data
Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Sat, 9 Mar 2019 16:22:39 +0000 (10:22 -0600)]
compiler/types: Add a new is_interface C wrapper
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Sat, 9 Mar 2019 21:05:25 +0000 (15:05 -0600)]
nir/validate: Allow 32-bit boolean load/store intrinsics
With UBOs and SSBOs we have boolean types but they're actually 32-bit
values. Make the validator a little less strict so that we can do a
32-bit load/store on boolean types. We're about to add a lowering pass
called gl_nir_lower_buffers which will lower boolean load/store
operations to 32-bit and insert i2b and b2i instructions to convert
to/from 1-bit booleans. We want that to be legal.
Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Sat, 9 Mar 2019 19:06:28 +0000 (13:06 -0600)]
nir/validate: Only require bare types to match for copy_deref
If we want to be able to use copy_deref instructions on explicitly laid
out types, we have to be a little more flexible about what types we
allow. Instead, of requiring the types to exactly match, only require
the bare types to match.
Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Sun, 10 Mar 2019 15:06:56 +0000 (10:06 -0500)]
nir/algebraic: Add a couple optimizations for iabs and ishr
Shader-db results on Kaby Lake:
total instructions in shared programs:
15225213 ->
15222365 (-0.02%)
instructions in affected programs: 43524 -> 40676 (-6.54%)
helped: 203
HURT: 0
Lots of shaders in Shadow Warrior had this pattern along with Deus Ex,
Civ, Shadow of Mordor, and several others.
Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Eric Anholt [Tue, 12 Mar 2019 22:18:43 +0000 (15:18 -0700)]
mesa/st: Fix leaks of TGSI tokens in VP variants.
Starting a glxgears and closing it, I was seeing a lot of leaked TGSI for
the fixed function VPs.
v2: drop unused delete_ir() arg.
Fixes:
3b4929ec6e64 ("st/mesa: Copy VP TGSI tokens if they exist, even for NIR shaders.")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Wed, 13 Mar 2019 00:07:16 +0000 (17:07 -0700)]
mesa/st: Make sure that prog_to_nir NIR gets freed.
GLSL NIR gets freed on relink by _mesa_delete_program(), but for ARB
programs we need to free the old NIR when PSN is used to set up new NIR in
the same gl_program. Additionally, set the base .nir field so that it
will get freed by _mesa_delete_program().
Fixes:
3d7611e9a6c6 ("st/nir: use NIR for asm programs")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Alyssa Rosenzweig [Wed, 13 Mar 2019 05:01:43 +0000 (05:01 +0000)]
panfrost/midgard: Implement fpow
We have a native op for this, which was just found in a disassembly --
so instead of lowering, use it!
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Wed, 13 Mar 2019 01:50:40 +0000 (01:50 +0000)]
panfrost: Compute viewport state on the fly
Previously, we were caching this incorrectly; there's no real reason to
given how variable it is (sensitive to changes in viewport, framebuffer
dimensions, and scissors) and how cheap it is to recompute. So, just do
it on the fly each draw.
Fixes glmark-es2 -bshadow and -brefract.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Wed, 13 Mar 2019 01:31:30 +0000 (01:31 +0000)]
panfrost; Disable AFBC for depth buffers
For inexplicable reasons, the depth buffer is faster if kept as linear,
whereas the colour buffers are faster if AFBC. Given both code paths are
available, we'll choose the faster one of each (which also helps with
testing coverage).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Wed, 13 Mar 2019 00:53:34 +0000 (00:53 +0000)]
panfrost: Allocate extra data for depth buffer
It's not clear why the hardware "spills" a little bit, but if we don't
do this, we get MMU faults with linear depth buffers.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Wed, 13 Mar 2019 00:53:18 +0000 (00:53 +0000)]
panfrost: Comment spelling fix
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Tue, 12 Mar 2019 23:16:37 +0000 (23:16 +0000)]
panfrost/mfbd: Respect per-job depth write flag
While a depth buffer may be supplied, it only needs to be written to if
the depth writemask is set for any draw AND if the depth buffer is not
immediately invalidated (as is the case for scanout). This refactors
panfrost_job to provide a depth write requirement, which is now
implemented for MFBD depth buffers.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Tue, 12 Mar 2019 22:49:33 +0000 (22:49 +0000)]
panfrost/mfbd: Implement linear depth buffers
This removes a clunky hack where the depth buffer was enabled during the
*clear*, instead of during depth buffer linking. That said, this does
not yet support writeback like AFBC depth buffers.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Tue, 12 Mar 2019 22:42:16 +0000 (22:42 +0000)]
panfrost: Minor comment cleanup (version detection)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Tue, 12 Mar 2019 22:41:11 +0000 (22:41 +0000)]
panfrost: Remove staging MFBD
Same idea as the previous commit, but for the MFBD this time instead of
the SFBD.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Tue, 12 Mar 2019 22:01:23 +0000 (22:01 +0000)]
panfrost: Remove staging SFBD for pan_context
The fragment framebuffer descriptor should not be a context entry;
rather, it should be constructed only at fragment time to keep analysis
tractable.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Tue, 12 Mar 2019 03:32:17 +0000 (03:32 +0000)]
panfrost: Break out fragment to SFBD/MFBD files
This substantially cleans up the corresponding logic at the expense of a
bit of code duplication; nevertheless, it's a net win since otherwise
incompatible hardware code is mixed confusingly.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Thu, 14 Mar 2019 04:14:37 +0000 (04:14 +0000)]
freedreno: Use shared drm_find_modifier util
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Alyssa Rosenzweig [Thu, 14 Mar 2019 04:16:07 +0000 (04:16 +0000)]
vc4: Use shared drm_find_modifier util
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Anholt <eric@anholt.net>
Alyssa Rosenzweig [Thu, 14 Mar 2019 04:15:20 +0000 (04:15 +0000)]
v3d: Use shared drm_find_modifier util
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Anholt <eric@anholt.net>
Alyssa Rosenzweig [Thu, 14 Mar 2019 04:13:45 +0000 (04:13 +0000)]
util: Add a drm_find_modifier helper
This function is replicated across vc4/v3d/freedreno and is needed in
Panfrost; let's make this shared code.
v2: Supply generic util_array_contains_u64 version (Eric Engestrom). Add
missing stdbool.h include (Eric Anholt). Mark inline (Christian
Gmeiner).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Mark Janes [Fri, 7 Dec 2018 00:35:44 +0000 (16:35 -0800)]
mesa: add logging function for formatted string
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Mark Janes [Fri, 7 Dec 2018 00:35:43 +0000 (16:35 -0800)]
mesa: rename logging functions to reflect that they format strings
In preparation for the definition of a function to log a formatted
string.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Mark Janes [Fri, 7 Dec 2018 00:35:42 +0000 (16:35 -0800)]
mesa: properly report the length of truncated log messages
_mesa_log_msg must provide the length of the string passed into the
KHR_debug api. When the string formatted by _mesa_gl_vdebugf exceeds
MAX_DEBUG_MESSAGE_LENGTH, the length is incorrectly set to the number
of characters that would have been written if enough space had been
available.
Fixes:
30256805784450b8bb9d4dabfb56226271ca9d24
("mesa: Add support for GL_ARB_debug_output with dynamic ID allocation.")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Jason Ekstrand [Wed, 13 Mar 2019 22:27:39 +0000 (17:27 -0500)]
anv: Only set 3DSTATE_PS::VectorMaskEnable on gen8+
We don't set it on HSW and earlier in i965 and disabling it appears to
make derivatives somewhat more reliable.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Engestrom [Thu, 14 Mar 2019 12:30:15 +0000 (12:30 +0000)]
travis: fix osx meson build
Samuel Pitoiset [Thu, 14 Mar 2019 13:27:03 +0000 (14:27 +0100)]
radv: always initialize HTILE when the src layout is UNDEFINED
HTILE should always be initialized when transitioning from
VK_IMAGE_LAYOUT_UNDEFINED to other image layouts. Otherwise,
if an app does a transition from UNDEFINED to GENERAL, the
driver doesn't initialize HTILE and it tries to decompress
the depth surface. For some reasons, this results in VM faults.
Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107563
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tomeu Vizoso [Thu, 14 Mar 2019 14:20:50 +0000 (15:20 +0100)]
panfrost: Adapt to uapi changes
Two ioctls had wrong DRM_IO* flags.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Plamena Manolova [Tue, 12 Mar 2019 19:25:36 +0000 (21:25 +0200)]
i965: Disable ARB_fragment_shader_interlock for platforms prior to GEN9
ARB_fragment_shader_interlock depends on memory fences to
ensure fragment ordering and this ordering guarantee is
only supported from GEN9 onwards.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109980
Fixes:
939312702e35 "i965: Add ARB_fragment_shader_interlock support."
Signed-off-by: Plamena Manolova <plamena.n.manolova@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Wed, 13 Mar 2019 22:35:28 +0000 (15:35 -0700)]
iris: Don't mutate box in transfer map code
Not mutating the boxes is arguably cleaner.
Split from a patch by Chris Wilson but reworked to use a pointer to the
original box rather than making a copy at all.
Tapani Pälli [Wed, 13 Mar 2019 10:13:09 +0000 (12:13 +0200)]
i965: remove scaling factors from P010, P012
Patch removes scaling factors introduced in
2a2e69f975b but leaves
option to use scaling in place as it could be useful with other upcoming
YUV formats.
We did this scaling because ffmpeg was shifting channel bits down, however
it seems this is not the right place as compositor wants to flip same
buffers directly to display as well and therefore bitshifting needs to be
done by the client when receiving frame from ffmpeg.
Now P0x formats are treated the same, e.g. P010 is same as P016 but with
lower 6 bits set to zeros.
Fixes:
2a2e69f975b "i965: add P0x formats and propagate required scaling factors"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 13 Mar 2019 03:55:14 +0000 (22:55 -0500)]
anv/pass: Flag the need for a RT flush for resolve attachments
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Jason Ekstrand [Tue, 12 Mar 2019 20:22:19 +0000 (15:22 -0500)]
anv: Stop using VK_TRUE/FALSE
We've been fairly inconsistent about this so we should really choose
whether we're going to use VK_TRUE/FALSE or the C boolean values. The
Vulkan #defines are set to 1 and 0 respectively so it's the same value
as C gives you when you cast a boolean expression to an integer. Since
there are several places where we set a VkBool32 to a C logical
expression, let's just embrace C booleans and stop using the VK defines.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Gurchetan Singh [Wed, 13 Mar 2019 22:58:22 +0000 (22:58 +0000)]
virgl: use uint16_t mask instead of separate booleans
This should save some space.
Suggested-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Albert Pal [Wed, 13 Mar 2019 20:28:06 +0000 (20:28 +0000)]
Fix link release notes for 19.0.0.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Rafael Antognolli [Fri, 22 Feb 2019 01:51:26 +0000 (17:51 -0800)]
iris: Enable auxiliary buffer support again
Now that we are properly resolving buffers before giving them to the
window system, let's enable aux support again.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Thu, 7 Mar 2019 23:32:38 +0000 (15:32 -0800)]
iris: Convert RGBX to RGBA always.
In i965, we disable the use of RGBX formats, so the higher layers of
Mesa choose the equivalent RGBA format, and swizzle the alpha channel to
1.0.
However, Gallium won't do that. We need to explicitly convert it to
RGBA.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Thu, 28 Feb 2019 19:08:32 +0000 (11:08 -0800)]
iris: Add resolve on iris_flush_resource.
The flush_resource hook is supposedly called when the resource content
needs to be made visible to external (okay, that's pretty vague). For
instance, it gets called before a surface gets handled to the window
system. So we need to resolve it if it's not resolved yet.
v2 (Ken):
- Check mod_info in iris_flush_resource instead of ISL_AUX_USAGE_NONE
- Drop my old broken resolve code from iris_resource_get_handle() now
that Rafael's got it hooked up in the right place.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eduardo Lima Mitev [Thu, 28 Feb 2019 17:17:50 +0000 (18:17 +0100)]
ir3/lower_io_offsets: Try propagate SSBO's SHR into a previous shift instruction
While we lack value range tracking, this patch tries to 'manually' propogate
the division by 4 to calculate SSBO element-offset, into a possible previous
shift operation (shift left or right); checking that it is safe to do so.
This should help in cases like ie. when accessing a field in an array of
structs, where the offset is likely defined as base plus a multiplication
by a struct or array element size.
See dEQP test 'dEQP-GLES31.functional.ssbo.atomic.xor.highp_uint'
for an example of a shader that benefits from this.
Reviewed-by: Rob Clark <robdclark@gmail.com>
Eduardo Lima Mitev [Tue, 26 Feb 2019 13:07:04 +0000 (14:07 +0100)]
ir3/compiler: Enable lower_io_offsets pass and handle new SSBO intrinsics
These intrinsics have the offset in dwords already computed in the last
source, so the change here is basically using that instead of emitting
the ir3_SHR to divide the byte-offset by 4.
The improvement in shader stats is significant, of up to ~15% in
instruction count in some cases. Tested only on a5xx.
shader-db is unfortunately not very useful here because shaders that use
SSBO require GLSL versions that are not supported by freedreno yet.
For examples, most Khronos CTS tests under 'dEQP-GLES31.functional.ssbo.*'
are helped.
A random case:
dEQP-GLES31.functional.ssbo.layout.2_level_array.packed.row_major_mat3x2
with current master:
; CL prog 14/1: 1252 instructions, 0 half, 48 full
; 8 const, 8 constlen
; 61 (ss), 43 (sy)
with the SSBO dword-offset moved to NIR:
; CL prog 14/1: 1053 instructions, 0 half, 45 full
; 7 const, 7 constlen
; 34 (ss), 73 (sy)
The SHR previously emitted for every single SSBO instruction disappears
in most cases, and the dword-offset ends up embedded in the STGB
instruction as immediate in many cases as well.
There are also a few of those tests that are currently failing on register
allocation, that start to pass as a result of reducing the pressure. At least
these, probably more:
dEQP-GLES31.functional.ssbo.layout.random.unsized_arrays.24
dEQP-GLES31.functional.ssbo.layout.random.arrays_of_arrays.6
dEQP-GLES31.functional.ssbo.layout.random.arrays_of_arrays.17
dEQP-GLES31.functional.ssbo.layout.random.nested_structs_arrays.14
dEQP-GLES31.functional.ssbo.layout.random.nested_structs_arrays_instance_arrays.5
dEQP-GLES31.functional.ssbo.layout.random.nested_structs_arrays_instance_arrays.7
No regressions observed with relevant CTS and piglit tests.
Reviewed-by: Rob Clark <robdclark@gmail.com>
Eduardo Lima Mitev [Sun, 13 Jan 2019 19:10:34 +0000 (20:10 +0100)]
ir3/nir: Add a new pass 'ir3_nir_lower_io_offsets'
This NIR->NIR pass implements offset computations that are currently
done on the IR3 backend compiler, to give NIR a better chance of
optimizing them.
For now, it supports lowering the dword-offset computation for SSBO
instructions. It will take an SSBO intrinsic and replace it with the
new ir3-specific version that adds an extra source. That source will
hold the SSA value resulting from inserting a division by 4 (an SHR op)
of the original byte-offset source already provided by NIR in one of
the intrinsic sources.
Note that on a6xx the original byte-offset is not needed, so we could
potentially replace that source instead of adding a new one. But to
keep things simple and consistent we always add the new source and
a6xx will just ignore the original one.
Reviewed-by: Rob Clark <robdclark@gmail.com>
Eduardo Lima Mitev [Tue, 26 Feb 2019 07:45:07 +0000 (08:45 +0100)]
nir: Add ir3-specific version of most SSBO intrinsics
These are ir3 specific versions of SSBO intrinsics that add an
extra source to hold the element offset (dword), which is what the
backend instructions need.
The original byte-offset source provided by NIR is not replaced
because on a4xx and a5xx the backend still needs it.
Reviewed-by: Rob Clark <robdclark@gmail.com>
Dylan Baker [Wed, 13 Mar 2019 19:36:27 +0000 (12:36 -0700)]
docs: update calendar, add news item, and link release notes for 19.0.0
Dylan Baker [Wed, 13 Mar 2019 19:09:08 +0000 (12:09 -0700)]
docs: Add SHA256 sums for 19.0.0
Dylan Baker [Wed, 13 Mar 2019 17:40:19 +0000 (10:40 -0700)]
docs: Add release notes for 19.0.0
Kevin Strasser [Mon, 28 Jan 2019 18:42:44 +0000 (10:42 -0800)]
egl/dri: Avoid out of bounds array access
indexConfigAttrib iterates over every index in the dri driver, possibly
exceeding __DRI_ATTRIB_MAX. In other words, if the dri driver has newer
attributes libEGL will end up reading from uninitialized memory through
dri2_to_egl_attribute_map[].
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Chris Wilson [Fri, 22 Feb 2019 20:53:41 +0000 (20:53 +0000)]
iris: Use streaming loads to read from tiled surfaces
Always use the streaming load (since we know we have Broadwell+, all of
our target CPU support sse41) for reading back form the tiled surface
for mapping the resource. This means we hit the fast WC handling paths
on Atoms (without LLC), and for big Core (with LLC) using the streaming
load is no less efficient as we do not require the tiled buffer to be
pulled into the CPU cache.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Fri, 22 Feb 2019 21:24:46 +0000 (21:24 +0000)]
iris: Use coherent allocation for PIPE_RESOURCE_STAGING
On !llc machines (Atoms), reading from a linear buffers is slow and so
copying from one resource into the linear staging buffer is still slow.
However, we can tell the GPU to snoop the CPU cache when reading from and
writing to the staging buffer eliminating the slow uncached reads.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Mon, 25 Feb 2019 09:42:49 +0000 (09:42 +0000)]
iris: Use PIPE_BUFFER_STAGING for the query objects
We prefer fast CPU access to read back the query results.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Caio Marcelo de Oliveira Filho [Mon, 11 Mar 2019 16:43:04 +0000 (09:43 -0700)]
intel/nir: Combine store_derefs to improve code from SPIR-V
Due to lack of write mask in SPIR-V store, generators may produce
multiple stores to the same vector but using different array derefs.
Use the combining store pass to clean this up. For example,
layout(binding = 3) buffer block {
vec4 v;
};
void main() {
v.x = 11;
v.y = 22;
}
after going to SPIR-V and NIR, ends up with in two store_derefs to
v[0] and v[1]
vec2 32 ssa_4 = deref_struct &ssa_3->field0 (ssbo vec4) /* &((block *)ssa_2)->field0 */
vec2 32 ssa_6 = deref_array &(*ssa_4)[0] (ssbo float) /* &((block *)ssa_2)->field0[0] */
intrinsic store_deref (ssa_6, ssa_7) (1, 0) /* wrmask=x */ /* access=0 */
vec1 32 ssa_13 = load_const (0x00000001 /* 0.000000 */)
vec2 32 ssa_14 = deref_array &(*ssa_4)[1] (ssbo float) /* &((block *)ssa_2)->field0[1] */
intrinsic store_deref (ssa_14, ssa_15) (1, 0) /* wrmask=x */ /* access=0 */
producing two different sends instructions in skl. The combining pass
transform the snippet above into
vec2 32 ssa_4 = deref_struct &ssa_3->field0 (ssbo vec4) /* &((block *)ssa_2)->field0 */
vec4 32 ssa_18 = vec4 ssa_7, ssa_15, ssa_16, ssa_17
intrinsic store_deref (ssa_4, ssa_18) (3, 0) /* wrmask=xy */ /* access=0 */
producing a single sends instruction.
v2: Move this from spirv_to_nir into the general optimization pass for
intel compiler. (Jason)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Caio Marcelo de Oliveira Filho [Fri, 8 Mar 2019 19:50:47 +0000 (11:50 -0800)]
intel/nir: Combine store_derefs after vectorizing IO
Shader-db results for skl:
total instructions in shared programs:
15232903 ->
15224781 (-0.05%)
instructions in affected programs: 61246 -> 53124 (-13.26%)
helped: 221
HURT: 0
total cycles in shared programs:
371440470 ->
371398018 (-0.01%)
cycles in affected programs: 281363 -> 238911 (-15.09%)
helped: 221
HURT: 0
Results for bdw are very similar.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Caio Marcelo de Oliveira Filho [Fri, 8 Mar 2019 18:08:20 +0000 (10:08 -0800)]
nir: Add a pass to combine store_derefs to same vector
v2: (all from Jason)
Reuse existing function for the end of the block combinations.
Check the SSA values are coming from the right place in tests.
Document the case when the store to array_deref is reused.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Samuel Pitoiset [Wed, 13 Mar 2019 13:04:14 +0000 (14:04 +0100)]
ac: use the raw tbuffer version for 16-bit SSBO loads
vindex is always 0.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>