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Claudio Fontana [Tue, 17 Dec 2013 19:42:33 +0000 (19:42 +0000)]
target-arm: A64: add support for conditional select
This patch adds support for the instruction group "C3.5.6
Conditional select": CSEL, CSINC, CSINV, CSNEG.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
[PMM: Improved code generated in the nomatch case as per RTH suggestions]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Alexander Graf [Tue, 17 Dec 2013 19:42:33 +0000 (19:42 +0000)]
target-arm: A64: add support for compare and branch imm
This patch adds emulation for the compare and branch insns,
CBZ and CBNZ.
Signed-off-by: Alexander Graf <agraf@suse.de>
[claudio: adapted to new decoder,
compare with immediate 0,
introduce read_cpu_reg to get the 0 extension on (!sf)]
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Alexander Graf [Tue, 17 Dec 2013 19:42:33 +0000 (19:42 +0000)]
target-arm: A64: add support for 'test and branch' imm
This patch adds emulation for the test and branch insns,
TBZ and TBNZ.
Signed-off-by: Alexander Graf <agraf@suse.de>
[claudio:
adapted for new decoder
always compare with 0
remove a TCG temporary
]
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Alexander Graf [Tue, 17 Dec 2013 19:42:33 +0000 (19:42 +0000)]
target-arm: A64: add support for conditional branches
This patch adds emulation for the conditional branch (b.cond) instruction.
Signed-off-by: Alexander Graf <agraf@suse.de>
[claudio: adapted to new decoder structure,
reused arm infrastructure for checking the flags]
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Alexander Graf [Tue, 17 Dec 2013 19:42:33 +0000 (19:42 +0000)]
target-arm: A64: add support for BR, BLR and RET insns
Implement BR, BLR and RET. This is all of the 'unconditional
branch (register)' instruction category except for ERET
and DPRS (which are system mode only).
Signed-off-by: Alexander Graf <agraf@suse.de>
[claudio: reimplemented on top of new decoder structure]
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Alexander Graf [Tue, 17 Dec 2013 19:42:32 +0000 (19:42 +0000)]
target-arm: A64: add support for B and BL insns
Implement the B and BL instructions (PC relative branches and calls).
For convenience in managing TCG temporaries which might be generated
if a source register is the zero-register XZR, we provide a simple
mechanism for creating a new temp which is automatically freed at the
end of decode of the instruction.
Signed-off-by: Alexander Graf <agraf@suse.de>
[claudio: renamed functions, adapted to new decoder layout]
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Claudio Fontana [Tue, 17 Dec 2013 19:42:32 +0000 (19:42 +0000)]
target-arm: A64: expand decoding skeleton for system instructions
Decode the various kinds of system instructions:
hints (HINT), which include NOP, YIELD, WFE, WFI, SEV, SEL
sync instructions, which include CLREX, DSB, DMB, ISB
msr_i, which move immediate to processor state field
sys, which include all SYS and SYSL instructions
msr, which move from a gp register to a system register
mrs, which move from a system register to a gp register
Provide implementations where they are trivial nops.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Claudio Fontana [Tue, 17 Dec 2013 19:42:32 +0000 (19:42 +0000)]
target-arm: A64: provide skeleton for a64 insn decoding
Provide a skeleton for a64 instruction decoding in translate-a64.c,
by dividing instructions into the classes defined by the
ARM Architecture Reference Manual(DDI0487A_a) section C3.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Alexander Graf [Tue, 17 Dec 2013 19:42:32 +0000 (19:42 +0000)]
target-arm: A64: add stubs for a64 specific helpers
We will need helpers that only make sense with AArch64. Add
helper-a64.{c,h} files as stubs that we can fill with these
helpers in the following patches.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Peter Maydell [Tue, 17 Dec 2013 19:42:32 +0000 (19:42 +0000)]
target-arm: Support fp registers in gdb stub
Register the aarch64-fpu XML and implement the necessary
read/write handlers so we can support reading and writing
of FP registers in the gdb stub.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Peter Maydell [Tue, 17 Dec 2013 19:42:31 +0000 (19:42 +0000)]
target-arm: A64: provide functions for accessing FPCR and FPSR
The information which AArch32 holds in the FPSCR is split for
AArch64 into two logically distinct registers, FPSR and FPCR.
Since they are carefully arranged to use non-overlapping bits,
we leave the underlying state in the same place, and provide
accessor functions which just update the appropriate bits
via vfp_get_fpscr() and vfp_set_fpscr().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Alexander Graf [Tue, 17 Dec 2013 19:42:31 +0000 (19:42 +0000)]
target-arm: A64: add set_pc cpu method
When executing translation blocks we need to be able to recover
our program counter. Add a method to set it for AArch64 CPUs.
This covers user-mode, but for system mode emulation we will
need to check if the CPU is in an AArch32 execution state.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Peter Maydell [Tue, 17 Dec 2013 19:42:31 +0000 (19:42 +0000)]
target-arm: Split A64 from A32/T32 gen_intermediate_code_internal()
The A32/T32 gen_intermediate_code_internal() is complicated because it
has to deal with:
* conditionally executed instructions
* Thumb IT blocks
* kernel helper page
* M profile exception-exit special casing
None of these apply to A64, so putting the "this is A64 so
call the A64 decoder" check in the middle of the A32/T32
loop is confusing and means the A64 decoder's handling of
things like conditional jump and singlestepping has to take
account of the conditional-execution jumps the main loop
might emit.
Refactor the code to give A64 its own gen_intermediate_code_internal
function instead.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Peter Maydell [Tue, 17 Dec 2013 19:42:31 +0000 (19:42 +0000)]
default-configs: Add config for aarch64-softmmu
Add a config for aarch64-softmmu; this enables building of this target.
The resulting executable doesn't know about any 64 bit CPUs, but all
the 32 bit CPUs and board models work.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1385645602-18662-8-git-send-email-peter.maydell@linaro.org
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Mian M. Hamayun [Tue, 17 Dec 2013 19:42:30 +0000 (19:42 +0000)]
hw/arm/boot: Add boot support for AArch64 processor
This commit adds support for booting a single AArch64 CPU by setting
appropriate registers. The bootloader includes placeholders for Board-ID
that are used to implement uniform indexing across different bootloaders.
Signed-off-by: Mian M. Hamayun <m.hamayun@virtualopensystems.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1385645602-18662-7-git-send-email-peter.maydell@linaro.org
[PMM:
* updated to use ARMInsnFixup style bootloader fragments
* dropped virt.c additions
* use runtime checks for "is this an AArch64 core" rather than ifdefs
* drop some unnecessary setting of registers in reset hook
]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Peter Maydell [Tue, 17 Dec 2013 19:42:30 +0000 (19:42 +0000)]
hw/arm/boot: Allow easier swapping in of different loader code
For AArch64 we will obviously require a different set of
primary and secondary boot loader code fragments. However currently
we hardcode the offsets into the loader code where we must write
the entrypoint and other data into arm_load_kernel(). This makes it
hard to substitute a different loader fragment, so switch to a more
flexible scheme where instead of a raw array of instructions we use
an array of (instruction, fixup-type) pairs that indicate which
words need special action or data written into them.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1385645602-18662-6-git-send-email-peter.maydell@linaro.org
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Peter Maydell [Tue, 17 Dec 2013 19:42:30 +0000 (19:42 +0000)]
configure: Enable KVM for aarch64 host/target combination
Enable KVM if the host and target CPU are both aarch64. Note
that host aarch64 + target arm is not valid for KVM acceleration:
the 64 bit kernel does not support the ioctl interface for
32 bit CPUs. 32 bit VMs on 64 bit hosts need to be created
using the 64 bit ioctl interface; when QEMU supports this it
will be on the arch64-softmmu target with a -cpu parameter for
a 32 bit CPU, which is still an aarch64/aarch64 combination
as far as configure is concerned.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1385645602-18662-5-git-send-email-peter.maydell@linaro.org
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Mian M. Hamayun [Tue, 17 Dec 2013 19:42:30 +0000 (19:42 +0000)]
target-arm: Add minimal KVM AArch64 support
Add the bare minimum set of functions needed for control of an
AArch64 KVM vcpu:
* CPU initialization
* minimal get/put register functions which only handle the
basic state of the CPU
Signed-off-by: Mian M. Hamayun <m.hamayun@virtualopensystems.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1385645602-18662-4-git-send-email-peter.maydell@linaro.org
[PMM: significantly overhauled; most notably:
* code lives in kvm64.c rather than using #ifdefs
* support '-cpu host' rather than implicitly using whatever the
host's CPU is regardless of what the user requests
* fix bug attempting to get/set nonexistent X[31]
* fix bug writing 64 bit kernel pstate into uint32_t env field
]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Peter Maydell [Tue, 17 Dec 2013 19:42:30 +0000 (19:42 +0000)]
target-arm: Clean up handling of AArch64 PSTATE
The env->pstate field is a little odd since it doesn't strictly
speaking represent an architectural register. However it's convenient
for QEMU to use it to hold the various PSTATE architectural bits
in the same format the architecture specifies for SPSR registers
(since this is the same format the kernel uses for signal handlers
and the KVM register). Add some structure to how we deal with it:
* document what env->pstate is
* add some #defines for various bits in it
* add helpers for reading/writing it taking account of caching
of NZCV, and use them where appropriate
* reset it on startup
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1385645602-18662-3-git-send-email-peter.maydell@linaro.org
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Peter Maydell [Tue, 17 Dec 2013 19:42:29 +0000 (19:42 +0000)]
target-arm/kvm: Split 32 bit only code into its own file
Split ARM KVM support code which is 32 bit specific out into its
own file, which we only compile on 32 bit hosts. This will give
us a place to add the 64 bit support code without adding lots of
ifdefs to kvm.c.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1385645602-18662-2-git-send-email-peter.maydell@linaro.org
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Antony Pavlov [Tue, 17 Dec 2013 19:42:29 +0000 (19:42 +0000)]
ARM: arm_cpu_reset: make it possible to use high vectors for reset_exc
If hivecs are being used on reset, the CPU should come out of reset at
the hivecs reset vector (0xFFFF0000)
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id:
3afc69c4f58f60aa2bbee7b91574a4eb414b1c23.
1387160489.git.peter.crosthwaite@xilinx.com
[ PC Changes:
* Fixed Grammar error in commit message
* Elaborated commit message.
]
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Antony Pavlov [Tue, 17 Dec 2013 19:42:29 +0000 (19:42 +0000)]
ARM: cpu: add "reset_hivecs" property
Add an ARM CPU property for the reset value of hivecs as it is a
board/SoC configurable setting.
The existence of the property is conditional on the ARM CPU not being M
class.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id:
b04216c6bda4bd163f44a55bba552d0e8267481f.
1387160489.git.peter.crosthwaite@xilinx.com
[ PC Changes:
* Elaborated commit message
* refactored to use qdev_property_add_static
]
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Crosthwaite [Tue, 17 Dec 2013 19:42:29 +0000 (19:42 +0000)]
arm/highbank.c: Fix MPCore periphbase name
GIC_BASE_ADDR is not the base address of the GIC. Its clear from the
code that this is the base address of the MPCore. Rename to
MPCORE_PERIPHBASE accordingly.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
90798bd3507205c16238b8b19a1a58c5437cf7ca.
1387160489.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Crosthwaite [Tue, 17 Dec 2013 19:42:29 +0000 (19:42 +0000)]
arm/xilinx_zynq: Implement CBAR initialisation
Fix the CBAR initialisation by using the newly defined static property.
Zynq will now correctly init the CBAR to the SCU base address.
Needed to boot Linux on the xilinx_zynq machine model.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
8db7d57ebe5418fed397fcc86ea719f98446c178.
1387160489.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Crosthwaite [Tue, 17 Dec 2013 19:42:28 +0000 (19:42 +0000)]
arm/xilinx_zynq: Use object_new() rather than cpu_arm_init()
To allow the machine model to set device properties before CPU
realization.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
e57658b4506b26ab6b6fadbe6d7827f669f51895.
1387160489.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Crosthwaite [Tue, 17 Dec 2013 19:42:28 +0000 (19:42 +0000)]
arm/highbank: Fix CBAR initialisation
Fix the CBAR initialisation by using the newly defined static property.
CBAR is now set before realization, so the intended value is now
actually used.
So I have kind of tested this. I booted an ARM kernel on Highbank with
the stock Highbank DTB. It doesn't boot (and I will be doing something
wrong), but before this patch I got this:
------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at /workspaces/pcrost/public/linux2.git/arch/arm/mm/ioremap.c:301 __arm_ioremap_pfn_caller+0x180/0x198()
CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 3.13.0-rc1-next-
20131126-dirty #2
[<
c0015164>] (unwind_backtrace) from [<
c00118c0>] (show_stack+0x10/0x14)
[<
c00118c0>] (show_stack) from [<
c02bd5fc>] (dump_stack+0x78/0x90)
[<
c02bd5fc>] (dump_stack) from [<
c001f110>] (warn_slowpath_common+0x68/0x84)
[<
c001f110>] (warn_slowpath_common) from [<
c001f1f4>] (warn_slowpath_null+0x1c/0x24)
[<
c001f1f4>] (warn_slowpath_null) from [<
c0017c6c>] (__arm_ioremap_pfn_caller+0x180/0x198)
[<
c0017c6c>] (__arm_ioremap_pfn_caller) from [<
c0017cd8>] (__arm_ioremap_caller+0x54/0x5c)
[<
c0017cd8>] (__arm_ioremap_caller) from [<
c0017d10>] (__arm_ioremap+0x18/0x1c)
[<
c0017d10>] (__arm_ioremap) from [<
c03913c0>] (highbank_init_irq+0x34/0x8c)
[<
c03913c0>] (highbank_init_irq) from [<
c038c228>] (init_IRQ+0x28/0x2c)
[<
c038c228>] (init_IRQ) from [<
c03899ec>] (start_kernel+0x234/0x398)
[<
c03899ec>] (start_kernel) from [<
00008074>] (0x8074)
---[ end trace
3406ff24bd97382f ]---
Which disappears with this patch.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
fedec366aaa512d75093635f523d1dbcb3358361.
1387160489.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Crosthwaite [Tue, 17 Dec 2013 19:42:28 +0000 (19:42 +0000)]
arm/highbank: Use object_new() rather than cpu_arm_init()
To allow the machine model to set device properties before CPU
realization.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
8c671e500390c8be0cc363e887e32867d1d1b0d2.
1387160489.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Crosthwaite [Tue, 17 Dec 2013 19:42:28 +0000 (19:42 +0000)]
target-arm/cpu: Convert reset CBAR to a property
The reset value of the CP15 CBAR is a vendor (machine) configurable
property. If ARM_FEATURE_CBAR is set, add it as a property at
post_init time.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id:
2f1eec3f912135deea6252360e03645003d12e0a.
1387160489.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Crosthwaite [Tue, 17 Dec 2013 19:42:28 +0000 (19:42 +0000)]
target-arm: Define and use ARM_FEATURE_CBAR
Some processors (notably A9 within Highbank) define and use the
CP15 configuration base address (CBAR). This is vendor specific
so its best implemented as a CPU property (otherwise we would need
vendor specific child classes for every ARM implementation).
This patch prepares support for converting CBAR reset value to
a CPU property by moving the CP registration out of the CPU
init fn, as registration will need to happen at realize time
to pick up any property updates. The easiest way to do this
is via definition of a new ARM_FEATURE to flag the existence
of the register.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
9f697ef1e2ee60a3b9ef971a7f3bc3fa6752a9b7.
1387160489.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Crosthwaite [Tue, 17 Dec 2013 19:42:27 +0000 (19:42 +0000)]
target-arm/helper.c: Allow cp15.c15 dummy override
The cp15.c15 space is implementation defined. Currently there is a
dummy placeholder register RAZing it. Allow overriding of this RAZ
so implementations of specific registers can take precedence.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
ed1bacec56dae00cb398c798f8240e8e685f949c.
1387160489.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Roy Franz [Tue, 17 Dec 2013 19:42:27 +0000 (19:42 +0000)]
Fix NOR flash device ID reading
Fix NOR flash manufacturer and device ID reading. This now
properly takes into account device widths and device max widths
as required. The reading of these IDs uses the same max_width
dependent addressing as CFI queries.
The old code remains for chips that don't specify a device width,
as the new code relies on a device width being set in order to
properly operate. The existing code seems very broken.
Only ident0 and ident1 are used in the new code, as other fields
relate to the lock state of blocks in flash.
The VExpress flash configuration has been updated to match
the new code, as the existing definition was 'wrong' in order
to return the expected results with the broken device ID code.
Signed-off-by: Roy Franz <roy.franz@linaro.org>
Message-id:
1386279359-32286-8-git-send-email-roy.franz@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Roy Franz [Tue, 17 Dec 2013 19:42:27 +0000 (19:42 +0000)]
Fix CFI query responses for NOR flash
This change fixes the CFI query responses to handle NOR device
widths that are different from the bank width. Support is also
added for multi-width devices in a x8 configuration. This is
typically x8/x16 devices, but the CFI specification mentions
x8/x32 devices so those should be supported as well if they
exist.
The query response data is now replicated per-device in the bank,
and is adjusted for x16 or x32 parts configured in x8 mode.
The existing code is left in place for boards that have not
been updated to specify an explicit device_width. The VExpress
board has been updated in an earlier patch in this series so
this is the only board currently affected.
Signed-off-by: Roy Franz <roy.franz@linaro.org>
Message-id:
1386279359-32286-7-git-send-email-roy.franz@linaro.org
[PMM: fixed a few formatting nits]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Roy Franz [Tue, 17 Dec 2013 19:42:27 +0000 (19:42 +0000)]
Add max device width parameter for NOR devices
For handling CFI and device ID reads, we need to not only know the
width that a NOR flash device is configured for, but also its maximum
width. The maximum width addressing mode is used for multi-width
parts no matter which width they are configured for. The most common
case is x16 parts that also support x8 mode. When configured for x8
operation these devices respond to CFI and device ID requests differently
than native x8 NOR parts.
Signed-off-by: Roy Franz <roy.franz@linaro.org>
Message-id:
1386279359-32286-6-git-send-email-roy.franz@linaro.org
[PMM: Added comment explaining the semantics of width vs device-width
vs max-device-width]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Roy Franz [Tue, 17 Dec 2013 19:42:26 +0000 (19:42 +0000)]
Set proper device-width for vexpress flash
Create vexpress specific pflash registration
function which properly configures the device-width
of 16 bits (2 bytes) for the NOR flash on the
vexpress platform. This change is required for
buffered flash writes to work properly.
Signed-off-by: Roy Franz <roy.franz@linaro.org>
Message-id:
1386279359-32286-5-git-send-email-roy.franz@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Roy Franz [Tue, 17 Dec 2013 19:42:26 +0000 (19:42 +0000)]
return status for each NOR flash device
Now that we know how wide each flash device that makes up the bank is,
return status for each device in the bank. Leave existing code
that treats 32 bit wide banks as composed of two 16 bit devices as otherwise
we may break configurations that do not set the device_width propery.
Signed-off-by: Roy Franz <roy.franz@linaro.org>
Message-id:
1386279359-32286-4-git-send-email-roy.franz@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Roy Franz [Tue, 17 Dec 2013 19:42:26 +0000 (19:42 +0000)]
Add device-width property to pflash_cfi01
The width of the devices that make up the flash interface
is required to mask certain commands, in particular the
write length for buffered writes. This length will be presented
to each device on the interface by the program writing the flash,
and the flash emulation code needs to be able to determine
the length of the write as recieved by each flash device.
The device-width defaults to the bank width which should
maintain existing behavior for platforms that don't need
this change.
This change is required to support buffered writes on the
vexpress platform that has a 32 bit flash interface with 2
16 bit devices on it.
Signed-off-by: Roy Franz <roy.franz@linaro.org>
Message-id:
1386279359-32286-3-git-send-email-roy.franz@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Roy Franz [Tue, 17 Dec 2013 19:42:26 +0000 (19:42 +0000)]
rename pflash_t member width to bank_width
Rename the 'width' member of the pflash_t structure
in preparation for adding a bank_width member.
Signed-off-by: Roy Franz <roy.franz@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1386279359-32286-2-git-send-email-roy.franz@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Ard Biesheuvel [Tue, 17 Dec 2013 19:42:25 +0000 (19:42 +0000)]
target-arm: add support for v8 AES instructions
This adds support for the AESE/AESD/AESMC/AESIMC instructions that
are available on some v8 implementations of Aarch32.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Message-id:
1386266078-6976-1-git-send-email-ard.biesheuvel@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Laszlo Ersek [Thu, 28 Nov 2013 17:12:59 +0000 (18:12 +0100)]
qemu_opts_parse(): always check return value
qemu_opts_parse() can always return NULL, even if the QemuOptsList.desc in
question would be trivial to satisfy (eg. because it's empty). For
example:
qemu_opts_parse()
opts_parse()
qemu_opts_create()
id_wellformed()
In practice:
$ .../qemu-system-x86_64 -acpitable id=3
qemu-system-x86_64: -acpitable id=3: Parameter 'id' expects an identifier
**
ERROR:vl.c:3491:main: assertion failed: (opts != NULL)
Aborted (core dumped)
$ .../qemu-system-x86_64 -smbios id=3
qemu-system-x86_64: -smbios id=3: Parameter 'id' expects an identifier
Segmentation fault (core dumped)
I checked all qemu_opts_parse() invocations (and all drive_def()
invocations too, because it blindly forwards the former's retval). Only
the two above examples look problematic.
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Message-id:
1385658779-7529-1-git-send-email-lersek@redhat.com
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
Anthony Liguori [Mon, 16 Dec 2013 17:44:13 +0000 (09:44 -0800)]
Merge remote-tracking branch 'spice/tags/pull-spice-1' into staging
Collection of little cleanups anf bugfixes.
nbd patches in preparation of spice-nbd.
# gpg: Signature made Mon 16 Dec 2013 01:27:45 AM PST using RSA key ID
D3E87138
# gpg: Can't check signature: public key not found
# By Marc-André Lureau (12) and Gerd Hoffmann (4)
# Via Gerd Hoffmann
* spice/tags/pull-spice-1:
spice: stop server for qxl hard reset
spice: move spice_server_vm_{start,stop} calls into qemu_spice_display_*()
spice: move qemu_spice_display_*() from spice-graphics to spice-core
nbd: avoid uninitialized warnings
nbd: finish any pending coroutine
nbd: make nbd_client_session_close() idempotent
nbd: pass export name as init argument
nbd: don't change socket block during negotiate
Split nbd block client code
spice-char: implement chardev port event
char: add qemu_chr_fe_event()
include: add missing config-host.h include
qmp_change_blockdev() remove unused has_format
spice-char: remove unused field
vscclient: do not add a socket watch if there is not data to send
spice: flip streaming video mode to off by default
Anthony Liguori [Mon, 16 Dec 2013 17:43:27 +0000 (09:43 -0800)]
Merge remote-tracking branch 'kwolf/tags/for-anthony' into staging
Block patches
# gpg: Signature made Fri 13 Dec 2013 09:47:03 AM PST using RSA key ID
C88F2FD6
# gpg: Can't check signature: public key not found
# By Peter Lieven (2) and others
# Via Kevin Wolf
* kwolf/tags/for-anthony:
blkdebug: Use QLIST_FOREACH_SAFE to resume IO
qemu-img: make progress output more accurate during convert
block: expect get_block_status errors in bdrv_make_zero
block/vvfat: Fix compiler warnings for OpenBSD
qapi-schema.json: Change 1.8 reference to 2.0
sheepdog: check if '-o redundancy' is passed from user
Message-id:
1386956943-19474-1-git-send-email-kwolf@redhat.com
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
Gerd Hoffmann [Mon, 9 Dec 2013 15:03:49 +0000 (16:03 +0100)]
spice: stop server for qxl hard reset
Hard reset can happen at any time. We should be able to put qxl into a
known-good state no matter what. Stop spice server thread for reset so
it can't be confused by fetching stale commands lingering around in the
rings while we reset is ongoing.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Gerd Hoffmann [Mon, 9 Dec 2013 15:00:15 +0000 (16:00 +0100)]
spice: move spice_server_vm_{start,stop} calls into qemu_spice_display_*()
So calling spice server to start/stop the worker goes
hand in hand with the status variable update.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Gerd Hoffmann [Mon, 9 Dec 2013 14:54:46 +0000 (15:54 +0100)]
spice: move qemu_spice_display_*() from spice-graphics to spice-core
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Marc-André Lureau [Sun, 1 Dec 2013 21:23:46 +0000 (22:23 +0100)]
nbd: avoid uninitialized warnings
==15815== Thread 1:
==15815== Syscall param socketcall.sendto(msg) points to uninitialised byte(s)
==15815== at 0x65AD5CB: send (send.c:31)
==15815== by 0x37F84B: nbd_wr_sync (nbd.c:145)
==15815== by 0x37F94B: write_sync (nbd.c:186)
==15815== by 0x380FA9: nbd_send_request (nbd.c:681)
==15815== by 0x1C4A2D: nbd_teardown_connection (nbd-client.c:337)
==15815== by 0x1C4AD8: nbd_client_session_close (nbd-client.c:354)
==15815== by 0x1ED2D8: close_socketpair (spicebd.c:132)
==15815== by 0x1EE265: spice_close (spicebd.c:457)
==15815== by 0x1ACBF6: bdrv_close (block.c:1519)
==15815== by 0x1AD804: bdrv_delete (block.c:1772)
==15815== by 0x1B4136: bdrv_unref (block.c:4476)
==15815== by 0x1ACCE0: bdrv_close (block.c:1541)
==15815== Address 0x7feffef98 is on thread 1's stack
Signed-off-by: Marc-André Lureau <marcandre.lureau@gmail.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Marc-André Lureau [Sun, 1 Dec 2013 21:23:45 +0000 (22:23 +0100)]
nbd: finish any pending coroutine
Make sure all pending coroutines are finished when closing the session.
Signed-off-by: Marc-André Lureau <marcandre.lureau@gmail.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Marc-André Lureau [Sun, 1 Dec 2013 21:23:44 +0000 (22:23 +0100)]
nbd: make nbd_client_session_close() idempotent
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Marc-André Lureau [Sun, 1 Dec 2013 21:23:43 +0000 (22:23 +0100)]
nbd: pass export name as init argument
There is no need to keep the export name around, and it seems a better
fit as an argument in the init() call.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Marc-André Lureau [Sun, 1 Dec 2013 21:23:42 +0000 (22:23 +0100)]
nbd: don't change socket block during negotiate
The caller might handle non-blocking using coroutine. Leave the choice
to the caller to use a blocking or non-blocking negotiate.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Marc-André Lureau [Sun, 1 Dec 2013 21:23:41 +0000 (22:23 +0100)]
Split nbd block client code
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Marc-André Lureau [Sun, 1 Dec 2013 21:23:40 +0000 (22:23 +0100)]
spice-char: implement chardev port event
Wire up chardev fe_event to Spice port.
Signed-off-by: Marc-André Lureau <marcandre.lureau@gmail.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Marc-André Lureau [Sun, 1 Dec 2013 21:23:39 +0000 (22:23 +0100)]
char: add qemu_chr_fe_event()
Teach the chardev frontend to send event. This is used by the Spice port
chardev currently.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Marc-André Lureau [Sun, 1 Dec 2013 21:23:38 +0000 (22:23 +0100)]
include: add missing config-host.h include
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Marc-André Lureau [Sun, 1 Dec 2013 21:23:37 +0000 (22:23 +0100)]
qmp_change_blockdev() remove unused has_format
Signed-off-by: Marc-André Lureau <marcandre.lureau@gmail.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Marc-André Lureau [Sun, 1 Dec 2013 21:23:36 +0000 (22:23 +0100)]
spice-char: remove unused field
Signed-off-by: Marc-André Lureau <marcandre.lureau@gmail.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Marc-André Lureau [Sun, 1 Dec 2013 21:23:35 +0000 (22:23 +0100)]
vscclient: do not add a socket watch if there is not data to send
Fixes the following error:
** (process:780): CRITICAL **: do_socket_send: assertion
`socket_to_send->len != 0' failed
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Gerd Hoffmann [Mon, 2 Dec 2013 10:17:04 +0000 (11:17 +0100)]
spice: flip streaming video mode to off by default
Video streaming detection heuristics in spice-server have problems
keeping modern desktop animations (as done by gnome shell) and real
video playback apart. This leads to jpeg compression artefacts on
your desktop, due to spice using mjpeg to send what it thinks is
a video stream.
Turn off video detection by default to avoid these artifacts.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Alon Levy <alevy@redhat.com>
Anthony Liguori [Fri, 13 Dec 2013 19:10:33 +0000 (11:10 -0800)]
Merge remote-tracking branch 'bonzini/virtio' into staging
# By Andreas Färber (18) and Paolo Bonzini (12)
# Via Paolo Bonzini
* bonzini/virtio: (30 commits)
virtio: Convert exit to unrealize
virtio: Complete converting VirtioDevice to QOM realize
virtio-scsi: Convert to QOM realize
virtio-rng: Convert to QOM realize
virtio-balloon: Convert to QOM realize
virtio-net: Convert to QOM realize
virtio-serial: Convert to QOM realize
virtio-blk: Convert to QOM realize
virtio-9p: Convert to QOM realize
virtio: Start converting VirtioDevice to QOM realize
virtio-scsi: QOM realize preparations
virtio-rng: QOM realize preparations
virtio-balloon: QOM realize preparations
virtio-net: QOM realize preparations
virtio-serial: QOM realize preparations
virtio-blk: QOM realize preparations
virtio-9p: QOM realize preparations
virtio-blk-dataplane: Improve error reporting
virtio-pci: add device_unplugged callback
virtio-rng: switch exit callback to VirtioDeviceClass
...
Anthony Liguori [Fri, 13 Dec 2013 19:10:19 +0000 (11:10 -0800)]
Merge remote-tracking branch 'mst/tags/for_anthony' into staging
acpi.pci,pc,memory core fixes
Most notably this includes changes to exec to support
full 64 bit addresses.
This also flushes out patches that got queued during 1.7 freeze.
There are new tests, and a bunch of bug fixes all over the place.
There are also some changes mostly useful for downstreams.
I'm also listing myself as pc co-maintainer. I'm doing this reluctantly,
but this seems to be necessary to make sure patches are not lost or delayed too
much, and posting the MAINTAINERS patch did not seem to make anyone else
volunteer.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
# gpg: Signature made Wed 11 Dec 2013 10:21:51 AM PST using RSA key ID
D28D5469
# gpg: Can't check signature: public key not found
# By Michael S. Tsirkin (14) and others
# Via Michael S. Tsirkin
* mst/tags/for_anthony: (28 commits)
pc: use macro for HPET type
hpet: fix build with CONFIG_HPET off
acpi unit-test: adjust the test data structure for better handling
acpi unit-test: load and check facs table
exec: separate sections and nodes per address space
memory.c: bugfix - ref counting mismatch in memory_region_find
hpet: enable to entitle more irq pins for hpet
hpet: inverse polarity when pin above ISA_NUM_IRQS
pci: fix pci bridge fw path
ACPI DSDT: Make control method `IQCR` serialized
acpi: strip compiler info in built-in DSDT
acpi unit-test: verify signature and checksum
smbios: Set system manufacturer, product & version by default
exec: reduce L2_PAGE_SIZE
exec: make address spaces 64-bit wide
exec: memory radix tree page level compression
exec: pass hw address to phys_page_find
exec: extend skip field to 6 bit, page entry to 32 bit
exec: replace leaf with skip
split definitions for exec.c and translate-all.c radix trees
...
Message-id: cover.
1386786228.git.mst@redhat.com
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
Anthony Liguori [Fri, 13 Dec 2013 19:10:02 +0000 (11:10 -0800)]
Merge remote-tracking branch 'bonzini/scsi-next' into staging
# By Paolo Bonzini (4) and Peter Lieven (1)
# Via Paolo Bonzini
* bonzini/scsi-next:
help: add id suboption to -iscsi
scsi-disk: fix WRITE SAME with large non-zero payload
block/iscsi: introduce bdrv_co_{readv, writev, flush_to_disk}
scsi-disk: fix VERIFY emulation
scsi-bus: fix transfer length and direction for VERIFY command
Message-id:
1386594157-17535-1-git-send-email-pbonzini@redhat.com
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
Fam Zheng [Fri, 13 Dec 2013 07:25:12 +0000 (15:25 +0800)]
blkdebug: Use QLIST_FOREACH_SAFE to resume IO
Qemu-iotest 030 was broken.
When the coroutine runs and finishes, it will remove itself from the req
list, so let's use safe version of foreach to avoid use after free.
Signed-off-by: Fam Zheng <famz@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Peter Lieven [Thu, 5 Dec 2013 14:54:53 +0000 (15:54 +0100)]
qemu-img: make progress output more accurate during convert
the progress output is very bumpy if the input images contains
a significant portion of unallocated sectors. This patch
checks how much sectors are allocated a priori if progress
output is selected.
Signed-off-by: Peter Lieven <pl@kamp.de>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Peter Lieven [Thu, 12 Dec 2013 12:57:05 +0000 (13:57 +0100)]
block: expect get_block_status errors in bdrv_make_zero
during testing around with 4k LUNs a bad target implementation
triggert an -EIO in iscsi_get_block_status, but it got never caught
resulting in an infinite loop.
CC: qemu-stable@nongnu.org
Signed-off-by: Peter Lieven <pl@kamp.de>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Stefan Weil [Wed, 11 Dec 2013 20:37:11 +0000 (21:37 +0100)]
block/vvfat: Fix compiler warnings for OpenBSD
The buildbot shows these compiler warnings:
block/vvfat.c: In function 'create_short_and_long_name':
block/vvfat.c:620: warning: array size (8) smaller than bound length (11)
block/vvfat.c:620: warning: array size (8) smaller than bound length (11)
block/vvfat.c:635: warning: array size (8) smaller than bound length (11)
block/vvfat.c:635: warning: array size (8) smaller than bound length (11)
They are caused by tricky code where 8 characters for the name are followed
by 3 characters for the extension, and some operations touch both name and
extension.
Using an 11 character name which includes the extension fixes the compiler
warning, satisfies cppcheck, valgrind and maybe other static and dynamic
code checkers, and even simplifies some parts of the code.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Kevin Wolf [Tue, 10 Dec 2013 13:01:27 +0000 (14:01 +0100)]
qapi-schema.json: Change 1.8 reference to 2.0
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Liu Yuan [Sun, 8 Dec 2013 16:11:20 +0000 (00:11 +0800)]
sheepdog: check if '-o redundancy' is passed from user
This fix a segfault (that is caused by
b3af018f3) of following command:
$ qemu-img convert some_img sheepdog:some_img
Cc: qemu-devel@nongnu.org
Cc: Kevin Wolf <kwolf@redhat.com>
Cc: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Liu Yuan <namei.unix@gmail.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Richard Henderson [Tue, 10 Dec 2013 23:40:21 +0000 (15:40 -0800)]
target-microblaze: Use the new qemu_ld/st opcodes
The ability of the new opcodes to byte-swap the memory operation
simplifies the code in and around dec_load and dec_store significantly.
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Tested-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Michael S. Tsirkin [Wed, 11 Dec 2013 00:48:49 +0000 (02:48 +0200)]
pc: use macro for HPET type
avoid hard-coding strings
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Michael S. Tsirkin [Wed, 11 Dec 2013 00:47:16 +0000 (02:47 +0200)]
hpet: fix build with CONFIG_HPET off
make hpet_find inline so we don't need
to build hpet.c to check if hpet is enabled.
Fixes link error with CONFIG_HPET off.
Cc: qemu-stable@nongnu.org
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Marcel Apfelbaum [Thu, 21 Nov 2013 19:33:22 +0000 (21:33 +0200)]
acpi unit-test: adjust the test data structure for better handling
Ensure more then one instance of test_data may exist
at a given time. It will help to compare different
acpi table versions.
Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Marcel Apfelbaum [Thu, 21 Nov 2013 19:33:21 +0000 (21:33 +0200)]
acpi unit-test: load and check facs table
FACS table does not have a checksum, so we can
check at least the signature (existence).
Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Marcel Apfelbaum [Sun, 1 Dec 2013 12:02:23 +0000 (14:02 +0200)]
exec: separate sections and nodes per address space
Every address space has its own nodes and sections, but
it uses the same global arrays of nodes/section.
This limits the number of devices that can be attached
to the guest to 20-30 devices. It happens because:
- The sections array is limited to 2^12 entries.
- The main memory has at least 100 sections.
- Each device address space is actually an alias to
main memory, multiplying its number of nodes/sections.
Remove the limitation by using separate arrays of
nodes and sections for each address space.
Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Marcel Apfelbaum [Mon, 2 Dec 2013 14:20:59 +0000 (16:20 +0200)]
memory.c: bugfix - ref counting mismatch in memory_region_find
'address_space_get_flatview' gets a reference to a FlatView.
If the flatview lookup fails, the code returns without
"unreferencing" the view.
Cc: qemu-stable@nongnu.org
Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Liu Ping Fan [Sun, 8 Dec 2013 09:38:17 +0000 (17:38 +0800)]
hpet: enable to entitle more irq pins for hpet
Owning to some different hardware design, piix and q35 need
different compat. So making them diverge.
On q35, IRQ2/8 can be reserved for hpet timer 0/1. And pin 16~23
can be assigned to hpet as guest chooses. So we introduce intcap
property to do that.
Consider the compat and piix/q35, we finally have the following
value for intcap: For piix, hpet's intcap is hard coded as IRQ2.
For pc-q35-1.7 and earlier, we use IRQ2 for compat reason. Otherwise
IRQ2, IRQ8, and IRQ16~23 are allowed.
Signed-off-by: Liu Ping Fan <pingfank@linux.vnet.ibm.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Liu Ping Fan [Sun, 8 Dec 2013 09:38:16 +0000 (17:38 +0800)]
hpet: inverse polarity when pin above ISA_NUM_IRQS
According to hpet spec, hpet irq is high active. But according to
ICH spec, there is inversion before the input of ioapic. So the OS
will expect low active on this IRQ line. (On bare metal, if OS driver
claims high active on this line, spurious irq is generated)
We fold the emulation of this inversion inside the hpet logic.
Signed-off-by: Liu Ping Fan <pingfank@linux.vnet.ibm.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Gerd Hoffmann [Fri, 6 Dec 2013 11:24:40 +0000 (12:24 +0100)]
pci: fix pci bridge fw path
qemu uses "pci" as name for pci bridges in the firmware device path.
seabios expects "pci-bridge". Result is that bootorder is broken for
devices behind pci bridges.
Some googling suggests that "pci-bridge" is the correct one. At least
PPC-based Apple machines are using this. See question "How do I boot
from a device attached to a PCI card" here:
http://www.netbsd.org/ports/macppc/faq.html
So lets change qemu to use "pci-bridge" too.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Anthony Liguori [Wed, 11 Dec 2013 00:14:36 +0000 (16:14 -0800)]
Merge remote-tracking branch 'rth/tcg-temp-order' into staging
# By Richard Henderson
# Via Richard Henderson
* rth/tcg-temp-order:
tcg: Use bitmaps for free temporaries
Message-id:
1386698065-6661-1-git-send-email-rth@twiddle.net
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
Anthony Liguori [Wed, 11 Dec 2013 00:14:20 +0000 (16:14 -0800)]
Merge remote-tracking branch 'stefanha/net-next' into staging
# By Vincenzo Maffione (2) and others
# Via Stefan Hajnoczi
* stefanha/net-next:
net: Update netdev peer on link change
virtio-net: don't update mac_table in error state
MAINTAINERS: Add netmap maintainers
net: Adding netmap network backend
Message-id:
1386594692-21278-1-git-send-email-stefanha@redhat.com
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
Anthony Liguori [Wed, 11 Dec 2013 00:13:32 +0000 (16:13 -0800)]
Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-
20131210' into staging
target-arm queue:
* support REFCNT register on integrator/cp board
* implement the A9MP's global timer
* add the 'virt' platform
* support '-cpu host' on KVM/ARM
* Cadence GEM ethernet device bugfixes
* Implement 32-bit ARMv8 VSEL, VMAXNM, VMINNM
* fix TTBCR write masking
* update 32 bit decoder to use new qemu_ld/st TCG opcodes
# gpg: Signature made Tue 10 Dec 2013 06:22:01 AM PST using RSA key ID
14360CDE
# gpg: Can't check signature: public key not found
# By Peter Crosthwaite (16) and others
# Via Peter Maydell
* pmaydell/tags/pull-target-arm-
20131210: (37 commits)
target-arm: fix TTBCR write masking
target-arm: Use new qemu_ld/st opcodes
target-arm: Implement ARMv8 SIMD VMAXNM and VMINNM instructions.
target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions.
softfloat: Add minNum() and maxNum() functions to softfloat.
softfloat: Remove unused argument from MINMAX macro.
target-arm: Implement ARMv8 VSEL instruction.
target-arm: Move call to disas_vfp_insn out of disas_coproc_insn.
net/cadence_gem: Don't rx packets when no rx buffer available
net/cadence_gem: Improve can_receive debug printfery
net/cadence_gem: Fix register w1c logic
net/cadence_gem: Fix small packet FCS stripping
net/cadence_gem: Fix rx multi-fragment packets
net/cadence_gem: Add missing VMSTATE_END_OF_LIST
net/cadence_gem: Implement SAR (de)activation
net/cadence_gem: Implement SAR match bit in rx desc
net/cadence_gem: Implement RX descriptor match mode flags
net/cadence_gem: Prefetch rx descriptors ASAP
net/cadence_gem: simplify rx buf descriptor walking
net/cadence_gem: Don't assert against 0 buffer address
...
Message-id:
1386686613-2390-1-git-send-email-peter.maydell@linaro.org
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
Anthony Liguori [Wed, 11 Dec 2013 00:11:21 +0000 (16:11 -0800)]
Merge remote-tracking branch 'kraxel/tags/pull-audio-1' into staging
Change audio wakeup rate from 250 Hz to 100 Hz.
Emulation bugfixes for intel-hda and adlib.
# gpg: Signature made Mon 09 Dec 2013 06:04:16 AM PST using RSA key ID
D3E87138
# gpg: Can't check signature: public key not found
# By Gerd Hoffmann (2) and others
# Via Gerd Hoffmann
* kraxel/tags/pull-audio-1:
intel-hda: fix position buffer
adlib: fix patching of port I/O addresses
audio: adjust pulse to 100Hz wakeup rate
audio: Lower default wakeup rate to 100 times / second
Message-id:
1386597974-26506-1-git-send-email-kraxel@redhat.com
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
Anthony Liguori [Wed, 11 Dec 2013 00:11:10 +0000 (16:11 -0800)]
Merge remote-tracking branch 'alon/libcacard_ccid.4' into staging
# By Stefan Weil
# Via Alon Levy
* alon/libcacard_ccid.4:
libcacard: Fix compilation for older versions of glib (bug #
1258168)
Message-id:
1386596263-26151-1-git-send-email-alevy@redhat.com
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
Anthony Liguori [Wed, 11 Dec 2013 00:09:34 +0000 (16:09 -0800)]
Merge remote-tracking branch 'mjt/trivial-patches' into staging
# By Stefan Weil
# Via Michael Tokarev
* mjt/trivial-patches:
qxl: Add missing trace.h (fix broken build)
Message-id:
1386441094-9971-1-git-send-email-mjt@msgid.tls.msk.ru
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
Richard Henderson [Thu, 19 Sep 2013 19:16:45 +0000 (12:16 -0700)]
tcg: Use bitmaps for free temporaries
We previously allocated 32-bits per temp for the next_free_temp entry.
We now allocate 4 bits per temp across the 4 bitmaps.
Using a linked list meant that if a translator is tweeked, resulting in
temps being freed in a different order, that would have follow-on effects
throughout the TB. Always allocating the lowest free temp means that
follow-on effects are minimized, which can make it easier to diff output
when debugging the translators.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Sergey Fedorov [Tue, 10 Dec 2013 06:41:49 +0000 (10:41 +0400)]
target-arm: fix TTBCR write masking
Current implementation is not accurate according to ARMv7-AR reference
manual. See "B4.1.153 TTBCR, Translation Table Base Control Register,
VMSA | TTBCR format when using the Long-descriptor translation table
format". When LPAE feature is supported, EAE, bit[31] selects
translation descriptor format and, therefore, TTBCR format.
Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1386657709-23399-1-git-send-email-s.fedorov@samsung.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Mon, 9 Dec 2013 22:37:06 +0000 (14:37 -0800)]
target-arm: Use new qemu_ld/st opcodes
Retain the existing gen_aa32_* inlines, to aid compilation for A64.
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-id:
1386628626-21627-1-git-send-email-rth@twiddle.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Will Newton [Fri, 6 Dec 2013 17:01:42 +0000 (17:01 +0000)]
target-arm: Implement ARMv8 SIMD VMAXNM and VMINNM instructions.
This adds support for the ARMv8 Advanced SIMD VMAXNM and VMINNM
instructions.
Signed-off-by: Will Newton <will.newton@linaro.org>
Message-id:
1386158099-9239-7-git-send-email-will.newton@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Will Newton [Fri, 6 Dec 2013 17:01:41 +0000 (17:01 +0000)]
target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions.
This adds support for the ARMv8 floating point VMAXNM and VMINNM
instructions.
Signed-off-by: Will Newton <will.newton@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1386158099-9239-6-git-send-email-will.newton@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Will Newton [Fri, 6 Dec 2013 17:01:41 +0000 (17:01 +0000)]
softfloat: Add minNum() and maxNum() functions to softfloat.
Add floatnn_minnum() and floatnn_maxnum() functions which are equivalent
to the minNum() and maxNum() functions from IEEE 754-2008. They are
similar to min() and max() but differ in the handling of QNaN arguments.
Signed-off-by: Will Newton <will.newton@linaro.org>
Message-id:
1386158099-9239-5-git-send-email-will.newton@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Will Newton [Fri, 6 Dec 2013 17:01:41 +0000 (17:01 +0000)]
softfloat: Remove unused argument from MINMAX macro.
The nan_exp argument is not used, so remove it.
Signed-off-by: Will Newton <will.newton@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1386158099-9239-4-git-send-email-will.newton@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Will Newton [Fri, 6 Dec 2013 17:01:40 +0000 (17:01 +0000)]
target-arm: Implement ARMv8 VSEL instruction.
This adds support for the VSEL floating point selection instruction
which was added in ARMv8.
Signed-off-by: Will Newton <will.newton@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1386158099-9239-3-git-send-email-will.newton@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Will Newton [Fri, 6 Dec 2013 17:01:40 +0000 (17:01 +0000)]
target-arm: Move call to disas_vfp_insn out of disas_coproc_insn.
Floating point is an extension to the instruction set rather than
a coprocessor, so call it directly from the ARM and Thumb decode
functions.
Signed-off-by: Will Newton <will.newton@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1386158099-9239-2-git-send-email-will.newton@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Crosthwaite [Wed, 4 Dec 2013 06:02:03 +0000 (22:02 -0800)]
net/cadence_gem: Don't rx packets when no rx buffer available
Return false from can_receive() when no valid buffer descriptor is
available. Ensures against mass packet droppage in some applications.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id:
cde00ef774e84e2586bf10fd37b542f75bf36cfb.
1386136219.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Crosthwaite [Wed, 4 Dec 2013 06:01:28 +0000 (22:01 -0800)]
net/cadence_gem: Improve can_receive debug printfery
Currently this just floods indicating that can_receive has been called
by the net framework. Instead, save the result of the most recent
can_receive callback as state and only print a message if the result
changes (indicating some sort of actual state change in GEM). Make said
debug message more meaningful as well.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id:
2eb74ca6a5756aea242d9f525961db95d6cfcf2c.
1386136219.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Crosthwaite [Wed, 4 Dec 2013 06:00:54 +0000 (22:00 -0800)]
net/cadence_gem: Fix register w1c logic
This write-1-clear logic was incorrect. It was always clearing w1c
bits regardless of whether the written value was 1 or not. i.e. it
was implementing a write-anything-to-clear strategy.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
ed905b04d3343966ded425f06aa2224bc7a35b59.
1386136219.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Crosthwaite [Wed, 4 Dec 2013 06:00:17 +0000 (22:00 -0800)]
net/cadence_gem: Fix small packet FCS stripping
The minimum packet size is 64, however this is before FCS stripping
occurs. So when FCS stripping the minimum packet size is 60. Fix.
Reported-by: Deepika Dhamija <deepika@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id:
8aac5bd737f9cf48b87f32943d7eb5939061e546.
1386136219.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Crosthwaite [Wed, 4 Dec 2013 05:59:43 +0000 (21:59 -0800)]
net/cadence_gem: Fix rx multi-fragment packets
Bytes_to_copy was being updated before its final use where it
advances the rx buffer pointer. This was causing total mayhem,
where packet data for any subsequent fragments was being fetched
from the wrong place.
Reported-by: Deepika Dhamija <deepika@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
c2a1c65c1fd06eb274442a0fa4a6839d940e145e.
1386136219.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Crosthwaite [Wed, 4 Dec 2013 05:59:08 +0000 (21:59 -0800)]
net/cadence_gem: Add missing VMSTATE_END_OF_LIST
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id:
8f8c2bfb15f40fb5f0d5766aa4cd3d54c596de6a.
1386136219.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Crosthwaite [Wed, 4 Dec 2013 05:58:34 +0000 (21:58 -0800)]
net/cadence_gem: Implement SAR (de)activation
The Specific address registers can be enabled or disabled by software.
QEMU was assuming they were always enabled. Implement the
disable/enable feature. SARs are disabled by writing to the lower half
register. They are re-enabled by then writing the upper half.
Reported-by: Deepika Dhamija <deepika@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id:
49efd1f7450af8f980b967d3054245bae137866c.
1386136219.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Crosthwaite [Wed, 4 Dec 2013 05:57:59 +0000 (21:57 -0800)]
net/cadence_gem: Implement SAR match bit in rx desc
Bit 27 of the RX buffer desc word 1 should be set when the packet was
accepted due to specific address register match. Implement.
This feature is absent from the Xilinx documentation (UG585) but the
behaviour is tested as accurate on real hardware.
Reported-by: Deepika Dhamija <deepika@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
7e3f26fc4ab244e8123efc12723e7164730abdcb.
1386136219.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Crosthwaite [Wed, 4 Dec 2013 05:57:24 +0000 (21:57 -0800)]
net/cadence_gem: Implement RX descriptor match mode flags
The various Rx packet address matching mode flags were not being set in
the rx descriptor. Implement.
Reported-by: Deepika Dhamija <deepika@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id:
6002a24a6a8ceaa11d3009ab5392840d1c084b28.
1386136219.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>