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Sanjay Patel [Mon, 19 Feb 2018 21:13:39 +0000 (21:13 +0000)]
[InstCombine] move fdiv tests; NFC
Also, use vector constants just to prove that already works.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325530
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Brian Gesiak [Mon, 19 Feb 2018 20:50:09 +0000 (20:50 +0000)]
[Coroutines] Move debug statement before assert
Summary:
Move a debug statement to above where an assertion is hit, so that the debug
statement can be inspected before a stack trace.
Test Plan: `check-llvm`
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325529
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Alexander Richardson [Mon, 19 Feb 2018 19:53:44 +0000 (19:53 +0000)]
[llvm-objcopy] Use the full filename in --add-gnu-debuglink
Summary:
The current implementation was writing the file name without the extension
whereas GNU objcopy writes the full filename. With this change GDB will now
load the .debug file instead of silently ignoring it.
Reviewers: jakehehrlich, jhenderson
Reviewed By: jakehehrlich
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D43474
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325528
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Craig Topper [Mon, 19 Feb 2018 19:23:35 +0000 (19:23 +0000)]
[X86] Stop swapping the operands of AVX512 setge.
We swapped the operands and used setle, but I don't see any reason to do that. I think this is a holdover from SSE where we swap and the invert to use pcmpgt. But with AVX512 we don't want an invert so we won't use pcmpgt. So there's no need to swap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325527
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Craig Topper [Mon, 19 Feb 2018 19:23:31 +0000 (19:23 +0000)]
[X86] Reduce the number of isel pattern variations needed for VPTESTM/VPTESTNM matching.
Canonicalize EQ/NE PCMPM to have build vector all zeros on the RHS so we don't have to pattern match it in both locations. This significantly reduces the number of isel patterns needed since we also had to multiply it out with loads being in either operand of the 'and' input node and in the 'and' masking node.
This removes over 24000 bytes from the isel table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325526
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Steven Wu [Mon, 19 Feb 2018 19:22:28 +0000 (19:22 +0000)]
bitcode support change for fast flags compatibility
Summary: The discussion and as per need, each vendor needs a way to keep the old fast flags and the new fast flags in the auto upgrade path of the IR upgrader. This revision addresses that issue.
Patched by Michael Berg
Reviewers: qcolombet, hans, steven_wu
Reviewed By: qcolombet, steven_wu
Subscribers: dexonsmith, vsk, mehdi_amini, andrewrk, MatzeB, wristow, spatel
Differential Revision: https://reviews.llvm.org/D43253
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325525
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Mark Searles [Mon, 19 Feb 2018 19:19:59 +0000 (19:19 +0000)]
[AMDGPU] Make note of existing waitcnt instrs; this is add-on work related to suppression of redundant waitcnt instrs. It is necessary to make note of these existing waitcnt instrs so that we do not fall into an infinite loop when handling loops. Also, [NFC] some minor code clean-up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325524
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Simon Pilgrim [Mon, 19 Feb 2018 18:08:16 +0000 (18:08 +0000)]
[SelectionDAG] ComputeKnownBits - add support for SMIN+SMAX clamp patterns
If we have a clamp pattern, SMIN(SMAX(X, LO),HI) or SMAX(SMIN(X, HI),LO) then we can deduce that the number of signbits (zeros/ones) will be at least the minimum of the LO and HI constants.
ComputeKnownBits equivalent of D43338.
Differential Revision: https://reviews.llvm.org/D43463
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325521
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Mark Searles [Mon, 19 Feb 2018 16:42:49 +0000 (16:42 +0000)]
[AMDGPU] Increased vector length for global/constant loads.
Summary: GCN ISA supports instructions that can read 16 consecutive dwords from memory through the scalar data cache; loadstoreVectorizer should take advantage of the wider vector length and pack 16/8 elements of dwords/quadwords.
Author: FarhanaAleen
Reviewed By: rampitec
Subscribers: llvm-commits, AMDGPU
Differential Revision: https://reviews.llvm.org/D43275
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325518
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David Green [Mon, 19 Feb 2018 16:28:24 +0000 (16:28 +0000)]
[Dominators] Update DominatorTree compare in case roots are different
The compare function, unusually, returns false on same, true on
different. This fixes the conditions for different roots.
Reviewed as a part of D41298.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325517
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Pavel Labath [Mon, 19 Feb 2018 16:12:20 +0000 (16:12 +0000)]
[CodeGen] Refactor AppleAccelTable
Summary:
This commit separates the abstract accelerator table data structure
from the code for writing out an on-disk representation of a specific
accelerator table format. The idea is that former (now called
AccelTable<T>) can be reused for the DWARF v5 accelerator tables
as-is, without any further customizations.
Some bits of the emission code (now living in the EmissionContext class)
can be reused for DWARF v5 as well, but the subtle differences in the
layout of various subtables mean the sharing is not always possible.
(Also, the individual emit*** functions are fairly simple so there's a
tradeoff between making a bigger general-purpose function, and two
smaller targeted functions.)
Another advantage of this setup is that more of the serialization logic
can be hidden in the .cpp file -- I have moved declarations of the
header and all the emission functions there.
Reviewers: JDevlieghere, aprantl, probinson, dblaikie
Subscribers: echristo, clayborg, vleschuk, llvm-commits
Differential Revision: https://reviews.llvm.org/D43285
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325516
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Sanjay Patel [Mon, 19 Feb 2018 16:11:44 +0000 (16:11 +0000)]
[TTI CostModel] change default cost of FP ops to 1 (PR36280)
This change was mentioned at least as far back as:
https://bugs.llvm.org/show_bug.cgi?id=26837#c26
...and I found a real program that is harmed by this:
Himeno running on AMD Jaguar gets 6% slower with SLP vectorization:
https://bugs.llvm.org/show_bug.cgi?id=36280
...but the change here appears to solve that bug only accidentally.
The div/rem costs for x86 look very wrong in some cases, but that's already true,
so we can fix those in follow-up patches. There's also evidence that more cost model
changes are needed to solve SLP problems as shown in D42981, but that's an independent
problem (though the solution may be adjusted after this change is made).
Differential Revision: https://reviews.llvm.org/D43079
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325515
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Rafael Espindola [Mon, 19 Feb 2018 16:02:38 +0000 (16:02 +0000)]
Bring back r323297.
It was reverted because it broke the grub build. The reason the grub
build broke is because grub does its own relocation processing and was
not handing R_386_PLT32. Since grub has no dynamic linker, the fix is
trivial: handle R_386_PLT32 exactly like R_386_PC32.
On the report it was noted that they are using
-fno-integrated-assembler. The upstream GAS (starting with
451875b4f976a527395e9303224c7881b65e12ed) will already be producing a
R_386_PLT32 anyway, so they have to update their code one way or the
other
Original message:
Don't assume a null GV is local for ELF and MachO.
This is already a simplification, and should help with avoiding a plt
reference when calling an intrinsic with -fno-plt.
With this change we return false for null GVs, so the caller only
needs to check the new metadata to decide if it should use foo@plt or
*foo@got.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325514
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Francis Visoiu Mistrih [Mon, 19 Feb 2018 15:51:17 +0000 (15:51 +0000)]
[CodeGen] Fix tests breaking after r325505
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325512
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Charles Saternos [Mon, 19 Feb 2018 15:14:50 +0000 (15:14 +0000)]
[ThinLTO] Add GraphTraits for FunctionSummaries
Add GraphTraits definitions to the FunctionSummary and ModuleSummaryIndex classes. These GraphTraits will be used to construct find SCC's in ThinLTO analysis passes.
Third attempt - moved function from lambda to static function due to build failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325506
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Francis Visoiu Mistrih [Mon, 19 Feb 2018 15:08:49 +0000 (15:08 +0000)]
Revert "[CodeGen] Move printing '\n' from MachineInstr::print to MachineBasicBlock::print"
This reverts commit r324681.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325505
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Simon Pilgrim [Mon, 19 Feb 2018 13:29:20 +0000 (13:29 +0000)]
[X86][SSE] combineTruncateWithSat - use truncateVectorWithPACK down to 64-bit subvectors
Add support for chaining PACKSS/PACKUS down to 64-bit vectors by using only a single 128-bit input.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325494
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Ivan A. Kosarev [Mon, 19 Feb 2018 12:10:20 +0000 (12:10 +0000)]
[Transforms] Propagate new-format TBAA tags on simplification of memory-transfer intrinsics
With this patch in place, when a new-format TBAA tag is available
for a memory-transfer intrinsic call, we prefer propagating that
new-format tag. Otherwise, we fallback to the old approach where
we try to construct a proper TBAA access tag from 'tbaa.struct'
metadata.
Differential Revision: https://reviews.llvm.org/D41543
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325488
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Igor Laevsky [Mon, 19 Feb 2018 11:57:07 +0000 (11:57 +0000)]
[llvm-opt-fuzzer] Add another pack of passes for continuous fuzzing
Differential Revision: https://reviews.llvm.org/D43384
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325487
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Dylan McKay [Mon, 19 Feb 2018 10:40:59 +0000 (10:40 +0000)]
[AVR] Set the program address space in the data layout
This adds the program memory address space setting to the AVR data
layout.
This setting was very recently added under r325479.
At the moment, there are no uses of this setting. In the future, things
such as switch lookup tables should reside there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325481
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Dylan McKay [Mon, 19 Feb 2018 09:56:22 +0000 (09:56 +0000)]
Add default address space for functions to the data layout (1/3)
Summary:
This adds initial support for letting targets specify which address
spaces their functions should reside in by default.
If a function is created by a frontend, it will get the default address space specified in the DataLayout, unless the frontend explicitly uses a more general `llvm::Function` constructor. Function address spaces will become a part of the bitcode and textual IR forms, as we do not have access to a data layout whilst parsing LL.
It will be possible to write IR that explicitly has `addrspace(n)` on a function. In this case, the function will reside in the specified space, ignoring the default in the DL.
This is the first step towards placing functions into the correct
address space for Harvard architectures.
Full patchset
* Add program address space to data layout D37052
* Require address space to be specified when creating functions D37054
* [clang] Require address space to be specified when creating functions D37057
Reviewers: pcc, arsenm, kparzysz, hfinkel, theraven
Reviewed By: theraven
Subscribers: arichardson, simoncook, rengolin, wdng, uabelho, bjope, asb, llvm-commits
Differential Revision: https://reviews.llvm.org/D37052
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325479
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Dylan McKay [Mon, 19 Feb 2018 08:28:38 +0000 (08:28 +0000)]
[AVR] Fix a lowering bug in AVRISelLowering.cpp
The parseFunctionArgs() method was directly reading the
arguments from a Function object, but is should have used the
arguments supplied by the SelectionDAGBuilder.
This was causing
the lowering code to only lower one argument, not two in some cases.
Thanks to @brainlag on GitHub for coming up with the working fix!
Patch-by: @brainlag on GitHub
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325474
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Eric Christopher [Mon, 19 Feb 2018 05:26:49 +0000 (05:26 +0000)]
Add LanaiMCTargetDesc.h to LanaiInstrInfo.h to make it self contained
with instruction enum definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325473
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Craig Topper [Sun, 18 Feb 2018 20:41:25 +0000 (20:41 +0000)]
[X86] Correct a typo I made in combineToExtendCMOV recently.
We're accidentally checking that the same node is a constant twice instead of checking the other node.
This isn't a functional problem since we didn't do anything below that explicitly requires constants. It just means we may have introduced a sign_extend or zero_extend that won't fold out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325469
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Sanjay Patel [Sun, 18 Feb 2018 18:05:08 +0000 (18:05 +0000)]
[PatternMatch, InstSimplify] enhance m_AllOnes() to ignore undef elements in vectors
Loosening the matcher definition reveals a subtle bug in InstSimplify (we should not
assume that because an operand constant matches that it's safe to return it as a result).
So I'm making that change here too (that diff could be independent, but I'm not sure how
to reveal it before the matcher change).
This also seems like a good reason to *not* include matchers that capture the value.
We don't want to encourage the potential misstep of propagating undef values when it's
not allowed/intended.
I didn't include the capture variant option here or in the related rL325437 (m_One),
but it already exists for other constant matchers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325466
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Sanjay Patel [Sun, 18 Feb 2018 17:39:09 +0000 (17:39 +0000)]
[InstSimplify] add tests with vector undef elts; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325465
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Amara Emerson [Sun, 18 Feb 2018 17:28:34 +0000 (17:28 +0000)]
Fix unused assertion variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325464
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Amara Emerson [Sun, 18 Feb 2018 17:10:49 +0000 (17:10 +0000)]
[AArch64][GlobalISel] Fix an assert fail/miscompile when fp16 types are copied
to gpr register banks.
PR36345.
rdar://
36478867
Differential Revision: https://reviews.llvm.org/D43310
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325463
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Amara Emerson [Sun, 18 Feb 2018 17:03:02 +0000 (17:03 +0000)]
[AArch64][GlobalISel] Support G_INSERT/G_EXTRACT of types < s32 bits.
These are needed for operations on fp16 types in a later patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325462
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Sanjay Patel [Sun, 18 Feb 2018 16:19:22 +0000 (16:19 +0000)]
[PatternMatch] reformatting and comment clean-ups; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325461
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Benjamin Kramer [Sun, 18 Feb 2018 16:05:40 +0000 (16:05 +0000)]
[Support] Replace hand-written scope_exit with make_scope_exit.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325460
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Haicheng Wu [Sun, 18 Feb 2018 13:51:33 +0000 (13:51 +0000)]
[AArch64] Coalesce Copy Zero during instruction selection
Add special case for copy of zero to avoid a double copy.
Differential Revision: https://reviews.llvm.org/D36104
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325459
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Jonas Paulsson [Sun, 18 Feb 2018 10:09:54 +0000 (10:09 +0000)]
[BPF] Return true in enableMultipleCopyHints().
Enable multiple COPY hints to eliminate more COPYs during register allocation.
Note that this is something all targets should do, see
https://reviews.llvm.org/D38128.
Review: Yonghong Song
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325457
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Craig Topper [Sun, 18 Feb 2018 02:37:33 +0000 (02:37 +0000)]
[X86] Make masked pcmpeq commutable during isel so we can fold loads in other operand to the shorter encoding.
Previously we used the immediate encoding if the load was in operand 0 and the short encoding if the load was in operand 1.
This added an insane number of bytes to the size of the isel table. I'm wondering if we should always use the immediate form during isel and change to the short form during emission. This would remove the need to pattern match every combination for both the immediate form and the short form during isel. We could do the same with vpcmpgt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325456
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Craig Topper [Sun, 18 Feb 2018 02:37:32 +0000 (02:37 +0000)]
[X86] Add -show-mc-encoding to the avx512-vec-cmp.ll test and add test case to show that we're failing to use the shorter pcmpeq encoding when the memory arguemnt is the first argument.
This can't be spotted without showing the encodings since they have the same mnemonic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325455
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Simon Pilgrim [Sun, 18 Feb 2018 00:01:36 +0000 (00:01 +0000)]
Revert: [llvm] r325448 - [ThinLTO] Add GraphTraits for FunctionSummaries
Add GraphTraits definitions to the FunctionSummary and ModuleSummaryIndex classes. These GraphTraits will be used to construct find SCC's in ThinLTO analysis passes.
Second attempt, since last patch caused stage2 build to fail (now using function_ref rather than std::function).
Reverted due to buildbot failures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325454
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Simon Pilgrim [Sat, 17 Feb 2018 22:45:56 +0000 (22:45 +0000)]
Fix Wparentheses warning. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325451
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Simon Pilgrim [Sat, 17 Feb 2018 22:19:50 +0000 (22:19 +0000)]
[SelectionDAG] ComputeNumSignBits - add support for SMIN+SMAX clamp patterns
If we have a clamp pattern, SMIN(SMAX(X, LO),HI) or SMAX(SMIN(X, HI),LO) then we can deduce that the number of signbits will be at least the minimum of the LO and HI constants.
I haven't bothered with the UMIN/UMAX equivalent as (1) we don't have any current use cases and (2) I wonder if we'd be better off immediately falling back for ComputeKnownBits for UMIN/UMAX which already has optimization patterns useful for unsigned cases.
Differential Revision: https://reviews.llvm.org/D43338
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325450
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Simon Pilgrim [Sat, 17 Feb 2018 21:49:40 +0000 (21:49 +0000)]
[SelectionDAG] SimplifyDemandedVectorElts - add support for VECTOR_INSERT_ELT
Differential Revision: https://reviews.llvm.org/D43431
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325449
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Charles Saternos [Sat, 17 Feb 2018 21:39:24 +0000 (21:39 +0000)]
[ThinLTO] Add GraphTraits for FunctionSummaries
Add GraphTraits definitions to the FunctionSummary and ModuleSummaryIndex classes. These GraphTraits will be used to construct find SCC's in ThinLTO analysis passes.
Second attempt, since last patch caused stage2 build to fail (now using function_ref rather than std::function).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325448
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Simon Pilgrim [Sat, 17 Feb 2018 21:29:45 +0000 (21:29 +0000)]
[MIPS][MSA] Convert vector integer min/max opcodes to use generic implementation
Found while investigating D43338
Simon^3 - the LLVM project needs more Simons.
Differential Revision: https://reviews.llvm.org/D43433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325447
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Sjoerd Meijer [Sat, 17 Feb 2018 19:59:29 +0000 (19:59 +0000)]
[ARM] Add LLVM tests for the vcvtr builtins
Follow up of Clang commit r325351; this adds the LLVM tests, which
were also missing.
Differential Revision: https://reviews.llvm.org/D43395
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325443
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Alex Bradbury [Sat, 17 Feb 2018 18:17:47 +0000 (18:17 +0000)]
[RISCV] Revert r324172 now r323991 was reverted
This fixes the build, now that r325421 was commited to revert r323991.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325441
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Sander de Smalen [Sat, 17 Feb 2018 17:43:24 +0000 (17:43 +0000)]
Made test dbg_value_fastisel.ll specific to AArch64 fast-isel.
Some buildbots failed on this test (rL325438) because they don't
build all targets. I set the triple to aarch64 and moved the test
to test/CodeGen/AArch64/fast-isel-dbg-value.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325440
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Craig Topper [Sat, 17 Feb 2018 16:52:49 +0000 (16:52 +0000)]
[X86] Add 'sahf' to getHostCPUFeatures so -march=native will pick it up correctly.
Summary: We probably mostly get this right due to family/model/stepping mapping to CPU names. But we should detect it explicitly.
Reviewers: RKSimon, echristo, dim, spatel
Reviewed By: dim
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D43418
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325439
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Sander de Smalen [Sat, 17 Feb 2018 16:42:54 +0000 (16:42 +0000)]
[DebugInfo][FastISel] Fix dropping dbg.value()
Summary:
https://llvm.org/PR36263 shows that when compiling at -O0 a dbg.value()
instruction (that remains from an original dbg.declare()) is dropped
by FastISel. Since FastISel selects instructions by iterating a basic
block backwards, it drops the dbg.value if one of its operands is not
yet instantiated by a previously selected instruction.
Instead of calling 'lookUpRegForValue()' we can call 'getRegForValue()'
instead that will insert a placeholder for the operand to be filled in
when continuing the instruction selection.
Reviewers: aprantl, dblaikie, probinson
Reviewed By: aprantl
Subscribers: llvm-commits, dstenb, JDevlieghere
Differential Revision: https://reviews.llvm.org/D43386
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325438
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Sanjay Patel [Sat, 17 Feb 2018 16:00:42 +0000 (16:00 +0000)]
[PatternMatch] enhance m_One() to ignore undef elements in vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325437
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Sanjay Patel [Sat, 17 Feb 2018 15:55:40 +0000 (15:55 +0000)]
[InstSimplify, InstCombine] add tests with vector undef elts; NFC
These would fold if the m_One pattern matcher accounted for undef elts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325436
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Simon Pilgrim [Sat, 17 Feb 2018 14:58:16 +0000 (14:58 +0000)]
[X86][3DNow!] Add PFRCP reg-reg disassembler test case (PR21168)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325435
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Sanjay Patel [Sat, 17 Feb 2018 14:50:13 +0000 (14:50 +0000)]
[InstSimplify] move select undef cond fold with other constant cond folds; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325434
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Martin Storsjo [Sat, 17 Feb 2018 14:26:32 +0000 (14:26 +0000)]
[AArch64] Implement dynamic stack probing for windows
This makes sure that alloca() function calls properly probe the
stack as needed.
Differential Revision: https://reviews.llvm.org/D42356
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325433
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Simon Pilgrim [Sat, 17 Feb 2018 13:48:23 +0000 (13:48 +0000)]
Fix unused variable warning. NFCI.
We were casting to AArch64InstrInfo but only using it for static methods which some compilers complain about.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325432
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Jonas Devlieghere [Sat, 17 Feb 2018 13:06:37 +0000 (13:06 +0000)]
[dwarfdump] Fix spurious verification errors for DW_AT_location attributes
Verifying any DWARF file that is optimized and contains at least one tag
with a DW_AT_location with a location list offset as a
DW_AT_form_dataXXX results in dwarfdump spuriously claiming that the
location list is invalid.
Differential revision: https://reviews.llvm.org/D40199
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325430
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Simon Pilgrim [Sat, 17 Feb 2018 12:36:56 +0000 (12:36 +0000)]
[DAGCombiner] Remove simplifyShuffleMask - now handled more generally by SimplifyDemandedVectorElts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325429
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Simon Pilgrim [Sat, 17 Feb 2018 12:29:47 +0000 (12:29 +0000)]
Fix signed/unsigned comparison warning in AsmGenMatcher generated code. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325428
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Sander de Smalen [Sat, 17 Feb 2018 11:06:53 +0000 (11:06 +0000)]
[DebugInfo] Removed assert on missing CountVarDIE
Summary:
The assert for a DISubrange's CountVarDIE to be available fails
when the dbg.value() has been optimized away for any reason.
Having the assert for that is a little heavy, so instead removing
it now in favor of not generating the 'count' expression.
Addresses http://llvm.org/PR36263 .
Reviewers: aprantl, dblaikie, probinson
Reviewed By: aprantl
Subscribers: JDevlieghere, llvm-commits, dstenb
Differential Revision: https://reviews.llvm.org/D43387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325427
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Serge Pavlov [Sat, 17 Feb 2018 10:21:33 +0000 (10:21 +0000)]
Report fatal error in the case of out of memory
This is partial recommit of r325224, reverted in 325227. The relevant
part of original comment is below.
Analysis of fails in the case of out of memory errors can be tricky on
Windows. Such error emerges at the point where memory allocation function
fails, but manifests itself when null pointer is used. These two points
may be distant from each other. Besides, next runs may not exhibit
allocation error.
Usual programming practice does not require checking result of 'operator
new' because it throws 'std::bad_alloc' in the case of allocation error.
However, LLVM is usually built with exceptions turned off, so 'new' can
return null pointer. This change installs custom new handler, which causes
fatal error in the case of out of memory. The handler is installed
automatically prior to call to 'main' during construction of a static
object defined in 'lib/Support/ErrorHandling.cpp'. If the application does
not use this file, the handler may be installed manually by a call to
'llvm::install_out_of_memory_new_handler', declared in
'include/llvm/Support/ErrorHandling.h".
Differential Revision: https://reviews.llvm.org/D43010
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325426
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Jonas Paulsson [Sat, 17 Feb 2018 10:00:28 +0000 (10:00 +0000)]
[AMDGPU] Return true in enableMultipleCopyHints().
Enable multiple COPY hints to eliminate more COPYs during register allocation.
Note that this is something all targets should do, see
https://reviews.llvm.org/D38128.
Review: Stanislav Mekhanoshin, Tom Stellard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325425
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Quentin Colombet [Sat, 17 Feb 2018 03:05:33 +0000 (03:05 +0000)]
Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
This reverts commit r323991.
This commit breaks target that don't model all the register constraints
in TableGen. So far the workaround was to set the
hasExtraXXXRegAllocReq, but it proves that it doesn't cover all the
cases.
For instance, when mutating an instruction (like in the lowering of
COPYs) the isRenamable flag is not properly updated. The same problem
will happen when attaching machine operand from one instruction to
another.
Geoff Berry is working on a fix in https://reviews.llvm.org/D43042.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325421
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Chandler Carruth [Sat, 17 Feb 2018 02:26:25 +0000 (02:26 +0000)]
[DAG, X86] Revert r324797, r324491, and r324359.
Sadly, r324359 caused at least PR36312. There is a patch out for review
but it seems to be taking a bit and we've already had these crashers in
tree for too long. We're hitting this PR in real code now and are
blocked on shipping new compilers as a consequence so I'm reverting us
back to green.
Sorry for the churn due to the stacked changes that I had to revert. =/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325420
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Sanjay Patel [Sat, 17 Feb 2018 01:18:53 +0000 (01:18 +0000)]
[InstSimplify] add vector select tests with undef elts in condition; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325419
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Craig Topper [Sat, 17 Feb 2018 00:30:30 +0000 (00:30 +0000)]
[X86] Turn selects with constant condition into vector shuffles during DAG combine
Summary:
Currently we convert to shuffles during lowering. This moves it to DAG combine so hopefully we can get it done before type legalization has to extend the condition.
I believe in some cases we're creating SHRUNKBLENDs that end up with constant conditions because we see the extended on the condition and think its a dynamic selelect before DAG combine gets a chance to constant fold the extend. We could add combines to turn SHRUNKBLENDs with constant condition back to vselect. But it seemed like it might be better to just send them to shuffles as early as possible so they never get a chance to become SHRUNKBLENDs. This the reason some tests went from blends controlled by a constant pool load to just move.
Some of the constant pool entries changed because the sign_extend introduced by type legalization turned undef elements in select condition into 0s. While the select->shuffle used -1 in the shuffle mask. So now the shuffle lowering can do what it wants with them.
I'll remove the lowering code as a follow up. We might be able to simplify some of the pre-checks for SHRUNKBLEND as the FIXME there says.
Reviewers: spatel, RKSimon, efriedma, zvi, andreadb
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D43367
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325417
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Rui Ueyama [Fri, 16 Feb 2018 23:41:48 +0000 (23:41 +0000)]
Remove "--full-shutdown" and instead use an environment variable LLD_IN_TEST.
We are running lld tests with "--full-shutdown" option because we don't
want to call _exit() in lld if it is running tests. Regular shutdown
is needed for leak sanitizer.
This patch changes the way how we tell lld that it is running tests.
Now "--full-shutdown" is removed, and LLD_IN_TEST environment variable
is used instead.
This patch enables full shutdown on all ports, e.g. ELF, COFF and wasm.
Previously, we enabled it only for ELF.
Differential Revision: https://reviews.llvm.org/D43410
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325413
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Vitaly Buka [Fri, 16 Feb 2018 23:38:22 +0000 (23:38 +0000)]
[ThinLTO] Allow indexing to request backend to ignore the module
Summary:
Gold plugin does not add pass to ThinLTO modules without useful symbols.
In this case ThinLTO can't create corresponding index file and some features, like CFI,
cannot be processes by backed correctly without index.
Given that we don't need the backed output we can request it to avoid
processing the module. This is implemented by this patch using new
"SkipModuleByDistributedBackend" flag.
Reviewers: pcc, tejohnson
Subscribers: mehdi_amini, inglorion, eraman, cfe-commits
Differential Revision: https://reviews.llvm.org/D42995
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325411
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Konstantin Zhuravlyov [Fri, 16 Feb 2018 23:04:11 +0000 (23:04 +0000)]
AMDGPU: Remove unused private member of AMDGPUTargetELFStreamer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325408
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Eric Christopher [Fri, 16 Feb 2018 23:02:28 +0000 (23:02 +0000)]
Run these tests, the errors were old and not valid anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325407
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Eric Christopher [Fri, 16 Feb 2018 22:46:47 +0000 (22:46 +0000)]
Remove an unused function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325403
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Eric Christopher [Fri, 16 Feb 2018 22:46:45 +0000 (22:46 +0000)]
Silence an unsigned vs signed compare warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325402
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Aditya Nandakumar [Fri, 16 Feb 2018 22:37:15 +0000 (22:37 +0000)]
[GISel]: Make GlobalISelEmitter rule prioritization compatible with selectionDAG
This patch changes GlobalISelEmitter to rank patterns similar to how the
DAG does it (ie it computes a score for a pattern and adds the added
complexity to it).
This is so that the decision tree for GISelSelector remains compatible
with that of SelectionDAG.
https://reviews.llvm.org/D43270
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325401
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Konstantin Zhuravlyov [Fri, 16 Feb 2018 22:33:59 +0000 (22:33 +0000)]
AMDGPU: Bring elf flags in sync with the spec
- Add MACH flags
- Add XNACK flag
- Add reserved flags
- Minor cleanups in docs
Differential Revision: https://reviews.llvm.org/D43356
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325399
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Sanjay Patel [Fri, 16 Feb 2018 22:32:54 +0000 (22:32 +0000)]
[Constant] add floating-point helpers for normal/finite-nz; NFC
...and delete the equivalent local functiona from InstCombine.
These might be useful to other InstCombine files or other passes
and makes FP queries more similar to integer constant queries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325398
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Rui Ueyama [Fri, 16 Feb 2018 22:19:38 +0000 (22:19 +0000)]
Make sure we invoke ld64.lld and ld-wasm in the build directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325397
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Craig Topper [Fri, 16 Feb 2018 21:36:29 +0000 (21:36 +0000)]
[X86] In lowerVSELECTtoVectorShuffle, don't map undef select condition to undef in shuffle mask.
Undef in select condition means we should pick the element from one side or the other. An undef in a shuffle mask means pick any element from either source or worse.
I suspect by the time we get here most of the undefs in a constant vector have been removed by other things, but doing this for safety.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325394
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Konstantin Zhuravlyov [Fri, 16 Feb 2018 21:26:25 +0000 (21:26 +0000)]
AMDGPU: Bring processors and features in sync with the spec
- Remove gfx800
- Make iceland gfx802
- Add xnack to gfx902
Differential Revision: https://reviews.llvm.org/D43355
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325393
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Zachary Turner [Fri, 16 Feb 2018 21:10:34 +0000 (21:10 +0000)]
Try again to fix the build.
This doesn't repro with clang or MSVC so I'm just blindly
guessing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325389
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Zachary Turner [Fri, 16 Feb 2018 20:58:25 +0000 (20:58 +0000)]
Try to fix broken build with some compilers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325388
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Zachary Turner [Fri, 16 Feb 2018 20:46:04 +0000 (20:46 +0000)]
Fix emission of PDB string table.
This was originally reported as a bug with the symptom being "cvdump
crashes when printing an LLD-linked PDB that has an S_FILESTATIC record
in it". After some additional investigation, I determined that this was
a symptom of a larger problem, and in fact the real problem was in the
way we emitted the global PDB string table. As evidence of this, you can
take any lld-generated PDB, run cvdump -stringtable on it, and it would
return no results.
My hypothesis was that cvdump could not *find* the string table to begin
with. Normally it would do this by looking in the "named stream map",
finding the string /names, and using its value as the stream index. If
this lookup fails, then cvdump would fail to load the string table.
To test this hypothesis, I looked at the name stream map generated by a
link.exe PDB, and I emitted exactly those bytes into an LLD-generated
PDB. Suddenly, cvdump could read our string table!
This code has always been hacky and we knew there was something we
didn't understand. After all, there were some comments to the effect of
"we have to emit strings in a specific order, otherwise things don't
work". The key to fixing this was finally understanding this.
The way it works is that it makes use of a generic serializable hash map
that maps integers to other integers. In this case, the "key" is the
offset into a buffer, and the value is the stream number. If you index
into the buffer at the offset specified by a given key, you find the
name. The underlying cause of all these problems is that we were using
the identity function for the hash. i.e. if a string's offset in the
buffer was 12, the hash value was 12. Instead, we need to hash the
string *at that offset*. There is an additional catch, in that we have
to compute the hash as a uint32 and then truncate it to uint16.
Making this work is a little bit annoying, because we use the same hash
table in other places as well, and normally just using the identity
function for the hash function is actually what's desired. I'm not
totally happy with the template goo I came up with, but it works in any
case.
The reason we never found this bug through our own testing is because we
were building a /parallel/ hash table (in the form of an
llvm::StringMap<>) and doing all of our lookups and "real" hash table
work against that. I deleted all of that code and now everything goes
through the real hash table. Then, to test it, I added a unit test which
adds 7 strings and queries the associated values. I test every possible
insertion order permutation of these 7 strings, to verify that it really
does work as expected.
Differential Revision: https://reviews.llvm.org/D43326
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325386
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Simon Pilgrim [Fri, 16 Feb 2018 20:41:06 +0000 (20:41 +0000)]
Remove useless comment - seems to be a copy+paste typo. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325385
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Evandro Menezes [Fri, 16 Feb 2018 20:00:57 +0000 (20:00 +0000)]
[AArch64] Fix BITCAST lowering crash
The data type is assumed to be a vector, but sometimes it is not, leading
to an assertion.
Add simple test-case to verify this.
Differential revision: https://reviews.llvm.org/D42599
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325378
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Changpeng Fang [Fri, 16 Feb 2018 19:14:17 +0000 (19:14 +0000)]
AMDGPU/SI: Extend promoting alloca to vector to arrays of up to 16 elements
Summary:
This patch extends the promotion of alloca to vector to the arrays of up to 16 elements. Also we introduce
an option, -disable-promote-alloca-to-vector, to switch promotion to vector off, if needed.
Reviewers:
arsenm
Differential Revision:
https://reviews.llvm.org/D33559
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325372
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Craig Topper [Fri, 16 Feb 2018 18:51:09 +0000 (18:51 +0000)]
[X86] Only reorder srl/and on last DAG combiner run
This seems to interfere with a target independent brcond combine that looks for the (srl (and X, C1), C2) pattern to enable TEST instructions. Once we flip, that combine doesn't fire and we end up exposing it to the X86 specific BT combine which causes us to emit a BT instruction. BT has lower throughput than TEST.
We could try to make the brcond combine aware of the alternate pattern, but since the flip was just a code size reduction and not likely to enable other combines, it seemed easier to just delay it until after lowering.
Differential Revision: https://reviews.llvm.org/D43201
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325371
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Craig Topper [Fri, 16 Feb 2018 18:34:46 +0000 (18:34 +0000)]
[X86] Remove call to ShrinkDemandedCosntant from the SHRUNKBLEND creation code.
We only run this code if know the condition isn't a constant vector. ShrinkDemandedConstant isn't going to find any different.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325368
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Sam Clegg [Fri, 16 Feb 2018 18:06:05 +0000 (18:06 +0000)]
[WebAssembly] MC: Make explicit our current lack of support for relocations against unnamed temporary symbols.
Add an explicit check before looking up symbol in SymbolIndices.
This was previously silently succeeding and returning zero for such
unnamed temporaries.
Differential Revision: https://reviews.llvm.org/D43365
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325367
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Sanjay Patel [Fri, 16 Feb 2018 17:52:32 +0000 (17:52 +0000)]
[InstCombine] clean up fdiv-with-fdiv folds; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325366
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Sanjay Patel [Fri, 16 Feb 2018 17:46:50 +0000 (17:46 +0000)]
[InstCombine] add FMF to better show current fdiv fold behavior; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325365
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Simon Pilgrim [Fri, 16 Feb 2018 17:26:59 +0000 (17:26 +0000)]
Fix signed/unsigned comparison warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325363
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Eugene Leviant [Fri, 16 Feb 2018 17:25:03 +0000 (17:25 +0000)]
[ThinLTO] Fix data race in test #2
Switched to the right option (-thinlto-threads)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325362
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Eugene Leviant [Fri, 16 Feb 2018 16:56:33 +0000 (16:56 +0000)]
[ThinLTO] Fix data race in test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325361
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Simon Pilgrim [Fri, 16 Feb 2018 16:52:50 +0000 (16:52 +0000)]
Fix signed/unsigned comparison warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325359
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Sanjay Patel [Fri, 16 Feb 2018 16:42:04 +0000 (16:42 +0000)]
[InstCombine] remove redundant debug info setting; NFC
The IRBuilder sets debuginfo in Insert(), so this was duplicating what already happened.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325358
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Brian M. Rzycki [Fri, 16 Feb 2018 16:35:17 +0000 (16:35 +0000)]
[JumpThreading] PR36133 enable/disable DominatorTree for LVI analysis
Summary:
The LazyValueInfo pass caches a copy of the DominatorTree when available.
Whenever there are pending DominatorTree updates within JumpThreading's
DeferredDominance object we cannot use the cached DT for LVI analysis.
This commit adds the new methods enableDT() and disableDT() to LVI.
JumpThreading also sets the appropriate usage model before calling LVI
analysis methods.
Fixes https://bugs.llvm.org/show_bug.cgi?id=36133
Reviewers: sebpop, dberlin, kuhar
Reviewed by: sebpop, kuhar
Subscribers: uabelho, llvm-commits, aprantl, hiraditya, a.elovikov
Differential Revision: https://reviews.llvm.org/D42717
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325356
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Changpeng Fang [Fri, 16 Feb 2018 16:31:30 +0000 (16:31 +0000)]
AMDGPU/SI: Turn off GPR Indexing Mode immediately after the interested instruction.
Summary:
In the current implementation of GPR Indexing Mode when the index is of non-uniform, the s_set_gpr_idx_off instruction
is incorrectly inserted after the loop. This will lead the instructions with vgpr operands (v_readfirstlane for example) to read incorrect
vgpr.
In this patch, we fix the issue by inserting s_set_gpr_idx_on/off immediately around the interested instruction.
Reviewers:
rampitec
Differential Revision:
https://reviews.llvm.org/D43297
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325355
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Simon Pilgrim [Fri, 16 Feb 2018 16:22:14 +0000 (16:22 +0000)]
[SelectionDAG] Enable SimplifyDemandedVectorElts support for simplifying shuffle masks
Based off the DemandedElts mask the and UNDEF elements returned from the SimplifyDemandedVectorElts calls to the shuffle operands, we can attempt to simplify the shuffle mask.
I had to be very conservative here as accepting post-legalized shuffle masks could cause problems for targets that legalize UNDEF mask elements back to inrange values (PowerPC), similarly combining to identity shuffle masks could cause too much UNDEF information to disappear for later combines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325354
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Sanjay Patel [Fri, 16 Feb 2018 16:13:20 +0000 (16:13 +0000)]
[InstCombine] reduce code duplication; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325353
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Simon Pilgrim [Fri, 16 Feb 2018 14:57:25 +0000 (14:57 +0000)]
[X86][SSE] Allow float domain crossing if we are merging 2 or more shuffles and the root started as a float domain shuffle
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325349
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Nemanja Ivanovic [Fri, 16 Feb 2018 14:49:01 +0000 (14:49 +0000)]
[PowerPC] Fix transform in table gen file causing UB
Running a bootstrap build with UBSan produces a number of instances where
we have signed integer overflow due to this transform. Change the type to
long to prevent this UB on 64-bit build machines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325347
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Simon Dardis [Fri, 16 Feb 2018 13:34:23 +0000 (13:34 +0000)]
[mips] Remove codegen support from some 16 bit instructions
These instructions conflict with their full length variants
for the purposes of FastISel as they cannot be distingushed
based on the number and type of operands and predicates.
Reviewers: atanasyan
Differential Revision: https://reviews.llvm.org/D41285
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325341
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Simon Pilgrim [Fri, 16 Feb 2018 12:21:08 +0000 (12:21 +0000)]
[SelectionDAG] Add initial SimplifyDemandedVectorElts support for simplifying VSELECT operands
This just adds a basic pass through - we can add constant selection mask handling in a future patch to fully match InstCombine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325338
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Ivan A. Kosarev [Fri, 16 Feb 2018 10:10:29 +0000 (10:10 +0000)]
[Transforms] Propagate TBAA info in SROA
Now that we have the new TBAA metadata format that is capable of
representing accesses to aggregates, we can propagate TBAA access
tags from memory setting and transferring intrinsics to load and
store instructions and vice versa.
Since SROA produces lots of new loads and stores on optimized
builds, this change significantly decreases the share of
undecorated memory accesses on such builds.
Differential Revision: https://reviews.llvm.org/D41563
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325329
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Jonas Paulsson [Fri, 16 Feb 2018 09:51:01 +0000 (09:51 +0000)]
[ARM] Return true in enableMultipleCopyHints().
Enable multiple COPY hints to eliminate more COPYs during register allocation.
Note that this is something all targets should do, see
https://reviews.llvm.org/D38128.
Review: Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325327
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