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Vinson Lee [Tue, 17 Jan 2012 02:01:22 +0000 (18:01 -0800)]
glsl: Fix 'control reaches end of non-void function' warning.
Fix this GCC warning on non-debug builds.
glsl_types.cpp: In member function 'gl_texture_index
glsl_type::sampler_index() const':
glsl_types.cpp:157: warning: control reaches end of non-void function
NOTE: This is a candidate for the 8.0 branch.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Alex Deucher [Fri, 20 Jan 2012 23:04:44 +0000 (18:04 -0500)]
r600g: use S_028B20_BUFFER_0_EN macro for streamout buffer enable
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 20 Jan 2012 23:01:58 +0000 (18:01 -0500)]
r600g: update streamout support for virtual addresses
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Matt Turner [Fri, 20 Jan 2012 21:53:31 +0000 (16:53 -0500)]
Remove reference to now deleted dri/Makefile.targets
Matt Turner [Sun, 15 Jan 2012 16:50:20 +0000 (11:50 -0500)]
automake: src/mesa/drivers/dri
Matt Turner [Sun, 15 Jan 2012 16:39:48 +0000 (11:39 -0500)]
automake: src/mesa/drivers/dri/swrast
Matt Turner [Sun, 15 Jan 2012 15:20:30 +0000 (10:20 -0500)]
automake: src/mesa/drivers/dri/nouveau
Matt Turner [Sun, 15 Jan 2012 15:04:58 +0000 (10:04 -0500)]
automake: src/mesa/drivers/dri/r200
Matt Turner [Sun, 15 Jan 2012 03:21:30 +0000 (22:21 -0500)]
automake: src/mesa/drivers/dri/radeon
Matt Turner [Sun, 15 Jan 2012 02:57:32 +0000 (21:57 -0500)]
automake: src/mesa/drivers/dri/i915
Vadim Girlin [Wed, 18 Jan 2012 09:46:26 +0000 (13:46 +0400)]
r600g: fix streamout on evergreen
Enable it in the evergreen_context_draw if needed.
Same as already done in the r600_context_draw for r6xx/r7xx.
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Vadim Girlin [Wed, 18 Jan 2012 19:17:29 +0000 (23:17 +0400)]
r600g: fix combined MEM_STREAM instructions
BURST_COUNT is clipped with ARRAY_SIZE, so set it to the max value
to avoid clipping.
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Matt Turner [Fri, 13 Jan 2012 19:30:36 +0000 (14:30 -0500)]
Always build shared dricore
Tested-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Matt Turner <mattst88@gmail.com>
Matt Turner [Wed, 11 Jan 2012 23:32:14 +0000 (18:32 -0500)]
Always build shared glapi
libglapi.so, libGL.so, libGLESv2.so, libGLESv1_CM.so must all
come from the same version of Mesa or bad things may happen.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Matt Turner <mattst88@gmail.com>
Matt Turner [Thu, 12 Jan 2012 00:02:26 +0000 (19:02 -0500)]
Remove -ffast-math from default CFLAGS
Fixes glsl-const-folding-01. inversesqrt(1.0) != 1.0 was evaluating as
true.
Signed-off-by: Matt Turner <mattst88@gmail.com>
Chad Versace [Thu, 19 Jan 2012 21:08:48 +0000 (13:08 -0800)]
intel/gen6: Some framebuffers having separate depthstencil should be unsupported
When the framebuffer has separate depth and stencil buffers, and HiZ is
not enabled on the depth buffer, mark the framebuffer as unsupported. This
happens when trying to create a framebuffer with Z16/S8 because we haven't
enabled HiZ on Z16 yet.
Fixes gles2conform test stencil8.
Note: This is a candiate for the 8.0 branch.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44948
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed--by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Chad Versace [Tue, 17 Jan 2012 20:01:34 +0000 (12:01 -0800)]
mesa: Loosen glBlitFramebuffer restrictions on depthstencil buffers (v2)
This loosens the format validation in glBlitFramebuffer. When blitting
depth bits, don't require an exact match between the depth formats; only
require that the two formats have the same number of depth bits and the
same depth datatype (float vs uint). Ditto for stencil.
Between S8_Z24 buffers, the EXT_framebuffer_blit spec allows
glBlitFramebuffer to blit the depth and stencil bits separately. So I see
no reason to prevent blitting the depth bits between X8_Z24 and S8_Z24 or
the stencil bits between S8 and S8_Z24. However, we of course don't want
to allow blitting from Z32 to Z32_FLOAT.
Fixes Piglit fbo/fbo-blit-d24s8 on Intel drivers with separate stencil
enabled.
The problem was that, on Intel drivers with separate stencil, the default
framebuffer has separate depth and stencil buffers with formats X8_Z24 and
S8. The test attempts to blit the depth bits from a S8_Z24 buffer into the
default framebuffer.
v2: Check that depth datatypes match.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44665
Note: This is a candidate for the 8.0 branch.
Reported-by: Xunx Fang <xunx.fang@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Christoph Bumiller [Fri, 20 Jan 2012 12:43:32 +0000 (13:43 +0100)]
nvc0: fix some limit cap values
NOTE: This is a candidate for the 8.0 branch.
Christoph Bumiller [Fri, 20 Jan 2012 12:29:42 +0000 (13:29 +0100)]
nvc0: handle discontiguous outputs in stream_output_info
Christoph Bumiller [Fri, 20 Jan 2012 12:24:46 +0000 (13:24 +0100)]
mesa: allocate transform_feedback_info::Outputs array dynamically
The nvc0 gallium driver is advertising 128 MAX_INTERLEAVED_COMPS
which made it always assert in the linker when TFB was used since
the Outputs array was smaller than that maximum.
v2: added assertions
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Dave Airlie [Wed, 18 Jan 2012 15:16:55 +0000 (15:16 +0000)]
r600g: fixup AR handling (v5)
So it appears R600s (except rv670) do AR handling different using a different
opcode. This patch fixes up r600g to work properly on r600.
This fixes ~100 piglit tests here (in GLSL1.30 mode) on rv610.
v3: add index_mode as per the docs.
This still fails any dst relative tests for some reason I can't quite see yet,
but it passes a lot more tests than without.
v4: add a nop after dst.rel this could be improved using a second pass,
where we only insert nops if two instructions are sure to collide.
The docs say r600, rv610, rv630 needs this, and not rv670, rs780, rs880,
need AMD to confirm rv620, rv635.
v5: add is_nop_inst.
NOTE: This is a candidate for stable branches.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Brian Paul [Fri, 20 Jan 2012 17:55:15 +0000 (10:55 -0700)]
mesa: include arrayobj.h to silence implicit function declaration warning
Caused by commit
7a1e941ebee43cb97a2c77fd2269999b202308a2.
Mathias Fröhlich [Thu, 29 Dec 2011 12:10:01 +0000 (13:10 +0100)]
mesa: Fix and speedup gl_array_object::_MaxElement computation.
Use a bitmask approach to compute gl_array_object::_MaxElement.
To make this work correctly depending on the shader type actually used,
make use of the newly introduced typed bitmask getters.
With this change I gain about 5% draw time on some osgviewer examples.
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Reviewed-by: Brian Paul <brianp@vmware.com>
Mathias Froehlich [Thu, 29 Dec 2011 12:10:00 +0000 (13:10 +0100)]
mesa: Introduce enabled bitfield helper functions.
Depending on the installed shader type, different arrays are used
from gl_array_object. Provide helper functions that compute
the bitmask of these arrays that are finally enabled for a given
shader type. The will be used in a followup change.
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Reviewed-by: Brian Paul <brianp@vmware.com>
Mathias Fröhlich [Thu, 29 Dec 2011 12:10:00 +0000 (13:10 +0100)]
mesa: Use BITFIELD64_RANGE for VERT_BIT_*_ALL.
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Reviewed-by: Brian Paul <brianp@vmware.com>
Stéphane Marchesin [Fri, 20 Jan 2012 01:18:55 +0000 (17:18 -0800)]
i915g: Fix indentation.
Stéphane Marchesin [Fri, 20 Jan 2012 00:28:23 +0000 (16:28 -0800)]
i915g: Fix indentation and comment.
Paul Berry [Tue, 17 Jan 2012 18:28:10 +0000 (10:28 -0800)]
glsl: Fix isinf() for non-C99-compliant compilers.
Commit
ede60bc4670a8d9c14921c77abee1ac57fc0e6bf (glsl: Add isinf() and
isnan() builtins) uses "+INF" in the .ir file to represent infinity.
This worked on C99-compliant compilers, since the s-expression reader
uses strtod() to read numbers, and C99 requires strtod() to understand
"+INF". However, it didn't work on non-C99-compliant compilers such
as MSVC.
This patch modifies the s-expression reader to explicitly check for
"+INF" rather than relying on strtod() to support it.
This is a candidate for the 8.0 branch.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44767
Tested-by: Morgan Armand <morgan.devel@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Alex Deucher [Fri, 20 Jan 2012 02:07:58 +0000 (21:07 -0500)]
r600g: fix typo in evergreen register
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Brian Paul [Thu, 19 Jan 2012 18:37:00 +0000 (11:37 -0700)]
svga: move svga_texture() casts/calls in svga_surface_copy()
To fix failed assertions when calling glCopyBufferSubData().
svga_texture() asserts that the resource is a texture. Simply move the
calls to svga_texture() after the code that handles non-texture copies
so that we don't call it with non-texture resources.
Fixes glean bufferObject failure.
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Brian Paul [Thu, 19 Jan 2012 17:20:24 +0000 (10:20 -0700)]
st/mesa: copy num_immediates field when copying the immediates array
Two assignments to num_immediates were missing in
get_pixel_transfer_visitor() and get_bitmap_visitor().
The uninitialized value led to valgrind errors and crashes in some
cases.
Added new assertions to catch future problems in this area. Also
changed num_immediates to unsigned to avoid signed/unsigned
comparison warnings.
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Ian Romanick [Wed, 18 Jan 2012 00:24:05 +0000 (16:24 -0800)]
mesa: Set default access flags based on the run-time API
The default access flags for OpenGL ES (via GL_OES_map_buffer) and
desktop OpenGL are different. The code previously tried to handle
this, but the decision was made at compile time. Since the same
driver binary can be used for both OpenGL ES and desktop OpenGL, the
decision must be made at run-time.
This should fix bug #44433. It appears that the test case does
various map and unmap operations and inspects the state of the buffer
object around each. When it sees that GL_BUFFER_ACCESS does not match
its expectations, it fails.
NOTE: This is a candidate for release branches.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44433
Brian Paul [Thu, 19 Jan 2012 16:41:30 +0000 (09:41 -0700)]
st/mesa: add fallback pipe formats for (compressed) R, RG formats
If we don't find an exact PIPE_FORMAT_x for a GL_(COMPRESSED)_RED/RG format,
try uncompressed formats. We were already doing this for the RGB(A) formats.
Fixes piglit arb_texture_compression-internal-format-query test.
NOTE: This is a candidate for the stable branches.
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Stéphane Marchesin [Thu, 19 Jan 2012 03:24:18 +0000 (19:24 -0800)]
i915g: Don't avoid flushing when we have a pending fence.
Otherwise the fence will never arrive.
Also check for a NULL i915->batch.
NOTE: This is a candidate for the 8.0 branch.
Stéphane Marchesin [Thu, 19 Jan 2012 03:23:48 +0000 (19:23 -0800)]
i915g: Don't invert signalled/unsignalled fences
NOTE: This is a candidate for the 8.0 branch.
Kenneth Graunke [Wed, 18 Jan 2012 08:55:12 +0000 (00:55 -0800)]
i965: Fix disassembly of data port writes on Ivybridge.
msg_type moved by a bit, so the message type was being disassembled
incorrectly. In particular, render target writes were showing up as
"OWORD block write".
NOTE: This is a candidate for stable release branches.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Wed, 18 Jan 2012 08:50:31 +0000 (00:50 -0800)]
i965: Fix disassembly of sampler messages on Ivybridge.
Compared to sampler_gen5, simd_mode shifted by a bit and msg_type grew
by a bit. So we were printing slightly incorrect numbers.
NOTE: This is a candidate for stable release branches.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Wed, 18 Jan 2012 12:53:40 +0000 (04:53 -0800)]
i965/vs: Take attributes into account when deciding urb_entry_size.
Both the VF and VS share space in the URB. First, the VF stores
attributes (shader inputs) there. The VS then reads the attributes,
executes, and reuses the space to store varyings (shader outputs).
Thus, we need to calculate the amount of URB space necessary for inputs,
outputs, and pick whichever is greater.
The old VS backend correctly did this (brw_vs_emit.c:408), but the new
VS backend only considered outputs.
Fixes vertex scrambling in GLBenchmark PRO on Ivybridge.
NOTE: This is a candidate for the 8.0 branch.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41318
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Stéphane Marchesin [Wed, 18 Jan 2012 21:03:56 +0000 (13:03 -0800)]
st/dri: Remove useless flush front.
In the following scenario:
- CreateContext C1
- MakeCurrent C1
- DestroyContext C1 (does not actually destroy the first context, postponed
until the next MakeCurrent)
- CreateContext C2
- MakeCurrent C2
MakeCurrent will call flush on a half destroyed context, leading to crashes.
Since the other paths (destroy and makecurrent) already flush the context,
there is no need to flush here, so we remove this useless flush front call.
This fixes GPU crashes with Chrome and gallium drivers.
Ian Romanick [Tue, 17 Jan 2012 20:41:15 +0000 (12:41 -0800)]
intel: Set depth to 6 for cubemaps
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41216
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43212
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43250
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: Jin Yang <jin.a.yang@intel.com>
Kristian Høgsberg [Wed, 18 Jan 2012 20:32:35 +0000 (15:32 -0500)]
gbm: Validate usage flags in gbm_bo_create_from_egl_image()
The entry point is supposed to validate that the EGLImage is suitable for
the passed in usage flags, but that was never implemented.
Eric Anholt [Fri, 18 Nov 2011 01:11:00 +0000 (17:11 -0800)]
i965: Add support for Z16 depth formats.
v2: Don't flag the format as being HiZ ready (there's DRI2 handshake
pain to go through).
Fixes piglit gl-3.0-required-sized-texture-formats
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Eric Anholt [Tue, 17 Jan 2012 19:28:56 +0000 (11:28 -0800)]
i965/gen7: Set up surface horizontal alignment field.
This is required for Z16 support for texturing, which is the first
thing to have a horizontal alignment of 8. Renderbuffers don't need
it, since they're always set up as the only mip level, but do it for
completeness anyway.
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Eric Anholt [Tue, 17 Jan 2012 19:27:11 +0000 (11:27 -0800)]
i965/gen7: Remove stale comment.
This field is actually set up above.
NOTE: This is a candidate for the 8.0 branch, to avoid conflicts.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Eric Anholt [Thu, 12 Jan 2012 21:16:33 +0000 (13:16 -0800)]
glsl: Fix leak of linked uniform names at relink/free of the shader_program.
NOTE: This is a candidate for the 8.0 branch.
Eric Anholt [Thu, 12 Jan 2012 21:10:26 +0000 (13:10 -0800)]
glsl: Fix leak of LinkedTransformFeedback.Varyings.
I copy-and-pasted the thing I was allocating for as the context, so
the first time it would be NULL (root of a ralloc context) and they'd
chain off each other from then on.
NOTE: This is a candidate for the 8.0 branch.
Eric Anholt [Thu, 12 Jan 2012 21:08:22 +0000 (13:08 -0800)]
mesa: Fix leak of uniform storage records on shader program link/free.
NOTE: This is a candidate for the 8.0 branch.
Eric Anholt [Thu, 12 Jan 2012 21:01:21 +0000 (13:01 -0800)]
i965: Fix leak of the program cache BO on context destroy.
NOTE: This is a candidate for the 8.0 branch.
Eric Anholt [Thu, 12 Jan 2012 20:59:15 +0000 (12:59 -0800)]
i965/vs: Fix leak of an empty hash_table structure per compile.
This statement got duplicated above, probably in a rebase resolution,
so we never freed the extra one.
NOTE: This is a candidate for the 8.0 branch.
Eric Anholt [Thu, 12 Jan 2012 20:55:06 +0000 (12:55 -0800)]
i965: Fix refcount leak of the gl_program structure.
Fixes a leak of almost 200kb on a minimal shader_runner program
(algebraic-add-add-1).
NOTE: This is a candidate for the 8.0 branch.
Eric Anholt [Thu, 12 Jan 2012 20:51:34 +0000 (12:51 -0800)]
mesa: Make the register allocator allocation take a ralloc context.
This fixes a memory leak on i965 context destruction.
NOTE: This is a candidate for the 8.0 branch.
Brian Paul [Tue, 17 Jan 2012 23:28:10 +0000 (16:28 -0700)]
svga: change PIPE_CAPF_MAX_TEXTURE_LOD_BIAS from 16.0 to 15.0
The legal range for the device is apparently [-16.0, +15.0].
Limiting the range to [-15, +15] fixes piglit's lodbias test.
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Brian Paul [Wed, 18 Jan 2012 17:06:42 +0000 (10:06 -0700)]
svga: fix min/max lod clamping
The interaction between the mipmap lod min/max limits and the texture
base/max level limits is kind of tricky. Changing the base level
didn't work as expected before.
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Brian Paul [Wed, 18 Jan 2012 17:05:25 +0000 (10:05 -0700)]
svga: add 0.5 in float->int conversion of sample min/max lod
This makes lod clamping more consistent with other drivers.
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Brian Paul [Tue, 17 Jan 2012 15:15:25 +0000 (08:15 -0700)]
st/mesa: pass GL_MAP_INVALIDATE_RANGE_BIT to gallium drivers
when mapping renderbuffers or texture images.
NOTE: This is a candidate for the 8.0 branch.
Brian Paul [Tue, 17 Jan 2012 15:12:30 +0000 (08:12 -0700)]
mesa: use GL_MAP_INVALIDATE_RANGE_BIT in glTexImage paths
Update the dd.h docs to indicate that GL_MAP_INVALIDATE_RANGE_BIT
can be used with GL_MAP_WRITE_BIT when mapping renderbuffers and
texture images.
Pass the flag when mapping texture images for glTexImage, glTexSubImage,
etc. It's up to drivers whether to actually make use of the flag.
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Brian Paul [Mon, 16 Jan 2012 17:08:08 +0000 (10:08 -0700)]
mesa: try RGBA_FLOAT16 before RGBA_FLOAT32 when choosing A,L,LA,I formats
To try to use less tex memory and maybe get better performance.
Spotted by Roland Scheidegger.
NOTE: This is a candidate for the 8.0 and 7.11 branches.
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Brian Paul [Mon, 16 Jan 2012 16:05:05 +0000 (09:05 -0700)]
mesa: fix tex format selection for GL_R32F and other R/G float formats
The i965 driver advertises GL_ARB_texture_float and GL_ARB_texture_rg
support but the ctx->TextureFormatSupported[] table entries for
MESA_FORMAT_R_FLOAT32 and MESA_FORMAT_RGBA_FLOAT32 are false on gen 4
hardware. So the case for GL_R32F would fail and we'd print an
implementation error.
This patch adds more Mesa tex format options for GL_R32F and other R/G
formats so we fall back to 16-bit formats when 32-bit formats aren't
available.
Eric made the same fix in commit
6216a5b4 for the non R/G formats.
v2: try 16-bit formats before 32-bit formats and try RG formats before
RGBA where possible.
This should fix https://bugs.freedesktop.org/show_bug.cgi?id=44039
NOTE: This is a candidate for the 8.0 and 7.11 branches.
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Brian Paul [Mon, 16 Jan 2012 16:59:20 +0000 (09:59 -0700)]
docs: add more potential dependencies for vmware guest driver
Alexander von Gluck IV [Tue, 17 Jan 2012 15:46:01 +0000 (15:46 +0000)]
scons: Add more machine architectures to the machine map
* BePC, BeBox, BeMac for Haiku.
* Add sparc architecture as Mesa looks for it.
Signed-off-by: José Fonseca <jfonseca@vmware.com>
Dave Airlie [Wed, 18 Jan 2012 12:14:49 +0000 (22:14 +1000)]
r600g: fix ISLT on r600/700
This fixes ISLT like evergreen.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 18 Jan 2012 11:54:07 +0000 (21:54 +1000)]
r600g: make r600/700 use correct ineg.
Noticed by Vadim Girlin on irc.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 18 Jan 2012 09:33:21 +0000 (19:33 +1000)]
r600g: fix some of the interpolation tests.
This enables linear gradients if we need a linear,
it also sets the flat shade flag for color/constant interpolations.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Kenneth Graunke [Tue, 17 Jan 2012 16:08:25 +0000 (08:08 -0800)]
i965: Bump Ivybridge's fake MRF range to g112-127 instead of g111-126.
When I originally implemented the hack to use GRFs 111+ as fake MRFs, I
did so purely to avoid rewriting all the code that dealt with MRFs.
However, it turns out that a similar hack is actually required.
Newly discovered language in the BSpec indicates that SEND instructions
with EOT set "should" use g112-g127 as their source registers. Based on
assertions in the simulator, this is actually a requirement on certain
platforms.
Since we're faking MRFs already, we may as well use the officially
sanctioned range. My guess is that we avoided this issue because we
seldom use m0: URB writes in the new VS backend start at m1, and RT
writes in the new FS backend start at m2.
NOTE: This is a candidate for stable release branches.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Tue, 17 Jan 2012 12:49:04 +0000 (04:49 -0800)]
i965: Remove the INTEL_OLD_VS option.
Now that we no longer generate Mesa IR from GLSL IR, it's impossible to
use the old vertex shader backend for GLSL programs. There's simply no
Mesa IR to codegen from.
Any attempt to do so would result in immediate GPU hangs, presumably due
to the driver uploading an empty program with no EOT message.
NOTE: This is a candidate for the 8.0 branch.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Kenneth Graunke [Mon, 16 Jan 2012 18:34:56 +0000 (10:34 -0800)]
mesa: Support GL_VERTEX_ATTRIB_ARRAY_INTEGER in GL 3.0 contexts.
According to Table 6.8 (Page 348) in the OpenGL 3.0 specification,
glGetVertexAttribiv supports GL_VERTEX_ATTRIB_ARRAY_INTEGER.
NOTE: This is a candidate for the 8.0 branch.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Vadim Girlin [Wed, 18 Jan 2012 07:54:53 +0000 (11:54 +0400)]
r600g: fix UINT_TO_FLT on evergreen
It should be processed as trans-only.
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Chad Versace [Tue, 17 Jan 2012 23:41:46 +0000 (15:41 -0800)]
i965/gen5: Fix rendering of depth buffers without stencil [v2]
Fixes the following OGLConform tests on gen5:
depth-stencil(misc.state_on.depth_int)
fbo_db_ARBfp(basic.OnlyDepthBuffDrawBufferRender)
The problem was that, if the depth buffer's Mesa format was X8_Z24, then
we emitted the hardware format D24_UNORM_X8. But, on gen5, D24_UNORM_S8
must be emitted.
This bug was introduced by:
commit
d84a180417d1eabd680554970f1eaaa93abcd41e
Author: Eric Anholt <eric@anholt.net>
i965: Base HW depth format setup based on MESA_FORMAT, not bpp.
v2: Deref 'intel' directly. Move the branch for newer chipset to top.
Quote the PRM. As requested by Ken.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43408
Note: This is a candidate for the 8.0 branch.
Reported-by: Xunx Fang <xunx.fang@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Anuj Phogat [Tue, 17 Jan 2012 21:21:52 +0000 (13:21 -0800)]
intel: Return if pointer to intel_context is null
It is better to test if(intel == NULL) and simply return in that case.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Alex Deucher [Tue, 17 Jan 2012 23:44:47 +0000 (18:44 -0500)]
r600g: add workaround for original R600 PS setup
The original R600 requires the UNCACHED_FIRST_INST bit
to be set in the PS.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Note: this is candidate for the stable branches.
Paul Berry [Tue, 17 Jan 2012 20:35:38 +0000 (12:35 -0800)]
i965: Add .gitignore file to exclude automake build artifacts from git.
With the conversion to automake in commit
e326480e4ebe8687948041c2dc5f5b7595559a2e, several additional build
artifacts are created:
src/mesa/drivers/dri/i965/.deps/
src/mesa/drivers/dri/i965/.libs/
src/mesa/drivers/dri/i965/Makefile
src/mesa/drivers/dri/i965/Makefile.in
src/mesa/drivers/dri/i965/i965_dri.la
src/mesa/drivers/dri/i965/i965_symbols_test
This patch adds all of these files to .gitignore.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Anuj Phogat [Tue, 17 Jan 2012 00:15:30 +0000 (16:15 -0800)]
mesa: Add condition in glGetTexImage for zero size textures
TestMipMaps() function in src/OGLconform/textureNPOT.c calls glTexImage2D()
with width = 0. Texture with zero size skips miptree allocation due to a
condition in function _mesa_store_teximage3d(). While calling glGetTexImage()
it results in assertion failure in intel_map_texture_image() due to null mt
pointer.
This patch fixes the issue by detecting the zero size texture early in
glGetTexImage and glGetCompressedTexImage functions. In such a case function
simply returns doing nothing.
Verified that below mentioned bug is fixed by this patch.
https://bugs.freedesktop.org/show_bug.cgi?id=42334
NOTE: This is a candidate for stable branches
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Alex Deucher [Tue, 17 Jan 2012 23:09:25 +0000 (18:09 -0500)]
radeon: share common fog code between radeon and r200
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 17 Jan 2012 22:14:19 +0000 (17:14 -0500)]
radeon: fix fog coordinate emit
Noticed by dungeon on phoronix:
http://phoronix.com/forums/showthread.php?65408-Radeon-R100-R200-Mesa-Driver-Sees-Attention&p=247018#post247018
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Note: this is a candidate for the stable branches.
Alex Deucher [Tue, 17 Jan 2012 22:06:18 +0000 (17:06 -0500)]
r200: fix fog coordinate emit
Noticed by dungeon on phoronix:
http://phoronix.com/forums/showthread.php?65408-Radeon-R100-R200-Mesa-Driver-Sees-Attention&p=247018#post247018
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Note: this is a candidate for the stable branches.
Dave Airlie [Tue, 17 Jan 2012 20:49:34 +0000 (06:49 +1000)]
r600g: fix recip_uint on r600.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Vadim Girlin [Mon, 16 Jan 2012 22:46:08 +0000 (02:46 +0400)]
r600g: fix USLT for r600-eg
Alexander von Gluck IV [Mon, 16 Jan 2012 17:44:43 +0000 (17:44 +0000)]
scons: Don't set visibility to hidden on Haiku
The Haiku swrast driver is out of tree.
Alexander von Gluck IV [Mon, 16 Jan 2012 12:42:05 +0000 (12:42 +0000)]
scons: Add Haiku build support
Enables building stock Mesa under the Haiku operating system.
Vadim Girlin [Tue, 17 Jan 2012 12:09:00 +0000 (16:09 +0400)]
r600g: rework IDIV/UDIV and implement MOD/UMOD (v2)
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Eric Anholt [Thu, 12 Jan 2012 22:56:56 +0000 (14:56 -0800)]
mesa: Enable silent automake rules when available.
Finally, a quiet build for the i965 driver, at least! (Note, you can
still get verbose builds at build-time by saying "make V=1")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Thu, 12 Jan 2012 22:28:37 +0000 (14:28 -0800)]
i965: Convert the build to using automake.
This does introduce a warning by the automake build system, that the
missing-symbols test build is non-portable. That's true -- Mac OS X
can't take something built as a loadable module and just link it as a
library. Of course, we aren't building this on OS X at all, so it
would be nice to be able to suppress it, but I haven't found a way.
Still, the build is going to be much quieter than we have ever had
before, so I think this is a fair tradeoff until we find a way to shut
that warning up.
v2: Put a link in /lib to avoid transition pains for people.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1)
Reviewed-by: Matt Turner <mattst88@gmail.com> (v1)
Eric Anholt [Thu, 12 Jan 2012 22:53:10 +0000 (14:53 -0800)]
intel: Drop the version override code now that we don't have any left.
Fixes a compiler warning.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Eric Anholt [Thu, 12 Jan 2012 22:32:50 +0000 (14:32 -0800)]
intel: Fix warnings of undefined ffs().
For some reason these started showing up with the automake conversion.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Scott Moreau [Tue, 17 Jan 2012 15:36:12 +0000 (10:36 -0500)]
Complete ARGB8888 naming convention format renames missed
Chad Versace [Tue, 27 Dec 2011 18:52:44 +0000 (10:52 -0800)]
i965: Fix gen6,gen7 when used with a non-HiZ capable DDX
Nothing works if HiZ is enabled and the DDX is incapable of HiZ (that is,
the DDX version is < 2.16).
The problem is that the refactoring that eliminated
intel_renderbuffer::stencil_rb broke the recovery path in
intel_verify_dri2_has_hiz(). Specifically, it broke line
intel_context.c:1445, which allocates the region for
DRI_BUFFER_DEPTH_STENCIL. That allocation was creating a separate stencil
miptree, despite the buffer being a packed depthstencil buffer. Havoc
ensued.
This patch introduces a bool flag that prevents allocation of that stencil
miptree.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44103
Tested-by: Ian Romanick <idr@freedesktop.org>
Note: This is a candidate for the 8.0 branch.
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Vinson Lee [Mon, 16 Jan 2012 21:02:03 +0000 (13:02 -0800)]
softpipe: Silence unused variable warning on non-LLVM builds.
Fix this GCC warning with non-LLVM builds.
sp_screen.c: In function ‘softpipe_get_shader_param’:
sp_screen.c:141:28: warning: unused variable ‘sp_screen’ [-Wunused-variable]
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Anuj Phogat [Wed, 11 Jan 2012 23:26:10 +0000 (15:26 -0800)]
intel: Fix segfault in glXSwapBuffers with no bound context
Calling glXSwapBuffers with no bound context causes segmentation
fault in function intelDRI2Flush. All the gl calls should be
ignored after setting the current context to null. So the contents
of framebuffer stay unchanged. But the driver should not seg fault.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44614
Reported-by: Yi Sun <yi.sun@intel.com>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Yi Sun <yi.sun@intel.com>
Vinson Lee [Mon, 16 Jan 2012 07:33:16 +0000 (23:33 -0800)]
llvmpipe: Remove unused variable 'packed' from lp_test_round.
Fix this GCC warning.
lp_test_round.c: In function ‘test_round’:
lp_test_round.c:126:13: warning: variable ‘packed’ set but not used
[-Wunused-but-set-variable]
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Vinson Lee [Mon, 16 Jan 2012 07:08:26 +0000 (23:08 -0800)]
util: Silence GCC unused-but-set-variable warning.
Fix this GCC 4.6 warning with 64-bit builds.
u_debug_stack.c: In function ‘debug_backtrace_capture’:
u_debug_stack.c:45:17: warning: variable ‘frame_pointer’ set but not
used [-Wunused-but-set-variable]
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
José Fonseca [Mon, 16 Jan 2012 12:21:03 +0000 (12:21 +0000)]
vl: Make array initialization portable.
Should fix MSVC build.
Stéphane Marchesin [Mon, 16 Jan 2012 07:32:59 +0000 (23:32 -0800)]
i915g: Fix the blending for the A8 destination buffer case.
The i915 GPU can't do A8 dst, so we abuse GREEN8 buffers for that
purpose. However, things get hairy as we start to do blending,
because then GL_DST_*_ALPHA should be replaced with GL_DST_*_COLOR.
This is what we do here.
Fixes piglt fbo-alpha.
Matt Turner [Sun, 15 Jan 2012 03:08:35 +0000 (22:08 -0500)]
r200: remove left-over EGL_SOURCES variable
Rest was removed in
2a928899e.
Signed-off-by: Matt Turner <mattst88@gmail.com>
Dave Airlie [Sun, 15 Jan 2012 16:53:10 +0000 (16:53 +0000)]
r600g: fix mullo_uint trans slot only on r600/r700
This fixes 8 piglit tests that currently assert.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Vadim Girlin [Sun, 15 Jan 2012 14:29:50 +0000 (09:29 -0500)]
r600g: implement clip distances
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Vadim Girlin [Fri, 6 Jan 2012 04:13:18 +0000 (08:13 +0400)]
r600g: implement two-sided lighting (v3)
v2: select the colors in the pixel shader
v3: fix rs state creation for pre-evergreen
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Vadim Girlin [Sun, 15 Jan 2012 14:56:36 +0000 (18:56 +0400)]
r600g: add support for ISHR/USHR/SHL on r600-evergreen
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Sun, 15 Jan 2012 14:56:35 +0000 (18:56 +0400)]
r600g: implement IDIV/UDIV on r600-evergreen
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Sun, 15 Jan 2012 14:56:34 +0000 (18:56 +0400)]
r600g: implement ISSG on r600-evergreen
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Sun, 15 Jan 2012 14:56:33 +0000 (18:56 +0400)]
r600g: implement IABS on r600-evergreen
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>