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Bas Nieuwenhuizen [Tue, 24 Dec 2019 13:44:03 +0000 (14:44 +0100)]
radv: Expose all sample counts for integer formats as well.
Things work the same between float and integer.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2261
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
a435f002c40f5adc99d37e65cf6b8bd478dc8e71)
Jason Ekstrand [Tue, 24 Dec 2019 04:19:29 +0000 (22:19 -0600)]
anv: Properly advertise sampledImageIntegerSampleCounts
We support the same set of samples for integer color formats as for
non-integer. We've been advertising it wrong since before the initial
Vulkan 1.0 release. :-(
Fixes:
d68974530371 "vk/0.210.0: Rework device features and limits"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit
ac70442ce1f061a42649f7c88c6a8d278fb73fb5)
Pierre-Eric Pelloux-Prayer [Tue, 17 Dec 2019 09:41:39 +0000 (10:41 +0100)]
radeon/vcn2: enable rate control for hevc encoding
Based on
b0626c1f306 ("radeon/vcn: enable rate control for hevc encoding").
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2225
Fixes:
587b9c5dae6 ("radeon/vcn: implement vcn 2.0 encode")
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3134>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3134>
(cherry picked from commit
9c2a3b4e7566108ad336c253e3cd0fcb2629ae6d)
Christian Gmeiner [Fri, 29 Nov 2019 08:44:43 +0000 (09:44 +0100)]
etnaviv: update resource status after flushing
Currently piglit spec@arb_occlusion_query@occlusion_query_conform
spins for ever as the resource status is never reset. See
etna_hw_get_query_result(..) for more details.
Fixes:
1456aa61cc5 ("etnaviv: Rework resource status tracking")
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marek Vasut <marex@denx.de>
(cherry picked from commit
6e75f2172b5cc9298dee6f17e55bed60ce0c15fb)
Samuel Pitoiset [Wed, 18 Dec 2019 12:29:39 +0000 (13:29 +0100)]
radv/gfx10: fix the out-of-bounds check for vertex descriptors
When stride is 0, it should check against the offset not the index.
This fixes black character models with Beat Saber and missing snow
with Dragon Quest.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2233
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1975
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3147>
(cherry picked from commit
f3cccd05d9f6e9d05c18d1a3a5f9eb863e4f264b)
Lionel Landwerlin [Wed, 18 Dec 2019 15:48:26 +0000 (17:48 +0200)]
loader: fix close on uninitialized file descriptor value
Using a drm syscall layer faking a kernel driver :
==581460== Conditional jump or move depends on uninitialised value(s)
==581460== by 0x48A4C2B: close (drm-hooks.cpp:185)
==581460== by 0x5A815F1: dri3_alloc_render_buffer (loader_dri3_helper.c:1469)
==581460== by 0x5A82050: dri3_get_buffer (loader_dri3_helper.c:1827)
==581460== by 0x5A82662: loader_dri3_get_buffers (loader_dri3_helper.c:2028)
==581460== by 0x6C78109: intel_update_image_buffers (brw_context.c:1870)
==581460== by 0x6C77805: intel_update_renderbuffers (brw_context.c:1499)
==581460== by 0x6C7789D: intel_prepare_render (brw_context.c:1520)
==581460== by 0x6C773D4: intelMakeCurrent (brw_context.c:1341)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
069fdd5f9fac ("egl/x11: Support DRI3 v1.1")
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3152>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3152>
(cherry picked from commit
fc2552b6445a1295c18acf8798411da85bbc5387)
Bas Nieuwenhuizen [Wed, 18 Dec 2019 09:21:40 +0000 (10:21 +0100)]
radv: Limit workgroup size to 1024.
Fixes a hang with geekbench.
The existence of RX 580 and NAVI10 results shows that the generations
before and after this do not have the issue. (They show up on the
website). So this is likely a GFX9 only issue.
This is not something weird like LDS size since none of the shaders
seem to use LDS.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3145>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3145>
(cherry picked from commit
a9a3108be774aea620fa4fc726c33100d9a49add)
Caio Marcelo de Oliveira Filho [Mon, 16 Dec 2019 22:43:53 +0000 (14:43 -0800)]
intel/vec4: Fix lowering of multiplication by 16-bit constant
Existing code was ignoring whether the type of the immediate source
was signed or not. If the source was signed, it would ignore small
negative values but it also would wrongly accept values between
INT16_MAX and UINT16_MAX, causing the atual value to later be
reinterpreted as a negative number (under 16-bits).
Fixes tests/shaders/glsl-mul-const.shader_test in Piglit for older
platforms that don't support MUL with 32x32 types and use vec4.
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
766fdeccf943d090694d4fbeebbe470904481d32)
Caio Marcelo de Oliveira Filho [Mon, 16 Dec 2019 21:37:41 +0000 (13:37 -0800)]
intel/fs: Fix lowering of dword multiplication by 16-bit constant
Existing code was ignoring whether the type of the immediate source
was signed or not. If the source was signed, it would ignore small
negative values but it also would wrongly accept values between
INT16_MAX and UINT16_MAX, causing the atual value to later be
reinterpreted as a negative number (under 16-bits).
Fixes tests/shaders/glsl-mul-const.shader_test in Piglit for platforms
that don't support MUL with 32x32 types, including ICL and TGL.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2186
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
2137be22fa2c75eda462456f2b7778684d0631fc)
Caio Marcelo de Oliveira Filho [Thu, 12 Dec 2019 21:25:33 +0000 (13:25 -0800)]
intel/fs: Lower 64-bit MOVs after lower_load_payload()
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
c06ba8358958279cfad6cdf2a52d9824a818f0b8)
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3130>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3130>
Dylan Baker [Wed, 18 Dec 2019 18:56:33 +0000 (10:56 -0800)]
dcos: add releanse notes for 19.3.1
Dylan Baker [Wed, 18 Dec 2019 18:34:24 +0000 (10:34 -0800)]
VERSION: bump version for 19.3.1
Dylan Baker [Wed, 18 Dec 2019 18:33:20 +0000 (10:33 -0800)]
docs: remove new_features.txt from stable branch
Now that the .0 is done, we shouldn't have any more new features added
to the branch
Lionel Landwerlin [Mon, 16 Dec 2019 15:58:41 +0000 (17:58 +0200)]
mesa: avoid triggering assert in implementation
When tearing down a GL context with an active performance query, the
implementation can be confused by a query marked active when it's
being deleted.
This shouldn't happen in the implementation because the context will
already be idle.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2235
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3115>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3115>
(cherry picked from commit
2c8742ed858c6446c93bddec117abf467a393c35)
Tapani Pälli [Fri, 15 Nov 2019 07:18:10 +0000 (09:18 +0200)]
i965: expose MESA_FORMAT_B8G8R8X8_SRGB visual
Patch adds BGRX sRGB visuals, required format translation information
to the __DRI_IMAGE_FOURCC_SXRGB8888 format and makes all BGRX visuals
sRGB capable just like is done with BGRA.
squashed patches from Yevhenii Kolesnikov:
dri: Add __DRI_IMAGE_FOURCC_SXRGB8888 conversion
i965: force visuals without alpha bits to use sRGB
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1501
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3077>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3077>
(cherry picked from commit
75caae2268f5c70b1f3005df8618876341ac14fd)
Tapani Pälli [Fri, 15 Nov 2019 07:12:15 +0000 (09:12 +0200)]
dri: add __DRI_IMAGE_FORMAT_SXRGB8
Add format definition and required plumbing to create images.
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3077>
(cherry picked from commit
8b6b5ce6691c80f3254964b746499d5ca75b59b1)
Gert Wollny [Mon, 16 Dec 2019 20:48:09 +0000 (21:48 +0100)]
virgl: Increase the shader transfer buffer by doubling the size
With only linearly increasing the size of the shader transfer buffer
the transfer of very large shaders may fail, so with each attempt double
the size of the buffer.
CTS:
dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.48
for VTK-GL-CTS
b5dcfb9c5 and newer
virglrenderer bug:
https://gitlab.freedesktop.org/virgl/virglrenderer/issues/150
Fixes:
a8987b88ff1db4ac00720a9b56c4bc3aeb666537
virgl: add driver for virtio-gpu 3D (v2)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3121>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3121>
(cherry picked from commit
cffa7bb99084eb9e5988c2be4427f6b188cc7bbe)
Iván Briano [Fri, 13 Dec 2019 00:07:19 +0000 (16:07 -0800)]
anv: Export filter_minmax support only when it's really supported
Fixes:
bea4d4c78c3 ("anv: add VK_EXT_sampler_filter_minmax support")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3071>
(cherry picked from commit
0fd93b95898f8048ced8aa9f8db5472d4309b9e0)
Bas Nieuwenhuizen [Thu, 12 Dec 2019 11:10:58 +0000 (12:10 +0100)]
amd/common: Always use addrlib for HTILE tc-compat.
Even without depth+stencil addrlib can (correctly!) decide to
disable tc compatible HTILE.
One example is 8x sampling with 32-bit depth on Stoney. The row size
on Stoney is 1024, while the tile size is 2048, which results in
tile splits which are not supported with tc-compat.
On Stoney, this fixes
dEQP-VK.glsl.builtin_var.fragdepth.*_list_d32_sfloat_multisample_8
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3054>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3054>
(cherry picked from commit
b53856aca31b1a1fde8cd87a6978934cd6ae94b1)
Bas Nieuwenhuizen [Wed, 11 Dec 2019 15:04:58 +0000 (16:04 +0100)]
amd/common: Fix tcCompatible degradation on Stoney.
addrlib sometimes returns smaller sizes for tcCompat as it does
not seem to take into account the depth+stencil matching config
gymnastics with tcCompat.
This fixes
dEQP-VK.pipeline.render_to_image.core.2d_array.huge.height.r8g8b8a8_unorm_d32_sfloat_s8_uint
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3054>
(cherry picked from commit
e197fb1c2fccf4719630d91a7c7f76308d88132b)
Luis Mendes [Sat, 9 Nov 2019 23:21:05 +0000 (23:21 +0000)]
radv: fix radv secure compile feature breaks compilation on armhf EABI and aarch64
__NR_select is not defined the same way across architectures, sometimes is
not even defined, like in armhf EABI and aarch64.
Signed-off-by: Luis Mendes <luis.p.mendes@gmail.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2042
(cherry picked from commit
0cb5c96a83e3da2986fc8219b10671a7caea9ee5)
Lionel Landwerlin [Wed, 11 Dec 2019 23:58:01 +0000 (01:58 +0200)]
anv: fix fence underlying primitive checks
We appear to have got lucky that the only type of temporary fence
payload we could have was a syncobj and that would only happen when
the type of the permanent payload was also a syncobj.
This code was broken if that assumption changed and it did in commit
f9a3d9738b12.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
(cherry picked from commit
52bc235f2adcae8a3f40c74b15c9aad9e2b5c5b9)
Kenneth Graunke [Wed, 11 Dec 2019 17:49:38 +0000 (09:49 -0800)]
iris: Default to X-tiling for scanout buffers without modifiers
Neither Mutter nor KWin's wayland compositors appear to use modifiers.
In the non-modifier case, iris was still trying to use Y-tiling for
scan-out surfaces, leading to this error:
(gnome-shell:7247): mutter-WARNING **: 09:23:47.787: meta_drm_buffer_gbm_new failed: drmModeAddFB failed: Invalid argument
We now fall back to the historical X-tiling for scanout buffers, which
ought to work everyone, at lower performance. To regain that, we need
to ensure modifiers are actually supported in environments people use.
Fixes:
fbf31247710 ("iris: Rework tiling/modifiers handling")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
dcb4230e5e51c1f2ff84c436134c231996af85e9)
Dylan Baker [Thu, 12 Dec 2019 18:22:03 +0000 (10:22 -0800)]
cherry-ignore: update for the 19.3.1 cycle
Dylan Baker [Thu, 12 Dec 2019 19:55:00 +0000 (11:55 -0800)]
docs/19.3.0: Add SHA256 sums
Dylan Baker [Thu, 12 Dec 2019 19:21:58 +0000 (11:21 -0800)]
VERSION: bump for 19.3.0 final
Dylan Baker [Thu, 12 Dec 2019 19:21:43 +0000 (11:21 -0800)]
docs: add release notes for 19.3.0
Dylan Baker [Thu, 12 Dec 2019 17:24:42 +0000 (09:24 -0800)]
Revert "egl: move #include of local headers out of Khronos headers"
This reverts commit
87efb9f3a4f366372bc873dee741a2c2f272e5c9.
This is breaking the QT build, so it needs to go until these symbols can
make their way to upstream khronos
Dylan Baker [Thu, 12 Dec 2019 17:23:54 +0000 (09:23 -0800)]
Revert "egl: avoid local modifications for eglext.h Khronos standard header file"
This reverts commit
2a497735ec75cfc5edaff378613e3b145b3bb22d.
This patch is built on the previous patch, which needs to be reverted.
Lionel Landwerlin [Tue, 10 Dec 2019 11:49:49 +0000 (03:49 -0800)]
anv: fix incorrect VMA alignment for CCS main surfaces
Maybe finer way of dealing with this requirement would be to increase
the number of pdevice->memory.types[] to add a category for special
alignment cases.
Meanwhile this fixes the problem of CCS surface alignment and it's
probably not going to cause issues given the size of our address
space.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
6af8a4acc4a4 ("anv: Add aux-map translation for gen12+")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
5fdea9f40182002899fc941bfb8c3f36ed5366a1)
Samuel Pitoiset [Tue, 10 Dec 2019 16:46:26 +0000 (17:46 +0100)]
ac/nir: fix out-of-bound access when loading constants from global
Global load/store instructions can't know if the offset is
out-of-bound because they don't use descriptors (no range).
Fix this by clamping the offset for arrays that are indexed
with a non-constant offset that's greater or equal to the array
size.
This fixes VM faults and GPU hangs with Dead Rising 4.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2148
Fixes:
71a67942003 ("ac/nir: Enable nir_opt_large_constants")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
a0f1a5fa051786c16de6f0062771051f8565daec)
Pierre-Eric Pelloux-Prayer [Fri, 6 Dec 2019 20:35:38 +0000 (21:35 +0100)]
radeonsi: use gfx9.surf_offset to compute texture offset
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2177
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
ff0f10866699a22216fd1a4af6cdb89c2fea10e1)
Mauro Rossi [Sat, 16 Nov 2019 17:39:31 +0000 (18:39 +0100)]
android: radeonsi: fix build after vl refactoring (v2)
vl functions moved from radeonsi to gallium/auxiliary/vl have left
android build of radeonsi in broken state.
libmesa_galliumvl static is need to build readeonsi,
gallium_dri building rules are reworked to avoid multiple symbols
and libmesa_galliumvl static dependency is needed in radeonsi.
Here is the changelog:
- android: gallium/auxiliary: add libmesa_galliumvl static
- android: gallium_dri: move libmesa_gallium to static to prevent multiple symbols
- android: radeonsi: fix build after vl refactoring
Fixes the following building error:
external/mesa/src/gallium/drivers/radeonsi/si_uvd.c:47:
error: undefined reference to 'vl_video_buffer_create_as_resource'
clang.real: error: linker command failed with exit code 1 (use -v to see invocation)
Fixes:
86e60bc ("radeonsi: remove si_vid_join_surfaces and use combined planar allocations")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
96aef08dc6f4ea4a79cdf995d867d08e8f838b2a)
Conflicts Resolved by Dylan Baker
Conflicts:
src/gallium/targets/dri/Android.mk
Panfrost is not enabled for android in 19.3, and the series is a bit
bigger than I'd like to pull into the stable branch for a .0 release
Jason Ekstrand [Mon, 2 Dec 2019 19:51:59 +0000 (13:51 -0600)]
anv: Don't leak when set_tiling fails
Fixes:
a44744e01d73 "anv: Require a dedicated allocation for..."
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit
0a36fafa95175efbad1a61b36706e535929afd2b)
Conflicts resolved by Dylan Baker
Conflicts:
src/intel/vulkan/anv_device.c
Nanley Chery [Fri, 15 Nov 2019 17:17:23 +0000 (09:17 -0800)]
iris: Fix import of multi-planar surfaces with modifiers
Multi-planar surfaces are allowed to have modifiers. Don't require
DRM_FORMAT_MOD_INVALID in order to create a surface for each plane
defined by the format.
Fixes:
246eebba4a8 ("iris: Export and import surfaces with modifiers that have aux data")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
21376cffb37018160ad3eef38b5a640ba1675a4f)
James Xiong [Thu, 4 Apr 2019 15:27:33 +0000 (08:27 -0700)]
iris: try to set the specified tiling when importing a dmabuf
When importing a dmabuf with a specified tiling, the dmabuf user
should always try to set the tiling mode because: 1) the exporter
can set tiling AFTER exporting/importing. 2) a dmabuf could be
exported from a kernel driver other than i915, in this case the
dmabuf user and exporter need to set tiling separately.
This patch fixes a problem when running vkmark under weston with
iris on ICL, it crashed to console with the following assert. i965
doesn't have this problem as it always tries to set the specified
tiling mode.
weston: ../src/gallium/drivers/iris/iris_resource.c:990: iris_resource_from_handle: Assertion `res->bo->tiling_mode == isl_tiling_to_i915_tiling(res->surf.tiling)' failed.
Signed-off-by: James Xiong <james.xiong@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
(cherry picked from commit
b6d45e7f748e9ff7e198391f5ce5d1253101fedb)
Nanley Chery [Fri, 15 Nov 2019 22:10:38 +0000 (14:10 -0800)]
gallium: Store the image format in winsys_handle
This format will be used to properly handle planar images with modifiers
in iris.
Fixes:
246eebba4a8 ("iris: Export and import surfaces with modifiers that have aux data")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
51ee8fff9b5e803592a2fd34730fdcfdfba469cb)
Bas Nieuwenhuizen [Tue, 10 Dec 2019 15:53:56 +0000 (16:53 +0100)]
radv: Fix RGBX Android<->Vulkan format correspondence.
This is correct per the Vulkan spec format equivalence table.
Fixes:
f36b52740a0 "radv/android: Add android hardware buffer queries."
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit
2e44bfc14f5c2e44ed820257615c2008955bc5bf)
Dylan Baker [Tue, 10 Dec 2019 19:15:37 +0000 (11:15 -0800)]
meson/broadcom: libbroadcom_cle also needs zlib
Fixes:
1ae8018a6af81eec4832a57d9d0346aa3dd98d28
("meson: Add support for the vc4 driver.")
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit
d0eebda99088d15199aa0ae2c2d62ab6939568ce)
Dylan Baker [Tue, 10 Dec 2019 18:19:04 +0000 (10:19 -0800)]
meson/broadcom: libbroadcom_cle needs expat headers
Fixes:
1ae8018a6af81eec4832a57d9d0346aa3dd98d28
("meson: Add support for the vc4 driver.")
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit
85a9698ac3a032aa8e2e71ff804b489749a754ec)
Lionel Landwerlin [Tue, 10 Dec 2019 11:49:16 +0000 (03:49 -0800)]
anv: fix missing gen12 handling
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
181be14d4303 ("anv: Build for gen12")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
dcfe1903c3f501429851d0278ba78742e907355b)
Pierre-Eric Pelloux-Prayer [Mon, 9 Dec 2019 08:48:37 +0000 (09:48 +0100)]
radeonsi: fix multi plane buffers creation
When using 3 planes, the sequence produces this chain:
plane0 -> plane2
This commit fixes this to produce:
plane0 -> plane1 -> plane2
Fixes:
86e60bc2659 ("radeonsi: remove si_vid_join_surfaces and use combined planar allocations")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2193
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
e3e91cebcd9307654eb3535e2f6521103ec8b997)
Alyssa Rosenzweig [Fri, 6 Dec 2019 21:45:57 +0000 (16:45 -0500)]
gallium/util: Support POLYGON in u_stream_outputs_for_vertices
u_decomposed_prims_for_vertices cannot support POLYGON, but POLYGON is
trivial to support as a special case directly (since we have the number
of vertices directly).
Fixes aborts in Panfrost in apps using GL_POLYGON.
Fixes:
e881aa8c12c ("gallium/util: Add u_stream_outputs_for_vertices helper")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Revewied-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit
a37822f5f740c55cd6f848adfd6c3d567ae4fd79)
Jason Ekstrand [Sat, 7 Dec 2019 00:26:59 +0000 (18:26 -0600)]
anv: Re-emit all compute state on pipeline switch
It's a very odd case to hit in the real world. However, there are some
CTS tests which switch back and forth between dispatch and clear without
changing the pipeline.
Fixes:
bc612536eb2f "anv: Emit a dummy MEDIA_VFE_STATE before switching..."
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
(cherry picked from commit
0f60aa4037dfb6aa86d5b9524fe649f13b2b8825)
Fritz Koenig [Thu, 5 Dec 2019 00:16:43 +0000 (16:16 -0800)]
freedreno: reorder format check
With the addition of the planar formats helper, the
planar formats no longer have a valid block.bits field.
Calling util_format_get_blocksize therefore asserts.
Reorder the check to see if the format is supported
before doing the query to get the blocksize.
Fixes:
20f132e5eff2d ("gallium/util: add planar format layouts and helpers")
Signed-off-by: Fritz Koenig <frkoenig@google.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
(cherry picked from commit
c496d442844183968f7c4903c8ed549aa990d15f)
Nanley Chery [Thu, 14 Nov 2019 21:59:58 +0000 (13:59 -0800)]
gallium/dri2: Fix creation of multi-planar modifier images
The commit noted below assumed and enforced that DRM_MOD_INVALID was the
only valid modifier for multi-planar imported images. Due to that, it
required that modifier on multi-planar images to:
1. Allow multiple planes.
2. Perform YUV format lowering and extent adjustments.
3. Use buffer_index to correctly map the given planes.
Fix these issues by removing or updating the code built on that
assumption.
Fixes:
2066966c106 ("gallium/dri2: Support creating multi-planar modifier images")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
d5c857837aae205c0e1fddee30300b4419e2bb3f)
Timothy Arceri [Thu, 5 Dec 2019 04:01:14 +0000 (15:01 +1100)]
glsl/nir: iterate the system values list when adding varyings
Iterate the system values list when adding varyings to the program
resource list in the NIR linker. This is needed to avoid CTS
regressions when using the NIR to build the GLSL resource list in
an upcoming series. Presumably it also fixes a bug with the current
ARB_gl_spirv support.
Fixes:
ffdb44d3a0a2 ("nir/linker: Add inputs/outputs to the program resource list")
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
(cherry picked from commit
1abca2b3c84a42ab64c466bc209db42c41bba5e3)
Ian Romanick [Tue, 19 Nov 2019 03:16:23 +0000 (19:16 -0800)]
intel/compiler: Fix 'comparison is always true' warning
Without looking at the assembly or something, I'm not sure what the
compiler does here. The brw_reg_type enum is marked packed, so I'm
guess that it gets represented as a uint8_t. That's the only reason I
could think that comparing with -1 would be always true.
This patch adds the same cast that exists in brw_hw_type_to_reg_type.
It might be better to add a #define outside the enum for
BRW_REGISTER_TYPE_INVALID as (enum brw_reg_type)-1.
src/intel/compiler/brw_eu_compact.c: In function ‘has_immediate’:
src/intel/compiler/brw_eu_compact.c:1515:20: warning: comparison is always true due to limited range of data type [-Wtype-limits]
1515 | return *type != -1;
| ^~
src/intel/compiler/brw_eu_compact.c:1518:20: warning: comparison is always true due to limited range of data type [-Wtype-limits]
1518 | return *type != -1;
| ^~
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
CID:
1455194
Fixes:
12d3b11908e ("intel/compiler: Add instruction compaction support on Gen12")
Cc: @mattst88
(cherry picked from commit
668635abd26dda458f9293f99dd39f56431a4d61)
Rob Clark [Wed, 4 Dec 2019 00:28:26 +0000 (16:28 -0800)]
nir/lower_clip: Fix incorrect driver loc for clipdist outputs
Somehow adjusting maxloc based on existing outputs got lost, resulting
in the clipdist varying clobbering the position varying. Causing a
shader that had no position output in freedreno/ir3, which triggers GPU
hangs in neverball.
Fixes:
d0f746b6458 ("nir: Save nir_variable pointers in nir_lower_clip_vs rather than locs.")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
(cherry picked from commit
372ed42d222a274abe712b62f4b037cbeb6fddb5)
Dylan Baker [Wed, 4 Dec 2019 21:01:02 +0000 (13:01 -0800)]
cherry-ignore: update for 19.3-rc7
Lionel Landwerlin [Tue, 3 Dec 2019 14:35:45 +0000 (16:35 +0200)]
intel/perf: fix improper pointer access
This expression was unused by the macro, probably why it didn't
register in the compilation.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
ddacd3d43b203e7c66ec366820e2a230b7e3aa67)
Lionel Landwerlin [Tue, 3 Dec 2019 14:33:25 +0000 (16:33 +0200)]
intel/perf: simplify the processing of OA reports
This is a more accurate description of what happens in processing the
OA reports.
Previously we only had a somewhat difficult to parse state machine
tracking the context ID.
What we really only need to do to decide if the delta between 2
reports (r0 & r1) should be accumulated in the query result is :
* whether the r0 is tagged with the context ID relevant to us
* if r0 is not tagged with our context ID and r1 is: does r0 have a
invalid context id? If not then we're in a case where i915 has
resubmitted the same context for execution through the execlist
submission port
v2: Update comment (Ken)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
8c0b05826304370ef9e5f1e607d0f0305a0eb759)
Lionel Landwerlin [Tue, 3 Dec 2019 14:19:24 +0000 (16:19 +0200)]
intel/perf: take into account that reports read can be fairly old
If we read the OA reports late enough after the query happens, we can
get a timestamp in the report that is significantly in the past
compared to the start timestamp of the query. The current code must
deal with the wraparound of the timestamp value (every ~6 minute). So
consider that if the difference is greater than half that wraparound
period, we're probably dealing with an old report and make the caller
aware it should read more reports when they're available.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
b364e920bf8c6805bcc3ff1cedf6b77dbb61b1e0)
Lionel Landwerlin [Tue, 3 Dec 2019 14:12:03 +0000 (16:12 +0200)]
intel/perf: set read buffer len to 0 to identify empty buffer
We always add an empty buffer in the list when creating the query.
Let's set the len appropriately so that we can recognize it when we
read OA reports up to the end of a query.
We were using an 0 timestamp value associated with the empty buffer
and incorrectly assuming this was a valid value. In turn that led to
not reading enough reports and resulted in deltas added to our counter
values which should have been discarded because those would be flagged
for a different context.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
9d0a5c817ce21adabeda5153035b30609e2862b2)
Lionel Landwerlin [Tue, 3 Dec 2019 14:08:12 +0000 (16:08 +0200)]
intel/perf: fix invalid hw_id in query results
Accumulation happens between 2 reports, it can be between a start/end
report from another context. So only consider updating the hw_id of
the results when it's not already valid and that we have a valid value
to put in there.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
41b54b5faf ("i965: move OA accumulation code to intel/perf")
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
acea59dbf8056b46444c820115d86c42d0411686)
Dylan Baker [Wed, 4 Dec 2019 21:14:01 +0000 (13:14 -0800)]
VERSION: bump version for 19.3-rc6
Daniel Schürmann [Fri, 29 Nov 2019 15:47:13 +0000 (16:47 +0100)]
aco: fix a couple of value numbering issues
Fixes:
3a20ef4a3299fddc886f9d5908d8b3952dd63a54 'aco: refactor value numbering'
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Jason Ekstrand [Tue, 26 Nov 2019 21:08:43 +0000 (15:08 -0600)]
anv: Set up SBE_SWIZ properly for gl_Viewport
gl_Viewport is also in the VUE header so we need to whack the read
offset to 0 and emit a default (no overrides) SBE_SWIZ entry in that
case as well.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit
b1f37688ba717db81a7e9c97e2a875d528d85112)
Jordan Justen [Sat, 25 May 2019 08:33:17 +0000 (01:33 -0700)]
iris: Allow max dynamic pool size of 2GB for gen12
Reworks:
* Adjust comment to list the state packets that curro found to be
affected.
Fixes:
8125d7960b6 ("intel/dev: Add preliminary device info for Tigerlake")
Cc: 19.3 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
(cherry picked from commit
e277009d8dbdc9aec4be26aed5357ec41f359937)
Rhys Perry [Thu, 14 Nov 2019 15:31:52 +0000 (15:31 +0000)]
nir/lower_io_to_vector: don't create arrays when not needed
Some backends require that there are no array varyings.
If there were no arrays in the input shader, the pass shouldn't have to
create new ones.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2103
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2167
Fixes:
bcd14756eec ('nir/lower_io_to_vector: add flat mode')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
(cherry picked from commit
5404b7aaa36fad18df19e12abcc8af69014e74c2)
Rhys Perry [Thu, 28 Nov 2019 11:30:55 +0000 (11:30 +0000)]
radv: set writes_memory for global memory stores/atomics
Fixes:
13ab63bb62b ('radv: Implement VK_EXT_buffer_device_address.')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
35fab1ba3395604f748cd13ba82991372ca0cae7)
Daniel Schürmann [Fri, 29 Nov 2019 15:43:24 +0000 (16:43 +0100)]
aco: don't split live-ranges of linear VGPRs
Fixes:
93c8ebfa780ebd1495095e794731881aef29e7d3 'aco: Initial commit of independent AMD compiler'
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
(cherry picked from commit
8861a82be7df2a5816254b45d390ddafad7d8711)
Rhys Perry [Wed, 27 Nov 2019 17:20:15 +0000 (17:20 +0000)]
aco: add v_nop inbetween exec write and VMEM/DS/FLAT
LLVM and the proprietary compiler seem to do this
Fixes:
b01847bd9 ("aco/gfx10: Fix mitigation of VMEMtoScalarWriteHazard.")
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
(cherry picked from commit
a9fc81b098ca36d063dbdb6f69ffde1ab215d34b)
Rhys Perry [Wed, 27 Nov 2019 17:24:23 +0000 (17:24 +0000)]
aco: fix i2i64
Fixes:
93c8ebfa ('aco: Initial commit of independent AMD compiler')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
(cherry picked from commit
11f43caaeca166c96ae49dbd506b6f58dd4a13fb)
Rhys Perry [Thu, 28 Nov 2019 15:29:40 +0000 (15:29 +0000)]
aco: propagate p_wqm on an image_sample's coordinate p_create_vector
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2156
Fixes:
93c8ebfa780 ('aco: Initial commit of independent AMD compiler')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
(cherry picked from commit
ff70ccad16a2efb3be1fbc4ca03453d38721a267)
Christian Gmeiner [Fri, 29 Nov 2019 14:15:27 +0000 (15:15 +0100)]
etnaviv: remove dead code
ptiled is always NULL so the if statement is useless.
CoverityID:
1415572
Fixes:
b9627765303 ("etnaviv: rework compatible render base")
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
(cherry picked from commit
1be220833c18139ff9f3c7c9237deeb726ba5c55)
Jonathan Gray [Thu, 28 Nov 2019 05:57:23 +0000 (16:57 +1100)]
i965: update Makefile.sources for perf changes
brw_performance_query_metrics.h was removed in
134e750e16bfc53480e0bba6f0ae3e1d2a7fb87c and
brw_performance_query.h was removed in
8ae6667992ccca41d08884d863b8aeb22a4c4e65
remove reference to these files from Makefile.sources
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Fixes:
134e750e16bfc53480e0 ("i965: extract performance query metrics")
Fixes:
8ae6667992ccca41d088 ("intel/perf: move query_object into perf")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
(cherry picked from commit
34dda0ca659a8dd4a25123d966ed04340b9a0e45)
Boris Brezillon [Thu, 14 Nov 2019 08:35:27 +0000 (09:35 +0100)]
panfrost: Make sure we reset the damage region of RTs at flush time
We must reset the damage info of our render targets here even though a
damage reset normally happens when the DRI layer swaps buffers. That's
because there can be implicit flushes the GL app is not aware of, and
those might impact the damage region: if part of the damaged portion
is drawn during those implicit flushes, you have to reload those areas
before next draws are pushed, and since the driver can't easily know
what's been modified by the draws it flushed, the easiest solution is
to reload everything.
Reported-by: Carsten Haitzler <raster@rasterman.com>
Fixes:
65ae86b85422 ("panfrost: Add support for KHR_partial_update()")
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
(cherry picked from commit
c6e2096c47f05aab6807325799bf0b6a4092084d)
Boris Brezillon [Fri, 8 Nov 2019 23:02:54 +0000 (00:02 +0100)]
gallium: Fix the ->set_damage_region() implementation
BACK_LEFT attachment can be outdated when the user calls
KHR_partial_update() (->lastStamp != ->texture_stamp), leading to a
damage region update on the wrong pipe_resource object.
Let's delay the ->set_damage_region() call until the attachments are
updated when we're in that case.
Reported-by: Carsten Haitzler <raster@rasterman.com>
Fixes:
492ffbed63a2 ("st/dri2: Implement DRI2bufferDamageExtension")
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
b196e1a8cfbd2c6b53f688542bcda5bb8f7f8888)
Bas Nieuwenhuizen [Fri, 22 Nov 2019 00:51:36 +0000 (01:51 +0100)]
radv: Fix timeline semaphore refcounting.
Was totally broken ...
Removed two if(point) {} because point is always non-NULL and we
were counting on that already for counting, since we NULL our
references to semaphores without active point earlier.
Fixes:
4aa75bb3bdd "radv: Add wait-before-submit support for timelines."
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2137
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
48fc65413c8607390b2ed8cdaccac490d8c8fdae)
Jonathan Gray [Thu, 28 Nov 2019 05:56:30 +0000 (16:56 +1100)]
winsys/amdgpu: avoid double simple_mtx_unlock()
pthread_mutex_unlock() when unlocked is documented by posix as
being undefined behaviour. On OpenBSD pthread_mutex_unlock() will call
abort(3) if this happens.
This occurs in amdgpu_winsys_create() after
cb446dc0fa5c68f681108f4613560543aa4cf553
winsys/amdgpu: Add amdgpu_screen_winsys
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Cc: 19.2 19.3 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
3fe3bde4f2c8813e13fa2992212ca46a894e68b6)
Bas Nieuwenhuizen [Wed, 27 Nov 2019 23:36:24 +0000 (00:36 +0100)]
radv: Unify max_descriptor_set_size.
They were out of sync. Besides syncing, lets ensure they never diverge
again.
Fixes:
8d2654a4197 "radv: Support VK_EXT_inline_uniform_block."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
4cde0e04e38ad2b9212d451cb5a84ed4ceaffd03)
Kenneth Graunke [Fri, 22 Nov 2019 09:37:02 +0000 (01:37 -0800)]
drirc: Set vs_position_always_invariant for Shadow of Mordor on Intel
When drawing the main character in Shadow of Mordor, the game appears
to draw Talion with one vertex shader, and the Wraith with another.
If the compiler optimizes those in different ways which lead to slight
imprecisions, then the resulting positions may not line up, leading to
Z-fighting occurring as the game decides which of the two are in front.
brw_nir_opt_peephole_ffma looks at usages of multiply adds across the
entire shader, and may make different decisions between the two, leading
to such imprecisions and Z-fighting. This started happening recently
after a NIR change to eliminate unnecessary MOVs (
7025dbe7), but that
change simply exposed the existing problem.
Improves performance on Skylake GT4e by 1.22945% +/- 0.398672% (n=3),
likely due to the fixed rendering.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1985
Fixes:
7025dbe794b ("nir: Skip emitting no-op movs from the builder.")
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit
51cc380894b6c541ac3383336389242cf3f9fd67)
Kenneth Graunke [Fri, 22 Nov 2019 00:11:15 +0000 (16:11 -0800)]
driconf, glsl: Add a vs_position_always_invariant option
Many applications use multi-pass rendering and require their vertex
shader position to be computed the same way each time. Optimizations
may consider, say, fusing a multiply-add based on global usage of an
expression in a shader. But a second shader with the same expression
may have different code, causing that optimization to make the other
choice the second time around.
The correct solution is for applications to mark their VS outputs
'invariant', indicating they need multiple shaders to compute that
output in the same manner. However, most applications fail to do so.
So, we add a new driconf option - vs_position_always_invariant - which
forces the gl_Position output in vertex shaders to be marked invariant.
Fixes:
7025dbe794b ("nir: Skip emitting no-op movs from the builder.")
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit
9b577f2a887968483b88b629673d3f9904a179ff)
Samuel Pitoiset [Fri, 23 Aug 2019 15:53:05 +0000 (17:53 +0200)]
radv/gfx10: fix implementation of exclusive scans
This implementation is loosely based on ROCm.
https://github.com/RadeonOpenCompute/ROCm-Device-Libs/blob/master/ockl/src/wfredscan.cl
This fixes dEQP-VK.subgroups.arithmetic.*.subgroupexclusive* on GFX10.
Fixes:
227c29a80de ("amd/common/gfx10: implement scan & reduce operations")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
c9aa843961d2c3cb34e7cb2dc843b93d723e0692)
Conflicts resolved by Dylan Baker
Samuel Pitoiset [Tue, 26 Nov 2019 17:29:00 +0000 (18:29 +0100)]
radv: fix enabling sample shading with SampleID/SamplePosition
When a fragment shader includes an input variable decorated with
SampleId or SamplePosition, sample shading should be enabled
because minSampleShadingFactor is expected to be 1.0.
Cc: 19.2, 19.3 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
86a5fbfd4afb4fb53ab8ea0a13dda33b32f8b79b)
Dylan Baker [Wed, 27 Nov 2019 17:07:13 +0000 (09:07 -0800)]
VERSION: Bump version for -rc5
Yevhenii Kolesnikov [Thu, 7 Nov 2019 15:22:26 +0000 (17:22 +0200)]
meson: Fix linkage of libgallium_nine with libgalliumvl
Do not link libgallium_nine with libgalliumvl_stub if it's already
linked with libgalliumvl. Linking with stub leads to "duplicate
symbol" errors.
Fixes:
6b4c7047d57178d3362a710ad503057c6a582ca3
("meson: build gallium nine state_tracker")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2040
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit
9af22ccddcd1a983df5e0c6732a4e8f5ebf4d9cf)
Bas Nieuwenhuizen [Mon, 25 Nov 2019 22:58:04 +0000 (23:58 +0100)]
radv: Allocate cmdbuffer space for buffer marker write.
Fixes:
946193ae008 "radv: add support for VK_AMD_buffer_marker"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
25bc9102d89f4390e0edc0a5f09fcde9de80f776)
Gert Wollny [Mon, 18 Nov 2019 10:57:00 +0000 (11:57 +0100)]
r600: Disable eight bit three channel formats
Commit
0899bf55 made some deqp-gles3 tests related to RGB8 PBOs fail
on R600 because it exposed PIPE_FORMAT_R8G8B8_UNORM and R600 doesn't
propely handle this. Disabling this format also for buffers fixes the
issue.
In addition, disabling also the related RGB8 integer formats for buffers
fixes some deqp-gles3 tests:
dEQP-GLES3.functional.texture.specification.teximage2d_pbo.rgb8ui_cube
dEQP-GLES3.functional.texture.specification.texsubimage2d_pbo.rgb8i_2d
dEQP-GLES3.functional.texture.specification.texsubimage2d_pbo.rgb8i_cube
dEQP-GLES3.functional.texture.specification.texsubimage2d_pbo.rgb8ui_2d
dEQP-GLES3.functional.texture.specification.texsubimage2d_pbo.rgb8ui_cube
dEQP-GLES3.functional.texture.specification.teximage3d_pbo.rgb8i_2d_array
dEQP-GLES3.functional.texture.specification.teximage3d_pbo.rgb8i_3d
dEQP-GLES3.functional.texture.specification.teximage3d_pbo.rgb8ui_2d_array
dEQP-GLES3.functional.texture.specification.teximage3d_pbo.rgb8ui_3d
dEQP-GLES3.functional.texture.specification.texsubimage3d_pbo.rgb8i_2d_array
dEQP-GLES3.functional.texture.specification.texsubimage3d_pbo.rgb8i_3d
dEQP-GLES3.functional.texture.specification.texsubimage3d_pbo.rgb8ui_2d_array
dEQP-GLES3.functional.texture.specification.texsubimage3d_pbo.rgb8ui_3d
Fixes:
0899bf55
st/mesa: Map MESA_FORMAT_RGB_UNORM8 <-> PIPE_FORMAT_R8G8B8_UNORM
Closes #2118
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit
e41958e344cb4b15d01008140a1ee08817104334)
Timothy Arceri [Sun, 24 Nov 2019 23:08:26 +0000 (10:08 +1100)]
radv: create a fresh fork for each pipeline compile
In order to prevent a potential malicious pipeline tainting our
secure compile process and interfering with successive pipelines
we want to create a fresh fork for each pipeline compile.
Benchmarking has shown that simply forking on each pipeline
creation doubles the total time it takes to compile a fossilize db
collection. So instead here we fork the process at device creation
so that we have a slim copy of the device and then fork this
otherwise idle and untainted process each time we compile a
pipeline. Forking this slim copy of the device results in only a
20% increase in compile time vs a 100% increase.
Fixes:
cff53da3 ("radv: enable secure compile support")
(cherry picked from commit
f54c4e85ce089964e4d2ed39157f07226a41d11f)
Timothy Arceri [Wed, 13 Nov 2019 03:51:48 +0000 (14:51 +1100)]
radv: add a secure_compile_open_fifo_fds() helper
This will be used to create a communication pipe between the user
facing device and a freshly forked (per pipeline compile) slim copy
of that device.
We can't use pipe() here because the fork will not be a direct fork
of the user facing process. Instead we use a previously forked
copy of the process that was forked at device creation in order to
reduce the resources required for the fork and avoid performance
issues.
Fixes:
cff53da3748d ("radv: enable secure compile support")
(cherry picked from commit
1663bb1f772dacadaec2d80f8286cfb76c4bb200)
Timothy Arceri [Sun, 24 Nov 2019 23:00:20 +0000 (10:00 +1100)]
radv: add some infrastructure for fresh forks for each secure compile
In the following commits we want to be able to fork an existing lightweight
fork created at device creation time. In order for the user facing process
to communicate with this new fresh fork we create some members here to hold
FIFO file descriptors and a unique id.
Here we also add a new fork enum that we use to tell the lightweight
process to create a fresh fork.
For more information on why we create a fresh fork see the following
commits.
(cherry picked from commit
ef54f15da9ac11fafcbd6c91a7fcdac734436db8)
Zebediah Figura [Tue, 5 Nov 2019 16:21:21 +0000 (10:21 -0600)]
Revert "draw: revert using correct order for prim decomposition."
This reverts commit
f97b731c82afb06cfd6ffebc90a3e098a9a1b308.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/250
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
(cherry picked from commit
a3c8bc10aa9294bd78c0e2cf5818fb4b8a42cd7a)
Ian Romanick [Mon, 18 Nov 2019 19:52:47 +0000 (11:52 -0800)]
intel/fs: Disable conditional discard optimization on Gen4 and Gen5
The CMP instruction on Gen4 and Gen5 generates one bit (the LSB) of
valid data and 31 bits of junk. Results of comparisons that are used as
Boolean values need to have a fixup applied to generate the proper 0/~0
values.
Calling fs_visitor::nir_emit_alu with need_dest=false prevents the fixup
code from being generated. This results in a sequence like:
cmp.l.f0.0(16) g8<1>F g14<8,8,1>F 0x0F /* 0F */
...
cmp.l.f0.0(16) g4<1>F g6<8,8,1>F 0x0F /* 0F */
(+f0.1) or.z.f0.1(16) null<1>UD g4<8,8,1>UD g8<8,8,1>UD
instead of
cmp.l.f0.0(16) g8<1>F g14<8,8,1>F 0x0F /* 0F */
...
cmp.l.f0.0(16) g4<1>F g6<8,8,1>F 0x0F /* 0F */
or(16) g4<1>UD g4<8,8,1>UD g8<8,8,1>UD
(+f0.1) and.z.f0.1(16) null<1>UD g4<8,8,1>UD 1UD
I examined a couple of the shaders hurt by this change, and ALL of them
would have been affected by this bug. :(
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1836
Fixes:
0ba9497e66a ("intel/fs: Improve discard_if code generation")
Iron Lake
total instructions in shared programs:
8122757 ->
8122957 (<.01%)
instructions in affected programs: 8307 -> 8507 (2.41%)
helped: 0
HURT: 100
HURT stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel) min: 0.84% max: 6.67% x̄: 2.81% x̃: 2.76%
95% mean confidence interval for instructions value: 2.00 2.00
95% mean confidence interval for instructions %-change: 2.58% 3.03%
Instructions are HURT.
total cycles in shared programs:
188510100 ->
188510376 (<.01%)
cycles in affected programs: 76018 -> 76294 (0.36%)
helped: 0
HURT: 55
HURT stats (abs) min: 2 max: 12 x̄: 5.02 x̃: 4
HURT stats (rel) min: 0.07% max: 3.75% x̄: 0.86% x̃: 0.56%
95% mean confidence interval for cycles value: 4.33 5.71
95% mean confidence interval for cycles %-change: 0.60% 1.12%
Cycles are HURT.
GM45
total instructions in shared programs:
4994403 ->
4994503 (<.01%)
instructions in affected programs: 4212 -> 4312 (2.37%)
helped: 0
HURT: 50
HURT stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel) min: 0.84% max: 6.25% x̄: 2.76% x̃: 2.72%
95% mean confidence interval for instructions value: 2.00 2.00
95% mean confidence interval for instructions %-change: 2.45% 3.07%
Instructions are HURT.
total cycles in shared programs:
128928750 ->
128928982 (<.01%)
cycles in affected programs: 67442 -> 67674 (0.34%)
helped: 0
HURT: 47
HURT stats (abs) min: 2 max: 12 x̄: 4.94 x̃: 4
HURT stats (rel) min: 0.09% max: 3.75% x̄: 0.75% x̃: 0.53%
95% mean confidence interval for cycles value: 4.19 5.68
95% mean confidence interval for cycles %-change: 0.50% 1.00%
Cycles are HURT.
(cherry picked from commit
e51eda99dfd6a66b066e371005e7a54ecc38fc11)
Yevhenii Kolesnikov [Mon, 7 Oct 2019 12:59:52 +0000 (15:59 +0300)]
glsl: Enable textureSize for samplerExternalOES
From OES_EGL_image_external_essl3
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1901
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Dave Airlie [Wed, 20 Nov 2019 19:53:03 +0000 (05:53 +1000)]
llvmpipe/ppc: fix if/ifdef confusion in backport.
Fixes:
32aba91c07f (llvmpipe: use ppc64le/ppc64 Large code model for JIT-compiled shaders)
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Hyunjun Ko [Fri, 21 Jun 2019 03:18:33 +0000 (03:18 +0000)]
freedreno/ir3: fix printing output registers of FS.
Fixes:
cea39af2fbf1 ("freedreno/ir3: Generalize ir3_shader_disasm()")
Reviewed-by: Rob Clark <robdclark@gmail.com>
(cherry picked from commit
d0f38394b146fa61197c66a0a0f95fa83f58cec8)
Alejandro Piñeiro [Tue, 19 Nov 2019 10:13:15 +0000 (11:13 +0100)]
v3d: adds an extra MOV for any sig.ld*
Specifically when we are in non-uniform control flow, as we would need
to set the condition for the last instruction. If (for example) a
image atomic load stores directly their value on a NIR register,
last_inst would be a nop, and would fail when set the condition.
Fixes piglit test:
spec/glsl-es-3.10/execution/cs-ssbo-atomic-if-else-2.shader_test
Fixes:
6281f26f064ada ("v3d: Add support for shader_image_load_store.")
v2: (Changes suggested by Eric Anholt)
* Cover all sig.ld* signals, not just ldunif and ldtmu, as all of
them have the same restriction.
* Update comment explaining why we add a MOV in that case
* Tweak commit message.
v3:
* Drop extra set of parens (Eric)
* Add missing ld signal to is_ld_signal to fix shader-db regression.
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit
b4bc59e37ec0969d70e87d233e4e82431ec2e092)
Jose Maria Casanova Crespo [Fri, 15 Nov 2019 13:46:30 +0000 (14:46 +0100)]
v3d: Fix predication with atomic image operations
Fixes dEQP test:
dEQP-GLES31.functional.synchronization.inter_call.with_memory_barrier.image_atomic_multiple_interleaved_write_read
Fixes piglit test:
spec/glsl-es-3.10/execution/cs-image-atomic-if-else.shader_test
Fixes:
6281f26f064ada ("v3d: Add support for shader_image_load_store.")
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit
d983055184320a843d0f056b4c0f7af53cff47ab)
Bas Nieuwenhuizen [Thu, 31 Oct 2019 21:53:30 +0000 (22:53 +0100)]
radv: Do not change scratch settings while shaders are active.
When the scratch ringbuffer settings are changed, the shader unit has
to be idle or we will have shaders using old and new settings.
That combination is not supported on the HW (likely the offset is
ringbuffer idx * WAVESIZE * 1024).
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
4eb2a1dc6fc32a047d53620a929eae0bb255f9da)
Eric Engestrom [Sun, 17 Nov 2019 09:51:52 +0000 (09:51 +0000)]
vulkan: delete typo'd header
Two files exist in that directory:
- vulkan_xlib_randr.h
- vulkan_xlib_xrandr.h
Both were imported in
205c271562db8cb2effc ("vulkan: Update the XML and
headers to 1.1.70") with identical contents (ie. the
VK_EXT_acquire_xlib_display extension), but the former was never
included anywhere and can't be found upstream [1], while the latter is
included in vulkan.h and found upstream.
[1] https://github.com/KhronosGroup/Vulkan-Headers/tree/master/include/vulkan
Fixes:
205c271562db8cb2effc ("vulkan: Update the XML and headers to 1.1.70")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
344859c32d00e444e4e820642541628b36c0622e)
Dylan Baker [Wed, 20 Nov 2019 17:25:03 +0000 (09:25 -0800)]
VERSION: bump for 19.3.0-rc4
Jason Ekstrand [Fri, 8 Nov 2019 15:33:07 +0000 (09:33 -0600)]
anv: Stop bounds-checking pushed UBOs
The bounds checking is actually less safe than just pushing the data.
If the bounds checking actually ever kicks in and it's not on the last
UBO push range, then the shrinking will cause all subsequent ranges to
be pushed to the wrong place in the GRF. One of the behaviors we
definitely don't want is for OOB UBO access to result in completely
unrelated UBOs returning garbage values. It's safer to just push the
UBOs as-requested. If we're really concerned about robustness, we can
emit shader code to do bounds checking which should be stupid cheap (a
CMP followed by SEL).
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Brian Paul [Wed, 9 Oct 2019 18:05:16 +0000 (12:05 -0600)]
Call shmget() with permission 0600 instead of 0777
A security advisory (TALOS-2019-0857/CVE-2019-5068) found that
creating shared memory regions with permission mode 0777 could allow
any user to access that memory. Several Mesa drivers use shared-
memory XImages to implement back buffers for improved performance.
This path changes the shmget() calls to use 0600 (user r/w).
Tested with legacy Xlib driver and llvmpipe.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
(cherry picked from commit
02c3dad0f3b4d26e0faa5cc51d06bc50d693dcdc)
Rob Clark [Mon, 18 Nov 2019 17:42:03 +0000 (09:42 -0800)]
Revert "freedreno/ir3: enable pre-fs texture fetch for a6xx"
This reverts commit
f30c256ec05618fb40dccbd94a3434b2f63db478.
See
088a2a4cab031f1505d531698109f330f94f3072
Fixes:
f30c256ec05 ("freedreno/ir3: enable pre-fs texture fetch for a6xx")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Danylo Piliaiev [Thu, 14 Nov 2019 13:36:27 +0000 (15:36 +0200)]
i965: Unify CC_STATE and BLEND_STATE atoms on Haswell as a workaround
Re-emitting 3DSTATE_CC_STATE_POINTERS after emitting
3DSTATE_BLEND_STATE_POINTERS fixes the shadow flickering in
SuperTuxCart and Tropico 6 which was seen only on Haswell.
The reason for this is unknown and fix was found empirically.
The closest mention in PRM is that it should improve performance.
From the HSW PRM, volume 2b, page 823 (3DSTATE_BLEND_STATE_POINTERS):
"When the BLEND_STATE pointer changes but not the CC_STATE pointer,
driver needs to force a CC_STATE pointer change to improve
blend performance in pixel backend."
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1834
Fixes:
eca4a654 ("i965: Disable dual source blending when shader doesn't support it on gen8+")
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
6f17fe0606a144f977d8b70a7ee9f8371abc144b)
Jonathan Marek [Fri, 15 Nov 2019 20:34:09 +0000 (15:34 -0500)]
freedreno/registers: fix a6xx_2d_blit_cntl ROTATE
A change from
b7093882 got overwritten by
610c8c93
Fixes:
610c8c93 ("freedreno/registers: Update with GS, HS and DS registers")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
(cherry picked from commit
75e58d1fae94f68d75c04770b1cadc6c1b112f6c)
Jonathan Marek [Fri, 15 Nov 2019 17:38:28 +0000 (12:38 -0500)]
freedreno/ir3: disable texture prefetch for 1d array textures
Prefetch only supports the basic 2D texture case, checking is_array is
needed because 1d array textures pass the coord num_components==2 test.
Fixes:
2a0d45ae ("freedreno/ir3: Add a NIR pass to select tex instructions eligible for pre-fetch")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
(cherry picked from commit
0f5743429c76b385db9c513102b2010213ffbb8c)
Ben Crocker [Wed, 13 Nov 2019 20:27:24 +0000 (20:27 +0000)]
llvmpipe: use ppc64le/ppc64 Large code model for JIT-compiled shaders
Large programs, e.g. gnome-shell and firefox, may tax the
addressability of the Medium code model once a (potentially unbounded)
number of dynamically generated JIT-compiled shader programs are
linked in and relocated. Yet the default code model as of LLVM 8 is
Medium or even Small.
The cost of changing from Medium to Large is negligible:
- an additional 8-byte pointer stored immediately before the shader entrypoint;
- change an add-immediate (addis) instruction to a load (ld).
Testing with WebGL Conformance
(https://www.khronos.org/registry/webgl/sdk/tests/webgl-conformance-tests.html)
yields clean runs with this change (and crashes without it).
Testing with glxgears shows no detectable performance difference.
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=
1753327,
1753789,
1543572,
1747110, and
1582226
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/223
Co-authored by: Nemanja Ivanovic <nemanjai@ca.ibm.com>, Tom Stellard <tstellar@redhat.com>
CC: mesa-stable@lists.freedesktop.org
Signed-off-by: Ben Crocker <bcrocker@redhat.com>
(cherry picked from commit
9c3be6d21fa6a45852045d0286b80fb420f82fe3)
Conflicts resolved Dylan (PIPE_ARCH -> UTIL_ARCH rename)