OSDN Git Service
Jakob Stoklund Olesen [Wed, 20 Mar 2013 23:09:50 +0000 (23:09 +0000)]
Add a catch-all WriteSystem SchedWrite type.
This is used for all the expensive system instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177598
91177308-0d34-0410-b5e6-
96231b3b80d8
Nadav Rotem [Wed, 20 Mar 2013 22:53:44 +0000 (22:53 +0000)]
When computing the demanded bits of Load SDNodes, make sure that we are looking at the loaded-value operand and not the ptr result (in case of pre-inc loads).
rdar://
13348420
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177596
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Wed, 20 Mar 2013 22:52:54 +0000 (22:52 +0000)]
Debug Info: Swap the 2nd and 3rd parameters to DICompileUnit to match the common DIScope prefix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177595
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Wed, 20 Mar 2013 22:37:16 +0000 (22:37 +0000)]
Annotate the remaining SSE MOV instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177592
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Wed, 20 Mar 2013 22:37:13 +0000 (22:37 +0000)]
Annotate SSE horizontal and integer instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177591
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Wed, 20 Mar 2013 22:34:33 +0000 (22:34 +0000)]
Remove unused field in DICompileUnit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177590
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Liao [Wed, 20 Mar 2013 22:01:10 +0000 (22:01 +0000)]
Correct cost model for vector shift on AVX2
- After moving logic recognizing vector shift with scalar amount from
DAG combining into DAG lowering, we declare to customize all vector
shifts even vector shift on AVX is legal. As a result, the cost model
needs special tuning to identify these legal cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177586
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakub Staszak [Wed, 20 Mar 2013 21:47:51 +0000 (21:47 +0000)]
Remove trailing spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177584
91177308-0d34-0410-b5e6-
96231b3b80d8
Bill Wendling [Wed, 20 Mar 2013 21:13:59 +0000 (21:13 +0000)]
Call the new llvm_gcov_init function to register the environment.
Use the new `llvm_gcov_init' function to register the writeout and flush
functions. The initialization function will also call `atexit' for some cleanups
and final writout calls. But it does this only once. This is better than
checking for the `main' function, because in a library that function may not
exist.
<rdar://problem/
12439551>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177579
91177308-0d34-0410-b5e6-
96231b3b80d8
Chris Lattner [Wed, 20 Mar 2013 21:04:53 +0000 (21:04 +0000)]
minor code style cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177576
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Wed, 20 Mar 2013 21:03:41 +0000 (21:03 +0000)]
xlC doesn't like Header being both a type and a member variable. Rename the
member variable.
Patch by Kai <kai@redstar.de>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177575
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Wed, 20 Mar 2013 21:00:22 +0000 (21:00 +0000)]
Add std prefixes to fix the build with xlc.
Patch by Kai <kai@redstar.de>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177574
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Wed, 20 Mar 2013 20:43:11 +0000 (20:43 +0000)]
Make sure TableGen exits with an error code after printing errors.
This makes it possible to report multiple errors in one invocation.
There are already calls to PrintError in CodeGenDAGPatterns.cpp which
previously would not cause TableGen to fail.
<rdar://problem/
13463339>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177573
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Wed, 20 Mar 2013 19:39:15 +0000 (19:39 +0000)]
Refactor file/directory path in namespace debug info to refer directly to the pair rather than the DIFile
(paired to a Clang test - excuse the buildbot skew/fallout)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177566
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Wed, 20 Mar 2013 19:14:16 +0000 (19:14 +0000)]
Enhance debug info namespace test to check for context/scope reference
The differing file (due to the #line directive in the original source) is for
future testing improvements coming soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177560
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Wed, 20 Mar 2013 18:25:12 +0000 (18:25 +0000)]
Remove blank line before block comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177550
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Wed, 20 Mar 2013 17:49:48 +0000 (17:49 +0000)]
DIBuilder: allow linkage name to be specified for global variables
Patch by Kai Nacke (kai@redstar.de)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177547
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Wed, 20 Mar 2013 17:39:02 +0000 (17:39 +0000)]
Make target-specific test case in r177474 only run when that target is built
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177545
91177308-0d34-0410-b5e6-
96231b3b80d8
Eli Bendersky [Wed, 20 Mar 2013 17:00:25 +0000 (17:00 +0000)]
Add timing of the IR parsing code with a new -time-ir-parsing flag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177543
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Wed, 20 Mar 2013 16:56:39 +0000 (16:56 +0000)]
Add some missing SSE annotations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177540
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Wed, 20 Mar 2013 16:56:36 +0000 (16:56 +0000)]
Annotate remaining IIC_BIN_* instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177539
91177308-0d34-0410-b5e6-
96231b3b80d8
Christian Konig [Wed, 20 Mar 2013 15:43:00 +0000 (15:43 +0000)]
Revert "pre-RA-sched: fix TargetOpcode usage"
This reverts commit
06091513c283c863296f01cc7c2e86b56bb50d02.
The code is obviously wrong, but the trivial fix causes
inefficient code generation on X86. Somebody with more
knowledge of the code needs to take a look here.
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177529
91177308-0d34-0410-b5e6-
96231b3b80d8
Justin Holewinski [Wed, 20 Mar 2013 14:51:01 +0000 (14:51 +0000)]
Move SDNode order propagation to SDNodeOrdering, which also fixes a missed
case of order propagation during isel.
Thanks Owen for the suggestion!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177525
91177308-0d34-0410-b5e6-
96231b3b80d8
Christian Konig [Wed, 20 Mar 2013 13:49:22 +0000 (13:49 +0000)]
pre-RA-sched: fix TargetOpcode usage
TargetOpcodes need to be treaded as Machine- and not ISD-Opcodes.
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177518
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Wed, 20 Mar 2013 07:40:56 +0000 (07:40 +0000)]
Fix a silly search-and-replace goof with r177495 that only broke
non-release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177498
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Wed, 20 Mar 2013 07:30:36 +0000 (07:30 +0000)]
[SROA] Don't preserve the IR names in release builds.
This is espcially important because the new SROA pass goes to great
lengths to provide helpful names for debugging, and as a consequence
they can become very slow to render.
Good for between 5% and 15% of the SROA runtime on some slow test cases
such as the one in PR15412.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177495
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Wed, 20 Mar 2013 06:47:00 +0000 (06:47 +0000)]
Move the endif to the correct line so we don't have warnings about
unused statistics variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177494
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Wed, 20 Mar 2013 06:30:46 +0000 (06:30 +0000)]
Introduce some new statistics to help track the exact behavior of the
new SROA pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177493
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Wed, 20 Mar 2013 06:27:06 +0000 (06:27 +0000)]
Reorder the DIFile parameter in DINameSpace
Moving the DIFile parameter to immediately proceed the tag so that it will be a
common prefix with other DIScopes (once the DIFile is replaced with the raw
file/directory pair).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177492
91177308-0d34-0410-b5e6-
96231b3b80d8
Hao Liu [Wed, 20 Mar 2013 06:18:06 +0000 (06:18 +0000)]
Add a test case for PR15318 fixed in r177472
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177489
91177308-0d34-0410-b5e6-
96231b3b80d8
Nick Lewycky [Wed, 20 Mar 2013 05:59:40 +0000 (05:59 +0000)]
Don't assume the test directory is writable, use %T to find a writable
directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177488
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Wed, 20 Mar 2013 05:15:37 +0000 (05:15 +0000)]
Test DW_TAG_namespace support in the backend
This is the backend portion of a Clang test case
(clang/test/CodeGenCXX/debug-info-namespace.cpp) that was roughly/coarsely
testing LLVM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177487
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Wed, 20 Mar 2013 05:14:14 +0000 (05:14 +0000)]
Provide more details for DINameSpace debug info in the IR comment annotations
Sorry for the version skew - I should've committed this before the
corresponding Clang test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177486
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Liao [Wed, 20 Mar 2013 02:33:21 +0000 (02:33 +0000)]
Fix PR15296
- Move SRA/SRL/SHL lowering support from DAG combination to DAG lowering
to support extended 256-bit integer in AVX but not AVX2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177478
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Liao [Wed, 20 Mar 2013 02:28:20 +0000 (02:28 +0000)]
Mark all variable shifts needing customizing
- Prepare moving logic from DAG combining into DAG lowering. There's no
functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177477
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Liao [Wed, 20 Mar 2013 02:20:36 +0000 (02:20 +0000)]
Move scalar immediate shift lowering into a dedicated func
- no functionality change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177476
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Wed, 20 Mar 2013 01:55:11 +0000 (01:55 +0000)]
Fix test case regression on ARM & PPC introduced r177239
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177474
91177308-0d34-0410-b5e6-
96231b3b80d8
Hao Liu [Wed, 20 Mar 2013 01:46:36 +0000 (01:46 +0000)]
Fix AsmPrinter crashes with assertion. Bug 15318 in Bugzilla
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177472
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Wed, 20 Mar 2013 00:26:26 +0000 (00:26 +0000)]
Refactor the DIFile (2nd) parameter to DITypes to be an MDNode reference to a raw directory/file pair
This makes DIType's first non-tag parameter the same as DIFile's, allowing them
to both share the common implementation of getFilename/getDirectory in DIScope.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177467
91177308-0d34-0410-b5e6-
96231b3b80d8
Justin Holewinski [Wed, 20 Mar 2013 00:10:32 +0000 (00:10 +0000)]
Propagate DAG node ordering during type legalization and instruction selection
A node's ordering is only propagated during legalization if (a) the new node does
not have an ordering (is not a CSE'd node), or (b) the new node has an ordering
that is higher than the node being legalized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177465
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Tue, 19 Mar 2013 23:44:03 +0000 (23:44 +0000)]
Fix pr13145 - Naming a function like a register name confuses the asm parser.
Patch by Stepan Dyatkovskiy <stpworld@narod.ru>
rdar://
13457826
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177463
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Tue, 19 Mar 2013 23:25:22 +0000 (23:25 +0000)]
Move the DIFile operand to DITypes from the 4th operand to the 2nd.
This is another step along the way to making all DIScopes have a common prefix
which can be added to in a general manner to support using directives
(DW_TAG_imported_module).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177462
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Tue, 19 Mar 2013 23:23:31 +0000 (23:23 +0000)]
Annotate various null idioms with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177461
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Tue, 19 Mar 2013 23:23:29 +0000 (23:23 +0000)]
Annotate SSE float conversions with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177460
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Tue, 19 Mar 2013 23:23:26 +0000 (23:23 +0000)]
Annotate X86InstrCMovSetCC.td with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177459
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Tue, 19 Mar 2013 23:10:26 +0000 (23:10 +0000)]
Formatting fixups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177458
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Tue, 19 Mar 2013 22:13:05 +0000 (22:13 +0000)]
Dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177451
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Tue, 19 Mar 2013 22:12:47 +0000 (22:12 +0000)]
Dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177450
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Tue, 19 Mar 2013 21:58:18 +0000 (21:58 +0000)]
[ms-inline asm] Move the immediate asm rewrite into the target specific
logic as a QOI cleanup. No functional change. Tests already in place.
rdar://
13456414
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177446
91177308-0d34-0410-b5e6-
96231b3b80d8
Quentin Colombet [Tue, 19 Mar 2013 21:46:49 +0000 (21:46 +0000)]
Update global merge pass according to Duncan's advices:
- Remove useless includes
- Change misleading comments
- Move code into doFinalization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177445
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Tue, 19 Mar 2013 21:16:56 +0000 (21:16 +0000)]
Annotate X86InstrCompiler.td with SchedRW lists.
Add a new WriteZero SchedWrite type for the common dependency-breaking
instructions that clear a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177442
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Tue, 19 Mar 2013 21:12:14 +0000 (21:12 +0000)]
[ms-inline asm] Remove the brackets from X86Operand in the IR. These will be
added back in by X86AsmPrinter::printIntelMemReference() during codegen.
Previously, this following example
void t() {
int i;
__asm mov eax, [i]
}
would generate the below assembly
mov eax, dword ptr [[eax]]
which resulted in a fatal error when compiling. Test case coming on the
clang side.
rdar://
13444264
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177440
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Tue, 19 Mar 2013 21:11:56 +0000 (21:11 +0000)]
[ms-inline asm] Create a helper function, CreateMemForInlineAsm, that creates
an X86Operand, but also performs a Sema lookup and adds the sizing directive
when appropriate. Use this when parsing a bracketed statement. This is
necessary to get the instruction matching correct as well. Test case coming
on clang side.
rdar://
13455408
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177439
91177308-0d34-0410-b5e6-
96231b3b80d8
Bill Wendling [Tue, 19 Mar 2013 21:03:22 +0000 (21:03 +0000)]
Register the GCOV writeout functions so that they're emitted serially.
We don't want to write out >1000 files at the same time. That could make things
prohibitively expensive. Instead, register the "writeout" function so that it's
emitted serially.
<rdar://problem/
12439551>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177437
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Tue, 19 Mar 2013 20:22:32 +0000 (20:22 +0000)]
Add a comment to the CodeGen/PowerPC/asym-regclass-copy.ll test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177434
91177308-0d34-0410-b5e6-
96231b3b80d8
Arnaud A. de Grandmaison [Tue, 19 Mar 2013 20:00:22 +0000 (20:00 +0000)]
IndVarSimplify: do not recompute an IV value outside of the loop if :
- it is trivially known to be used inside the loop in a way that can not be optimized away
- there is no use outside of the loop which can take advantage of the computation hoisting
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177432
91177308-0d34-0410-b5e6-
96231b3b80d8
Ulrich Weigand [Tue, 19 Mar 2013 19:53:27 +0000 (19:53 +0000)]
Add missing mayLoad flag to LHAUX8 and LWAUX.
All pre-increment load patterns need to set the mayLoad flag (since
they don't provide a DAG pattern).
This was missing for LHAUX8 and LWAUX, which is added by this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177431
91177308-0d34-0410-b5e6-
96231b3b80d8
Ulrich Weigand [Tue, 19 Mar 2013 19:52:30 +0000 (19:52 +0000)]
Rewrite LHAU8 pattern to use standard memory operand.
As opposed to to pre-increment store patterns, the pre-increment
load patterns were already using standard memory operands, with
the sole exception of LHAU8.
As there's no real reason why LHAU8 should be different here,
this patch simply rewrites the pattern to also use a memri
operand, just like all the other patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177430
91177308-0d34-0410-b5e6-
96231b3b80d8
Ulrich Weigand [Tue, 19 Mar 2013 19:52:04 +0000 (19:52 +0000)]
Rewrite pre-increment store patterns to use standard memory operands.
Currently, pre-increment store patterns are written to use two separate
operands to represent address base and displacement:
stwu $rS, $ptroff($ptrreg)
This causes problems when implementing the assembler parser, so this
commit changes the patterns to use standard (complex) memory operands
like in all other memory access instruction patterns:
stwu $rS, $dst
To still match those instructions against the appropriate pre_store
SelectionDAG nodes, the patch uses the new feature that allows a Pat
to match multiple DAG operands against a single (complex) instruction
operand.
Approved by Hal Finkel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177429
91177308-0d34-0410-b5e6-
96231b3b80d8
Ulrich Weigand [Tue, 19 Mar 2013 19:51:09 +0000 (19:51 +0000)]
Extend TableGen instruction selection matcher to improve handling
of complex instruction operands (e.g. address modes).
Currently, if a Pat pattern creates an instruction that has a complex
operand (i.e. one that consists of multiple sub-operands at the MI
level), this operand must match a ComplexPattern DAG pattern with the
correct number of output operands.
This commit extends TableGen to alternatively allow match a complex
operands against multiple separate operands at the DAG level.
This allows using Pat patterns to match pre-increment nodes like
pre_store (which must have separate operands at the DAG level) onto
an instruction pattern that uses a multi-operand memory operand,
like the following example on PowerPC (will be committed as a
follow-on patch):
def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst),
"stwu $rS, $dst", LdStStoreUpd, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff),
(STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>;
Here, the pair of "ptroff" and "ptrreg" operands is matched onto the
complex operand "dst" of class "memri" in the "STWU" instruction.
Approved by Jakob Stoklund Olesen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177428
91177308-0d34-0410-b5e6-
96231b3b80d8
Ulrich Weigand [Tue, 19 Mar 2013 19:50:30 +0000 (19:50 +0000)]
Fix sub-operand size mismatch in tocentry operands.
The tocentry operand class refers to 64-bit values (it is only used in 64-bit,
where iPTR is a 64-bit type), but its sole suboperand is designated as 32-bit
type. This causes a mismatch to be detected at compile-time with the TableGen
patch I'll check in shortly.
To fix this, this commit changes the suboperand to a 64-bit type as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177427
91177308-0d34-0410-b5e6-
96231b3b80d8
Ulrich Weigand [Tue, 19 Mar 2013 19:49:52 +0000 (19:49 +0000)]
Remove an invalid and unnecessary Pat pattern from the X86 backend:
def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))),
(MOV64rm tglobaltlsaddr :$dst)>;
This pattern is invalid because the MOV64rm instruction expects a
source operand of type "i64mem", which is a subclass of X86MemOperand
and thus actually consists of five MI operands, but the Pat provides
only a single MI operand ("tglobaltlsaddr" matches an SDnode of
type ISD::TargetGlobalTLSAddress and provides a single output).
Thus, if the pattern were ever matched, subsequent uses of the MOV64rm
instruction pattern would access uninitialized memory. In addition,
with the TableGen patch I'm about to check in, this would actually be
reported as a build-time error.
Fortunately, the pattern does in fact never match, for at least two
independent reasons.
First, the code generator actually never generates a pattern of the
form (load (X86Wrapper (tglobaltlsaddr))). For most combinations of
TLS and code models, (tglobaltlsaddr) represents just an offset that
needs to be added to some base register, so it is never directly
dereferenced. The only exception is the initial-exec model, where
(tglobaltlsaddr) refers to the (pc-relative) address of a GOT slot,
which *is* in fact directly dereferenced: but in that case, the
X86WrapperRIP node is used, not X86Wrapper, so the Pat doesn't match.
Second, even if some patterns along those lines *were* ever generated,
we should not need an extra Pat pattern to match it. Instead, the
original MOV64rm instruction pattern ought to match directly, since
it uses an "addr" operand, which is implemented via the SelectAddr
C++ routine; this routine is supposed to accept the full range of
input DAGs that may be implemented by a single mov instruction,
including those cases involving ISD::TargetGlobalTLSAddress (and
actually does so e.g. in the initial-exec case as above).
To avoid build breaks (due to the above-mentioned error) after the
TableGen patch is checked in, I'm removing this Pat here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177426
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Tue, 19 Mar 2013 18:51:05 +0000 (18:51 +0000)]
Prepare to make r0 an allocatable register on PPC
Currently the PPC r0 register is unconditionally reserved. There are two reasons
for this:
1. r0 is treated specially (as the constant 0) by certain instructions, and so
cannot be used with those instructions as a regular register.
2. r0 is used as a temporary register in the CR-register spilling process
(where, under some circumstances, we require two GPRs).
This change addresses the first reason by introducing a restricted register
class (without r0) for use by those instructions that treat r0 specially. These
register classes have a new pseudo-register, ZERO, which represents the r0-as-0
use. This has the side benefit of making the existing target code simpler (and
easier to understand), and will make it clear to the register allocator that
uses of r0 as 0 don't conflict will real uses of the r0 register.
Once the CR spilling code is improved, we'll be able to allocate r0.
Adding these extra register classes, for some reason unclear to me, causes
requests to the target to copy 32-bit registers to 64-bit registers. The
resulting code seems correct (and causes no test-suite failures), and the new
test case covers this new kind of asymmetric copy.
As r0 is still reserved, no functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177423
91177308-0d34-0410-b5e6-
96231b3b80d8
Nadav Rotem [Tue, 19 Mar 2013 18:38:27 +0000 (18:38 +0000)]
Optimize sext <4 x i8> and <4 x i16> to <4 x i64>.
Patch by Ahmad, Muhammad T <muhammad.t.ahmad@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177421
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Tue, 19 Mar 2013 18:03:58 +0000 (18:03 +0000)]
Annotate X86InstrExtension.td with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177418
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Tue, 19 Mar 2013 18:03:55 +0000 (18:03 +0000)]
Annotate a lot of X86InstrInfo.td with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177417
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Tue, 19 Mar 2013 17:32:17 +0000 (17:32 +0000)]
[ms-inline asm] Move the size directive asm rewrite into the target specific
logic as a QOI cleanup.
rdar://
13445327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177413
91177308-0d34-0410-b5e6-
96231b3b80d8
Eli Bendersky [Tue, 19 Mar 2013 16:04:19 +0000 (16:04 +0000)]
Update documentation of llvm-link to reflect recent cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177411
91177308-0d34-0410-b5e6-
96231b3b80d8
Eli Bendersky [Tue, 19 Mar 2013 16:04:02 +0000 (16:04 +0000)]
Remove stale comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177410
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Samsonov [Tue, 19 Mar 2013 15:33:18 +0000 (15:33 +0000)]
Fix for r177390: map values are pointers, use DeleteContainerSeconds() instead of .clear()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177409
91177308-0d34-0410-b5e6-
96231b3b80d8
Eli Bendersky [Tue, 19 Mar 2013 15:26:24 +0000 (15:26 +0000)]
The Linker interface has some dead code after the cleanup in r172749
(and possibly others). The attached patch removes it, and tries to
update comments accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177406
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Tue, 19 Mar 2013 15:23:39 +0000 (15:23 +0000)]
Cleanup PPC64 unaligned i64 load/store
Remove an accidentally-added instruction definition and add a comment in the
test case. This is in response to a post-commit review by Bill Schmidt.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177404
91177308-0d34-0410-b5e6-
96231b3b80d8
Sean Silva [Tue, 19 Mar 2013 15:22:02 +0000 (15:22 +0000)]
[docs] Remove incorrect information about lit.
Lit does support redirects in the 2>&1 style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177403
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitry Vyukov [Tue, 19 Mar 2013 10:24:42 +0000 (10:24 +0000)]
llvm-symbolizer: flush internal caches functionality
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177390
91177308-0d34-0410-b5e6-
96231b3b80d8
David Tweed [Tue, 19 Mar 2013 10:16:40 +0000 (10:16 +0000)]
The testing to ensure a vector of zeros of type floating point isn't misclassified as negative zero can be simplified, as pointed out by Duncan Sands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177386
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Samsonov [Tue, 19 Mar 2013 10:10:03 +0000 (10:10 +0000)]
Enable -Wnon-virtual-dtor build warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177385
91177308-0d34-0410-b5e6-
96231b3b80d8
Renato Golin [Tue, 19 Mar 2013 08:15:38 +0000 (08:15 +0000)]
Improve long vector sext/zext lowering on ARM
The ARM backend currently has poor codegen for long sext/zext
operations, such as v8i8 -> v8i32. This patch addresses this
by performing a custom expansion in ARMISelLowering. It also
adds/changes the cost of such lowering in ARMTTI.
This partially addresses PR14867.
Patch by Pete Couperus
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177380
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Tue, 19 Mar 2013 08:09:38 +0000 (08:09 +0000)]
Don't reserve R31 on PPC64 unless the frame pointer is needed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177379
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrew Trick [Tue, 19 Mar 2013 05:10:27 +0000 (05:10 +0000)]
Revert "Cleanup some SCEV logic a bit."
This reverts commit
82cd8f7382322bee7a71cdc31f7a923c44d37d32.
Just add a comment instead!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177377
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrew Trick [Tue, 19 Mar 2013 04:14:59 +0000 (04:14 +0000)]
Cleanup some SCEV logic a bit.
Make the code more obvious to scan-build and humans.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177375
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrew Trick [Tue, 19 Mar 2013 04:14:57 +0000 (04:14 +0000)]
Tighten up an internal LSR API that should check for NULL.
No test case, but should fix a scan_build warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177374
91177308-0d34-0410-b5e6-
96231b3b80d8
Nick Lewycky [Tue, 19 Mar 2013 01:37:55 +0000 (01:37 +0000)]
Emit the linkage name instead of the function name, when available. This means
that we'll prefer to emit the mangled C++ name (pending a clang change).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177371
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Mon, 18 Mar 2013 23:58:28 +0000 (23:58 +0000)]
Fix a sign-extension bug in PPCCTRLoops
Don't sign extend the immediate value from the OR instruction in
an LIS/OR pair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177361
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakub Staszak [Mon, 18 Mar 2013 23:45:45 +0000 (23:45 +0000)]
Move #include of BitVector from .h to .cpp file.
Also remove unneeded #include and forward declaration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177357
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakub Staszak [Mon, 18 Mar 2013 23:40:46 +0000 (23:40 +0000)]
Add some constantness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177356
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakub Staszak [Mon, 18 Mar 2013 23:33:44 +0000 (23:33 +0000)]
Remove unneeded #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177351
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakub Staszak [Mon, 18 Mar 2013 23:33:14 +0000 (23:33 +0000)]
Make methods const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177350
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakub Staszak [Mon, 18 Mar 2013 23:31:30 +0000 (23:31 +0000)]
Make method private. Keep coding standard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177348
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Mon, 18 Mar 2013 23:31:24 +0000 (23:31 +0000)]
[ms-inline asm] Avoid emitting a redundant sizing directive, if we've already
parsed one. Test case coming shortly.
rdar://
13446980
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177347
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakub Staszak [Mon, 18 Mar 2013 23:08:01 +0000 (23:08 +0000)]
Change NULL to 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177342
91177308-0d34-0410-b5e6-
96231b3b80d8
Bill Wendling [Mon, 18 Mar 2013 23:04:39 +0000 (23:04 +0000)]
Register the flush function for each compile unit.
For each compile unit, we want to register a function that will flush that
compile unit. Otherwise, __gcov_flush() would only flush the counters within the
current compile unit, and not any outside of it.
PR15191 & <rdar://problem/
13167507>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177340
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakub Staszak [Mon, 18 Mar 2013 23:04:30 +0000 (23:04 +0000)]
Remove trailing spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177339
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Mon, 18 Mar 2013 23:00:58 +0000 (23:00 +0000)]
Fix PPC unaligned 64-bit loads and stores
PPC64 supports unaligned loads and stores of 64-bit values, but
in order to use the r+i forms, the offset must be a multiple of 4.
Unfortunately, this cannot always be determined by examining the
immediate itself because it might be available only via a TOC entry.
In order to get around this issue, we additionally predicate the
selection of the r+i form on the alignment of the load or store
(forcing it to be at least 4 in order to select the r+i form).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177338
91177308-0d34-0410-b5e6-
96231b3b80d8
Arnold Schwaighofer [Mon, 18 Mar 2013 22:47:09 +0000 (22:47 +0000)]
ARM cost model: Make some vector integer to float casts cheaper
The default logic marks them as too expensive.
For example, before this patch we estimated:
cost of 16 for instruction: %r = uitofp <4 x i16> %v0 to <4 x float>
While this translates to:
vmovl.u16 q8, d16
vcvt.f32.u32 q8, q8
All other costs are left to the values assigned by the fallback logic. Theses
costs are mostly reasonable in the sense that they get progressively more
expensive as the instruction sequences emitted get longer.
radar://
13445992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177334
91177308-0d34-0410-b5e6-
96231b3b80d8
Arnold Schwaighofer [Mon, 18 Mar 2013 22:47:06 +0000 (22:47 +0000)]
ARM cost model: Correct cost for some cheap float to integer conversions
Fix cost of some "cheap" cast instructions. Before this patch we used to
estimate for example:
cost of 16 for instruction: %r = fptoui <4 x float> %v0 to <4 x i16>
While we would emit:
vcvt.s32.f32 q8, q8
vmovn.i32 d16, q8
vuzp.8 d16, d17
All other costs are left to the values assigned by the fallback logic. Theses
costs are mostly reasonable in the sense that they get progressively more
expensive as the instruction sequences emitted get longer.
radar://
13434072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177333
91177308-0d34-0410-b5e6-
96231b3b80d8
Quentin Colombet [Mon, 18 Mar 2013 22:30:07 +0000 (22:30 +0000)]
Extend global merge pass to optionally consider global constant variables.
Also add some checks to not merge globals used within landing pad instructions or marked as "used".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177331
91177308-0d34-0410-b5e6-
96231b3b80d8
Bill Schmidt [Mon, 18 Mar 2013 22:12:04 +0000 (22:12 +0000)]
Change test cases to handle unaligned references.
Hal Finkel recently added code to allow unaligned memory references
for PowerPC. Two tests were temporarily modified with
-disable-ppc-unaligned to keep them from failing. This patch adjusts
the expected code generation for the unaligned references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177328
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Mon, 18 Mar 2013 22:08:16 +0000 (22:08 +0000)]
Remove unnecessary leading comment characters in lit-only file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177327
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Mon, 18 Mar 2013 22:01:35 +0000 (22:01 +0000)]
Add SchedRW annotations to most of X86InstrSSE.td.
We hitch a ride with the existing OpndItins class that was used to add
instruction itinerary classes in the many multiclasses in this file.
Use the link provided by the X86FoldableSchedWrite.Folded to find the
right SchedWrite for folded loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177326
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Mon, 18 Mar 2013 21:32:39 +0000 (21:32 +0000)]
Annotate X86 arithmetic instructions with SchedRW lists.
This new-style scheduling information is going to replace the
instruction iteneraries.
This also serves as a test case for Andy's fix in r177317.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177323
91177308-0d34-0410-b5e6-
96231b3b80d8