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Krzysztof Parzyszek [Mon, 26 Mar 2018 15:32:03 +0000 (15:32 +0000)]
[Hexagon] Give priority to post-incremementing memory accesses in LSR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328506
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Simon Pilgrim [Mon, 26 Mar 2018 15:30:47 +0000 (15:30 +0000)]
[X86][Btver2] Add CVTSD2SI/CVTSS2SI scheduler costs
Account for the "+i" integer pipe transfer cost (1cy use of JALU0 for GPR PRF write)
This also adds missing vcvttss2si tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328505
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Ilya Biryukov [Mon, 26 Mar 2018 15:12:30 +0000 (15:12 +0000)]
Migrate dockerfiles to use multi-stage builds.
Summary:
We previously emulated multi-staged builds using two dockerfiles,
native support from Docker allows us to merge them into one,
simplifying our scripts.
For more details about multi-stage builds, see:
https://docs.docker.com/develop/develop-images/multistage-build/
Reviewers: mehdi_amini, klimek, sammccall
Reviewed By: sammccall
Subscribers: llvm-commits, ioeric, cfe-commits
Differential Revision: https://reviews.llvm.org/D44787
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328503
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Sanjay Patel [Mon, 26 Mar 2018 15:03:57 +0000 (15:03 +0000)]
[InstCombine] distribute fmul over fadd/fsub
This replaces a large chunk of code that was looking for compound
patterns that include these sub-patterns. Existing tests ensure that
all of the previous examples are still folded as expected.
We still need to loosen the FMF check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328502
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Simon Pilgrim [Mon, 26 Mar 2018 14:44:24 +0000 (14:44 +0000)]
[X86][Btver2] Fix YMM BLENDPD/BLENDPS + UNPCKPD/UNPCKP instructions costs
These should match the YMM MOVDUP/ PERMILPD/PERMILPS + SHUFPD/SHUFPS shuffles instead of using the WriteFShuffle defaults.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328501
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Andrea Di Biagio [Mon, 26 Mar 2018 14:25:52 +0000 (14:25 +0000)]
[llvm-mca] Fix how views are added to the InstructionTables.
This should fix the stack-use-after-scope reported by the asan buildbots after
revision 328493.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328499
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Sanjay Patel [Mon, 26 Mar 2018 14:25:43 +0000 (14:25 +0000)]
[InstCombine] check uses before creating instructions for fmul distribution
As the tests show, we could create extra instructions without any obvious benefit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328498
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Simon Pilgrim [Mon, 26 Mar 2018 14:03:40 +0000 (14:03 +0000)]
[X86][Btver2] Add (V)SQRTPD/(V)SQRTSD costs
The xmm sd/pd versions were using the WriteFSQRT default which is modelled on sqrtss/sqrtps
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328497
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Nicolai Haehnle [Mon, 26 Mar 2018 13:56:53 +0000 (13:56 +0000)]
AMDGPU: Introduce common SOP_Pseudo and VOP_Pseudo TableGen base classes
Differential revision: https://reviews.llvm.org/D44820
Change-Id: I732979e2964006aa15d78a333d8886e6855f319a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328496
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Andrea Di Biagio [Mon, 26 Mar 2018 13:44:54 +0000 (13:44 +0000)]
[llvm-mca] Add a flag -instruction-info to enable/disable the instruction info view.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328493
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Andrea Di Biagio [Mon, 26 Mar 2018 13:21:48 +0000 (13:21 +0000)]
[llvm-mca] Update the commandline docs after r328305.
Document that flag -resource-pressure can be used to enable/disable the resource
pressure view. This change should have been part of r328305.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328492
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Simon Pilgrim [Mon, 26 Mar 2018 13:15:20 +0000 (13:15 +0000)]
[X86][Btver2] Double the AGU and schedule pipe resources for YMM
Both the AGUs and schedule pipes are double pumped for 256-bit instructions as well as the functional units which we already model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328491
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Krzysztof Parzyszek [Mon, 26 Mar 2018 13:10:09 +0000 (13:10 +0000)]
[LSR] Allow giving priority to post-incrementing addressing modes
Implement TTI interface for targets to indicate that the LSR should give
priority to post-incrementing addressing modes.
Combination of patches by Sebastian Pop and Brendon Cahoon.
Differential Revision: https://reviews.llvm.org/D44758
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328490
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Andrea Di Biagio [Mon, 26 Mar 2018 12:04:53 +0000 (12:04 +0000)]
[llvm-mca] Add flag -instruction-tables to print the theoretical resource pressure distribution for instructions (PR36874)
The goal of this patch is to address most of PR36874. To fully fix PR36874 we
need to split the "InstructionInfo" view from the "SummaryView". That would make
easy to check the latency and rthroughput as well.
The patch reuses all the logic from ResourcePressureView to print out the
"instruction tables".
We have an entry for every instruction in the input sequence. Each entry reports
the theoretical resource pressure distribution. Resource pressure is uniformly
distributed across all the processor resource units of a group.
At the moment, the backend pipeline is not configurable, so the only way to fix
this is by creating a different driver that simply sends instruction events to
the resource pressure view. That means, we don't use the Backend interface.
Instead, it is simpler to just have a different code-path for when flag
-instruction-tables is specified.
Once Clement addresses bug 36663, then we can port the "instruction tables"
logic into a stage of our configurable pipeline.
Updated the BtVer2 test cases (thanks Simon for the help). Now we pass flag
-instruction-tables to each modified test.
Differential Revision: https://reviews.llvm.org/D44839
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328487
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Carlos Alberto Enciso [Mon, 26 Mar 2018 11:38:01 +0000 (11:38 +0000)]
Test commit - adding a new line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328484
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Max Kazantsev [Mon, 26 Mar 2018 11:31:46 +0000 (11:31 +0000)]
[LoopUnroll] Fix dangling pointers in SCEV
Current logic of loop SCEV invalidation in Loop Unroller implicitly relies on
fact that exit count of outer loops cannot rely on exiting blocks of
inner loops, which is true in current implementation of backedge taken count
calculation but is wrong in general. As result, when we only forget the loop that
we have just unrolled, we may still have cached data for its outer loops (in particular,
exit counts) which keeps references on blocks of inner loop that could have been
changed or even deleted.
The attached test demonstrates a situaton when after unrolling of innermost loop
the outermost loop contains a dangling pointer on non-existant block. The problem
shows up when we apply patch https://reviews.llvm.org/D44677 that makes SCEV
smarter about exit count calculation. I am not sure if the bug exists without this patch,
it appears that now it is accidentally correct just because in practice exact backedge
taken count for outer loops with complex control flow inside is never calculated.
But when SCEV learns to do so, this problem shows up.
This patch replaces existing logic of SCEV loop invalidation with a correct one, which
happens to be invalidation of outermost loop (which also leads to invalidation of all
loops inside of it). It is the only way to ensure that no outer loop keeps dangling pointers
on removed blocks, or just outdated information that has changed after unrolling.
Differential Revision: https://reviews.llvm.org/D44818
Reviewed By: samparker
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328483
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Hans Wennborg [Mon, 26 Mar 2018 10:07:51 +0000 (10:07 +0000)]
Revert r328386 "[X86] Fix Windows `i1 zeroext` conventions to use i8 instead of i32"
This broke Chromium (see crbug.com/825748). It looks like mstorsjo's follow-up
patch at D44876 fixes this, but let's revert back to green for now until that's
ready to land.
(Also reverts r328443.)
> Both GCC and MSVC only look at the low byte of a boolean when it is
> passed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328482
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Benjamin Kramer [Mon, 26 Mar 2018 09:44:24 +0000 (09:44 +0000)]
[DeadArgElim] Strip allocsize attributes when deleting an argument.
Since allocsize refers to the argument number it gets invalidated when
an argument is removed and the numbers shift.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328481
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Sam Parker [Mon, 26 Mar 2018 09:29:42 +0000 (09:29 +0000)]
[IRCE] Enable increasing loops of variable bounds
CanBeMin is currently used which will report true for any unknown
values, but often a check is performed outside the loop which covers
this situation:
for (int i = 0; i < N; ++i)
...
if (N > 0)
for (int i = 0; i < N; ++i)
...
So I've add 'LoopGuardedAgainstMin' which reports whether N is
greater than the minimum value which then allows loop with a variable
loop count to be optimised. I've also moved the increasing bound
checking into its own function and replaced SumCanReachMax is another
isLoopEntryGuardedByCond function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328480
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Martin Storsjo [Mon, 26 Mar 2018 08:41:10 +0000 (08:41 +0000)]
[ARM] Simplify constructing the ARMArchFeature string. NFC.
Differential Revision: https://reviews.llvm.org/D44819
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328478
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Craig Topper [Mon, 26 Mar 2018 05:05:12 +0000 (05:05 +0000)]
[X86] Fix the SchedRW for intrinsic register form of SQRT/RCP/RSQRT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328474
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Craig Topper [Mon, 26 Mar 2018 05:05:10 +0000 (05:05 +0000)]
[X86] Merge the SSE and AVX versions of fp divs and sqrts in the SandyBridge/Haswell/Broadwell/Skylake scheduler models.
I've used Agner's data as best I could to get the values to converge on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328473
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Craig Topper [Mon, 26 Mar 2018 04:20:36 +0000 (04:20 +0000)]
[X86] Add itinerary to intrinsic version of sqrtss, rcpss, and rsqrtss instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328472
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Craig Topper [Mon, 26 Mar 2018 02:17:15 +0000 (02:17 +0000)]
[X86] Correct the itineraries for the dot production instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328471
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Craig Topper [Mon, 26 Mar 2018 02:17:14 +0000 (02:17 +0000)]
[X86] Use the same itinerary for VCVTDQ2PD as the SSE version so that the generated scheduler classes will merge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328470
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Craig Topper [Mon, 26 Mar 2018 02:17:13 +0000 (02:17 +0000)]
[X86] Swap the itineraries on the memory and register forms of CVTDQ2PD.
They were backwards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328469
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Craig Topper [Mon, 26 Mar 2018 02:17:12 +0000 (02:17 +0000)]
[X86] Give VMOVSX/ZX the same itinerary as the SSE version so they'll reuse the same generated scheduler class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328468
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Craig Topper [Sun, 25 Mar 2018 23:52:06 +0000 (23:52 +0000)]
[X86] Give vpmsadbw the same itinerary as the SSE version so they'll be able to share the same generated scheduler class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328466
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Craig Topper [Sun, 25 Mar 2018 23:40:56 +0000 (23:40 +0000)]
[X86] Move (v)movss to port 5 only for Skylake. Move (v)movups/d to port 015 for Skylake.
This matches Agner's data and is consistent with what the EVEX instructions were doing on SKX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328465
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Erik Pilkington [Sun, 25 Mar 2018 22:50:33 +0000 (22:50 +0000)]
[demangler] Use a back-patching scheme to resolve forward references.
Strictly in a conversion operator's type, a <template-param> refers to a
<template-arg> that is further ahead in the mangled name. Instead of
doing a second parse to resolve these, introduce a
ForwardTemplateReference Node and back-patch the referenced
<template-arg> when we're in the right context.
This is also a correctness fix, previously we would only do a second
parse if the <template-param> was out of bounds in the current set of
<template-args>. This lead to misdemangles (gasp!) when the conversion
operator was a member of a templated struct, for instance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328464
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Erik Pilkington [Sun, 25 Mar 2018 22:49:57 +0000 (22:49 +0000)]
[demangler] Tweak how parameter pack sizes are determined.
Rather than eagerly propagating up parameter pack sizes in Node ctors,
find the parameter pack size during printing. This is being done to
support back-patching forward referencing <template-param>s.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328463
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Erik Pilkington [Sun, 25 Mar 2018 22:49:16 +0000 (22:49 +0000)]
[demangler] Support for clang's enable_if attribute.
Fixes PR33569.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328462
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Sanjay Patel [Sun, 25 Mar 2018 21:16:33 +0000 (21:16 +0000)]
[PatternMatch] allow undef elements when matching vector FP +0.0
This continues the FP constant pattern matching improvements from:
https://reviews.llvm.org/rL327627
https://reviews.llvm.org/rL327339
https://reviews.llvm.org/rL327307
Several integer constant matchers also have this ability. I'm
separating matching of integer/pointer null from FP positive zero
and renaming/commenting to make the functionality clearer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328461
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Simon Pilgrim [Sun, 25 Mar 2018 20:16:53 +0000 (20:16 +0000)]
[X86] Use WriteResPair for WriteIDiv to cleanup sched defs. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328460
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Simon Pilgrim [Sun, 25 Mar 2018 19:20:08 +0000 (19:20 +0000)]
[SchedModel] Remove instregex entries that don't match any instructions
This patch throws a fatal error if an instregex entry doesn't actually match any instructions. This is part of the work to reduce the compile time impact of increased instregex usage (PR35955), although the x86 models seem to be relatively clean.
All the cases I encountered have now been fixed in trunk and this will ensure they don't get reintroduced.
Differential Revision: https://reviews.llvm.org/D44687
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328459
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Simon Pilgrim [Sun, 25 Mar 2018 19:17:17 +0000 (19:17 +0000)]
[X86][SkylakeClient] Fix missing comma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328458
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Simon Pilgrim [Sun, 25 Mar 2018 19:07:17 +0000 (19:07 +0000)]
[ARM] Remove sched model instregex entries that don't match any instructions (D44687)
Reviewed by @javed.absar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328457
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Simon Pilgrim [Sun, 25 Mar 2018 18:49:48 +0000 (18:49 +0000)]
[X86] Add missing full stop to comment. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328456
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Sanjay Patel [Sun, 25 Mar 2018 17:48:20 +0000 (17:48 +0000)]
[InstSimplify, InstCombine] add/update tests with FP +0.0 vector with undef; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328455
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Craig Topper [Sun, 25 Mar 2018 17:33:14 +0000 (17:33 +0000)]
[X86][SkylakeClient] Fix a set of regular expressions that were checking for optionally starting with 'Y' instead of 'V'
These bad regexs were introduced by r328435
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328454
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Simon Pilgrim [Sun, 25 Mar 2018 17:28:06 +0000 (17:28 +0000)]
[X86][MMX] MOVQ2DQ/MOVDQ2Q are better described as WriteVecMove than WriteMove
Not that it makes a difference to current cost values, but will when we try to better model GPR-SIMD transfer costs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328453
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Simon Pilgrim [Sun, 25 Mar 2018 17:25:37 +0000 (17:25 +0000)]
[X86][SkylakeServer] Merge multiple instregex. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328452
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Craig Topper [Sun, 25 Mar 2018 15:58:12 +0000 (15:58 +0000)]
[X86] Update cost model for Goldmont. Add fsqrt costs for Silvermont
Add fdiv costs for Goldmont using table 16-17 of the Intel Optimization Manual. Also add overrides for FSQRT for Goldmont and Silvermont.
Reviewers: RKSimon
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44644
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328451
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Sanjay Patel [Sun, 25 Mar 2018 14:24:32 +0000 (14:24 +0000)]
[InstCombine] adjust test comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328450
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Sanjay Patel [Sun, 25 Mar 2018 14:19:25 +0000 (14:19 +0000)]
[InstCombine] consolidate casted icmp vector tests
We have thorough coverage of predicates and scalar types,
so we just need a sampling of vector tests to show that
things are working or not with vectors types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328449
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Sanjay Patel [Sun, 25 Mar 2018 14:01:42 +0000 (14:01 +0000)]
[InstCombine] peek through more icmp of FP cast + bitcast
This is an extension of rL328426 as noted in D44367.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328448
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Simon Pilgrim [Sun, 25 Mar 2018 10:21:19 +0000 (10:21 +0000)]
[X86] Add the ability to override memory folding latency to schedules and add 1uop for memory folds for Intel models
The Intel models need an extra 1uop for memory folded instructions, plus a lot of instructions take a non-default memory latency which should allow us to use the multiclass a lot more to tidy things up.
Differential Revision: https://reviews.llvm.org/D44840
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328446
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Craig Topper [Sun, 25 Mar 2018 01:28:43 +0000 (01:28 +0000)]
[X86] Consistently prefix all defs in X86ScheduleSLM.td with 'SLM'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328444
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Martin Storsjo [Sat, 24 Mar 2018 23:00:00 +0000 (23:00 +0000)]
[X86] Update a partially stale comment, since SVN r328386. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328443
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Craig Topper [Sat, 24 Mar 2018 22:58:03 +0000 (22:58 +0000)]
[SchedModel] Remove an unneeded temporary vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328442
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Craig Topper [Sat, 24 Mar 2018 22:58:02 +0000 (22:58 +0000)]
[SchedModel] Use std::move in a couple places to reduce copying
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328441
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Craig Topper [Sat, 24 Mar 2018 22:58:00 +0000 (22:58 +0000)]
[SchedModel] Use std::move to replace a vector instead of vector::swap
We don't really care about the old vector value so we don't care to swap it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328440
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Eric Fiselier [Sat, 24 Mar 2018 22:14:02 +0000 (22:14 +0000)]
Fix module.modulemap after r328395
This patch removes the MachineValueType module since the
header was removed in r328395.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328439
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Craig Topper [Sat, 24 Mar 2018 21:57:35 +0000 (21:57 +0000)]
[SchedModel] Remove std::vectors that were created with 1 element and then passed to an ArrayRef parameter.
ArrayRef can capture a single element. We don't need a vector for that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328438
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Simon Pilgrim [Sat, 24 Mar 2018 21:22:32 +0000 (21:22 +0000)]
[SchedModel] Record::getName() returns StringRef - avoid std::string creation. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328437
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Simon Pilgrim [Sat, 24 Mar 2018 21:04:20 +0000 (21:04 +0000)]
[SchedModel] Avoid std::string creation for instregex patterns that don't contain regex metas. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328436
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Simon Pilgrim [Sat, 24 Mar 2018 20:40:14 +0000 (20:40 +0000)]
[X86][SkylakeClient] Merge xmm/ymm instructions instregex entries to reduce regex matches to reduce compile time
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328435
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Simon Pilgrim [Sat, 24 Mar 2018 19:37:28 +0000 (19:37 +0000)]
[X86][Broadwell] Merge xmm/ymm instructions instregex entries to reduce regex matches to reduce compile time
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328434
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Mandeep Singh Grang [Sat, 24 Mar 2018 18:37:19 +0000 (18:37 +0000)]
[RISCV] Use init_array instead of ctors for RISCV target, by default
Summary:
LLVM defaults to the newer .init_array/.fini_array scheme for static
constructors rather than the less desirable .ctors/.dtors (the UseCtors
flag defaults to false). This wasn't being respected in the RISC-V
backend because it fails to call TargetLoweringObjectFileELF::InitializeELF with the the appropriate
flag for UseInitArray.
This patch fixes this by implementing RISCVELFTargetObjectFile and overriding its Initialize method to call
InitializeELF(TM.Options.UseInitArray).
Reviewers: asb, apazos
Reviewed By: asb
Subscribers: mgorny, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, llvm-commits
Differential Revision: https://reviews.llvm.org/D44750
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328433
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Simon Pilgrim [Sat, 24 Mar 2018 18:36:01 +0000 (18:36 +0000)]
[X86][Haswell] Merge xmm/ymm instructions instregex entries to reduce regex matches to reduce compile time
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328432
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Simon Pilgrim [Sat, 24 Mar 2018 18:12:59 +0000 (18:12 +0000)]
[X86][SandyBridge] Merge xmm/ymm instructions instregex entries to reduce regex matches to reduce compile time
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328431
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Mandeep Singh Grang [Sat, 24 Mar 2018 17:34:37 +0000 (17:34 +0000)]
[Hexagon] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer the comments section in D44363 for a list of all the required patches.
Reviewers: kparzysz
Reviewed By: kparzysz
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44857
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328430
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Mandeep Singh Grang [Sat, 24 Mar 2018 17:15:04 +0000 (17:15 +0000)]
[AMDGPU] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Reviewers: tstellar, RKSimon, arsenm
Reviewed By: arsenm
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D44856
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328429
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Andrea Di Biagio [Sat, 24 Mar 2018 16:05:36 +0000 (16:05 +0000)]
[llvm-mca] run clang-format on all files.
This also addresses Simon's review comment in D44839.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328428
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Andrea Di Biagio [Sat, 24 Mar 2018 15:48:25 +0000 (15:48 +0000)]
[llvm-mca] Remove unused field in InstrBuilder. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328427
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Sanjay Patel [Sat, 24 Mar 2018 15:45:02 +0000 (15:45 +0000)]
[InstCombine] peek through FP casts for sign-bit compares (PR36682)
This pattern came up in PR36682:
https://bugs.llvm.org/show_bug.cgi?id=36682
https://godbolt.org/g/LhuD9A
Equality checks are planned as a follow-up enhancement.
Differential Revision: https://reviews.llvm.org/D44367
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328426
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Sanjay Patel [Sat, 24 Mar 2018 15:41:59 +0000 (15:41 +0000)]
[InstCombine] fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328425
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Simon Pilgrim [Sat, 24 Mar 2018 15:05:12 +0000 (15:05 +0000)]
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets
Add skylake server tests as well
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328424
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Simon Pilgrim [Sat, 24 Mar 2018 14:51:52 +0000 (14:51 +0000)]
[X86][SSE] Ensure we're testing both non-VEX/VEX variants of SSE instructions on AVX targets
And ensure we don't use later instruction sets in SSE schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328423
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Sanjay Patel [Sat, 24 Mar 2018 14:45:41 +0000 (14:45 +0000)]
[InstCombine] add multi-use/vector tests for intrinsic shrinking; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328422
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Simon Pilgrim [Sat, 24 Mar 2018 13:47:48 +0000 (13:47 +0000)]
[X86][AVX1] Ensure we don't use later instruction sets in AVX1 schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328421
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Simon Pilgrim [Sat, 24 Mar 2018 13:47:01 +0000 (13:47 +0000)]
[X86][AVX2] Ensure we don't use later instruction sets in AVX2 schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328420
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Craig Topper [Sat, 24 Mar 2018 07:48:54 +0000 (07:48 +0000)]
[X86] Add a new disassembler opcode map for 3DNow. Stop treating 3DNow as an attribute.
This reduces the size of llvm-mc by at least 150k since we no longer have to multiply the attribute across 7 tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328416
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Craig Topper [Sat, 24 Mar 2018 07:15:47 +0000 (07:15 +0000)]
[X86] Use unique_ptr to simplify memory management. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328413
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Craig Topper [Sat, 24 Mar 2018 07:15:46 +0000 (07:15 +0000)]
[X86] Use X86_INSTR_MRM_MAPPING macro instead of listing all MRM_C0-MRM_FF format encodings. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328412
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Craig Topper [Sat, 24 Mar 2018 07:15:45 +0000 (07:15 +0000)]
[X86] Remove an unnecessary switch around two other switches. NFC
The outer switch only had one valid block so didn't provide any value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328411
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Craig Topper [Sat, 24 Mar 2018 06:04:12 +0000 (06:04 +0000)]
[X86] Merge the Has3DNow0F0FOpcode TSFlag into the OpMap encoding. NFC
The 3DNow instructions are encoded a little weird, but we can still represent it as an opcode map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328410
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Eric Christopher [Sat, 24 Mar 2018 02:56:58 +0000 (02:56 +0000)]
Add REQUIRES lines for the targets being checked in this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328408
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Craig Topper [Sat, 24 Mar 2018 01:52:01 +0000 (01:52 +0000)]
[X86] Add a DAG combine to simplify PMULDQ/PMULUDQ nodes
These nodes only use the lower 32 bits of their inputs so we can use SimplifyDemandedBits to simplify them.
Differential Revision: https://reviews.llvm.org/D44375
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328405
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Eric Christopher [Sat, 24 Mar 2018 00:07:38 +0000 (00:07 +0000)]
Allow FDE references outside the +/-2GB range supported by PC relative
offsets for code models other than small/medium. For JIT application,
memory layout is less controlled and can result in truncations
otherwise.
Patch based on one by Olexa Bilaniuk!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328400
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David Blaikie [Sat, 24 Mar 2018 00:06:14 +0000 (00:06 +0000)]
Remove unused header from EntryExitInstrumenter
Fixes layering, since Transforms/Utils doesn't depend on CodeGen, so
shouldn't include headers from it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328399
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Craig Topper [Sat, 24 Mar 2018 00:02:46 +0000 (00:02 +0000)]
[X86] Correct the value AdSizeX in X86II enum. NFC
Should be NFC since nothing used the enum value. The instruction descriptions are generated from tablegen which had the correct value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328398
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David Blaikie [Fri, 23 Mar 2018 23:58:31 +0000 (23:58 +0000)]
Fix layering by moving ValueTypes.h from CodeGen to IR
ValueTypes.h is implemented in IR already.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328397
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David Blaikie [Fri, 23 Mar 2018 23:58:27 +0000 (23:58 +0000)]
Fix layering of CodeGen/TargetOpcodes.def by moving it to Support
It's also used by utils/TableGen so needs to reside somewhere common to
TableGen and CodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328396
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David Blaikie [Fri, 23 Mar 2018 23:58:25 +0000 (23:58 +0000)]
Fix layering of MachineValueType.h by moving it from CodeGen to Support
This is used by llvm tblgen as well as by LLVM Targets, so the only
common place is Support for now. (maybe we need another target for these
sorts of things - but for now I'm at least making them correct & we can
make them better if/when people have strong feelings)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328395
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David Blaikie [Fri, 23 Mar 2018 23:58:21 +0000 (23:58 +0000)]
Fix layering by moving Support/CodeGenCWrappers.h to Target
This includes llvm-c/TargetMachine.h which is logically part of
libTarget (since libTarget implements llvm-c/TargetMachine.h's
functions).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328394
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David Blaikie [Fri, 23 Mar 2018 23:58:20 +0000 (23:58 +0000)]
Fix layering by moving X86DisassemblerDecoderCommon to Support
This is used from llvm tblgen and the X86Disassembler - the only common
library (apart from TableGen, which probably doesn't make sense to have
as a dependency from a release tool (rather than a use-while-building-llvm
tool) of LLVM)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328393
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David Blaikie [Fri, 23 Mar 2018 23:58:19 +0000 (23:58 +0000)]
Move TargetLoweringObjectFile from CodeGen to Target to fix layering
It's implemented in Target & include from other Target headers, so the
header should be in Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328392
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Philip Reames [Fri, 23 Mar 2018 23:41:47 +0000 (23:41 +0000)]
[GuardWidening] Group code by class [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328387
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Reid Kleckner [Fri, 23 Mar 2018 23:38:53 +0000 (23:38 +0000)]
[X86] Fix Windows `i1 zeroext` conventions to use i8 instead of i32
Both GCC and MSVC only look at the low byte of a boolean when it is
passed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328386
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David Blaikie [Fri, 23 Mar 2018 22:11:06 +0000 (22:11 +0000)]
Fix Layering, move instrumentation transform headers into Instrumentation subdirectory
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328379
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Fedor Sergeev [Fri, 23 Mar 2018 21:46:16 +0000 (21:46 +0000)]
[PM][FunctionAttrs] add NoUnwind attribute inference to PostOrderFunctionAttrs pass
Summary:
This was motivated by absence of PrunEH functionality in new PM.
It was decided that a proper way to do PruneEH is to add NoUnwind inference
into PostOrderFunctionAttrs and then perform normal SimplifyCFG on top.
This change generalizes attribute handling implemented for (a removal of)
Convergent attribute, by introducing a generic builder-like class
AttributeInferer
It registers all the attribute inference requests, storing per-attribute
predicates into a vector, and then goes through an SCC Node, scanning all
the instructions for not breaking attribute assumptions.
The main idea is that as soon all the instructions from all the functions
of SCC Node conform to attribute assumptions then we are free to infer
the attribute as set for all the functions of SCC Node.
It handles two distinct cases of attributes:
- those that might break due to derefinement of the function code
for these attributes we are allowed to apply inference only if all the
functions are "exact definitions". Example - NoUnwind.
- those that do not care about derefinement
for these attributes we are allowed to apply inference as soon as we see
any function definition. Example - removal of Convergent attribute.
Also in this commit:
* Converted all the FunctionAttrs tests to use FileCheck and added new-PM
invocations to them
* FunctionAttrs/convergent.ll test demonstrates a difference in behavior between
new and old PM implementations. Marked with FIXME.
* PruneEH tests were converted to new-PM as well, using function-attrs+simplify-cfg
combo as intended
* some of "other" tests were updated since function-attrs now infers 'nounwind'
even for old PM pipeline
* -disable-nounwind-inference hidden option added as a possible workaround for a supposedly
rare case when nounwind being inferred by default presents a problem
Reviewers: chandlerc, jlebar
Reviewed By: jlebar
Subscribers: eraman, llvm-commits
Differential Revision: https://reviews.llvm.org/D44415
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328377
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Sanjay Patel [Fri, 23 Mar 2018 21:18:12 +0000 (21:18 +0000)]
[InstCombine] simplify code for FP intrinsic shrinking; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328372
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Sanjay Patel [Fri, 23 Mar 2018 21:13:53 +0000 (21:13 +0000)]
[InstCombine] increase test coverage for intrinsic shrinking; NFC
There were no tests with vector types before this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328371
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Krzysztof Parzyszek [Fri, 23 Mar 2018 20:43:02 +0000 (20:43 +0000)]
[Hexagon] Make findLoopInstr member of HexagonInstrInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328367
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Krzysztof Parzyszek [Fri, 23 Mar 2018 20:41:44 +0000 (20:41 +0000)]
[Hexagon] Correct update of instruction offet in HW loop fixup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328366
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Krzysztof Parzyszek [Fri, 23 Mar 2018 20:11:00 +0000 (20:11 +0000)]
[Hexagon] Boost profit for word-mask immediates, reduce for others
This avoids unnecessary splitting due to uninteresting immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328364
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Zachary Turner [Fri, 23 Mar 2018 19:57:25 +0000 (19:57 +0000)]
[PDB] Resubmit "Support embedding natvis files in PDBs."
This was reverted several times due to what ultimately turned out
to be incompatibilities in our serialized hash table format.
Several changes went in prior to this to fix those issues since
they were more fundamental and independent of supporting injected
sources, so now that those are fixed this change should hopefully
pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328363
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Krzysztof Parzyszek [Fri, 23 Mar 2018 19:47:13 +0000 (19:47 +0000)]
[Hexagon] Assume all extendable branches to be of size 8 in relaxation
The branch relaxation pass collects sizes of all instructions at the
beginning, before any changes have been made. It then performs one pass
over all branches to see which ones need to be extended. It does not
account for the case when a previously valid branch becomes out-of-range
due to relaxing other branches.
This approach fixes this problem by assuming from the beginning that
all extendable branches have been extended. This may cause unneeded
relaxation in some cases, but avoids iteration and recomputing instruction
sizes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328360
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Andrea Di Biagio [Fri, 23 Mar 2018 19:40:04 +0000 (19:40 +0000)]
[llvm-mca] Split the InstructionInfoView from the SummaryView.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328358
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