OSDN Git Service
Richard Henderson [Mon, 11 Jan 2021 23:57:39 +0000 (13:57 -1000)]
target/arm: Add cpu properties to control pauth
The crypto overhead of emulating pauth can be significant for
some workloads. Add two boolean properties that allows the
feature to be turned off, on with the architected algorithm,
or on with an implementation defined algorithm.
We need two intermediate booleans to control the state while
parsing properties lest we clobber ID_AA64ISAR1 into an invalid
intermediate state.
Tested-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210111235740.462469-3-richard.henderson@linaro.org
[PMM: fixed docs typo, tweaked text to clarify that the impdef
algorithm is specific to QEMU]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Mon, 11 Jan 2021 23:57:38 +0000 (13:57 -1000)]
target/arm: Implement an IMPDEF pauth algorithm
Without hardware acceleration, a cryptographically strong
algorithm is too expensive for pauth_computepac.
Even with hardware accel, we are not currently expecting
to link the linux-user binaries to any crypto libraries,
and doing so would generally make the --static build fail.
So choose XXH64 as a reasonably quick and decent hash.
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20210111235740.462469-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Tue, 19 Jan 2021 11:57:07 +0000 (11:57 +0000)]
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging
* Refactor next-cube interrupt and register handling into a proper QOM device
# gpg: Signature made Tue 19 Jan 2021 08:15:39 GMT
# gpg: using RSA key
27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "huth@tuxfamily.org"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* remotes/huth-gitlab/tags/pull-request-2021-01-19:
hw/m68k/next-cube: Add missing header comment to next-cube.h
hw/m68k/next-cube: Add vmstate for NeXTPC device
hw/m68k/next-cube: Remove unused fields from NeXTState
hw/m68k/next-cube: Move rtc into NeXTPC struct
hw/m68k/next-cube: Make next_irq GPIO inputs to NEXT_PC device
hw/m68k/next-cube: Move int_status and int_mask to NeXTPC struct
hw/m68k/next-cube: Make next_irq take NeXTPC* as its opaque
hw/m68k/next-cube: Move scr_ops into NeXTPC device
hw/m68k/next-cube: Move mmio_ops into NeXTPC device
hw/m68k/next-cube: Move register/interrupt functionality into a device
hw/m68k/next-cube: Make next_irq() function static
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Tue, 19 Jan 2021 10:00:22 +0000 (10:00 +0000)]
Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.0-
20210119' into staging
ppc patch queue 2021-01-19
Next pull request for qemu-6.0. Not a huge amount here, but it does
have some important fixes from Greg Kurz. Includes:
* A number of minor cleanups from Daniel Barboza (preliminaries for
some hotplug changes that are still under review)
* Improved handling of memory hotplug from Greg Kurz
* A number of fixes for sam460ex and other 440 based platforms from
Zolan Balaton
* Some fixes for the QOMification of the PPC 4xx UIC interrupt
controller from Peter Maydell
# gpg: Signature made Tue 19 Jan 2021 06:22:45 GMT
# gpg: using RSA key
75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full]
# gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full]
# gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full]
# gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dg-gitlab/tags/ppc-for-6.0-
20210119:
spapr_cpu_core.c: use g_auto* in spapr_create_vcpu()
spapr_rtas.c: fix identation of rtas_ibm_suspend_me() args
spapr_hcall.c: make do_client_architecture_support static
spapr.h: fix trailing whitespace in phb_placement
spapr: Improve handling of memory unplug with old guests
sam460ex: Use type cast macro instead of simple cast
Revert "ppc4xx: Move common dependency on serial to common option"
Revert "sam460ex: Remove FDT_PPC dependency from KConfig"
hw/ppc: Remove unused ppcuic_init()
hw/ppc/ppc405_uc: Drop use of ppcuic_init()
hw/intc/ppc-uic: Make default dcr-base 0xc0, not 0x30
hw/ppc: Delete unused ppc405cr_init() code
hw/ppc/sam460ex: Drop use of ppcuic_init()
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Fri, 15 Jan 2021 20:12:06 +0000 (20:12 +0000)]
hw/m68k/next-cube: Add missing header comment to next-cube.h
The next-cube.h file is missing the usual copyright-and-license
header; add it (same as the next-cube.c one).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20210115201206.17347-12-peter.maydell@linaro.org>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Peter Maydell [Fri, 15 Jan 2021 20:12:05 +0000 (20:12 +0000)]
hw/m68k/next-cube: Add vmstate for NeXTPC device
Add the vmstate for the new NeXTPC devic; this is in theory
a migration compatibility break, but this machine doesn't have
working migration currently anyway.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20210115201206.17347-11-peter.maydell@linaro.org>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Peter Maydell [Fri, 15 Jan 2021 20:12:04 +0000 (20:12 +0000)]
hw/m68k/next-cube: Remove unused fields from NeXTState
The fields scsi_irq, scsi_dma, scsi_reset and fd_irq in
NeXTState are all unused, except in commented out
"this should do something like this" code. Remove the
unused fields. As and when the functionality that might
use them is added, we can put in the correct kind of
wiring (which might or might not need to be a qemu_irq,
but which in any case will need to be in the NeXTPC
device, not in NeXTState).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20210115201206.17347-10-peter.maydell@linaro.org>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Peter Maydell [Fri, 15 Jan 2021 20:12:03 +0000 (20:12 +0000)]
hw/m68k/next-cube: Move rtc into NeXTPC struct
Move the rtc into the NeXTPC struct. Since this is the last
use of the 'backdoor' NextState pointer we can now remove that.
Probably the RTC should be its own device at some point: in hardware
there is a separate MCS1850 RTC chip connected to the Peripheral
Controller via a 1-bit serial interface. That goes beyond the remit
of the current refactoring, though.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20210115201206.17347-9-peter.maydell@linaro.org>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Peter Maydell [Fri, 15 Jan 2021 20:12:02 +0000 (20:12 +0000)]
hw/m68k/next-cube: Make next_irq GPIO inputs to NEXT_PC device
Make the next_irq function be GPIO inputs to the NEXT_PC
device, rather than a freestanding set of qemu_irq lines.
This fixes a minor Coverity issue where it correctly points
out the trivial memory leak of the memory allocated in the
call to qemu_allocate_irqs().
Fixes: CID
1421962
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20210115201206.17347-8-peter.maydell@linaro.org>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Peter Maydell [Fri, 15 Jan 2021 20:12:01 +0000 (20:12 +0000)]
hw/m68k/next-cube: Move int_status and int_mask to NeXTPC struct
All the code which accesses int_status and int_mask is now doing
so via the NeXTPC->NeXTState indirection, so we can move these
fields into the NeXTPC struct where they belong.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20210115201206.17347-7-peter.maydell@linaro.org>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Peter Maydell [Fri, 15 Jan 2021 20:12:00 +0000 (20:12 +0000)]
hw/m68k/next-cube: Make next_irq take NeXTPC* as its opaque
Make the next_irq function take a NeXTPC* as its opaque rather than
the M68kCPU*. This will make it simpler to turn the next_irq
function into a gpio input line of the NeXTPC device in the next
commit.
For this to work we have to pass the CPU to the NeXTPC device via a
link property, in the same way we do in q800.c (and for the same
reason).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20210115201206.17347-6-peter.maydell@linaro.org>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Peter Maydell [Fri, 15 Jan 2021 20:11:59 +0000 (20:11 +0000)]
hw/m68k/next-cube: Move scr_ops into NeXTPC device
Move the registers handled by the scr_ops struct into the NeXTPC
device.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20210115201206.17347-5-peter.maydell@linaro.org>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Peter Maydell [Fri, 15 Jan 2021 20:11:58 +0000 (20:11 +0000)]
hw/m68k/next-cube: Move mmio_ops into NeXTPC device
Move the registers handled by the mmio_ops struct into the NeXTPC
device. This allows us to also move the scr1 and scr2 data fields.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20210115201206.17347-4-peter.maydell@linaro.org>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Peter Maydell [Fri, 15 Jan 2021 20:11:57 +0000 (20:11 +0000)]
hw/m68k/next-cube: Move register/interrupt functionality into a device
Currently the next-cube board code open-codes a lot of handling of
interrupts and some miscellaneous registers. Move this into a proper
QOM device.
In the real hardware this functionality seems to be the
responsibility of the Peripheral Controller (PC) chip, so name the
device that.
There are several different things that will need to be moved into
this device:
* the mmio_iops register set
* the scr_ops register set
* the next_irq IRQ handling
To ease review, we structure the change as a sequence of commits: in
this first commit we create the skeleton of the NeXTPC device with no
content, but with a backdoor pointer to the NeXTState machine's state
struct so we can move parts of the code and still have refactored and
non-refactored code using the same struct data fields. Further
commits will move functionality into the new device piece by piece.
At the end we will be able to remove the backdoor pointer because all
the data fields will be in the NeXTPC struct and not the NeXTState
struct.
We'll add the VMState for the new device at the end of all that; this
is in theory a migration compatibility break but this machine does
not currently support migration at all anyway.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20210115201206.17347-3-peter.maydell@linaro.org>
[huth: Add a comment in front of struct NeXTPC]
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Peter Maydell [Fri, 15 Jan 2021 20:11:56 +0000 (20:11 +0000)]
hw/m68k/next-cube: Make next_irq() function static
The next_irq() function is global, but isn't actually used anywhere
outside next-cube.c. Make it static.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20210115201206.17347-2-peter.maydell@linaro.org>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Daniel Henrique Barboza [Thu, 14 Jan 2021 18:06:26 +0000 (15:06 -0300)]
spapr_cpu_core.c: use g_auto* in spapr_create_vcpu()
Use g_autoptr() with Object and g_autofree with the string to
avoid the need of a cleanup path.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <
20210114180628.
1675603-6-danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Daniel Henrique Barboza [Thu, 14 Jan 2021 18:06:25 +0000 (15:06 -0300)]
spapr_rtas.c: fix identation of rtas_ibm_suspend_me() args
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <
20210114180628.
1675603-5-danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Daniel Henrique Barboza [Thu, 14 Jan 2021 18:06:23 +0000 (15:06 -0300)]
spapr_hcall.c: make do_client_architecture_support static
The function is called only inside spapr_hcall.c.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <
20210114180628.
1675603-3-danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Daniel Henrique Barboza [Thu, 14 Jan 2021 18:06:22 +0000 (15:06 -0300)]
spapr.h: fix trailing whitespace in phb_placement
This whitespace was messing with lots of diffs if you happen
to use an editor that eliminates trailing whitespaces on file
save.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <
20210114180628.
1675603-2-danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Greg Kurz [Fri, 8 Jan 2021 17:31:27 +0000 (18:31 +0100)]
spapr: Improve handling of memory unplug with old guests
Since commit
1e8b5b1aa16b ("spapr: Allow memory unplug to always succeed")
trying to unplug memory from a guest that doesn't support it (eg. rhel6)
no longer generates an error like it used to. Instead, it leaves the
memory around : only a subsequent reboot or manual use of drmgr within
the guest can complete the hot-unplug sequence. A flag was added to
SpaprMachineClass so that this new behavior only applies to the default
machine type.
We can do better. CAS processes all pending hot-unplug requests. This
means that we don't really care about what the guest supports if
the hot-unplug request happens before CAS.
All guests that we care for, even old ones, set enough bits in OV5
that lead to a non-empty bitmap in spapr->ov5_cas. Use that as a
heuristic to decide if CAS has already occured or not.
Always accept unplug requests that happen before CAS since CAS will
process them. Restore the previous behavior of rejecting them after
CAS when we know that the guest doesn't support memory hot-unplug.
This behavior is suitable for all machine types : this allows to
drop the pre_6_0_memory_unplug flag.
Fixes:
1e8b5b1aa16b ("spapr: Allow memory unplug to always succeed")
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <
161012708715.801107.
11418801796987916516.stgit@bahia.lan>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
BALATON Zoltan [Fri, 8 Jan 2021 22:07:38 +0000 (23:07 +0100)]
sam460ex: Use type cast macro instead of simple cast
Use the PCI_BUS type cast macro to convert result of qdev_get_child_bus().
Also remove the check for NULL afterwards which should not be needed
because sysbus_create_simple() uses error_abort and we create the PCI
host object here that's expected to have a PCI bus so this shouldn't
fail. Even if it would fail that would be due to a programmer error so
an error message is not necessary.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <
a4dc55b56eed3ce899b7bf9835b980a114c52598.
1610143658.git.balaton@eik.bme.hu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
BALATON Zoltan [Fri, 8 Jan 2021 22:07:38 +0000 (23:07 +0100)]
Revert "ppc4xx: Move common dependency on serial to common option"
This reverts commit
e6d5106786 which was added mistakenly. While this
change works it was suggested during review that keeping dependencies
explicit for each board may be better than listing them in a common
option so keep the previous version and revert this change.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <
8c65807fc7dc1c4c4f6320f2fd6409a3091c88ff.
1610143658.git.balaton@eik.bme.hu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
BALATON Zoltan [Fri, 8 Jan 2021 22:07:38 +0000 (23:07 +0100)]
Revert "sam460ex: Remove FDT_PPC dependency from KConfig"
This reverts commit
038da2adf that was mistakenly added, this
dependency is still needed to get libfdt dependencies even if fdt.o is
not needed by sam460ex.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <
15a9fa72eed4f02bdbeaef206803d5e22260e2de.
1610143658.git.balaton@eik.bme.hu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Peter Maydell [Fri, 8 Jan 2021 17:12:12 +0000 (17:12 +0000)]
hw/ppc: Remove unused ppcuic_init()
Now we've converted all the callsites to directly create the QOM UIC
device themselves, the ppcuic_init() function is unused and can be
removed. The enum defining PPCUIC symbolic constants can be moved
to the ppc-uic.h header where it more naturally belongs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-Id: <
20210108171212.16500-5-peter.maydell@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Peter Maydell [Fri, 8 Jan 2021 17:12:11 +0000 (17:12 +0000)]
hw/ppc/ppc405_uc: Drop use of ppcuic_init()
Switch the ppc405_uc boards to directly creating and configuring the
UIC, rather than doing it via the old ppcuic_init() helper function.
We retain the API feature of ppc405ep_init() where it passes back
something allowing the callers to wire up devices to the UIC if
they need to, even though neither of the callsites currently makes
use of this ability -- instead of passing back the qemu_irq array
we pass back the UIC DeviceState.
This fixes a trivial Coverity-detected memory leak where
we were leaking the array of IRQs returned by ppcuic_init().
Fixes: Coverity CID
1421922
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20210108171212.16500-4-peter.maydell@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Peter Maydell [Mon, 11 Jan 2021 21:30:07 +0000 (21:30 +0000)]
hw/intc/ppc-uic: Make default dcr-base 0xc0, not 0x30
In commit
34d0831f38fd8 the ppc-uic device was added, with a dcr-base
property. The intention was that the default value of dcr-base should be
the one that most of our boards need, so that in the common case they
don't need to specify a property value.
All QEMU boards with a UIC use a dcr-base of 0xc0, with the exception of
sam460ex which has four UICs and so puts them at 0xc0, 0xd0, 0xe0, 0xf0.
So 0xc0 is the obvious right choice for the default dcr-base.
The board code conversions in commits
0270d74ef88623505 (bamboo) and
c5ac9dc64fa552a6 (virtex_ml507) assumed that default was 0xc0. Unfortunately
the actual default in
34d0831f38fd8 was 0x30, by mistake, so the
bamboo and virtex_ml507 boards were broken as they were converted
away from ppcuic_init() (which always specifies the dcr_base property
value explicitly).
Set the default dcr-base to 0xc0 as was intended, fixing bamboo and
virtex_ml507.
Fixes:
34d0831f38fd8
Reported-by: Nathan Chancellor <natechancellor@gmail.com>
Suggested-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20210111213007.7381-1-peter.maydell@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Peter Maydell [Fri, 8 Jan 2021 17:12:10 +0000 (17:12 +0000)]
hw/ppc: Delete unused ppc405cr_init() code
The function ppc405cr_init() has apparently been unused since it was
added in commit
8ecc7913525ecb in 2007.
Remove this dead code, so we don't have to convert it away from using
ppcuic_init().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20210108171212.16500-3-peter.maydell@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Peter Maydell [Fri, 8 Jan 2021 17:12:09 +0000 (17:12 +0000)]
hw/ppc/sam460ex: Drop use of ppcuic_init()
Switch the sam460ex board to directly creating and configuring the
UIC, rather than doing it via the old ppcuic_init() helper function.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20210108171212.16500-2-peter.maydell@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Peter Maydell [Mon, 18 Jan 2021 15:19:06 +0000 (15:19 +0000)]
Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.0-pull-request' into staging
Trivial patches
20210118
Fix memory leaks
Use qemu_log_mask(GUEST_ERROR) rather than error_report().
# gpg: Signature made Mon 18 Jan 2021 11:31:10 GMT
# gpg: using RSA key
CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg: issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* remotes/vivier2/tags/trivial-branch-for-6.0-pull-request:
hw/ide/ahci: Replace fprintf() by qemu_log_mask(GUEST_ERROR)
misc/mos6522: Use timer_free() in the finalize function to avoid memleak
pl031: Use timer_free() in the finalize function to avoid memleaks
hw/virtio-pci: Replace error_report() by qemu_log_mask(GUEST_ERROR)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Mon, 18 Jan 2021 12:09:21 +0000 (12:09 +0000)]
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-misc-180121-2' into staging
Testing, gdbstub and semihosting patches:
- clean-ups to docker images
- drop duplicate jobs from shippable
- prettier tag generation (+gtags)
- generate browsable source tree
- more Travis->GitLab migrations
- fix checkpatch to deal with commits
- gate gdbstub tests on 8.3.1, expand tests
- support Xfer:auxv:read gdb packet
- better gdbstub cleanup
- use GDB's SVE register layout
- make arm-compat-semihosting common
- add riscv semihosting support
- add HEAPINFO, ELAPSED, TICKFREQ, TMPNAM and ISERROR to semihosting
# gpg: Signature made Mon 18 Jan 2021 10:09:11 GMT
# gpg: using RSA key
6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full]
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44
* remotes/stsquad/tags/pull-testing-and-misc-180121-2: (30 commits)
semihosting: Implement SYS_ISERROR
semihosting: Implement SYS_TMPNAM
semihosting: Implement SYS_ELAPSED and SYS_TICKFREQ
riscv: Add semihosting support for user mode
riscv: Add semihosting support
semihosting: Support SYS_HEAPINFO when env->boot_info is not set
semihosting: Change internal common-semi interfaces to use CPUState *
semihosting: Change common-semi API to be architecture-independent
semihosting: Move ARM semihosting code to shared directories
target/arm: use official org.gnu.gdb.aarch64.sve layout for registers
gdbstub: ensure we clean-up when terminated
gdbstub: drop gdbserver_cleanup in favour of gdb_exit
gdbstub: drop CPUEnv from gdb_exit()
gdbstub: add support to Xfer:auxv:read: packet
gdbstub: implement a softmmu based test
Revert "tests/tcg/multiarch/Makefile.target: Disable run-gdbstub-sha1 test"
configure: gate our use of GDB to 8.3.1 or above
test/guest-debug: echo QEMU command as well
scripts/checkpatch.pl: fix git-show invocation to include diffstat
gitlab: migrate the minimal tools and unit tests from Travis
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
# Conflicts:
# default-configs/targets/riscv32-linux-user.mak
# default-configs/targets/riscv64-linux-user.mak
Philippe Mathieu-Daudé [Tue, 12 Jan 2021 11:29:55 +0000 (12:29 +0100)]
hw/ide/ahci: Replace fprintf() by qemu_log_mask(GUEST_ERROR)
Replace fprintf() calls by qemu_log_mask(LOG_GUEST_ERROR).
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <
20210112112955.
1849212-1-philmd@redhat.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Gan Qixin [Tue, 12 Jan 2021 11:27:05 +0000 (19:27 +0800)]
misc/mos6522: Use timer_free() in the finalize function to avoid memleak
When running device-introspect-test, a memory leak occurred in the mos6522_init
function, this patch use timer_free() in the finalize function to fix it.
ASAN shows memory leak stack:
Direct leak of 96 byte(s) in 2 object(s) allocated from:
#0 0xfffd5fe9e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0)
#1 0xfffd5f7b6800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800)
#2 0xaaae50303d0c in timer_new_full qemu/include/qemu/timer.h:523
#3 0xaaae50303d0c in timer_new qemu/include/qemu/timer.h:544
#4 0xaaae50303d0c in timer_new_ns qemu/include/qemu/timer.h:562
#5 0xaaae50303d0c in mos6522_init qemu/hw/misc/mos6522.c:490
#6 0xaaae50b77d70 in object_init_with_type qemu/qom/object.c:371
#7 0xaaae50b7ae84 in object_initialize_with_type qemu/qom/object.c:515
#8 0xaaae50b7b0f8 in object_new_with_type qemu/qom/object.c:729
#9 0xaaae50bb6d58 in qmp_device_list_properties qemu/qom/qom-qmp-cmds.c:153
#10 0xaaae50d7e1dc in qmp_marshal_device_list_properties qemu/qapi/qapi-commands-qdev.c:59
#11 0xaaae50dc87a0 in do_qmp_dispatch_bh qemu/qapi/qmp-dispatch.c:110
#12 0xaaae50d931a0 in aio_bh_call qemu/util/async.c:136
Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Gan Qixin <ganqixin@huawei.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20210112112705.380534-3-ganqixin@huawei.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Gan Qixin [Tue, 12 Jan 2021 11:27:04 +0000 (19:27 +0800)]
pl031: Use timer_free() in the finalize function to avoid memleaks
When running device-introspect-test, a memory leak occurred in the pl031_init
function, this patch use timer_free() in the finalize function to fix it.
ASAN shows memory leak stack:
Direct leak of 48 byte(s) in 1 object(s) allocated from:
#0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0)
#1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800)
#2 0xaaabf5621cfc in timer_new_full qemu/include/qemu/timer.h:523
#3 0xaaabf5621cfc in timer_new qemu/include/qemu/timer.h:544
#4 0xaaabf5621cfc in timer_new_ns qemu/include/qemu/timer.h:562
#5 0xaaabf5621cfc in pl031_init qemu/hw/rtc/pl031.c:194
#6 0xaaabf6339f6c in object_initialize_with_type qemu/qom/object.c:515
#7 0xaaabf633a1e0 in object_new_with_type qemu/qom/object.c:729
#8 0xaaabf6375e40 in qmp_device_list_properties qemu/qom/qom-qmp-cmds.c:153
#9 0xaaabf5a95540 in qdev_device_help qemu/softmmu/qdev-monitor.c:283
#10 0xaaabf5a96940 in qmp_device_add qemu/softmmu/qdev-monitor.c:801
#11 0xaaabf5a96e70 in hmp_device_add qemu/softmmu/qdev-monitor.c:916
#12 0xaaabf5ac0a2c in handle_hmp_command qemu/monitor/hmp.c:1100
Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Gan Qixin <ganqixin@huawei.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20210112112705.380534-2-ganqixin@huawei.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Philippe Mathieu-Daudé [Thu, 10 Dec 2020 17:28:34 +0000 (18:28 +0100)]
hw/virtio-pci: Replace error_report() by qemu_log_mask(GUEST_ERROR)
Replace I/O write error reported with error_report() by
qemu_log_mask(GUEST_ERROR) which allow filtering.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Message-Id: <
20201210172834.178052-1-philmd@redhat.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Peter Maydell [Mon, 18 Jan 2021 10:28:26 +0000 (10:28 +0000)]
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-
20210117-3' into staging
First RISC-V PR for 6.0
This PR:
- Fixes some issues with the m25p80
- Improves GDB support for RISC-V
- Fixes some Linux boot issues, specifiaclly 32-bit boot failures
- Enforces PMP exceptions correctly
- Fixes some Coverity issues
# gpg: Signature made Sun 17 Jan 2021 21:53:19 GMT
# gpg: using RSA key
F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-
20210117-3:
riscv: Pass RISCVHartArrayState by pointer
target/riscv: Remove built-in GDB XML files for CSRs
target/riscv: Generate the GDB XML file for CSR registers dynamically
target/riscv: Add CSR name in the CSR function table
target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite
hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type
target/riscv/pmp: Raise exception if no PMP entry is configured
RISC-V: Place DTB at 3GB boundary instead of 4GB
gdb: riscv: Add target description
hw/block: m25p80: Implement AAI-WP command support for SST flashes
hw/block: m25p80: Don't write to flash if write is disabled
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Keith Packard [Fri, 8 Jan 2021 22:42:56 +0000 (22:42 +0000)]
semihosting: Implement SYS_ISERROR
Part of Semihosting for AArch32 and AArch64 Release 2.0
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <
20210107170717.
2098982-10-keithp@keithp.com>
Message-Id: <
20210108224256.2321-21-alex.bennee@linaro.org>
Keith Packard [Fri, 8 Jan 2021 22:42:55 +0000 (22:42 +0000)]
semihosting: Implement SYS_TMPNAM
Part of Semihosting for AArch32 and AArch64 Release 2.0
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <
20210107170717.
2098982-9-keithp@keithp.com>
Message-Id: <
20210108224256.2321-20-alex.bennee@linaro.org>
Keith Packard [Fri, 8 Jan 2021 22:42:54 +0000 (22:42 +0000)]
semihosting: Implement SYS_ELAPSED and SYS_TICKFREQ
These are part of Semihosting for AArch32 and AArch64 Release 2.0
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <
20210107170717.
2098982-8-keithp@keithp.com>
Message-Id: <
20210108224256.2321-19-alex.bennee@linaro.org>
Kito Cheng [Fri, 8 Jan 2021 22:42:53 +0000 (22:42 +0000)]
riscv: Add semihosting support for user mode
This could made testing more easier and ARM/AArch64 has supported on
their linux user mode too, so I think it should be reasonable.
Verified GCC testsuite with newlib/semihosting.
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210107170717.
2098982-7-keithp@keithp.com>
Message-Id: <
20210108224256.2321-18-alex.bennee@linaro.org>
Keith Packard [Fri, 8 Jan 2021 22:42:52 +0000 (22:42 +0000)]
riscv: Add semihosting support
Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting version 0.2 as
documented in
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <
20210107170717.
2098982-6-keithp@keithp.com>
Message-Id: <
20210108224256.2321-17-alex.bennee@linaro.org>
Keith Packard [Fri, 8 Jan 2021 22:42:51 +0000 (22:42 +0000)]
semihosting: Support SYS_HEAPINFO when env->boot_info is not set
env->boot_info is only set in some ARM startup paths, so we cannot
rely on it to support the SYS_HEAPINFO semihosting function. When not
available, fallback to finding a RAM memory region containing the
current stack and use the base of that.
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <
20210107170717.
2098982-5-keithp@keithp.com>
Message-Id: <
20210108224256.2321-16-alex.bennee@linaro.org>
Keith Packard [Fri, 8 Jan 2021 22:42:50 +0000 (22:42 +0000)]
semihosting: Change internal common-semi interfaces to use CPUState *
This makes all of the internal interfaces architecture-independent and
renames the internal functions to use the 'common_semi' prefix instead
of 'arm' or 'arm_semi'.
To do this, some new architecture-specific internal helper functions
were created:
static inline target_ulong
common_semi_arg(CPUState *cs, int argno)
Returns the argno'th semihosting argument, where argno can be
either 0 or 1.
static inline void
common_semi_set_ret(CPUState *cs, target_ulong ret)
Sets the semihosting return value.
static inline bool
common_semi_sys_exit_extended(CPUState *cs, int nr)
This detects whether the specified semihosting call, which
is either TARGET_SYS_EXIT or TARGET_SYS_EXIT_EXTENDED should
be executed using the TARGET_SYS_EXIT_EXTENDED semantics.
static inline target_ulong
common_semi_rambase(CPUState *cs)
Returns the base of RAM region used for heap and stack. This
is used to construct plausible values for the SYS_HEAPINFO
call.
In addition, several existing functions have been changed to flag
areas of code which are architecture specific:
static target_ulong
common_semi_flen_buf(CPUState *cs)
Returns the current stack pointer minus 64, which is
where a stat structure will be placed on the stack
#define GET_ARG(n)
This fetches arguments from the semihosting command's argument
block. The address of this is available implicitly through the
local 'args' variable. This is *mostly* architecture
independent, but does depend on the current ABI's notion of
the size of a 'long' parameter, which may need run-time checks
(as it does on AARCH64)
#define SET_ARG(n, val)
This mirrors GET_ARG and stores data back into the argument
block.
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <
20210107170717.
2098982-4-keithp@keithp.com>
Message-Id: <
20210108224256.2321-15-alex.bennee@linaro.org>
Keith Packard [Fri, 8 Jan 2021 22:42:49 +0000 (22:42 +0000)]
semihosting: Change common-semi API to be architecture-independent
The public API is now defined in
hw/semihosting/common-semi.h. do_common_semihosting takes CPUState *
instead of CPUARMState *. All internal functions have been renamed
common_semi_ instead of arm_semi_ or arm_. Aside from the API change,
there are no functional changes in this patch.
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <
20210107170717.
2098982-3-keithp@keithp.com>
Message-Id: <
20210108224256.2321-14-alex.bennee@linaro.org>
Keith Packard [Fri, 8 Jan 2021 22:42:48 +0000 (22:42 +0000)]
semihosting: Move ARM semihosting code to shared directories
This commit renames two files which provide ARM semihosting support so
that they can be shared by other architectures:
1. target/arm/arm-semi.c -> hw/semihosting/common-semi.c
2. linux-user/arm/semihost.c -> linux-user/semihost.c
The build system was modified use a new config variable,
CONFIG_ARM_COMPATIBLE_SEMIHOSTING, which has been added to the ARM
softmmu and linux-user default configs. The contents of the source
files has not been changed in this patch.
Signed-off-by: Keith Packard <keithp@keithp.com>
[AJB: rename arm-compat-semi, select SEMIHOSTING]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <
20210107170717.
2098982-2-keithp@keithp.com>
Message-Id: <
20210108224256.2321-13-alex.bennee@linaro.org>
Alex Bennée [Fri, 8 Jan 2021 22:42:46 +0000 (22:42 +0000)]
target/arm: use official org.gnu.gdb.aarch64.sve layout for registers
While GDB can work with any XML description given to it there is
special handling for SVE registers on the GDB side which makes the
users life a little better. The changes aren't that major and all the
registers save the $vg reported the same. All that changes is:
- report org.gnu.gdb.aarch64.sve
- use gdb nomenclature for names and types
- minor re-ordering of the types to match reference
- re-enable ieee_half (as we know gdb supports it now)
- $vg is now a 64 bit int
- check $vN and $zN aliasing in test
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Luis Machado <luis.machado@linaro.org>
Message-Id: <
20210108224256.2321-11-alex.bennee@linaro.org>
Alex Bennée [Fri, 8 Jan 2021 22:42:45 +0000 (22:42 +0000)]
gdbstub: ensure we clean-up when terminated
If you kill the inferior from GDB we end up leaving our socket lying
around. Fix this by calling gdb_exit() first.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210108224256.2321-10-alex.bennee@linaro.org>
Alex Bennée [Fri, 8 Jan 2021 22:42:44 +0000 (22:42 +0000)]
gdbstub: drop gdbserver_cleanup in favour of gdb_exit
Despite it's name it didn't actually clean-up so let us document
gdb_exit() better and use that.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210108224256.2321-9-alex.bennee@linaro.org>
Alex Bennée [Fri, 8 Jan 2021 22:42:43 +0000 (22:42 +0000)]
gdbstub: drop CPUEnv from gdb_exit()
gdb_exit() has never needed anything from env and I doubt we are going
to start now.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210108224256.2321-8-alex.bennee@linaro.org>
Lirong Yuan [Fri, 8 Jan 2021 22:42:42 +0000 (22:42 +0000)]
gdbstub: add support to Xfer:auxv:read: packet
This allows gdb to access the target’s auxiliary vector,
which can be helpful for telling system libraries important details
about the hardware, operating system, and process.
Signed-off-by: Lirong Yuan <yuanzi@google.com>
[AJB: minor tweaks to test case, update MAINTAINERS, restrict to Linux]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20200730193932.
3654677-1-yuanzi@google.com>
Message-Id: <
20210108224256.2321-7-alex.bennee@linaro.org>
Alex Bennée [Fri, 8 Jan 2021 22:42:41 +0000 (22:42 +0000)]
gdbstub: implement a softmmu based test
This adds a new tests that allows us to test softmmu only features
including watchpoints. To do achieve this we need to:
- add _exit: labels to the boot codes
- write a memory.py test case
- plumb the test case into the build system
- tweak the run_test script to:
- re-direct output when asked
- use socket based connection for all tests
- add a small pause before connection
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210108224256.2321-6-alex.bennee@linaro.org>
Alex Bennée [Fri, 8 Jan 2021 22:42:40 +0000 (22:42 +0000)]
Revert "tests/tcg/multiarch/Makefile.target: Disable run-gdbstub-sha1 test"
We won't attempt to run the test now it's gated on a newer version of
gdb.
This reverts commit
a930cadd83b4681a98ce72abf530a791ee2e42a6.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <
20210108224256.2321-5-alex.bennee@linaro.org>
Alex Bennée [Fri, 8 Jan 2021 22:42:39 +0000 (22:42 +0000)]
configure: gate our use of GDB to 8.3.1 or above
The support of socket based debugging which we need for linux-user
testing is only really stable as of 8.3.1 so lets gate our use of GDB
on having a relatively modern version.
For direct testing you can just point to a locally compiled version of
gdb via configure, e.g.:
../../configure --gdb=$HOME/src/binutils-gdb.git/builds/all/install/bin/gdb
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <
20210108224256.2321-4-alex.bennee@linaro.org>
Alex Bennée [Fri, 8 Jan 2021 22:42:38 +0000 (22:42 +0000)]
test/guest-debug: echo QEMU command as well
This helps with debugging.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <
20210108224256.2321-3-alex.bennee@linaro.org>
Alex Bennée [Thu, 14 Jan 2021 16:57:30 +0000 (16:57 +0000)]
scripts/checkpatch.pl: fix git-show invocation to include diffstat
Without this checkpatch keeps complaining about new/changed files even
when MAINTAINERS has been updated. Normal invocations of checkpatch on
patch files rather than commit IDs are unaffected.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <
20210114165730.31607-13-alex.bennee@linaro.org>
Alex Bennée [Thu, 14 Jan 2021 16:57:29 +0000 (16:57 +0000)]
gitlab: migrate the minimal tools and unit tests from Travis
These tests are good at shaking out missing stubs which otherwise work
if we have built targets. Rather than create a new job just add the
checks to the existing tools-and-docs build.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <
20210114165730.31607-12-alex.bennee@linaro.org>
Lukas Straub [Thu, 14 Jan 2021 16:57:28 +0000 (16:57 +0000)]
Fix build with new yank feature by adding stubs
Fixes:
50186051f42 ("Introduce yank feature")
Signed-off-by: Lukas Straub <lukasstraub2@web.de>
[AJB: tweak MAINTAINERS]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <
20210114141918.
5201cc9c@gecko.fritz.box>
Message-Id: <
20210114165730.31607-11-alex.bennee@linaro.org>
Alex Bennée [Thu, 14 Jan 2021 16:57:27 +0000 (16:57 +0000)]
gitlab: move docs and tools build across from Travis
While we are at it we might as well check the tag generation. For
bonus points we run GNU globals htags into the public pages directory
for publishing with the auto generated pages.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Message-Id: <
20210114165730.31607-10-alex.bennee@linaro.org>
Alex Bennée [Thu, 14 Jan 2021 16:57:26 +0000 (16:57 +0000)]
docker: expand debian-amd64 image to include tag tools
This is going to be helpful when we want to both test the tool
integration and in the case of global generate a xref doc build.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <
20210114165730.31607-9-alex.bennee@linaro.org>
Alex Bennée [Thu, 14 Jan 2021 16:57:25 +0000 (16:57 +0000)]
Makefile: wrap cscope in quiet-command calls
For prettier output.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <
20210114165730.31607-8-alex.bennee@linaro.org>
Alex Bennée [Thu, 14 Jan 2021 16:57:24 +0000 (16:57 +0000)]
Makefile: wrap etags in quiet-command calls
For prettier output.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <
20210114165730.31607-7-alex.bennee@linaro.org>
Alex Bennée [Thu, 14 Jan 2021 16:57:23 +0000 (16:57 +0000)]
Makefile: wrap ctags in quiet-command calls
For prettier output.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <
20210114165730.31607-6-alex.bennee@linaro.org>
Alessandro Di Federico [Thu, 14 Jan 2021 16:57:22 +0000 (16:57 +0000)]
Add newline when generating Dockerfile
Signed-off-by: Alessandro Di Federico <ale@rev.ng>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <
1610080146-14968-36-git-send-email-tsimpson@quicinc.com>
Message-Id: <
20210114165730.31607-5-alex.bennee@linaro.org>
Philippe Mathieu-Daudé [Thu, 14 Jan 2021 16:57:21 +0000 (16:57 +0000)]
shippable.yml: Remove jobs duplicated on Gitlab-CI
The following jobs are duplicated on Gitlab-CI since commit
6bcb5fc0f7a ("gitlab-ci: Add cross-compiling build tests"):
- IMAGE=debian-armel-cross
TARGET_LIST=arm-softmmu -> cross-armel-system
TARGET_LIST=arm-linux-user -> cross-armel-user
TARGET_LIST=armeb-linux-user -> cross-armel-user
- IMAGE=debian-armhf-cross
TARGET_LIST=arm-softmmu -> cross-armhf-system
TARGET_LIST=arm-linux-user -> cross-armhf-user
TARGET_LIST=armeb-linux-user -> cross-armhf-user
- IMAGE=debian-arm64-cross
TARGET_LIST=aarch64-softmmu -> cross-arm64-system
TARGET_LIST=aarch64-linux-user -> cross-arm64-user
- IMAGE=debian-s390x-cross
TARGET_LIST=s390x-softmmu -> cross-s390x-system
TARGET_LIST=s390x-linux-user -> cross-s390x-user
- IMAGE=debian-mips-cross
TARGET_LIST=mipsel-linux-user -> cross-mips-user
- IMAGE=debian-mips64el-cross
TARGET_LIST=mips64el-softmmu -> cross-mips64el-system
TARGET_LIST=mips64el-linux-user -> cross-mips64el-user
- IMAGE=debian-ppc64el-cross
TARGET_LIST=ppc64-softmmu -> cross-ppc64el-system
TARGET_LIST=ppc64-linux-user -> cross-ppc64el-user
TARGET_LIST=ppc64abi32-linux-user -> cross-ppc64el-user
Remove them from Shippable CI.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <
20210108145103.269353-1-f4bug@amsat.org>
Message-Id: <
20210114165730.31607-4-alex.bennee@linaro.org>
Alex Bennée [Thu, 14 Jan 2021 16:57:20 +0000 (16:57 +0000)]
Makefile: add GNU global tags support
GNU Global is another tags engine which is more like cscope in being
able to support finding both references and definitions. You will be
un-surprised to know it also integrates well with Emacs.
The main benefit of integrating it into find-src-path is it takes less
time to rebuild the database from scratch when you have a lot of build
directories under your source tree.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <
20210114165730.31607-3-alex.bennee@linaro.org>
Philippe Mathieu-Daudé [Thu, 14 Jan 2021 16:57:19 +0000 (16:57 +0000)]
tests/docker: Remove Debian 9 remnant lines
Debian 9 base container has been removed in commits
e3755276d1f and
c9d78b06c06. Remove the last remnants.
Fixes:
e3755276d1f ("tests/docker: Remove old Debian 9 containers")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Message-Id: <
20210107072933.
3828450-1-f4bug@amsat.org>
Message-Id: <
20210114165730.31607-2-alex.bennee@linaro.org>
Peter Maydell [Sun, 17 Jan 2021 17:04:40 +0000 (17:04 +0000)]
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
pc,pci,virtio: fixes, features
Fixes all over the place.
PXB support for ARM.
boot index for vhost-user-fs.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
# gpg: Signature made Sun 17 Jan 2021 11:44:55 GMT
# gpg: using RSA key
5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg: issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* remotes/mst/tags/for_upstream:
acpi: Update _DSM method in expected files
acpi: Enable pxb unit-test for ARM virt machine
Kconfig: Compile PXB for ARM_VIRT
acpi/gpex: Exclude pxb's resources from PCI0
acpi/gpex: Inform os to keep firmware resource map
acpi: Add addr offset in build_crs
acpi: Fix unmatched expected DSDT.pxb file
acpi: Allow DSDT acpi table changes
vhost-user-fs: add the "bootindex" property
pci/shpc: don't push attention button when ejecting powered-off device
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Jiahui Cen [Thu, 14 Jan 2021 10:06:43 +0000 (18:06 +0800)]
acpi: Update _DSM method in expected files
A new _DSM #5 method is added.
Update expected DSDT files accordingly, and re-enable their testing.
Full diff of changed files disassembly:
tests/data/acpi/microvm/DSDT.pcie.dsl:
@@ -5,13 +5,13 @@
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/microvm/DSDT.pcie, Thu Jan 14 13:39:35 2021
+ * Disassembly of tests/data/acpi/microvm/DSDT.pcie, Thu Jan 14 13:51:13 2021
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x00000BCF (3023)
+ * Length 0x00000BD7 (3031)
* Revision 0x02
- * Checksum 0x29
+ * Checksum 0x99
* OEM ID "BOCHS "
* OEM Table ID "BXPCDSDT"
* OEM Revision 0x00000001 (1)
@@ -1302,9 +1302,14 @@
{
Return (Buffer (One)
{
- 0x01 // .
+ 0x21 // !
})
}
+
+ If ((Arg2 == 0x05))
+ {
+ Return (Zero)
+ }
}
Return (Buffer (One)
tests/data/acpi/virt/DSDT.dsl:
@@ -5,13 +5,13 @@
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/virt/DSDT, Thu Jan 14 13:39:35 2021
+ * Disassembly of tests/data/acpi/virt/DSDT, Thu Jan 14 13:51:13 2021
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x0000144C (5196)
+ * Length 0x00001454 (5204)
* Revision 0x02
- * Checksum 0xF0
+ * Checksum 0x60
* OEM ID "BOCHS "
* OEM Table ID "BXPCDSDT"
* OEM Revision 0x00000001 (1)
@@ -1838,9 +1838,14 @@
{
Return (Buffer (One)
{
- 0x01 // .
+ 0x21 // !
})
}
+
+ If ((Arg2 == 0x05))
+ {
+ Return (Zero)
+ }
}
Return (Buffer (One)
tests/data/acpi/virt/DSDT.memhp.dsl:
@@ -5,13 +5,13 @@
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/virt/DSDT.memhp, Thu Jan 14 13:39:35 2021
+ * Disassembly of tests/data/acpi/virt/DSDT.memhp, Thu Jan 14 13:51:13 2021
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x0000199D (6557)
+ * Length 0x000019A5 (6565)
* Revision 0x02
- * Checksum 0x11
+ * Checksum 0x90
* OEM ID "BOCHS "
* OEM Table ID "BXPCDSDT"
* OEM Revision 0x00000001 (1)
@@ -1840,9 +1840,14 @@
{
Return (Buffer (One)
{
- 0x01 // .
+ 0x21 // !
})
}
+
+ If ((Arg2 == 0x05))
+ {
+ Return (Zero)
+ }
}
Return (Buffer (One)
tests/data/acpi/virt/DSDT.numamem.dsl:
@@ -5,13 +5,13 @@
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/virt/DSDT.numamem, Thu Jan 14 13:39:35 2021
+ * Disassembly of tests/data/acpi/virt/DSDT.numamem, Thu Jan 14 13:51:13 2021
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x0000144C (5196)
+ * Length 0x00001454 (5204)
* Revision 0x02
- * Checksum 0xF0
+ * Checksum 0x60
* OEM ID "BOCHS "
* OEM Table ID "BXPCDSDT"
* OEM Revision 0x00000001 (1)
@@ -1838,9 +1838,14 @@
{
Return (Buffer (One)
{
- 0x01 // .
+ 0x21 // !
})
}
+
+ If ((Arg2 == 0x05))
+ {
+ Return (Zero)
+ }
}
Return (Buffer (One)
tests/data/acpi/virt/DSDT.pxb.dsl:
@@ -5,13 +5,13 @@
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/virt/DSDT.pxb, Thu Jan 14 13:39:35 2021
+ * Disassembly of tests/data/acpi/virt/DSDT.pxb, Thu Jan 14 13:51:13 2021
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x00001DF9 (7673)
+ * Length 0x00001E09 (7689)
* Revision 0x02
- * Checksum 0x42
+ * Checksum 0x30
* OEM ID "BOCHS "
* OEM Table ID "BXPCDSDT"
* OEM Revision 0x00000001 (1)
@@ -1810,9 +1810,14 @@
{
Return (Buffer (One)
{
- 0x01 // .
+ 0x21 // !
})
}
+
+ If ((Arg2 == 0x05))
+ {
+ Return (Zero)
+ }
}
Return (Buffer (One)
@@ -3025,9 +3030,14 @@
{
Return (Buffer (One)
{
- 0x01 // .
+ 0x21 // !
})
}
+
+ If ((Arg2 == 0x05))
+ {
+ Return (Zero)
+ }
}
Return (Buffer (One)
Acked-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
Message-Id: <
20210114100643.10617-9-cenjiahui@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Jiahui Cen [Thu, 14 Jan 2021 10:06:42 +0000 (18:06 +0800)]
acpi: Enable pxb unit-test for ARM virt machine
No matter whether the pxb is enabled or not, the CONFIG_PXB macro in test
would keep undefined. And since pxb is now enabled for ARM Virt machine
by default, let's enable pxb unit-test by removing the CONFIG_PXB.
Acked-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
Message-Id: <
20210114100643.10617-8-cenjiahui@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Jiahui Cen [Thu, 14 Jan 2021 10:06:41 +0000 (18:06 +0800)]
Kconfig: Compile PXB for ARM_VIRT
PXB is now supported on ARM, so let's compile for arm_virt machine.
Acked-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
Message-Id: <
20210114100643.10617-7-cenjiahui@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Jiahui Cen [Thu, 14 Jan 2021 10:06:40 +0000 (18:06 +0800)]
acpi/gpex: Exclude pxb's resources from PCI0
Exclude the resources of extra root bridges from PCI0's _CRS. Otherwise,
the resource windows would overlap in guest, and the IO resource window
would fail to be registered.
Acked-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
Message-Id: <
20210114100643.10617-6-cenjiahui@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Jiahui Cen [Thu, 14 Jan 2021 10:06:39 +0000 (18:06 +0800)]
acpi/gpex: Inform os to keep firmware resource map
There may be some differences in pci resource assignment between guest os
and firmware.
Eg. A Bridge with Bus [d2]
-+-[0000:d2]---01.0-[d3]----01.0
where [d2:01.00] is a pcie-pci-bridge with BAR0 (mem, 64-bit, non-pref) [size=256]
[d3:01.00] is a PCI Device with BAR0 (mem, 64-bit, pref) [size=128K]
BAR4 (mem, 64-bit, pref) [size=64M]
In EDK2, the Resource Map would be:
PciBus: Resource Map for Bridge [D2|01|00]
Type = PMem64; Base = 0x8004000000; Length = 0x4100000; Alignment = 0x3FFFFFF
Base = 0x8004000000; Length = 0x4000000; Alignment = 0x3FFFFFF; Owner = PCI [D3|01|00:20]
Base = 0x8008000000; Length = 0x20000; Alignment = 0x1FFFF; Owner = PCI [D3|01|00:10]
Type = Mem64; Base = 0x8008100000; Length = 0x100; Alignment = 0xFFF
It would use 0x4100000 to calculate the root bus's PMem64 resource window.
While in Linux, kernel will use 0x1FFFFFF as the alignment to calculate
the PMem64 size, which would be 0x6000000. So kernel would try to
allocate 0x6000000 from the PMem64 resource window, but since the window
size is 0x4100000 as assigned by EDK2, the allocation would fail.
The diffences could result in resource assignment failure.
Using _DSM #5 method to inform guest os not to ignore the PCI configuration
that firmware has done at boot time could handle the differences.
Acked-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
Message-Id: <
20210114100643.10617-5-cenjiahui@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Jiahui Cen [Thu, 14 Jan 2021 10:06:38 +0000 (18:06 +0800)]
acpi: Add addr offset in build_crs
AML needs Address Translation offset to describe how a bridge translates
addresses accross the bridge when using an address descriptor, and
especially on ARM, the translation offset of pio resource is usually
non zero.
Therefore, it's necessary to pass offset for pio, mmio32, mmio64 and bus
number into build_crs.
Acked-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
Message-Id: <
20210114100643.10617-4-cenjiahui@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Jiahui Cen [Thu, 14 Jan 2021 10:06:37 +0000 (18:06 +0800)]
acpi: Fix unmatched expected DSDT.pxb file
Commit
fe1127da11 ("unit-test: Add the binary file and clear diff.h") does
not use the up-to-date expected file for pxb for ARM virt.
Fix the expected DSDT.pxb file.
Full diff of changed file disassembly:
@@ -5,13 +5,13 @@
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/virt/DSDT.pxb, Thu Jan 14 09:33:09 2021
+ * Disassembly of tests/data/acpi/virt/DSDT.pxb, Thu Jan 14 13:34:47 2021
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x00001E7A (7802)
+ * Length 0x00001DF9 (7673)
* Revision 0x02
- * Checksum 0x57
+ * Checksum 0x42
* OEM ID "BOCHS "
* OEM Table ID "BXPCDSDT"
* OEM Revision 0x00000001 (1)
@@ -45,32 +45,6 @@
})
}
- Device (FLS0)
- {
- Name (_HID, "LNRO0015") // _HID: Hardware ID
- Name (_UID, Zero) // _UID: Unique ID
- Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
- {
- Memory32Fixed (ReadWrite,
- 0x00000000, // Address Base
- 0x04000000, // Address Length
- )
- })
- }
-
- Device (FLS1)
- {
- Name (_HID, "LNRO0015") // _HID: Hardware ID
- Name (_UID, One) // _UID: Unique ID
- Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
- {
- Memory32Fixed (ReadWrite,
- 0x04000000, // Address Base
- 0x04000000, // Address Length
- )
- })
- }
-
Device (FWCF)
{
Name (_HID, "QEMU0002") // _HID: Hardware ID
@@ -665,9 +639,6 @@
{
Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
- Name (_ADR, Zero) // _ADR: Address
- Name (_CCA, One) // _CCA: Cache Coherency Attribute
- Name (_SEG, Zero) // _SEG: PCI Segment
Name (_BBN, 0x80) // _BBN: BIOS Bus Number
Name (_UID, 0x80) // _UID: Unique ID
Name (_STR, Unicode ("pxb Device")) // _STR: Description String
@@ -1857,7 +1828,7 @@
Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, Zero) // _SEG: PCI Segment
Name (_BBN, Zero) // _BBN: BIOS Bus Number
- Name (_UID, "PCI0") // _UID: Unique ID
+ Name (_UID, Zero) // _UID: Unique ID
Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_PRT, Package (0x80) // _PRT: PCI Routing Table
@@ -2983,41 +2954,37 @@
Return (0x0000004010000000)
}
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
- Return (ResourceTemplate ()
- {
- WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
- 0x0000, // Granularity
- 0x0000, // Range Minimum
- 0x007F, // Range Maximum
- 0x0000, // Translation Offset
- 0x0080, // Length
- ,, )
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
- 0x00000000, // Granularity
- 0x10000000, // Range Minimum
- 0x3EFEFFFF, // Range Maximum
- 0x00000000, // Translation Offset
- 0x2EFF0000, // Length
- ,, , AddressRangeMemory, TypeStatic)
- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x00000000, // Granularity
- 0x00000000, // Range Minimum
- 0x0000FFFF, // Range Maximum
- 0x3EFF0000, // Translation Offset
- 0x00010000, // Length
- ,, , TypeStatic, DenseTranslation)
- QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
- 0x0000000000000000, // Granularity
- 0x0000008000000000, // Range Minimum
- 0x000000FFFFFFFFFF, // Range Maximum
- 0x0000000000000000, // Translation Offset
- 0x0000008000000000, // Length
- ,, , AddressRangeMemory, TypeStatic)
- })
- }
-
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x007F, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0080, // Length
+ ,, )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x10000000, // Range Minimum
+ 0x3EFEFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x2EFF0000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000, // Granularity
+ 0x00000000, // Range Minimum
+ 0x0000FFFF, // Range Maximum
+ 0x3EFF0000, // Translation Offset
+ 0x00010000, // Length
+ ,, , TypeStatic, DenseTranslation)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000008000000000, // Range Minimum
+ 0x000000FFFFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000008000000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
Name (SUPP, Zero)
Name (CTRL, Zero)
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
Fixes:
fe1127da11 ("unit-test: Add the binary file and clear diff.h")
Acked-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
Message-Id: <
20210114100643.10617-3-cenjiahui@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Jiahui Cen [Thu, 14 Jan 2021 10:06:36 +0000 (18:06 +0800)]
acpi: Allow DSDT acpi table changes
Acked-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
Message-Id: <
20210114100643.10617-2-cenjiahui@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Alistair Francis [Fri, 15 Jan 2021 23:00:27 +0000 (15:00 -0800)]
riscv: Pass RISCVHartArrayState by pointer
We were accidently passing RISCVHartArrayState by value instead of
pointer. The type is 824 bytes long so let's correct that and pass it by
pointer instead.
Fixes: Coverity CID
1438099
Fixes: Coverity CID
1438100
Fixes: Coverity CID
1438101
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Message-id:
f3e04424723e0e222769991896cc82308fd23f76.
1610751609.git.alistair.francis@wdc.com
Bin Meng [Sat, 16 Jan 2021 05:41:23 +0000 (13:41 +0800)]
target/riscv: Remove built-in GDB XML files for CSRs
Now that we have switched to generate the RISC-V CSR XML dynamically,
remove the built-in hardcoded XML files.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id:
20210116054123.5457-3-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Bin Meng [Sat, 16 Jan 2021 05:41:22 +0000 (13:41 +0800)]
target/riscv: Generate the GDB XML file for CSR registers dynamically
At present QEMU RISC-V uses a hardcoded XML to report the feature
"org.gnu.gdb.riscv.csr" [1]. There are two major issues with the
approach being used currently:
- The XML does not specify the "regnum" field of a CSR entry, hence
consecutive numbers are used by the remote GDB client to access
CSRs. In QEMU we have to maintain a map table to convert the GDB
number to the hardware number which is error prone.
- The XML contains some CSRs that QEMU does not implement at all,
which causes an "E14" response sent to remote GDB client.
Change to generate the CSR register list dynamically, based on the
availability presented in the CSR function table. This new approach
will reflect a correct list of CSRs that QEMU actually implements.
[1] https://sourceware.org/gdb/current/onlinedocs/gdb/RISC_002dV-Features.html#RISC_002dV-Features
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id:
20210116054123.5457-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Bin Meng [Tue, 12 Jan 2021 04:52:02 +0000 (12:52 +0800)]
target/riscv: Add CSR name in the CSR function table
In preparation to generate the CSR register list for GDB stub
dynamically, let's add the CSR name in the CSR function table.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id:
1610427124-49887-3-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Bin Meng [Tue, 12 Jan 2021 04:52:01 +0000 (12:52 +0800)]
target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
In preparation to generate the CSR register list for GDB stub
dynamically, change csr_ops[] to non-static so that it can be
referenced externally.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id:
1610427124-49887-2-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Green Wan [Wed, 4 Nov 2020 09:29:00 +0000 (17:29 +0800)]
hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite
Fix code coverage issues by checking return value and handling fail case
of blk_pread() and blk_pwrite(). Return default value 0xff if read fails.
Fixes: Coverity CID
1435959
Fixes: Coverity CID
1435960
Fixes: Coverity CID
1435961
Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id:
20201104092900.21214-1-green.wan@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Bin Meng [Sat, 9 Jan 2021 14:36:37 +0000 (22:36 +0800)]
hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type
SIFIVE_U_CPU is conditionally set to SIFIVE_U34 or SIFIVE_U54, hence
there is no need to use #idef to set the mc->default_cpu_type.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id:
20210109143637.29645-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Atish Patra [Wed, 23 Dec 2020 19:25:53 +0000 (11:25 -0800)]
target/riscv/pmp: Raise exception if no PMP entry is configured
As per the privilege specification, any access from S/U mode should fail
if no pmp region is configured.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id:
20201223192553.332508-1-atish.patra@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Atish Patra [Thu, 7 Jan 2021 09:11:27 +0000 (01:11 -0800)]
RISC-V: Place DTB at 3GB boundary instead of 4GB
Currently, we place the DTB at 2MB from 4GB or end of DRAM which ever is
lesser. However, Linux kernel can address only 1GB of memory for RV32.
Thus, it can not map anything beyond 3GB (assuming 2GB is the starting address).
As a result, it can not process DT and panic if opensbi dynamic firmware
is used. While at it, place the DTB further away to avoid in memory placement
issues in future.
Fix this by placing the DTB at 16MB from 3GB or end of DRAM whichever is lower.
Fixes:
66b1205bc5ab ("RISC-V: Copy the fdt in dram instead of ROM")
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Message-id:
20210107091127.
3407870-1-atish.patra@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Sylvain Pelissier [Wed, 6 Jan 2021 20:41:41 +0000 (21:41 +0100)]
gdb: riscv: Add target description
Target description is not currently implemented in RISC-V
architecture. Thus GDB won't set it properly when attached.
The patch implements the target description response.
Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id:
20210106204141.14027-1-sylvain.pelissier@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Xuzhou Cheng [Wed, 23 Dec 2020 02:00:25 +0000 (10:00 +0800)]
hw/block: m25p80: Implement AAI-WP command support for SST flashes
Auto Address Increment (AAI) Word-Program is a special command of
SST flashes. AAI-WP allows multiple bytes of data to be programmed
without re-issuing the next sequential address location.
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id:
1608688825-81519-2-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Bin Meng [Wed, 23 Dec 2020 02:00:24 +0000 (10:00 +0800)]
hw/block: m25p80: Don't write to flash if write is disabled
When write is disabled, the write to flash should be avoided
in flash_write8().
Fixes:
82a2499011a7 ("m25p80: Initial implementation of SPI flash device")
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id:
1608688825-81519-1-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Peter Maydell [Fri, 15 Jan 2021 22:21:21 +0000 (22:21 +0000)]
Merge remote-tracking branch 'remotes/kraxel/tags/audio-
20210115-pull-request' into staging
audio: improvements for sdl, pulse, fsound.
audio: cleanups & codestyle fixes.
# gpg: Signature made Fri 15 Jan 2021 13:20:56 GMT
# gpg: using RSA key
A0328CFFB93A17A79901FE7D4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full]
# gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full]
# gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
# Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138
* remotes/kraxel/tags/audio-
20210115-pull-request: (30 commits)
audio: space prohibited between function name and parenthesis'('
audio: Suspect code indent for conditional statements
audio: Don't use '%#' in format strings
audio: Fix lines over 90 characters
audio: foo* bar" should be "foo *bar".
audio: Add spaces around operator/delete redundant spaces
audio: Add braces for statements/fix braces' position
dsoundaudio: fix log message
dsoundaudio: enable f32 audio sample format
dsoundaudio: rename dsound_open()
dsoundaudio: replace GetForegroundWindow()
paaudio: send recorded data in smaller chunks
paaudio: limit minreq to 75% of audio timer_rate
paaudio: comment bugs in functions qpa_init_*
paaudio: remove unneeded code
paaudio: wait until the playback stream is ready
paaudio: wait for PA_STREAM_READY in qpa_write()
paaudio: avoid to clip samples multiple times
audio: remove remaining unused plive code
sdlaudio: enable (in|out).mixing-engine=off
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Fri, 15 Jan 2021 16:35:18 +0000 (16:35 +0000)]
Merge remote-tracking branch 'remotes/kraxel/tags/ui-
20210115-pull-request' into staging
ui/gtk: refresh rate fixes.
ui/vnc: add support for desktop resize and power contol.
ui/vnc: misc bugfixes.
# gpg: Signature made Fri 15 Jan 2021 10:24:10 GMT
# gpg: using RSA key
A0328CFFB93A17A79901FE7D4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full]
# gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full]
# gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
# Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138
* remotes/kraxel/tags/ui-
20210115-pull-request:
vnc: add support for extended desktop resize
vnc: move initialization to framebuffer_update_request
vnc: move check into vnc_cursor_define
vnc: Fix a memleak in vnc_display_connect()
ui: add support for remote power control to VNC server
vnc: fix unfinalized tlscreds for VncDisplay
ui/gtk: update monitor interval on egl displays
ui/gtk: expose gd_monitor_update_interval
ui/gtk: limit virtual console max update interval
ui/gtk: rename variable window to widget
ui/gtk: don't try to redefine SI prefixes
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Fri, 15 Jan 2021 15:32:05 +0000 (15:32 +0000)]
Merge remote-tracking branch 'remotes/gkurz-gitlab/tags/9p-next-2021-01-15' into staging
Fix for CVE-2021-20181
# gpg: Signature made Fri 15 Jan 2021 08:52:19 GMT
# gpg: using RSA key
B4828BAF943140CEF2A3491071D4D5E5822F73D6
# gpg: Good signature from "Greg Kurz <groug@kaod.org>" [full]
# gpg: aka "Gregory Kurz <gregory.kurz@free.fr>" [full]
# gpg: aka "[jpeg image of size 3330]" [full]
# Primary key fingerprint: B482 8BAF 9431 40CE F2A3 4910 71D4 D5E5 822F 73D6
* remotes/gkurz-gitlab/tags/9p-next-2021-01-15:
9pfs: Fully restart unreclaim loop (CVE-2021-20181)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Fri, 15 Jan 2021 13:22:54 +0000 (13:22 +0000)]
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-
20210114' into staging
MIPS patches queue
- Simplify CPU/ISA definitions
- Various maintenance code movements in translate.c
- Convert part of the MSA ASE instructions to decodetree
- Convert some instructions removed from Release 6 to decodetree
- Remove deprecated 'fulong2e' machine alias
# gpg: Signature made Thu 14 Jan 2021 16:16:29 GMT
# gpg: using RSA key
FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd-gitlab/tags/mips-
20210114: (69 commits)
docs/system: Remove deprecated 'fulong2e' machine alias
target/mips: Remove vendor specific CPU definitions
target/mips: Remove CPU_NANOMIPS32 definition
target/mips: Remove CPU_R5900 definition
target/mips: Convert Rel6 LL/SC opcodes to decodetree
target/mips: Convert Rel6 LLD/SCD opcodes to decodetree
target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree
target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree
target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree
target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree
target/mips: Convert Rel6 COP1X opcode to decodetree
target/mips: Convert Rel6 Special2 opcode to decodetree
target/mips: Remove now unreachable LSA/DLSA opcodes code
target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes
target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes
target/mips: Extract LSA/DLSA translation generators
target/mips: Use decode_ase_msa() generated from decodetree
target/mips: Introduce decode tree bindings for MSA ASE
target/mips: Pass TCGCond argument to MSA gen_check_zero_element()
target/mips: Extract MSA translation routines
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Zhang Han [Fri, 15 Jan 2021 01:24:31 +0000 (09:24 +0800)]
audio: space prohibited between function name and parenthesis'('
Delete spaces between function name and open parenthesis'('
Signed-off-by: Zhang Han <zhanghan64@huawei.com>
Message-id:
20210115012431.79533-1-zhanghan64@huawei.com
Message-Id: <
20210115012431.79533-8-zhanghan64@huawei.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Zhang Han [Fri, 15 Jan 2021 01:24:30 +0000 (09:24 +0800)]
audio: Suspect code indent for conditional statements
Fix code indent.
Signed-off-by: Zhang Han <zhanghan64@huawei.com>
Message-id:
20210115012431.79533-1-zhanghan64@huawei.com
Message-Id: <
20210115012431.79533-7-zhanghan64@huawei.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Zhang Han [Fri, 15 Jan 2021 01:24:29 +0000 (09:24 +0800)]
audio: Don't use '%#' in format strings
Use '0x' prefix instead of '%#'
Signed-off-by: Zhang Han <zhanghan64@huawei.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id:
20210115012431.79533-1-zhanghan64@huawei.com
Message-Id: <
20210115012431.79533-6-zhanghan64@huawei.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Zhang Han [Fri, 15 Jan 2021 01:24:28 +0000 (09:24 +0800)]
audio: Fix lines over 90 characters
Fix the line width of code.
Signed-off-by: Zhang Han <zhanghan64@huawei.com>
Message-id:
20210115012431.79533-1-zhanghan64@huawei.com
Message-Id: <
20210115012431.79533-5-zhanghan64@huawei.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Zhang Han [Fri, 15 Jan 2021 01:24:27 +0000 (09:24 +0800)]
audio: foo* bar" should be "foo *bar".
transfer "foo* " to "foo *"
Signed-off-by: Zhang Han <zhanghan64@huawei.com>
Message-id:
20210115012431.79533-1-zhanghan64@huawei.com
Message-Id: <
20210115012431.79533-4-zhanghan64@huawei.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Zhang Han [Fri, 15 Jan 2021 01:24:26 +0000 (09:24 +0800)]
audio: Add spaces around operator/delete redundant spaces
Fix problems about spaces:
-operator needs spaces around it, add them.
-somespaces are redundant, remove them.
Signed-off-by: Zhang Han <zhanghan64@huawei.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id:
20210115012431.79533-1-zhanghan64@huawei.com
Message-Id: <
20210115012431.79533-3-zhanghan64@huawei.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Zhang Han [Fri, 15 Jan 2021 01:24:25 +0000 (09:24 +0800)]
audio: Add braces for statements/fix braces' position
Fix problems about braces:
-braces are necessary for all arms of if/for/while statements
-else should follow close brace '}'
Signed-off-by: Zhang Han <zhanghan64@huawei.com>
Message-id:
20210115012431.79533-1-zhanghan64@huawei.com
Message-Id: <
20210115012431.79533-2-zhanghan64@huawei.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Volker Rümelin [Sun, 10 Jan 2021 10:02:39 +0000 (11:02 +0100)]
dsoundaudio: fix log message
There is a mismatch between message and used argument. Change
the argument from frequency to format.
Signed-off-by: Volker Rümelin <vr_qemu@t-online.de>
Message-id:
9315afe5-5958-c0b4-ea1e-
14769511a9d5@t-online.de
Message-Id: <
20210110100239.27588-23-vr_qemu@t-online.de>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Volker Rümelin [Sun, 10 Jan 2021 10:02:38 +0000 (11:02 +0100)]
dsoundaudio: enable f32 audio sample format
Enable the f32 audio sample format for the DirectSound backend.
Signed-off-by: Volker Rümelin <vr_qemu@t-online.de>
Message-id:
9315afe5-5958-c0b4-ea1e-
14769511a9d5@t-online.de
Message-Id: <
20210110100239.27588-22-vr_qemu@t-online.de>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Volker Rümelin [Sun, 10 Jan 2021 10:02:37 +0000 (11:02 +0100)]
dsoundaudio: rename dsound_open()
Rename dsound_open() to dsound_set_cooperative_level(). The
only task of that function is to set the cooperative level for
DirectSound.
Signed-off-by: Volker Rümelin <vr_qemu@t-online.de>
Message-id:
9315afe5-5958-c0b4-ea1e-
14769511a9d5@t-online.de
Message-Id: <
20210110100239.27588-21-vr_qemu@t-online.de>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>