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Sanjay Patel [Fri, 5 Oct 2018 14:56:14 +0000 (14:56 +0000)]
[x86] regenerate full checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343855
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Sanjay Patel [Fri, 5 Oct 2018 14:49:20 +0000 (14:49 +0000)]
[x86] add test for fneg matching failure; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343854
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Simon Pilgrim [Fri, 5 Oct 2018 14:41:00 +0000 (14:41 +0000)]
[X86][AVX] getFauxShuffleMask - add support for INSERT_SUBVECTOR subvector shuffles
Decode subvector shuffles from INSERT_SUBVECTOR(SRC0, SHUFFLE(EXTRACT_SUBVECTOR(SRC1))
This was found necessary while investigating PR39161
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343853
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Jonas Paulsson [Fri, 5 Oct 2018 14:34:04 +0000 (14:34 +0000)]
[LoopVectorizer] Use TTI.getOperandInfo()
Call getOperandInfo() instead of using (near) duplicated code in
LoopVectorizationCostModel::getInstructionCost().
This gets the OperandValueKind and OperandValueProperties values for a Value
passed as operand to an arithmetic instruction.
getOperandInfo() used to be a static method in TargetTransformInfo.cpp, but
is now instead a public member.
Review: Florian Hahn
https://reviews.llvm.org/D52883
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343852
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Jonas Paulsson [Fri, 5 Oct 2018 14:23:11 +0000 (14:23 +0000)]
[TargetRegisterInfo] Remove temporary hook enableMultipleCopyHints()
Finally all targets are enabling multiple regalloc hints, so the hook to
disable this can now be removed.
NFC.
Review: Simon Pilgrim
https://reviews.llvm.org/D52316
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343851
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Neil Henning [Fri, 5 Oct 2018 09:39:07 +0000 (09:39 +0000)]
Add missing period to comment to match style of file.
This is a test commit to show that my commit access is working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343842
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Tom Stellard [Fri, 5 Oct 2018 04:34:09 +0000 (04:34 +0000)]
AMDGPU/GlobalISel: Add support for G_INTTOPTR
Summary: This is a no-op.
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D52916
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343839
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Thomas Lively [Fri, 5 Oct 2018 00:45:20 +0000 (00:45 +0000)]
[WebAssembly] Saturating arithmetic intrinsics
Summary: Depends on D52805.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52813
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343833
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Shoaib Meenai [Fri, 5 Oct 2018 00:08:27 +0000 (00:08 +0000)]
[cmake] Also create lowercase extension WinSDK symlinks
Some projects rely on using libraries from the Windows SDK with their
original casing, just with a lowercase extension. E.g. the WinSock2 lib
is named WS2_32.Lib in the Windows SDK, and we would previously only
create a ws2_32.lib symlink for it (i.e. all lowercase). Also create a
WS2_32.lib symlink (i.e. original casing with lowercase extension) to
cover users of this casing. As a drive-by fix, only create these
symlinks when they differ from the original name to reduce the amount of
noise in the library symlinks directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343832
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Wouter van Oortmerssen [Thu, 4 Oct 2018 23:48:53 +0000 (23:48 +0000)]
[WebAssembly] Fixed missing "global" symbol type in AsmParser.
Summary:
These are emitted by the wasm backend for e.g.
__stack_pointer@GLOBAL which previously wasn't accepted by the
assembler.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, llvm-commits, sunfish
Differential Revision: https://reviews.llvm.org/D52911
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343830
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Daniel Sanders [Thu, 4 Oct 2018 23:47:37 +0000 (23:47 +0000)]
[globalisel][combine] When placing truncates, handle the case when the BB is empty
GlobalISel uses MIR with implicit fallthrough on each basic block. As a result,
getFirstNonPhi() can return end().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343829
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Craig Topper [Thu, 4 Oct 2018 23:40:31 +0000 (23:40 +0000)]
[SimplifyCFG] Pass AggressiveInsts to DominatesMergePoint by reference. Remove null check.
Summary:
At some point in the past the recursion in DominatesMergePoint used to pass null for AggressiveInsts as part of the recursion. It no longer does this. So there is no way for AggressiveInsts to be null.
This passes it by reference and removes the null check to make this explicit.
Reviewers: efriedma, reames
Reviewed By: efriedma
Subscribers: xbolva00, llvm-commits
Differential Revision: https://reviews.llvm.org/D52575
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343828
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Yury Delendik [Thu, 4 Oct 2018 23:31:00 +0000 (23:31 +0000)]
[WebAssembly] Ignore DBG_VALUE in WebAssemblyCFGStackify pass when looking for block start
Summary:
Fixes https://bugs.llvm.org/show_bug.cgi?id=39158 and regression caused by
D49034. Though it is possible the problem was existed before and was exposed by
additional DBG_VALUEs.
Reviewers: sunfish, dschuff, aheejin
Reviewed By: aheejin
Subscribers: sbc100, aheejin, llvm-commits, alexcrichton, jgravelle-google
Differential Revision: https://reviews.llvm.org/D52837
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343827
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Matt Davis [Thu, 4 Oct 2018 22:16:39 +0000 (22:16 +0000)]
[llvm-mca] Remove unused/stale forward decl. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343823
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Ana Pazos [Thu, 4 Oct 2018 21:50:54 +0000 (21:50 +0000)]
[RISCV] Support named operands for CSR instructions.
Reviewers: asb, mgrang
Reviewed By: asb
Subscribers: jocewei, mgorny, jfb, PkmX, MartinMosbeck, brucehoult, the_o, rkruppe, rogfer01, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones
Differential Revision: https://reviews.llvm.org/D46759
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343822
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Daniel Sanders [Thu, 4 Oct 2018 21:44:32 +0000 (21:44 +0000)]
[globalisel][combine] Fix a rare crash when encountering an instruction whose op0 isn't a reg
The simplest instance of this is an intrinsic with no results which will have the
intrinsic ID as operand 0.
Also fix some benign incorrectness when op0 is a reg but isn't a def that was
guarded against by checking for the extension opcodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343821
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Sanjay Patel [Thu, 4 Oct 2018 21:36:50 +0000 (21:36 +0000)]
[InstCombine] drop poison flags in SimplifyVectorDemandedElts
We established the (unfortunately complicated) rules for UB/poison
propagation with vector ops in:
D48893
D48987
D49047
It's clear from the affected tests that we are potentially creating
poison where none existed before the transforms. For add/sub/mul,
the answer is simple: just drop the flags because the extra undef
vector lanes are generally more valuable for analysis and codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343819
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Craig Topper [Thu, 4 Oct 2018 21:24:24 +0000 (21:24 +0000)]
[X86][LegalizeVectorOps] Use MERGE_VALUES to return two results from LowerLoad. Remove special case code in LegalizeVectorOps that allowed us to only return one result.
Previously we replaced the chain use ourself and return the data result. LegalizeVectorOps then detected that we'd done this and assumed the chain had already been handled.
This commit instead returns a MERGE_VALUES node with two results joined from nodes. This allows LegalizeVectorOps to do all the replacements for us without any special casing. The MERGE_VALUES will be removed by DAG combine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343817
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Craig Topper [Thu, 4 Oct 2018 21:11:52 +0000 (21:11 +0000)]
[SimplifyCFG] Change recursive calls to llvm::SimplifyCFG to instead use an outer while loop to revisit.
Summary:
The llvm::SimplifyCFG function creates a SimplifyCFGOpt object and calls run on it. There were numerous places reached from this run function that called back out llvm::SimplifyCFG which would create another SimplifyCFGOpt object. This is an inefficient use of stack space at minimum. We are also not passing along the LoopHeaders pointer passed into the outer llvm::SimplifyCFG call. So if its not null we lose it on the first recursion and get nullptr from there on.
This patch adds an outer loop around the main BasicBlock simplifying code and adds a flag to the SimplifyCFGOpt class that can be set by to request another iteration. I don't think we can iterate based just on the change flag alone since some of the simplifications delete a basic block entirely leaving nothing to iterate on.
Reviewers: bogner, eli.friedman, reames
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52760
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343816
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Heejin Ahn [Thu, 4 Oct 2018 21:03:35 +0000 (21:03 +0000)]
[WebAssembly] Don't modify preds/succs iterators while erasing from them
Summary:
This caused out-of-bound bugs. Found by
`-DLLVM_ENABLE_EXPENSIVE_CHECKS=ON`.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52902
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343814
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Konstantin Zhuravlyov [Thu, 4 Oct 2018 21:02:16 +0000 (21:02 +0000)]
AMDGPU: Rename isAmdCodeObjectV2 -> isAmdHsaOrMesa
The isAmdCodeObjectV2 is a misleading name which actually checks whether the os
is amdhsa or mesa.
Also add a test to make sure we do not generate old kernel header for code
object v3.
Differential Revision: https://reviews.llvm.org/D52897
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343813
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Martin Storsjo [Thu, 4 Oct 2018 20:43:38 +0000 (20:43 +0000)]
[COFF] [X86] Don't use llvm_unreachable for unsupported relocation types
This can happen if assembling a reference to _GLOBAL_OFFSET_TABLE_.
While it doesn't make sense to try to assemble that for COFF,
the fact that we previously used llvm_unreachable meant that the code
had undefined behaviour if something tried to assemble that.
The configure script of libgmp would try to assemble such a snippet
(which should signal a failure). If llvm is built without assertions,
the undefined behaviour meant a (near) infinite loop.
Differential Revision: https://reviews.llvm.org/D52903
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343811
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Sanjay Patel [Thu, 4 Oct 2018 19:12:07 +0000 (19:12 +0000)]
[InstCombine] reduce code duplication in SimplifyDemandedVectorElts; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343806
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James Y Knight [Thu, 4 Oct 2018 18:49:21 +0000 (18:49 +0000)]
Give same-named members unique timestamps on Darwin in llvm-ar.
This change ensures that the (membername,timestamp) tuple uniquely
identifies an entry in an archive for format=darwin, in deterministic
mode (which is the default).
That, then, enables lldb and dsymutil to locate the appropriate object
within the archive.
Differential Revision: https://reviews.llvm.org/D47659
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343805
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Daniel Sanders [Thu, 4 Oct 2018 18:44:58 +0000 (18:44 +0000)]
[globalisel][combine] Improve the truncate placement for the extending-loads combine
This brings the extending loads patch back to the original intent but minus the
PHI bug and with another small improvement to de-dupe truncates that are
inserted into the same block.
The truncates are sunk to their uses unless this would require inserting before a
phi in which case it sinks to the _beginning_ of the predecessor block for that
path (but no earlier than the def).
The reason for choosing the beginning of the predecessor is that it makes de-duping
multiple truncates in the same block simple, and optimized code is going to run a
scheduler at some point which will likely change the position anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343804
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Sanjay Patel [Thu, 4 Oct 2018 17:59:30 +0000 (17:59 +0000)]
[x86] add test for SSE sqrtss register dep (PR22206)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343803
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Matthias Braun [Thu, 4 Oct 2018 17:02:53 +0000 (17:02 +0000)]
AArch64: Fix XSeqPairs/WSeqPairs problems
- Fix spill/reloads of XSeqPairs failing with vregs (only physregs
worked correctly)
- Add missing spill/reload code for WSeqPairs class
Differential Revision: https://reviews.llvm.org/D52761
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343799
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Farhana Aleen [Thu, 4 Oct 2018 16:57:37 +0000 (16:57 +0000)]
[AMDGPU] Match signed dot4/8 pattern.
Summary: This patch matches signed dot4 and dot8 pattern.
Author: FarhanaAleen
Reviewed By: msearles
Differential Revision: https://reviews.llvm.org/D52520
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343798
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Simon Pilgrim [Thu, 4 Oct 2018 16:26:56 +0000 (16:26 +0000)]
[llvm-mca][x86] Add PR36951 ReadAfterLd test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343795
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Sanjay Patel [Thu, 4 Oct 2018 16:25:05 +0000 (16:25 +0000)]
[InstCombine] allow bitcast to/from FP for vector insert/extract transform
This is a follow-up to rL343482 / D52439.
This was a pattern that initially caused the commit to be reverted because
the transform requires a bitcast as shown here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343794
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Andrea Di Biagio [Thu, 4 Oct 2018 15:20:56 +0000 (15:20 +0000)]
[llvm-mca] Move field 'AllowZeroMoveEliminationOnly' to class RegisterFile. NFC.
Flag 'AllowZeroMoveEliminationOnly' should have been a property of the PRF, and
not set at register granularity.
This change also restricts move elimination to writes that update a full
physical register. We assume that there is a strong correlation between
logical registers that allow move elimination, and how those same registers are
allocated to physical registers by the register renamer.
This is still a no functional change, because this experimental code path is
disabled for now. This is done in preparation for another patch that will add
the ability to describe how move elimination works in scheduling models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343787
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Simon Pilgrim [Thu, 4 Oct 2018 15:06:09 +0000 (15:06 +0000)]
[X86][AVX] Add PR39161 test case for v4f64 zzww shuffle
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343786
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Greg Bedwell [Thu, 4 Oct 2018 14:42:19 +0000 (14:42 +0000)]
[utils] Ensure that update_mca_test_checks.py writes prefixes in alphabetical order
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343783
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Greg Bedwell [Thu, 4 Oct 2018 14:42:06 +0000 (14:42 +0000)]
[utils] simple refactor in update_mca_test_checks.py to make intent more readable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343782
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Alex Bradbury [Thu, 4 Oct 2018 14:30:03 +0000 (14:30 +0000)]
[RISCV] Remove overzealous is64Bit checks
lowerGlobalAddress, lowerBlockAddress, and insertIndirectBranch contain
overzealous checks for is64Bit. These functions are all safe as-implemented
for RV64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343781
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David Greene [Thu, 4 Oct 2018 14:07:59 +0000 (14:07 +0000)]
[X86] Set correct MMO offset on scalarized load pieces
When scalarizing a load, be sure to update the offset in the
MachineMemOperand for each scalar load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343776
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Simon Pilgrim [Thu, 4 Oct 2018 13:05:42 +0000 (13:05 +0000)]
[llvm-mca][x86] Add tests demonstrating ReadAfterLd delay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343773
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Fedor Sergeev [Thu, 4 Oct 2018 12:49:57 +0000 (12:49 +0000)]
[PassTimingInfo] cleanup on TimingData's Timer handling
Replacing Timer* with unique_ptr<Timer> in a pass-to-timer map.
That allows to get rid of unpretty raw deletes in PassTimingInfo destructor.
Strictly cleanup, not intended to change any visible behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343772
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Guillaume Chatelet [Thu, 4 Oct 2018 12:33:46 +0000 (12:33 +0000)]
[llvm-exegesis][NFC] Improve parsing of the YAML files
Summary: sscanf turns out to be slow for reading floating points.
Reviewers: courbet
Subscribers: tschuett, llvm-commits, RKSimon
Differential Revision: https://reviews.llvm.org/D52866
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343771
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Kristof Umann [Thu, 4 Oct 2018 12:33:33 +0000 (12:33 +0000)]
[doc] Update the programmer's manual about SmallSet's iterator
Since rL337818, you can now iterate the SmallSet.
Differential Revision: https://reviews.llvm.org/D52828
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343770
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Andrea Di Biagio [Thu, 4 Oct 2018 10:36:49 +0000 (10:36 +0000)]
[llvm-mca] Check for inconsistencies when constructing instruction descriptors.
This should help with catching inconsistent definitions of instructions with
zero opcodes, which also declare to consume scheduler/pipeline resources.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343766
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Simon Pilgrim [Thu, 4 Oct 2018 10:25:52 +0000 (10:25 +0000)]
Fix MSVC "not all control paths return a value" warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343765
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Alex Bradbury [Thu, 4 Oct 2018 07:35:52 +0000 (07:35 +0000)]
[RISCV][NFC] Remove dead CHECK lines from vararg.ll test
The RISCV32 check prefix is no longer used so these lines are dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343757
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Alex Bradbury [Thu, 4 Oct 2018 07:28:49 +0000 (07:28 +0000)]
[RISCV] Bugfix for floats passed on the stack with the ILP32 ABI on RV32F
f32 values passed on the stack would previously cause an assertion in
unpackFromMemLoc.. This would only trigger in the presence of the F extension
making f32 a legal type. Otherwise the f32 would be legalized.
This patch fixes that by keeping LocVT=f32 when a float is passed on the
stack. It also adds test coverage for this case, and tests that also
demonstrate lw/sw/flw/fsw will be selected when most profitable. i.e. there is
no unnecessary i32<->f32 conversion in registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343756
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Clement Courbet [Thu, 4 Oct 2018 07:07:16 +0000 (07:07 +0000)]
[llvm-exegesis][NFC] Test sched class names only in !NDEBUG mode.
Sched classes have no names in NDEBUG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343755
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Craig Topper [Thu, 4 Oct 2018 06:13:27 +0000 (06:13 +0000)]
[X86] Merge matchANDXORWithAllOnesAsANDNP into combineANDXORWithAllOnesIntoANDNP. NFCI
It's the only caller and the logic pretty easy to combine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343754
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Alex Bradbury [Thu, 4 Oct 2018 05:27:50 +0000 (05:27 +0000)]
[RISCV][NFC] Fix naming of RISCVISelLowering::{LowerRETURNADDR,LowerFRAMEADDR}
Rename to lowerRETURNADDR, lowerFRAMEADDR in order to be consistent with the
LLVM coding style and the other functions in this file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343752
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Fangrui Song [Thu, 4 Oct 2018 03:32:47 +0000 (03:32 +0000)]
[llvm-exegesis] Unbreak analysis-uops-variant.test introduced in D52825
A `defined(NDEBUG) && !defined(LLVM_ENABLE_DUMP)` build does not call
writeEscaped and there will be no `SBWriteZeroLatency` in the output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343751
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Craig Topper [Thu, 4 Oct 2018 02:40:35 +0000 (02:40 +0000)]
[LegalizeIntegerTypes] Fix typo in comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343750
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Derek Schuff [Wed, 3 Oct 2018 23:56:52 +0000 (23:56 +0000)]
[WebAssembly] Add WebAssembly to LLVM_ALL_TARGETS
Summary:
After fixing memory leaks in rL343362 and rL343733 the sanitizer builds are
clean and we should be good to build by default again.
Differential Revision: https://reviews.llvm.org/D52850
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343746
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Jordan Rupprecht [Wed, 3 Oct 2018 23:39:49 +0000 (23:39 +0000)]
[llvm-nm] Print an explicit "no symbols" message when an object file has no symbols
Summary:
GNU nm (and other nm implementations, such as "go tool nm") prints an explicit "no symbols" message when an object file has no symbols. Currently llvm-nm just doesn't print anything. Adding an explicit "no symbols" message will allow llvm-nm to be used in place of nm: some scripts and build processes use `nm <file> | grep "no symbols"` as a test to see if a file has no symbols. It will also be more familiar to anyone used to nm.
That said, the format implemented here is slightly different, in that it doesn't print the tool name in the message (which IMHO is not useful to include).
Demo:
```
$ for nm in nm bin/llvm-nm ; do echo "nm implementation: $nm"; $nm /tmp/foo{1,2}.o; echo; done
nm implementation: nm
/tmp/foo1.o:
nm: /tmp/foo1.o: no symbols
/tmp/foo2.o:
0000000000000000 T foo2
nm implementation: bin/llvm-nm
/tmp/foo1.o:
no symbols
/tmp/foo2.o:
0000000000000000 T foo2
```
Reviewers: MaskRay
Reviewed By: MaskRay
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52810
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343742
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Alex Bradbury [Wed, 3 Oct 2018 23:30:16 +0000 (23:30 +0000)]
[RISCV] Handle redundant SplitF64+BuildPairF64 pairs in a DAGCombine
r343712 performed this optimisation during instruction selection. As Eli
Friedman pointed out in post-commit review, implementing this as a DAGCombine
might allow opportunities for further optimisations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343741
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Thomas Lively [Wed, 3 Oct 2018 23:02:23 +0000 (23:02 +0000)]
[WebAssembly] Bitselect intrinsic and instruction
Summary: Depends on D52755.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52805
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343739
91177308-0d34-0410-b5e6-
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Alex Bradbury [Wed, 3 Oct 2018 22:53:25 +0000 (22:53 +0000)]
[RISCV][NFC] Refactor LocVT<->ValVT converstion in RISCVISelLowering
There was some duplicated logic for using the LocInfo of a CCValAssign in
order to convert from the ValVT to LocVT or vice versa. Resolve this by
factoring out convertLocVTFromValVT from unpackFromRegLoc. Also rename
packIntoRegLoc to the more appropriate convertValVTToLocVT and call these
helper functions consistently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343737
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Derek Schuff [Wed, 3 Oct 2018 22:22:48 +0000 (22:22 +0000)]
[WebAssembly] Refactor WasmSignature and use it for MCSymbolWasm
MCContext does not destroy MCSymbols on shutdown. So, rather than putting
SmallVectors (which may heap-allocate) inside MCSymbolWasm, use unowned pointer
to a WasmSignature instead. The signatures are now owned by the AsmPrinter.
Also uses WasmSignature instead of param and result vectors in TargetStreamer,
and leaves some TODOs for further simplification.
Differential Revision: https://reviews.llvm.org/D52580
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343733
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Daniel Sanders [Wed, 3 Oct 2018 22:05:31 +0000 (22:05 +0000)]
[machineverifier] Detect PHI's that are preceeded by non-PHI's
If present, PHI nodes must appear before non-PHI nodes in a basic block. The
register allocator relies on this and will fail to eliminate PHI's that do not
meet this requirement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343731
91177308-0d34-0410-b5e6-
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Simon Atanasyan [Wed, 3 Oct 2018 22:02:23 +0000 (22:02 +0000)]
[mips] Remove -allow-deprecated-dag-overlap flag from tests. NFC
Fix DAG check statements in MIPS codegen tests to remove
-allow-deprecated-dag-overlap flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343730
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Sanjay Patel [Wed, 3 Oct 2018 21:44:59 +0000 (21:44 +0000)]
[InstCombine] allow SimplifyDemandedVectorElts to work with FP binops
We're a long way from D50992 and D51553, but this is where we have to start.
We weren't back-propagating undefs into binop constant values for anything but
add/sub/mul/and/or/xor.
This is likely because we have to be careful about not introducing UB/poison
with div/rem/shift. But I suspect we already are getting the poison part wrong
for add/sub/mul (although it may not be possible to expose the bug currently
because we use SimplifyDemandedVectorElts from a limited set of opcodes).
See the discussion/implementation from D48987 and D49047.
This patch just enables functionality for FP ops because those do not have
UB/poison potential.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343727
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Heejin Ahn [Wed, 3 Oct 2018 21:30:15 +0000 (21:30 +0000)]
Make meanings of variables clearer in action table generation (NFC)
Summary:
Reviewers: kristina, zhmu, dschuff, rnk
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52680
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343724
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Craig Topper [Wed, 3 Oct 2018 21:10:29 +0000 (21:10 +0000)]
[X86] Stop promoting vector ISD::SELECT to vXi64.
The additional patterns needed for this aren't overwhelming and introducing extra bitcasts during lowering limits our ability to do computeNumSignBits. Not that I have a good example of that for select. I'm just becoming increasingly grumpy about promotion of AND/OR/XOR. SELECT was just a lot easier to fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343723
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Sanjay Patel [Wed, 3 Oct 2018 20:35:25 +0000 (20:35 +0000)]
[InstCombine] add tests for binop undef-into-constant propagation; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343714
91177308-0d34-0410-b5e6-
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Craig Topper [Wed, 3 Oct 2018 20:28:43 +0000 (20:28 +0000)]
[X86] Add CMOV_VK2/VK4 pseudos and remove lowering code that turned v2i1/v4i1 SELECT into v8i1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343713
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Alex Bradbury [Wed, 3 Oct 2018 20:12:10 +0000 (20:12 +0000)]
[RISCV][NFCI] Handle redundant splitf64+buildpairf64 pairs during instruction selection
Although we can't write a tablegen pattern to remove redundant
splitf64+buildf64 pairs due to the multiple return values, we can handle it
with some C++ selection code. This is simpler than removing them after
instruction selection through RISCVDAGToDAGISel::PostprocessISelDAG, as was
done previously.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343712
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Craig Topper [Wed, 3 Oct 2018 19:48:26 +0000 (19:48 +0000)]
[X86] Add CMOV pseudos for VR128X and VR256X register classes. Use them when AVX512VL is enabled.
This allows the phi nodes to be generated with the correct register class when expanded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343710
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Craig Topper [Wed, 3 Oct 2018 19:48:23 +0000 (19:48 +0000)]
[X86] Don't break CMOV pseudo instructions down by type. Just by register class.
The register class is all that's important for the pseudo instructions. We can use patterns to handle the different types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343709
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Simon Pilgrim [Wed, 3 Oct 2018 19:02:38 +0000 (19:02 +0000)]
[X86] PUSH/POP 'mem-mem' instructions are not RMW - these are 2 different addresses
This patch adds a 'WriteCopy' [WriteLoad, WriteStore] schedule sequence instead to better model the behaviour
Found by @andreadb during llvm-mca testing on btver2 which was crashing on "zero uop" WriteRMW only instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343708
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Matthew Voss [Wed, 3 Oct 2018 18:44:53 +0000 (18:44 +0000)]
Emit template type and value parameter DIEs for template variables.
Summary:
Ensure the TemplateParam attribute of the DIGlobalVariable node is translated into the proper DIEs.
Resolves https://bugs.llvm.org/show_bug.cgi?id=22119
Reviewers: dblaikie, probinson, aprantl, JDevlieghere, clayborg, whitequark, deadalnix
Reviewed By: dblaikie
Subscribers: llvm-commits
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D52057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343706
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Simon Pilgrim [Wed, 3 Oct 2018 18:38:28 +0000 (18:38 +0000)]
[X86] Move Atomic binops to use WriteALURMW schedule class
These were being tagged as <WriteALULd, WriteRMW> instead of properly using the RMW sequence
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343705
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Simon Pilgrim [Wed, 3 Oct 2018 18:18:50 +0000 (18:18 +0000)]
[X86][Btver2] Fix MMX PSHUFB schedule
Match AMD Fam16h SOG + llvm-exegesis tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343701
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Simon Pilgrim [Wed, 3 Oct 2018 18:05:01 +0000 (18:05 +0000)]
[X86] Move Atomic CMPXCHG to WriteCMPXCHGRMW schedule class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343700
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Simon Pilgrim [Wed, 3 Oct 2018 16:45:26 +0000 (16:45 +0000)]
[X86] Add SkylakeClient uops counter - same as the other Intel models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343697
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Daniel Sanders [Wed, 3 Oct 2018 16:29:24 +0000 (16:29 +0000)]
Correct implementation of -verify-machineinstrs such that it's still overridable for EXPENSIVE_CHECKS
-verify-machineinstrs was implemented as a simple bool. As a result, the
'VerifyMachineCode == cl::BOU_UNSET' used by EXPENSIVE_CHECKS to make it on by
default but possible to disable didn't work as intended. Changed
-verify-machineinstrs to a boolOrDefault to correct this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343696
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Sanjay Patel [Wed, 3 Oct 2018 15:46:03 +0000 (15:46 +0000)]
[InstCombine] clean up foldVectorBinop(); NFC
1. Fix include ordering.
2. Improve variable name (width is bitwidth not number-of-elements).
3. Add local Opcode variable to reduce code duplication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343694
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Daniel Sanders [Wed, 3 Oct 2018 15:43:39 +0000 (15:43 +0000)]
[globalisel][combines] Don't sink G_TRUNC down to use if that use is a G_PHI
This fixes a problem where the register allocator fails to eliminate a PHI
because there's a non-PHI in the middle of the PHI instructions at the start
of a BB.
This G_TRUNC can be better placed but this at least fixes the correctness issue
quickly. I'll follow up with a patch to the verifier to catch this kind of bug
in future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343693
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Sanjay Patel [Wed, 3 Oct 2018 15:20:58 +0000 (15:20 +0000)]
[InstCombine] name change: foldShuffledBinop -> foldVectorBinop; NFC
This function will deal with more than shuffles with D50992, and I
have another potential per-element fold that could live here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343692
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Andrea Di Biagio [Wed, 3 Oct 2018 15:02:44 +0000 (15:02 +0000)]
[llvm-mca] Add support for move elimination in class RegisterFile.
This patch teaches class RegisterFile how to analyze register writes from
instructions that are move elimination candidates.
In particular, it teaches it how to check if a move can be effectively eliminated
by the underlying PRF, and (if necessary) how to perform move elimination.
The long term goal is to allow processor models to describe instructions that
are valid move elimination candidates.
The idea is to let register file definitions in tablegen declare if/when moves
can be eliminated.
This patch is a non functional change.
The logic that performs move elimination is currently disabled. A future patch
will add support for move elimination in the processor models, and enable this
new code path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343691
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Simon Pilgrim [Wed, 3 Oct 2018 14:51:09 +0000 (14:51 +0000)]
[llvm-exegesis] Avoid yaml parser from calling sscanf for obvious non-matches (PR39102)
deserializeMCOperand - ensure that we at least match the first character of the sscanf pattern before calling
This reduces llvm-exegesis uops analysis of the instructions supported from btver2 from 5m13s to 2m1s on debug builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343690
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Nirav Dave [Wed, 3 Oct 2018 14:13:30 +0000 (14:13 +0000)]
[X86] Correctly use SSE registers if no-x87 is selected.
Fix use of SSE1 registers for f32 ops in no-x87 mode.
Notably, allow use of SSE instructions for f32 operations in 64-bit
mode (but not 32-bit which is disallowed by callign convention).
Also avoid translating memset/memcopy/memmove into SSE registers
without X87 for 32-bit mode.
This fixes PR38738.
Reviewers: nickdesaulniers, craig.topper
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D52555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343689
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Alex Bradbury [Wed, 3 Oct 2018 13:13:13 +0000 (13:13 +0000)]
[RISCV][NFC] Refactor RISCVDAGToDAGISel::Select
Introduce and use a switch on the opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343688
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James Henderson [Wed, 3 Oct 2018 13:00:20 +0000 (13:00 +0000)]
[ThinLTO]Expose cache entry expiration time option in llvm-lto and fix a test
Two cases in a ThinLTO test were passing for the wrong reasons, since
rL340374. The tests were supposed to be testing that files were being
pruned due to the cache size, but they were in fact being pruned because
they were older than the default expiration period of 1 week.
This change fixes the tests by explicitly setting the expiration time to
the maximum value. This required the option to be exposed in llvm-lto.
By assigning all files in the cache a similar time, it is possible to see
that the newest files are still being kept, and that we aren't passing
for the wrong reason again. In the event that the entry expiration were
to expire for them, then the test would start failing, because these
files would be removed too.
Reviewed by: rnk, inglorion
Differential Revision: https://reviews.llvm.org/D51992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343687
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Jonas Paulsson [Wed, 3 Oct 2018 12:51:19 +0000 (12:51 +0000)]
[RA CopyHints] Fix compile-time regression
This patch makes sure that a register is only hinted once to RA. In extreme
cases the same register can otherwise be hinted numerous times and cause a
compile time slowdown.
Review: Simon Pilgrim
https://reviews.llvm.org/D52826
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343686
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Clement Courbet [Wed, 3 Oct 2018 12:48:50 +0000 (12:48 +0000)]
[llvm-exegesis][NFC] Revert rL343682 "Fix unused variable warning".
That was not the proper fix: the variable is used in debug mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343685
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Clement Courbet [Wed, 3 Oct 2018 12:35:35 +0000 (12:35 +0000)]
[llvm-exegesis] Fix rL343680 in release mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343684
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Clement Courbet [Wed, 3 Oct 2018 12:27:43 +0000 (12:27 +0000)]
[llvm-exegesis][NFC] Fix unused variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343682
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Clement Courbet [Wed, 3 Oct 2018 11:50:25 +0000 (11:50 +0000)]
[llvm-exegesis] Resolve variant classes in analysis.
Summary: See PR38884.
Reviewers: gchatelet
Subscribers: tschuett, RKSimon, llvm-commits
Differential Revision: https://reviews.llvm.org/D52825
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343680
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Alex Bradbury [Wed, 3 Oct 2018 11:35:22 +0000 (11:35 +0000)]
[RISCV] Gate float<->int and double<->int conversion patterns on IsRV32
The patterns as defined are correct only when XLen==32.
This is another preparatory patch for a set of patches that flesh out RV64
codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343679
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Alex Bradbury [Wed, 3 Oct 2018 11:14:26 +0000 (11:14 +0000)]
[RISCV] Remove XLenVT==i32 assumptions from RISCVInstrInfo td
1. brcond operates on an condition.
2. atomic_fence and the pseudo AMO instructions should all take xlen immediates
This allows the same definitions and patterns to work for RV64 (XLenVT==i64).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343678
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Alex Bradbury [Wed, 3 Oct 2018 11:04:59 +0000 (11:04 +0000)]
[RISCV] Gate simm32 materialisation pattern and SW pattern on IsRV32
These patterns are not correct for RV64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343677
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Florian Hahn [Wed, 3 Oct 2018 11:01:23 +0000 (11:01 +0000)]
[LoopInterchange] Remove unused variable PreserveLCSSA (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343676
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Alex Bradbury [Wed, 3 Oct 2018 10:59:42 +0000 (10:59 +0000)]
[RISCV] Remove RV64 test lines from umulo-128-legalisation-lowering.ll
The generated code is incorrect anyway, and this test adds noise to the
upcoming set of patches that flesh out RV64 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343675
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Jonas Toth [Wed, 3 Oct 2018 10:59:19 +0000 (10:59 +0000)]
[CodeGen] NFC fix pedantic warning from extra semicolon
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343674
91177308-0d34-0410-b5e6-
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Tim Renouf [Wed, 3 Oct 2018 10:29:43 +0000 (10:29 +0000)]
[AMDGPU] Fix for negative offsets in buffer/tbuffer intrinsics
Summary:
The new buffer/tbuffer intrinsics handle an out-of-range immediate
offset by moving/adding offset&-4096 to a vgpr, leaving an in-range
immediate offset, with a chance of the move/add being CSEd for similar
loads/stores.
However it turns out that a negative offset in a vgpr is illegal, even
if adding the immediate offset makes it legal again.
Therefore, this commit disables the offset&-4096 thing if the offset is
negative.
Differential Revision: https://reviews.llvm.org/D52683
Change-Id: Ie02f0a74f240a138dc2a29d17cfbd9e350e4ed13
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343672
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Simon Pilgrim [Wed, 3 Oct 2018 10:28:43 +0000 (10:28 +0000)]
[X86][Btver2] Most RMW instructions don't require an additional uop
Remove uop on WriteRMW and move it into the few instructions that need it.
Match AMD Fam16h SOG + llvm-exegesis tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343671
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Simon Pilgrim [Wed, 3 Oct 2018 10:01:13 +0000 (10:01 +0000)]
[X86] ALU/ADC RMW instructions should use the WriteRMW sequence class
I was expecting this to be a nfc but Silvermont seems to be setup a little differently:
// A folded store needs a cycle on MEC_RSV for the store data, but it does not need an extra port cycle to recompute the address.
def : WriteRes<WriteRMW, [SLM_MEC_RSV]>;
So moving from WriteStore to WriteRMW reduces predicted port pressure, confirmed by @craig.topper that this is correct.
Differential Revision: https://reviews.llvm.org/D52740
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343670
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Aditya Kumar [Wed, 3 Oct 2018 06:21:05 +0000 (06:21 +0000)]
Improve static analysis of cold basic blocks
Differential Revision: https://reviews.llvm.org/D52704
Reviewers: sebpop, tejohnson, brzycki, SirishP
Reviewed By: sebpop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343663
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Aditya Kumar [Wed, 3 Oct 2018 05:55:20 +0000 (05:55 +0000)]
Add support for new pass manager
Modified the testcases to use both pass managers
Use single commandline flag for both pass managers.
Differential Revision: https://reviews.llvm.org/D52708
Reviewers: sebpop, tejohnson, brzycki, SirishP
Reviewed By: tejohnson, brzycki
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343662
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Fangrui Song [Wed, 3 Oct 2018 03:38:22 +0000 (03:38 +0000)]
[AMDGPU] Rename pass "isel" to "amdgpu-isel"
Summary: The AMDGPU target specific pass "isel" is a misleading name.
Reviewers: tstellar, echristo, javed.absar, arsenm
Reviewed By: arsenm
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D52759
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343659
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Daniel Sanders [Wed, 3 Oct 2018 02:52:54 +0000 (02:52 +0000)]
[globalisel] Fix one more missing Verifier pass from gisel-commandline-option.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343658
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Matt Arsenault [Wed, 3 Oct 2018 02:47:25 +0000 (02:47 +0000)]
AMDGPU: Always run AMDGPUAlwaysInline
Even if calls are enabled, it still needs to be run
for forcing inline of functions that use LDS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343657
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Wed, 3 Oct 2018 02:37:15 +0000 (02:37 +0000)]
Add atomicrmw operation to error messages
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343656
91177308-0d34-0410-b5e6-
96231b3b80d8