OSDN Git Service

android-x86/external-llvm.git
6 years ago[ARM] Select result 1 from ConvertBooleanCarryToCarryFlag's result automatically...
Amaury Sechet [Mon, 7 May 2018 01:43:42 +0000 (01:43 +0000)]
[ARM] Select result 1 from ConvertBooleanCarryToCarryFlag's result automatically. NFC

The old behavior return the value 0, which is error prone.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331614 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[TargetLowering] Use StringRef::split instead of SplitString. NFC
Craig Topper [Mon, 7 May 2018 01:32:18 +0000 (01:32 +0000)]
[TargetLowering] Use StringRef::split instead of SplitString. NFC

SplitString splits based on a list of delimeters, but we're only using one delimeter so we should use the simpler split.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331613 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Fix copy/paste mistake in comment. NFC
Craig Topper [Mon, 7 May 2018 00:47:02 +0000 (00:47 +0000)]
[X86] Fix copy/paste mistake in comment. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331611 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-dwp] Define InitLLVM.
Fangrui Song [Sun, 6 May 2018 23:08:29 +0000 (23:08 +0000)]
[llvm-dwp] Define InitLLVM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331610 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[NFC][DAGCombine] unfoldMaskedMerge(): rename two variables
Roman Lebedev [Sun, 6 May 2018 20:02:22 +0000 (20:02 +0000)]
[NFC][DAGCombine] unfoldMaskedMerge(): rename two variables

The current names can be confused with the A and B sides
of the canonical masked merge pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331609 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Enable reciprocal estimates for v16f32 vectors by using VRCP14PS/VRSQRT14PS
Craig Topper [Sun, 6 May 2018 17:48:21 +0000 (17:48 +0000)]
[X86] Enable reciprocal estimates for v16f32 vectors by using VRCP14PS/VRSQRT14PS

Summary:
The legacy VRCPPS/VRSQRTPS instructions aren't available in 512-bit versions. The new increased precision versions are. So we can use those to implement v16f32 reciprocal estimates.

For KNL CPUs we can probably use VRCP28PS/VRSQRT28PS and avoid the NR step altogether, but I leave that for a future patch.

Reviewers: spatel

Reviewed By: spatel

Subscribers: RKSimon, llvm-commits, mehdi_amini

Differential Revision: https://reviews.llvm.org/D46498

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331606 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Add test cases for reciprocal estimation for v16f32 vectors with AVX512F.
Craig Topper [Sun, 6 May 2018 17:45:40 +0000 (17:45 +0000)]
[X86] Add test cases for reciprocal estimation for v16f32 vectors with AVX512F.

We should be able to use the vrsqrt14ps and vrcp14ps instructions for these cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331605 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAdd test cases for large integer legalization of add and sub. NFC
Amaury Sechet [Sun, 6 May 2018 16:00:23 +0000 (16:00 +0000)]
Add test cases for large integer legalization of add and sub. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331604 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[globalisel] Remove redundant -global-isel option from tests that use -run-pass. NFC
Daniel Sanders [Sat, 5 May 2018 21:19:59 +0000 (21:19 +0000)]
[globalisel] Remove redundant -global-isel option from tests that use -run-pass. NFC

As Roman Tereshin pointed out in https://reviews.llvm.org/D45541, the
-global-isel option is redundant when -run-pass is given. -global-isel sets up
the GlobalISel passes in the pass manager but -run-pass skips that entirely and
configures it's own pipeline.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331603 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[MC] Remove unused MCOI::GenericOperandType
Fangrui Song [Sat, 5 May 2018 20:54:03 +0000 (20:54 +0000)]
[MC] Remove unused MCOI::GenericOperandType

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331602 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[globalisel] Update GlobalISel emitter to match new representation of extending loads
Daniel Sanders [Sat, 5 May 2018 20:53:24 +0000 (20:53 +0000)]
[globalisel] Update GlobalISel emitter to match new representation of extending loads

Summary:
Previously, a extending load was represented at (G_*EXT (G_LOAD x)).
This had a few drawbacks:
* G_LOAD had to be legal for all sizes you could extend from, even if
  registers didn't naturally hold those sizes.
* All sizes you could extend from had to be allocatable just in case the
  extend went missing (e.g. by optimization).
* At minimum, G_*EXT and G_TRUNC had to be legal for these sizes. As we
  improve optimization of extends and truncates, this legality requirement
  would spread without considerable care w.r.t when certain combines were
  permitted.
* The SelectionDAG importer required some ugly and fragile pattern
  rewriting to translate patterns into this style.

This patch changes the representation to:
* (G_[SZ]EXTLOAD x)
* (G_LOAD x) any-extends when MMO.getSize() * 8 < ResultTy.getSizeInBits()
which resolves these issues by allowing targets to work entirely in their
native register sizes, and by having a more direct translation from
SelectionDAG patterns.

Each extending load can be lowered by the legalizer into separate extends
and loads, however a target that supports s1 will need the any-extending
load to extend to at least s8 since LLVM does not represent memory accesses
smaller than 8 bit. The legalizer can widenScalar G_LOAD into an
any-extending load but sign/zero-extending loads need help from something
else like a combiner pass. A follow-up patch that adds combiner helpers for
for this will follow.

The new representation requires that the MMO correctly reflect the memory
access so this has been corrected in a couple tests. I've also moved the
extending loads to their own tests since they are (mostly) separate opcodes
now. Additionally, the re-write appears to have invalidated two tests from
select-with-no-legality-check.mir since the matcher table no longer contains
loads that result in s1's and they aren't legal in AArch64 anymore.

Depends on D45540

Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, javed.absar

Reviewed By: rtereshin

Subscribers: javed.absar, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D45541

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331601 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[MIRPraser] Improve error checking for typed immediate operands
Heejin Ahn [Sat, 5 May 2018 20:53:23 +0000 (20:53 +0000)]
[MIRPraser] Improve error checking for typed immediate operands

Summary:
This improves error checks for typed immediate operands introduced in
D45948 (rL331586), and removes a code block copied by mistake.

Reviewers: rtereshin

Subscribers: dschuff, sbc100, jgravelle-google, llvm-commits

Differential Revision: https://reviews.llvm.org/D46491

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331600 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoSimplify LLVM_ATTRIBUTE_USED call sites.
Fangrui Song [Sat, 5 May 2018 20:14:38 +0000 (20:14 +0000)]
Simplify LLVM_ATTRIBUTE_USED call sites.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331599 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[DAGCombiner] Masked merge: don't touch "not" xor's.
Roman Lebedev [Sat, 5 May 2018 15:45:40 +0000 (15:45 +0000)]
[DAGCombiner] Masked merge: don't touch "not" xor's.

Summary:
Split off form D46031.

It seems we don't want to transform the pattern if the `xor`'s are actually `not`'s.
In vector case, this breaks `andnpd` / `vandnps` patterns.

That being said, we may want to re-visit this `not` handling, maybe in D46073.

Reviewers: spatel, craig.topper, javed.absar

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46492

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331595 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-mca] removes flag -instruction-tables from the "View Options" category.
Andrea Di Biagio [Sat, 5 May 2018 15:36:47 +0000 (15:36 +0000)]
[llvm-mca] removes flag -instruction-tables from the "View Options" category.

This patch also improves the description of a couple of flags in the view
options. With this change, the -help now specifies which views are enabled by
default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331594 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[LTO] Handle Task=-1 passed to addSaveTemps
Teresa Johnson [Sat, 5 May 2018 14:37:20 +0000 (14:37 +0000)]
[LTO] Handle Task=-1 passed to addSaveTemps

Summary:
This change is necessary for D46464, which will pass -1 as the Task
ID for distributed backends, so that the save temps files don't end
up with "4294967295" in their path. For distributed back ends, when -1
is passed, don't append any Task ID.

An existing test (tools/clang/test/CodeGen/thinlto_backend.ll) will
fail without this change after D46464.

Reviewers: pcc

Subscribers: mehdi_amini, inglorion, llvm-commits

Differential Revision: https://reviews.llvm.org/D46488

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331591 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-mca] minor tweak to the resource pressure printing functionality. NFC.
Andrea Di Biagio [Sat, 5 May 2018 12:21:54 +0000 (12:21 +0000)]
[llvm-mca] minor tweak to the resource pressure printing functionality. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331590 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[NFC][DagCombiner] unfoldMaskedMerge(): improve readability.
Roman Lebedev [Sat, 5 May 2018 10:39:54 +0000 (10:39 +0000)]
[NFC][DagCombiner] unfoldMaskedMerge(): improve readability.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331588 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[CaptureTracking] Handle capturing of launder.invariant.group
Piotr Padlewski [Sat, 5 May 2018 10:23:27 +0000 (10:23 +0000)]
[CaptureTracking] Handle capturing of launder.invariant.group

Summary:
launder.invariant.group has the same rules of capturing as
bitcast, gep, etc - the original value is not captured
if the returned pointer is not captured.

With this patch, we mark 40% more functions as noalias when compiling with -fstrict-vtable-pointers;
1078 vs 1778  (39.37%)

Reviewers: sanjoy, davide, nlewycky, majnemer, mehdi_amini

Subscribers: JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D32673

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331587 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[MIRParser] Allow register class names in the form of integer/scalar
Heejin Ahn [Sat, 5 May 2018 07:05:51 +0000 (07:05 +0000)]
[MIRParser] Allow register class names in the form of integer/scalar

Summary:
The current code cannot handle register class names like 'i32', which is
a valid register class name in WebAssembly. This patch removes special
handling for integer/scalar/pointer type parsing and treats them as
normal identifiers.

Reviewers: thegameg

Subscribers: jfb, dschuff, sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D45948

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331586 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Option] Remove an unnecessary conversion function.
Fangrui Song [Sat, 5 May 2018 06:05:31 +0000 (06:05 +0000)]
[Option] Remove an unnecessary conversion function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331585 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRange-ify for loop; NFC
George Burgess IV [Sat, 5 May 2018 04:52:26 +0000 (04:52 +0000)]
Range-ify for loop; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331582 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoGlobalISel/InstructionSelector: Implement GIR_CopyFConstantAsFPImm
Tom Stellard [Sat, 5 May 2018 02:52:41 +0000 (02:52 +0000)]
GlobalISel/InstructionSelector: Implement GIR_CopyFConstantAsFPImm

Summary: AMDGPU will need this to enable the TableGen'd GlobalISel selector.

Reviewers: dsanders, aditya_nandakumar

Reviewed By: dsanders

Subscribers: rovka, kristof.beyls, tpr, llvm-commits

Differential Revision: https://reviews.llvm.org/D45990

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331579 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFix a bunch of places where operator-> was used directly on the return from dyn_cast.
Craig Topper [Sat, 5 May 2018 01:57:00 +0000 (01:57 +0000)]
Fix a bunch of places where operator-> was used directly on the return from dyn_cast.

Inspired by r331508, I did a grep and found these.

Mostly just change from dyn_cast to cast. Some cases also showed a dyn_cast result being converted to bool, so those I changed to isa.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331577 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoLowerTypeTests: Fix non-determinism in code that handles icall branch funnels.
Peter Collingbourne [Sat, 5 May 2018 00:51:55 +0000 (00:51 +0000)]
LowerTypeTests: Fix non-determinism in code that handles icall branch funnels.

This was exposed by enabling expensive checks, which causes llvm::sort
to sort randomly.

Differential Revision: https://reviews.llvm.org/D45901

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331573 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[LTO] Allow pass remarks with hotness to be set when emitting to stderr
Teresa Johnson [Fri, 4 May 2018 23:59:34 +0000 (23:59 +0000)]
[LTO] Allow pass remarks with hotness to be set when emitting to stderr

Summary:
Set setDiagnosticsHotnessRequested before the early exit check for a
diagnostic output file, so that pass remarks with hotness works when
emitting pass remarks to stderr (e.g. via -pass-remarks=.).

Also fix the llvm-lto2 diagnistic handler so that it only calls exit(1)
when the diagnistic is an error type. Otherwise the new test invocation
of llvm-lto2 with -pass-remarks causes it to fail. The new code is
consistent with the diagnostic handler elsewhere (e.g. on the
LLVMContext).

Reviewers: pcc, davide

Subscribers: fhahn, mehdi_amini, llvm-commits, inglorion

Differential Revision: https://reviews.llvm.org/D46387

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331569 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-mc-assemble-fuzzer] Catch up with API changes.
Davide Italiano [Fri, 4 May 2018 23:41:25 +0000 (23:41 +0000)]
[llvm-mc-assemble-fuzzer] Catch up with API changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331568 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoMapping SDNode flags to MachineInstr flags
Michael Berg [Fri, 4 May 2018 23:41:15 +0000 (23:41 +0000)]
Mapping SDNode flags to MachineInstr flags

Summary: Providing the glue to map SDNode fast math sub flags to MachineInstr fast math sub flags.

Reviewers: spatel, arsenm, wristow

Reviewed By: spatel

Subscribers: wdng

Differential Revision: https://reviews.llvm.org/D46447

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331567 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAMDGPU/NFC: Update D16PreservesUnusedBits description based Tony Tye's comments
Konstantin Zhuravlyov [Fri, 4 May 2018 22:53:55 +0000 (22:53 +0000)]
AMDGPU/NFC: Update D16PreservesUnusedBits description based Tony Tye's comments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331564 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[LICM] Compute a must execute property for the prefix of the header as we go
Philip Reames [Fri, 4 May 2018 21:35:00 +0000 (21:35 +0000)]
[LICM] Compute a must execute property for the prefix of the header as we go

Computing this property within the existing walk ensures that the cost is linear with the size of the block. If we did this from within isGuaranteedToExecute, it would be quadratic without some very fancy caching.

This allows us to reliably catch a hoistable instruction within a header which may throw at some point *after* our hoistable instruction. It doesn't do anything for non-header cases, but given how common single block loops are, this seems very worthwhile.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331557 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAMDGPU/NFC: Fix formatting for 900, 902 ISA Version features
Konstantin Zhuravlyov [Fri, 4 May 2018 20:21:31 +0000 (20:21 +0000)]
AMDGPU/NFC: Fix formatting for 900, 902 ISA Version features

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331553 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAMDGPU: Add D16 instructions preserve unused bits feature
Konstantin Zhuravlyov [Fri, 4 May 2018 20:06:57 +0000 (20:06 +0000)]
AMDGPU: Add D16 instructions preserve unused bits feature

- Predicate D16 patterns on this new feature
- Added this new feature to gfx900/2/4

Differential Revision: https://reviews.llvm.org/D46366

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331551 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[MachineLICM] Debug intrinsics shouldn't affect hoist decisions
Geoff Berry [Fri, 4 May 2018 19:25:09 +0000 (19:25 +0000)]
[MachineLICM] Debug intrinsics shouldn't affect hoist decisions

Summary:
When checking if an instruction stores to a given frame index, check
that the instruction can write to memory before looking at the memory
operands list to avoid e.g. DBG_VALUE instructions that reference a
frame index preventing a load from that index from being hoisted.

Reviewers: dblaikie, MatzeB, qcolombet, reames, javed.absar

Subscribers: mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D46284

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331549 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ObjCARC] Account for catchswitch in bitcast insertion
Shoaib Meenai [Fri, 4 May 2018 19:03:11 +0000 (19:03 +0000)]
[ObjCARC] Account for catchswitch in bitcast insertion

A catchswitch is both a pad and a terminator, meaning it must be the
only non-phi instruction in its basic block. When we're inserting a
bitcast in the incoming basic block for a phi, if that incoming block is
a catchswitch, we should go up the dominator tree to find a valid
insertion point rather than attempting to insert before the catchswitch
(which would result in invalid IR).

Differential Revision: https://reviews.llvm.org/D46412

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331548 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFast Math Flag mapping into SDNode
Michael Berg [Fri, 4 May 2018 18:48:20 +0000 (18:48 +0000)]
Fast Math Flag mapping into SDNode

Summary: Adding support for Fast flags in the SDNode to leverage fast math sub flag usage.

Reviewers: spatel, arsenm, jbhateja, hfinkel, escha, qcolombet, echristo, wristow, javed.absar

Reviewed By: spatel

Subscribers: llvm-commits, rampitec, nhaehnle, tstellar, FarhanaAleen, nemanjai, javed.absar, jbhateja, hfinkel, wdng

Differential Revision: https://reviews.llvm.org/D45710

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331547 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Add WriteEMMS scheduler class
Simon Pilgrim [Fri, 4 May 2018 18:16:13 +0000 (18:16 +0000)]
[X86] Add WriteEMMS scheduler class

Filled in the missing values from Btver2 SoG or Agner

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331546 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Finish splitting WriteVecShift and WriteVecIMul to remove InstRW overrides.
Simon Pilgrim [Fri, 4 May 2018 17:47:46 +0000 (17:47 +0000)]
[X86] Finish splitting WriteVecShift and WriteVecIMul to remove InstRW overrides.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331543 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[LoopIdiomRecognize] Don't create an IRBuilder just to call getTrue/getFalse.
Craig Topper [Fri, 4 May 2018 17:39:08 +0000 (17:39 +0000)]
[LoopIdiomRecognize] Don't create an IRBuilder just to call getTrue/getFalse.

We can call the methods in ConstantInt directly. We just need a context.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331542 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AArch64] Add missing testcase for r331522
Adhemerval Zanella [Fri, 4 May 2018 17:21:26 +0000 (17:21 +0000)]
[AArch64] Add missing testcase for r331522

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331541 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-mca] Add descriptive names for the TimelineView report characters. NFC.
Matt Davis [Fri, 4 May 2018 17:19:40 +0000 (17:19 +0000)]
[llvm-mca] Add descriptive names for the TimelineView report characters. NFC.

Summary:
This change makes the TimelineView source simpler to read and easier to modify in the future.
This patch introduces a class of static chars used as the display values in the TimelineView report, this change just eliminates a few magic characters.

Reviewers: andreadb, courbet, RKSimon

Reviewed By: andreadb

Subscribers: tschuett, gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D46409

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331540 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoObject: The default alignment of a section without alignment flags is 16.
Peter Collingbourne [Fri, 4 May 2018 16:45:57 +0000 (16:45 +0000)]
Object: The default alignment of a section without alignment flags is 16.

Differential Revision: https://reviews.llvm.org/D46420

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331538 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoobj2yaml: Correctly round-trip default alignment.
Peter Collingbourne [Fri, 4 May 2018 16:28:41 +0000 (16:28 +0000)]
obj2yaml: Correctly round-trip default alignment.

Previously we were emitting the "cooked" alignment, which made it hard
to distinguish between that and the default alignment.

Differential Revision: https://reviews.llvm.org/D46418

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331537 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoDwarfCompileUnit: Fix another assertion failure on malformed input
Adrian Prantl [Fri, 4 May 2018 16:10:43 +0000 (16:10 +0000)]
DwarfCompileUnit: Fix another assertion failure on malformed input
that is not rejected by the Verifier.

Thanks to Björn Pettersson for providing a reproducer!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331535 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-exegesis] Fix pfm counter names for BDW.
Clement Courbet [Fri, 4 May 2018 15:26:12 +0000 (15:26 +0000)]
[llvm-exegesis] Fix pfm counter names for BDW.

Summary: They are not consistent with other microarchitectures.

Reviewers: gchatelet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D46434

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331532 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Cleanup SchedWriteFMA classes and use X86SchedWriteWidths directly.
Simon Pilgrim [Fri, 4 May 2018 15:20:18 +0000 (15:20 +0000)]
[X86] Cleanup SchedWriteFMA classes and use X86SchedWriteWidths directly.

Rename scalar and XMM versions, this is to match/simplify an upcoming change to split MUL/DIV/SQRT scalar/xmm/ymm/zmm classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331531 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[bindings/go] Add Go bindings for volatile loads/stores
David Bolvansky [Fri, 4 May 2018 15:14:00 +0000 (15:14 +0000)]
[bindings/go] Add Go bindings for volatile loads/stores

Reviewers: whitequark

Reviewed By: whitequark

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46235

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331530 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Hexagon] Remove leftover debugging code after r331527
Krzysztof Parzyszek [Fri, 4 May 2018 15:07:30 +0000 (15:07 +0000)]
[Hexagon] Remove leftover debugging code after r331527

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331528 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Hexagon] Handle non-immediate constants in HexagonSplitDouble
Krzysztof Parzyszek [Fri, 4 May 2018 15:04:48 +0000 (15:04 +0000)]
[Hexagon] Handle non-immediate constants in HexagonSplitDouble

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331527 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[mips] Correct the predicates of sign extension instructions
Simon Dardis [Fri, 4 May 2018 15:00:54 +0000 (15:00 +0000)]
[mips] Correct the predicates of sign extension instructions

And eliminatw the duplication of those instructions for microMIPS32r6.

Reviewers: smaksimovic, abeserminji, atanasyan

Differential Revision: https://reviews.llvm.org/D46117

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331526 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Add WriteVecMOVMSKY scheduler class
Simon Pilgrim [Fri, 4 May 2018 14:54:33 +0000 (14:54 +0000)]
[X86] Add WriteVecMOVMSKY scheduler class

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331525 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AArch64] Custom Lower MULLH{S,U} for v16i8, v8i16, and v4i32
Adhemerval Zanella [Fri, 4 May 2018 14:33:55 +0000 (14:33 +0000)]
[AArch64] Custom Lower MULLH{S,U} for v16i8, v8i16, and v4i32

This patch adds a custom lowering for ISD::MULH{S,U} used on divide by
constant optimization (DAGCombiner::BuildSDIV and DAGCombiner::BuildUDIV).

New patterns for smull and umull are added, so AArch64ISD::{S,U}MULL
can be correctly lowered to smull2 and umull2.

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D46009

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331522 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Hexagon] Skip reserved physical registers when updating liveness
Krzysztof Parzyszek [Fri, 4 May 2018 13:59:05 +0000 (13:59 +0000)]
[Hexagon] Skip reserved physical registers when updating liveness

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331518 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-mca] use colors for warnings and notes generated by InstrBuilder.
Andrea Di Biagio [Fri, 4 May 2018 13:52:12 +0000 (13:52 +0000)]
[llvm-mca] use colors for warnings and notes generated by InstrBuilder.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331517 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-mca] remove unused argument from method InstrBuilder::createInstrDescImpl.
Andrea Di Biagio [Fri, 4 May 2018 13:10:10 +0000 (13:10 +0000)]
[llvm-mca] remove unused argument from method InstrBuilder::createInstrDescImpl.

We don't need to pass the instruction index to the method that constructs new
instruction descriptors.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331516 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Add SchedWriteFRnd fp rounding scheduler classes
Simon Pilgrim [Fri, 4 May 2018 12:59:24 +0000 (12:59 +0000)]
[X86] Add SchedWriteFRnd fp rounding scheduler classes

Split off from SchedWriteFAdd for fp rounding/bit-manipulation instructions.

Fixes an issue on btver2 which only had the ymm version using the JSTC pipe instead of JFPA.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331515 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Add test case for PR30290s failing behaviour
Jeremy Morse [Fri, 4 May 2018 10:05:10 +0000 (10:05 +0000)]
[X86] Add test case for PR30290s failing behaviour

Following the advice in review D45022, this currently tests for the broken llc
output where an instruction is mis-scheduled. This test is committed in advance
to improve the eventual fixing patch in D45022, making the bad behaviour that
that patch fixes clearer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331514 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoWord wrap a test-file comment to 80 columns
Jeremy Morse [Fri, 4 May 2018 08:58:06 +0000 (08:58 +0000)]
Word wrap a test-file comment to 80 columns

This is a test commit to check whether my account works.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331512 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[SelectionDAG] Refactor code by adding RegsForValue::getRegsAndSizes(). NFCI
Bjorn Pettersson [Fri, 4 May 2018 08:50:48 +0000 (08:50 +0000)]
[SelectionDAG] Refactor code by adding RegsForValue::getRegsAndSizes(). NFCI

Summary:
Added a helper method in RegsForValue to get a list with
all the <RegNumber, RegSize> pairs that we want to iterate
over in SelectionDAGBuilder::EmitFuncArgumentDbgValue and
in SelectionDAGBuilder::visitIntrinsicCall.

Reviewers: vsk

Reviewed By: vsk

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46360

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331510 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[RegUsageInfoCollector] Bugfix for handling of register aliases.
Jonas Paulsson [Fri, 4 May 2018 07:50:05 +0000 (07:50 +0000)]
[RegUsageInfoCollector]  Bugfix for handling of register aliases.

Don't assume the alias of a defined reg is always already in the set.

As the test case in https://bugs.llvm.org/show_bug.cgi?id=36587 discovered,
it is wrong to assume that all the aliases of the defined register in the
*current function* is already present in the UsedPhysRegsMask.

This patch changes this so that any definition in the current function of a
phys-reg always results in all its aliases inserted into the set of defined
registers.

Review: Quentin Colombet
https://reviews.llvm.org/D45157

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331509 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[IRCE] Fix misuse of dyn_cast which leads to UB
Max Kazantsev [Fri, 4 May 2018 07:34:35 +0000 (07:34 +0000)]
[IRCE] Fix misuse of dyn_cast which leads to UB

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331508 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[XRay][compiler-rt+docs] Introduce __xray_log_init_mode(...).
Dean Michael Berris [Fri, 4 May 2018 06:01:12 +0000 (06:01 +0000)]
[XRay][compiler-rt+docs] Introduce __xray_log_init_mode(...).

Summary:
This addresses http://llvm.org/PR36790.

The change Deprecates a number of functions and types in
`include/xray/xray_log_interface.h` to recommend using string-based
configuration of XRay through the __xray_log_init_mode(...) function. In
particular, this deprecates the following:

- `__xray_set_log_impl(...)` -- users should instead use the
`__xray_log_register_mode(...)` and `__xray_log_select_mode(...)` APIs.

- `__xray_log_init(...)` -- users should instead use the
`__xray_log_init_mode(...)` function, which also requires using the
`__xray_log_register_mode(...)` and `__xray_log_select_mode(...)`
functionality.

- `__xray::FDRLoggingOptions` -- in following patches, we'll be
migrating the FDR logging implementations (and tests) to use the
string-based configuration. In later stages we'll remove the
`__xray::FDRLoggingOptions` type, and ask users to migrate to using the
string-based configuration mechanism instead.

- `__xray::BasicLoggingOptions` -- same as `__xray::FDRLoggingOptions`,
we'll be removing this type later and instead rely exclusively on the
string-based configuration API.

We also update the documentation to reflect the new advice and remove
some of the deprecated notes.

Reviewers: eizan, kpw, echristo, pelikan

Reviewed By: kpw

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46173

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331503 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[MachineCSE] Rewrite a loop checking if a block is in a set of blocks without using...
Michael Zolotukhin [Fri, 4 May 2018 01:40:05 +0000 (01:40 +0000)]
[MachineCSE] Rewrite a loop checking if a block is in a set of blocks without using a set. NFC.

Summary:
Using a set is unnecessary here an in some cases (see e.g. PR37277)
takes significant amount of time to just insert values into it. In this
particular case all we need is just to check if we find the block we are
looking for or not.

Reviewers: davide

Subscribers: hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D46411

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331502 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[LoopIdiomRecognize] Replace more unchecked dyn_casts with cast.
Craig Topper [Fri, 4 May 2018 01:04:28 +0000 (01:04 +0000)]
[LoopIdiomRecognize] Replace more unchecked dyn_casts with cast.

Two of these are immediately dereferenced on the next line. The other two are passed immediately to the IRBuilder constructor which can't handle a nullptr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331500 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[LoopIdiomRecognize] Use a regular array instead of a SmallVector and explicit ArrayRef.
Craig Topper [Fri, 4 May 2018 01:04:26 +0000 (01:04 +0000)]
[LoopIdiomRecognize] Use a regular array instead of a SmallVector and explicit ArrayRef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331499 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[LoopIdiomRecognize] Turn two uncheck dyn_casts into regular casts.
Craig Topper [Fri, 4 May 2018 01:04:24 +0000 (01:04 +0000)]
[LoopIdiomRecognize] Turn two uncheck dyn_casts into regular casts.

These are casts on users of a PHINode to Instruction. I think since PHINode is an Instruction any users would also be Instructions. At least a cast will give us an assertion if its wrong.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331498 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[LoopIdiomRecognize] Add a test case to show incorrect transformation of an infinite...
Craig Topper [Thu, 3 May 2018 23:50:29 +0000 (23:50 +0000)]
[LoopIdiomRecognize] Add a test case to show incorrect transformation of an infinite loop with side effets into a countable loop using ctlz.

We currently recognize this idiom where x is signed and thus the shift in an ashr.

int cnt = 0;
while (x) {
  x >>= 1; // arithmetic shift right
  ++cnt;
}

and turn it into (bitwidth - ctlz(x)). And if there is anything else in the loop we will create a new loop that runs that many times.

If x is initially negative, the shift result will never be 0 and thus the loop is infinite. If you put something with side effects in the loop, that side effect will now only happen bitwidth times instead of an infinite number of times.

So this transform is only safe for logical shift right (which we don't currently recognize) or if we can prove that x cannot be negative before the loop.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331493 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAMDGPU: Make getSubRegFromChannel a static member of AMDGPURegisterInfo
Tom Stellard [Thu, 3 May 2018 22:38:06 +0000 (22:38 +0000)]
AMDGPU: Make getSubRegFromChannel a static member of AMDGPURegisterInfo

Summary:
This makes is possible to have R600RegisterInfo and SIRegisterInfo
not inherit from AMDGPURegisterInfo.

Reviewers: arsenm, nhaehnle

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D46280

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331490 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Add WriteDPPD/WriteDPPS dot product scheduler classes
Simon Pilgrim [Thu, 3 May 2018 22:31:19 +0000 (22:31 +0000)]
[X86] Add WriteDPPD/WriteDPPS dot product scheduler classes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331489 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86][Znver1] Use SchedAlias to tag microcoded scheduler classes
Simon Pilgrim [Thu, 3 May 2018 22:12:23 +0000 (22:12 +0000)]
[X86][Znver1] Use SchedAlias to tag microcoded scheduler classes

Avoids extra entries in the class tables.

Found a typo that missed the MMX_PHSUBSW instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331488 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFix include of config.h that was incorrectly changed in r331184
Justin Bogner [Thu, 3 May 2018 21:59:13 +0000 (21:59 +0000)]
Fix include of config.h that was incorrectly changed in r331184

The RWMutex implementation depends on config.h macros (specifically
HAVE_PTHREAD_H and HAVE_PTHREAD_RWLOCK_INIT), so we need to be
including it and not just llvm-config.h here or we fall back to a much
slower implementation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331487 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine] refine select-of-constants to bitwise ops
Sanjay Patel [Thu, 3 May 2018 21:58:44 +0000 (21:58 +0000)]
[InstCombine] refine select-of-constants to bitwise ops

Add logic for the special case when a cmp+select can clearly be
reduced to just a bitwise logic instruction, and remove an
over-reaching chunk of general purpose bit magic. The primary goal
is to remove cases where we are not improving the IR instruction
count when doing these select transforms, and in all cases here that
is true.

In the motivating 3-way compare tests, there are further improvements
because we can combine/propagate select values (not sure if that
belongs in instcombine, but it's there for now).

DAGCombiner has folds to turn some of these selects into bit magic,
so there should be no difference in the end result in those cases.
Not all constant combinations are handled there yet, however, so it
is possible that some targets will see more cmov/csel codegen with
this change in IR canonicalization.

Ideally, we'll go further to *not* turn selects into multiple
logic/math ops in instcombine, and we'll canonicalize to selects.
But we should make sure that this step does not result in regressions
first (and if it does, we should fix those in the backend).

The general direction for this change was discussed here:
http://lists.llvm.org/pipermail/llvm-dev/2016-September/105373.html
http://lists.llvm.org/pipermail/llvm-dev/2017-July/114885.html

Alive proofs for the new bit magic:
https://rise4fun.com/Alive/XG7

Differential Revision: https://reviews.llvm.org/D46086

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331486 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoGlobalISel: Use a callback to compute constrained reg class for unallocatble registers
Tom Stellard [Thu, 3 May 2018 21:44:16 +0000 (21:44 +0000)]
GlobalISel: Use a callback to compute constrained reg class for unallocatble registers

Summary:
constrainOperandRegClass() currently fails if it tries to constrain the
register class of an operand that is defeined with an unallocatable register
class.  This patch resolves this by adding a target callback to compute
register constriants in this case.

This is required by the AMDGPU because many of its instructions have source opreands
defined with the unallocatable register classe VS_32 which is a union of two allocatable
register classes VGPR_32 and SReg_32.

Reviewers: dsanders, aditya_nandakumar

Reviewed By: aditya_nandakumar

Subscribers: rovka, kristof.beyls, tpr, llvm-commits

Differential Revision: https://reviews.llvm.org/D45991

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331485 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ThinLTO] Add support for optimization remarks to thinBackend
Teresa Johnson [Thu, 3 May 2018 20:24:12 +0000 (20:24 +0000)]
[ThinLTO] Add support for optimization remarks to thinBackend

Summary:
Support was added to the regular LTO backend, but not thinBackend.
This patch adds that support.

Reviewers: pcc, davide

Subscribers: mehdi_amini, inglorion, llvm-commits

Differential Revision: https://reviews.llvm.org/D46376

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331481 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[PowerPC] add more FMF debug output; NFC
Sanjay Patel [Thu, 3 May 2018 18:49:35 +0000 (18:49 +0000)]
[PowerPC] add more FMF debug output; NFC

We can't see all of the problems currently unless
we look at debug output when the global 'unsafe' is
on. It's a mess. This is another attempt to make
sure that D45710 is not making changes unintentionally.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331476 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86][AVX512] VPLZCNT instructions match SchedWriteVecIMul scheduling class not Sched...
Simon Pilgrim [Thu, 3 May 2018 18:22:49 +0000 (18:22 +0000)]
[X86][AVX512] VPLZCNT instructions match SchedWriteVecIMul scheduling class not SchedWriteVecALU.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331473 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Split WriteVecShift/WriteVarVecShift into MMX, XMM and YMM/ZMM scheduler classes
Simon Pilgrim [Thu, 3 May 2018 17:56:43 +0000 (17:56 +0000)]
[X86] Split WriteVecShift/WriteVarVecShift into MMX, XMM and YMM/ZMM scheduler classes

This took a bit of extra work as on Intel targets the old (V)PSLLDrr/(V)PSLLDrm style instructions act differently - I ended up creating WriteVecShiftImm classes for XMM/YMM/ZMM vector shift by immediate and retaining WriteVecShift as the default (used only by MMX) plus WriteVecShiftX/WriteVecShiftY. X86SchedWriteWidths hides most of this thank goodness.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331472 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[PowerPC] add tests for FMF propagation; NFC
Sanjay Patel [Thu, 3 May 2018 17:41:37 +0000 (17:41 +0000)]
[PowerPC] add tests for FMF propagation; NFC

I'm choosing PPC out of convenience because it does
all of the transforms of interest in these tests by
default. There are multiple FMF problems shown in the
current checks. D45710 is proposing to fix part of
that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331471 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[DebugInfo] Correction for an assert in DIExpression::createFragmentExpression
Bjorn Pettersson [Thu, 3 May 2018 17:04:21 +0000 (17:04 +0000)]
[DebugInfo] Correction for an assert in DIExpression::createFragmentExpression

Summary:
When we create a fragment expression, and there already is an
old fragment expression, we assert that the new fragment is
within the range for the old fragment.

If for example the old fragment expression says that we
describe bit 10-16 of a variable (Offset=10, Size=6),
and we now want to create a new fragment expression only
describing bit 3-6 of the original value, then the resulting
fragment expression should have Offset=13, Size=3.

The assert is supposed to catch if the resulting fragment
expression is outside the range for the old fragment. However,
it used to verify that the Offset+Size of the new fragment was
smaller or equal than Offset+Size for the old fragment. What
we really want to check is that Offset+Size of the new fragment
is smaller than the Size of the old fragment.

Reviewers: aprantl, vsk

Reviewed By: aprantl

Subscribers: davide, llvm-commits, JDevlieghere

Differential Revision: https://reviews.llvm.org/D46391

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331465 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoReapply "[SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)"
Bjorn Pettersson [Thu, 3 May 2018 17:04:16 +0000 (17:04 +0000)]
Reapply "[SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)"

Summary:
This reverts SVN r331441 (reapplies r331337), together with a fix
in to handle an already existing fragment expression in the
dbg.value that must be fragmented due to a split PHI node.

This should solve the problem seen in PR37321, which was the
reason for the revert of r331337.

The situation in PR37321 is that we have a PHI node like this

   %u.sroa = phi i80 [ %u.sroa.x, %if.x ],
                     [ %u.sroa.y, %if.y ],
                     [ %u.sroa.z, %if.z ]

and a dbg.value like this

  call void @llvm.dbg.value(metadata i80 %u.sroa,
                            metadata !13,
                            metadata !DIExpression(DW_OP_LLVM_fragment, 0, 80))

The phi node is split into three 32-bit PHI nodes

  %30:gr32 = PHI %11:gr32, %bb.4, %14:gr32, %bb.5, %27:gr32, %bb.8
  %31:gr32 = PHI %12:gr32, %bb.4, %15:gr32, %bb.5, %28:gr32, %bb.8
  %32:gr32 = PHI %13:gr32, %bb.4, %16:gr32, %bb.5, %29:gr32, %bb.8

but since the original value only is 80 bits we need to adjust the size
of the last fragment expression, and with this patch we get

  DBG_VALUE debug-use %30:gr32, debug-use $noreg, !"u", !DIExpression(DW_OP_LLVM_fragment, 0, 32)
  DBG_VALUE debug-use %31:gr32, debug-use $noreg, !"u", !DIExpression(DW_OP_LLVM_fragment, 32, 32)
  DBG_VALUE debug-use %32:gr32, debug-use $noreg, !"u", !DIExpression(DW_OP_LLVM_fragment, 64, 16)

Reviewers: vsk, aprantl, mstorsjo

Reviewed By: aprantl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46384

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331464 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agouse LLVM's standard CMakeLists.txt layout for llvm-xray
Nico Weber [Thu, 3 May 2018 14:25:57 +0000 (14:25 +0000)]
use LLVM's standard CMakeLists.txt layout for llvm-xray

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331455 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[CodeGen][X86][NFC] Copy two selectcc tests from AArch64.
Roman Lebedev [Thu, 3 May 2018 13:33:07 +0000 (13:33 +0000)]
[CodeGen][X86][NFC] Copy two selectcc tests from AArch64.

These tests are for DAGCombiner::foldSelectCCToShiftAnd().
Right now, they were only tested for AArch64,
but given the upcoming X86 changes to the hasAndNot(),
the test coverage needs to be added.

These tests originated from D27489 / rL289738

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331454 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Split WriteVecALU/WritePHAdd into XMM and YMM/ZMM scheduler classes
Simon Pilgrim [Thu, 3 May 2018 13:27:10 +0000 (13:27 +0000)]
[X86] Split WriteVecALU/WritePHAdd into XMM and YMM/ZMM scheduler classes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331453 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoARM: don't try to over-align large vectors as arguments.
Tim Northover [Thu, 3 May 2018 12:54:25 +0000 (12:54 +0000)]
ARM: don't try to over-align large vectors as arguments.

By default LLVM thinks very large vectors get aligned to their size when
passed across functions. Unfortunately no-one told the ARM backend so it
doesn't trigger stack realignment and so accesses can cause the usual
misalignment issues (e.g. a data abort).

This changes the ABI alignment to the stack alignment, which in practice
(and as a bonus) also coincides with the alignment "natural" vectors get.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331451 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoperform DSE through launder.invariant.group
Piotr Padlewski [Thu, 3 May 2018 11:03:53 +0000 (11:03 +0000)]
perform DSE through launder.invariant.group

Summary:
Alias Analysis knows that llvm.launder.invariant.group
returns pointer that mustalias argument, but this information
wasn't used, therefor we didn't DSE through launder.invariant.group

Reviewers: chandlerc, dberlin, bogner, hfinkel, efriedma

Reviewed By: dberlin

Subscribers: amharc, llvm-commits, nlewycky, rsmith

Differential Revision: https://reviews.llvm.org/D31581

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331449 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRename invariant.group.barrier to launder.invariant.group
Piotr Padlewski [Thu, 3 May 2018 11:03:01 +0000 (11:03 +0000)]
Rename invariant.group.barrier to launder.invariant.group

Summary:
This is one of the initial commit of "RFC: Devirtualization v2" proposal:
https://docs.google.com/document/d/16GVtCpzK8sIHNc2qZz6RN8amICNBtvjWUod2SujZVEo/edit?usp=sharing

Reviewers: rsmith, amharc, kuhar, sanjoy

Subscribers: arsenm, nhaehnle, javed.absar, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D45111

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331448 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86][AVX512] VPAVG instructions should be tagged as SchedWriteVecALU
Simon Pilgrim [Thu, 3 May 2018 10:53:17 +0000 (10:53 +0000)]
[X86][AVX512] VPAVG instructions should be tagged as SchedWriteVecALU

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331446 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Split WriteVecIMul/WriteVecPMULLD/WriteMPSAD/WritePSADBW into XMM and YMM/ZMM...
Simon Pilgrim [Thu, 3 May 2018 10:31:20 +0000 (10:31 +0000)]
[X86] Split WriteVecIMul/WriteVecPMULLD/WriteMPSAD/WritePSADBW into XMM and YMM/ZMM scheduler classes

Also retagged VDBPSADBW instructions as SchedWritePSADBW instead of SchedWriteVecIMul which matches the behaviour on SkylakeServer (the only thing that supports it...)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331445 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Update MMX instructions to be tagged with X86SchedWriteWidths types
Simon Pilgrim [Thu, 3 May 2018 09:11:32 +0000 (09:11 +0000)]
[X86] Update MMX instructions to be tagged with X86SchedWriteWidths types

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331443 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[WebAssembly] MC: Don't litter test directory.
Benjamin Kramer [Thu, 3 May 2018 08:25:14 +0000 (08:25 +0000)]
[WebAssembly] MC: Don't litter test directory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331442 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRevert "[SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)"
Martin Storsjo [Thu, 3 May 2018 07:09:33 +0000 (07:09 +0000)]
Revert "[SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)"

This reverts SVN r331337, see PR37321 for details on the regression
it introduced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331441 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[TableGen][NFC] Make ResourceCycles definitions more explicit.
Clement Courbet [Thu, 3 May 2018 06:08:47 +0000 (06:08 +0000)]
[TableGen][NFC] Make ResourceCycles definitions more explicit.

https://reviews.llvm.org/D46356

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331439 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[LoopIdiomRecognize] When looking for 'x & (x -1)' for popcnt, make sure the left...
Craig Topper [Thu, 3 May 2018 05:48:49 +0000 (05:48 +0000)]
[LoopIdiomRecognize] When looking for 'x & (x -1)' for popcnt, make sure the left hand side of the 'and' matches the left hand side of the 'subtract'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331437 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[LoopIdiomRecognize] Add a test case showing that we transform to ctpop without fully...
Craig Topper [Thu, 3 May 2018 05:48:48 +0000 (05:48 +0000)]
[LoopIdiomRecognize] Add a test case showing that we transform to ctpop without fully checking the 'x & (x-1)' part.

The code fails to check that the same value is used twice. We only make sure the left hand side of the and is part of the loop recurrence. The 'x' in the subtract can be any value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331436 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[LoopIdiomRecognize] Remove unnecessary cast from BinaryOperator to Instruction. NFC
Craig Topper [Thu, 3 May 2018 05:00:18 +0000 (05:00 +0000)]
[LoopIdiomRecognize] Remove unnecessary cast from BinaryOperator to Instruction. NFC

BinaryOperator is a sub class of Instruction. We don't need an explicit cast back to Instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331432 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agolit: flesh out `SubsituteCaptures` further
Saleem Abdulrasool [Thu, 3 May 2018 04:45:43 +0000 (04:45 +0000)]
lit: flesh out `SubsituteCaptures` further

Add overloads for `__len__` and `__getitem__` to allow use of this class
on Linux as well as Windows.  With these overloads, lit can be used on
both hosts for the swift testsuite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331431 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRe-enable "[SCEV] Make computeExitLimit more simple and more powerful"
Max Kazantsev [Thu, 3 May 2018 02:37:55 +0000 (02:37 +0000)]
Re-enable "[SCEV] Make computeExitLimit more simple and more powerful"

This patch was temporarily reverted because it has exposed bug 37229 on
PowerPC platform. The bug is unrelated to the patch and was just a general
bug in the optimization done for PowerPC platform only. The bug was fixed
by the patch rL331410.

This patch returns the disabled commit since the bug was fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331427 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Support] Support building LLVM for Fuchsia
Petr Hosek [Thu, 3 May 2018 01:38:49 +0000 (01:38 +0000)]
[Support] Support building LLVM for Fuchsia

These are necessary changes to support building LLVM for Fuchsia.
While these are not sufficient to run on Fuchsia, they are still
useful when cross-compiling LLVM libraries and runtimes for Fuchsia.

Differential Revision: https://reviews.llvm.org/D46345

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331423 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ObjCARC] Convert an if to an early continue. NFC
Shoaib Meenai [Thu, 3 May 2018 01:20:36 +0000 (01:20 +0000)]
[ObjCARC] Convert an if to an early continue. NFC

This reduces nesting and makes the logic slightly easier to follow.

Differential Revision: https://reviews.llvm.org/D46371

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331422 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoCommit r331416 breaks the big-endian PPC bot. On the big endian build, we
Nemanja Ivanovic [Thu, 3 May 2018 01:04:13 +0000 (01:04 +0000)]
Commit r331416 breaks the big-endian PPC bot. On the big endian build, we
actually encounter constants wider than 64-bits. Add the guard to prevent
tripping the assert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331420 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[gcov] Switch to an explicit if clunky array to satisfy some compilers
Chandler Carruth [Thu, 3 May 2018 00:11:03 +0000 (00:11 +0000)]
[gcov] Switch to an explicit if clunky array to satisfy some compilers
on various build bots that are unhappy with using makeArrayRef with an
initializer list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331418 91177308-0d34-0410-b5e6-96231b3b80d8