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Olof Johansson [Tue, 27 Jan 2015 04:29:58 +0000 (20:29 -0800)]
Merge tag 'omap-for-v3.20/dm816x-data' of git://git./linux/kernel/git/tmlind/linux-omap into next/soc
Merge "omap changes to make dm816x usable" from Tony Lindgren:
Patches to add necessary SoC related clockdomain and interconnect
data to make dm816x boot with basic devices. This finally gets
dm816x into a usable shape for further work to happen after a few
years of stalled effort of making this SoC to work with the mainline
kernel.
As most of the devices are similar to the other omap variants, we
get at least serial, MMC, Ethernet, I2C, EDMA, pinctrl, SPI and GPMC
working for these SoCs with the related device tree changes.
* tag 'omap-for-v3.20/dm816x-data' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Add dm816x hwmod support
ARM: OMAP2+: Add clock domain support for dm816x
ARM: OMAP2+: Add board-generic.c entry for ti81xx
ARM: OMAP2+: Disable omap3 PM init for ti81xx
ARM: OMAP2+: Fix reboot for 81xx
ARM: OMAP2+: Fix dm814 and dm816 for clocks and timer init
ARM: OMAP2+: Fix ti81xx class type
ARM: OMAP2+: Fix ti81xx devtype
ARM: OMAP2+: Fix error handling for omap2_clk_enable_init_clocks
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Tue, 27 Jan 2015 04:23:45 +0000 (20:23 -0800)]
Merge tag 'sunxi-core-for-3.20' of https://git./linux/kernel/git/mripard/linux into next/soc
Merge "Allwinner core changes for 3.20" from Maxime Ripard:
- Support for the A31s
- Adding support for cpufreq using cpufreq-dt
* tag 'sunxi-core-for-3.20' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
ARM: sunxi: Register cpufreq-dt for sun[45678]i
ARM: sunxi: Add "allwinner,sun6i-a31s" to mach-sunxi
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Tue, 27 Jan 2015 02:40:58 +0000 (18:40 -0800)]
Merge tag 'at91-cleanup3' of git://git./linux/kernel/git/nferre/linux-at91 into next/soc
Merge "at91: cleanup/soc for 3.20 #3 (bis) from Nicolas Ferre:
Third batch of cleanup/soc for 3.20:
- several fixes and adjustments following the last cleanup batch
- removal of some unused Kconfig options
- slight PM and pm_idle rework to ease future rework
- removal of unneeded mach/system_rev.h
* tag 'at91-cleanup3' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91:
ARM: at91: pm: remove warning to remove SOC_AT91SAM9263 usage
ARM: at91: remove unused mach/system_rev.h
ARM: at91: stop using HAVE_AT91_DBGUx
ARM: at91: fix ordering of SRAM and PM initialization
ARM: at91: sam9: set arm_pm_idle from sam9_dt_device_init
ARM: at91: fix sam9n12 and sam9x5 arm_pm_idle
ARM: at91: mark const init data with __initconst instead of __initdata
ARM: at91: fix PM initialization for newer SoCs
ARM: at91: fix Kconfig.debug by adding DEBUG_AT91_UART option
Signed-off-by: Olof Johansson <olof@lixom.net>
Tony Lindgren [Mon, 26 Jan 2015 17:26:32 +0000 (09:26 -0800)]
ARM: OMAP2+: Add dm816x hwmod support
Add minimal hwmod support that works at least on dm8168. This
is based on the code in the earlier TI CDP tree, and an earlier
patch by Aida Mynzhasova <aida.mynzhasova@skitlab.ru>.
I've set up things to work pretty much the same way as for
am33xx. We are basically using cm33xx.c with a different set
of clocks and clockdomains.
This code is based on the TI81XX-LINUX-PSP-04.04.00.02 patches
published at:
http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html
Cc: Aida Mynzhasova <aida.mynzhasova@skitlab.ru>
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Aida Mynzhasova [Mon, 26 Jan 2015 17:26:32 +0000 (09:26 -0800)]
ARM: OMAP2+: Add clock domain support for dm816x
This patch adds required definitions and structures for clockdomain
initialization, so omap3xxx_clockdomains_init() was substituted by
new ti81xx_clockdomains_init() while early initialization of
TI81XX platform.
Note that we now need to have 81xx in a separate CONFIG_SOC_TI81XX
block instead inside the ifdef block for omap3 to avoid make
randconfig build errors.
This code is based on the TI81XX-LINUX-PSP-04.04.00.02 patches
published at:
http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Aida Mynzhasova <aida.mynzhasova@skitlab.ru>
[tony@atomide.com: updated to apply, renamed to clockdomains81xx.c,
fixed to use am33xx_clkdm_operations, various fixes suggested by
Paul Walmsley]
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tony Lindgren [Mon, 26 Jan 2015 17:26:31 +0000 (09:26 -0800)]
ARM: OMAP2+: Add board-generic.c entry for ti81xx
This allows booting ti81xx boards when a .dts file
is in place.
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Alexandre Belloni [Thu, 15 Jan 2015 21:58:12 +0000 (22:58 +0100)]
ARM: at91: pm: remove warning to remove SOC_AT91SAM9263 usage
The SOC_AT91SAM9263 is being removed, stop using it.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Thu, 15 Jan 2015 21:58:06 +0000 (22:58 +0100)]
ARM: at91: remove unused mach/system_rev.h
mach/system_rev.h is not used, remove it.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Thu, 15 Jan 2015 21:58:11 +0000 (22:58 +0100)]
ARM: at91: stop using HAVE_AT91_DBGUx
In order to remove SOC_SAM9xxx options, stop using HAVE_AT91_DBGUx.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Nicolas Ferre [Fri, 23 Jan 2015 10:47:37 +0000 (11:47 +0100)]
ARM: at91: fix ordering of SRAM and PM initialization
The PM initialization needs internal SRAM for allocating a gen_pool and
use it to store its PM code. So we need to have of_platform_populate() before
this code.
Suggested-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Thu, 15 Jan 2015 21:58:08 +0000 (22:58 +0100)]
ARM: at91: sam9: set arm_pm_idle from sam9_dt_device_init
As all sam9 SoCs are setting arm_pm_idle to at91sam9_idle(), do it from
sam9_dt_device_init().
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Suggested-by: Arnd Bergmann <arnd@arndb.de>
[nicolas.ferre@atmel.com: adapt patch to newer series]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Thu, 15 Jan 2015 21:58:07 +0000 (22:58 +0100)]
ARM: at91: fix sam9n12 and sam9x5 arm_pm_idle
sam9n12 and sam9x5 don't set arm_pm_idle because of an oversight, fix that.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Thu, 22 Jan 2015 16:19:04 +0000 (17:19 +0100)]
ARM: at91: mark const init data with __initconst instead of __initdata
As long as there is no other non-const variable marked __initdata in the
same compilation unit it doesn't hurt. If there were one however
compilation would fail with
error: $variablename causes a section type conflict
because a section containing const variables is marked read only and so
cannot contain non-const variables.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
[nicolas.ferre@atmel.com: update the paths after having re-arranged the patches]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Nicolas Ferre [Thu, 22 Jan 2015 15:54:50 +0000 (16:54 +0100)]
ARM: at91: fix PM initialization for newer SoCs
Newer SoCs: at91sam9x5, at91sam9n12, sama5d3 and sama5d4 embed a DDR controller
and have a different PMC status register layout than the at91sam9g45. Create
another at91_sam9x5_pm_init() function to match this compatibility.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Nicolas Ferre [Tue, 20 Jan 2015 10:38:02 +0000 (11:38 +0100)]
ARM: at91: fix Kconfig.debug by adding DEBUG_AT91_UART option
The DEBUG_AT91_UART Kconfig option was forgotten when moving the
AT91 debug-macro.S file. Add it and use it for the at91.S compilation.
Reported-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Olof Johansson [Fri, 23 Jan 2015 22:57:23 +0000 (14:57 -0800)]
Merge tag 'qcom-soc-for-3.20-2' of git://git./linux/kernel/git/galak/linux-qcom into next/soc
merge "qcom SoC changes for v3.20-2" from Kumar Gala:
Qualcomm ARM Based SoC Updates for v3.20-2
* Various bug fixes and minor feature additions to scm code
* Added big-endian support to debug MSM uart
* Added big-endian support to ARCH_QCOM
* Cleaned up some Kconfig options associated with ARCH_QCOM
* Added Andy Gross as co-maintainer
* tag 'qcom-soc-for-3.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom:
MAINTAINERS: Add co-maintainer for ARM/Qualcomm Support
ARM: qcom: Drop unnecessary selects from ARCH_QCOM
ARM: qcom: Fix SCM interface for big-endian kernels
ARM: qcom: scm: Clarify boot interface
ARM: qcom: Add SCM warmboot flags for quad core targets.
ARM: qcom: scm: Add logging of actual return code from scm call
ARM: qcom: scm: Flush the command buffer only instead of the entire cache
ARM: qcom: scm: Get cacheline size from CTR
ARM: qcom: scm: Fix incorrect cache invalidation
ARM: qcom: Select ARCH_SUPPORTS_BIG_ENDIAN
ARM: debug: msm: Support big-endian CPUs
ARM: debug: Update MSM and QCOM DEBUG_LL help
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Fri, 23 Jan 2015 22:53:54 +0000 (14:53 -0800)]
Merge tag 'tegra-for-3.20-soc' of git://git./linux/kernel/git/tegra/linux into next/soc
Merge "ARM: tegra: Core code changes for v3.20" from Thierry Reding:
This contains a couple of preparatory patches for 64-bit support. A new
feature is implemented in the power-management controller which allows
it to switch off the SoC if it overheats.
* tag 'tegra-for-3.20-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
soc: tegra: Add thermal reset (thermtrip) support to PMC
ARM: tegra: Add PMC thermtrip programming to Jetson TK1 device tree
of: Add descriptions of thermtrip properties to Tegra PMC bindings
soc/tegra: pmc: Add Tegra132 support
soc/tegra: fuse: Add Tegra132 support
soc/tegra: fuse: Constify tegra_fuse_info structures
soc/tegra: Add Tegra132 support
clocksource: Build Tegra timer on 32-bit ARM only
soc/tegra: pmc: restrict compilation of suspend-related support to ARM
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Fri, 23 Jan 2015 22:38:55 +0000 (14:38 -0800)]
Merge tag 'imx-soc-3.20' of git://git./linux/kernel/git/shawnguo/linux into next/soc
Merge "ARM: imx: soc changes for 3.20" from Shawn Guo:
The i.MX SoC changes for 3.20:
- Add .disable_unused function hook for shared gate clock to ensure
the clock tree use count matches the hardware state
- Add a deeper idle state for i.MX6SX cpuidle driver powering off the
ARM core
- One correction on i.MX6Q esai_ipg parent clock setting
- Add a missing iounmap call for imx6q_opp_check_speed_grading()
- Add missing clocks for VF610 UART4, UART5 and SNVS blocks
- Expand VF610 device tree compatible matching table to cover more
Vybrid family SoCs
- Expand i.MX clk-pllv3 a bit with the shift for frequency multiplier
to support Vybrid's USB PLL oddity
* tag 'imx-soc-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: clk-imx6q: refine esai_ipg's parent
ARM i.MX6q: unmap memory mapped at imx6q_opp_check_speed_grading()
ARM: imx: clk-vf610: Add clock for SNVS
ARM: imx: clk-vf610: Add clock for UART4 and UART5
ARM: imx: drop CPUIDLE_FLAG_TIME_VALID from cpuidle-imx6sx
ARM: imx: support arm power off in cpuidle for i.mx6sx
ARM: imx: remove unnecessary setting for DSM
ARM: imx: correct the hardware clock gate setting for shared nodes
ARM: imx: pllv3: add shift for frequency multiplier
ARM vf610: add compatibilty strings of supported Vybrid SoC's
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Fri, 23 Jan 2015 22:20:43 +0000 (14:20 -0800)]
Merge tag 'v3.20-next-soc1' of https://github.com/mbgg/linux-mediatek into next/soc
Merge "ARM: mediatek: soc changes for v3.20" from Matthias Brugger:
This adds config options for the different Mediatek SoC. We need this so that
the pinctrl driver does not bloat the kernel binary.
Apart we change the Kconfig description and add the config option for mt6592
low-level debug option.
* tag 'v3.20-next-soc1' of https://github.com/mbgg/linux-mediatek:
ARM: mediatek: Low-level-debug for mt6592
ARM: mediatek: Add config options for mediatek SoCs.
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Fri, 23 Jan 2015 22:13:15 +0000 (14:13 -0800)]
Merge tag 'mvebu-soc-3.20-2' of git://git.infradead.org/linux-mvebu into next/soc
Merge "mvebu/soc #2" from Andrew Lunn:
Soc patches for mvebu for v3.20, part #2.
* tag 'mvebu-soc-3.20-2' of git://git.infradead.org/linux-mvebu:
bus: mvebu-mbus: make sure SDRAM CS for DMA don't overlap the MBus bridge window
bus: mvebu-mbus: fix support of MBus window 13 on Armada XP/375/38x
ARM: mvebu: use arm_coherent_dma_ops and re-enable hardware I/O coherency
bus: mvebu-mbus: use automatic I/O synchronization barriers
bus: mvebu-mbus: fix support of MBus window 13
ARM: mvebu: completely disable hardware I/O coherency
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Fri, 23 Jan 2015 22:01:47 +0000 (14:01 -0800)]
Merge tag 'v3.20-rockchip-soc1' of git://git./linux/kernel/git/mmind/linux-rockchip into next/soc
Merge "ARM: rockchip: soc updates for v3.20" from Heiko Stübner:
SoC parts of basic suspend support and removal of
Cortex-A9 reference from the machine name.
* tag 'v3.20-rockchip-soc1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: rockchip: remove cpu-core name from machine name
ARM: rockchip: Add pmu-sram binding
ARM: rockchip: add suspend and resume for RK3288
Signed-off-by: Olof Johansson <olof@lixom.net>
Andy Gross [Thu, 22 Jan 2015 04:39:24 +0000 (22:39 -0600)]
MAINTAINERS: Add co-maintainer for ARM/Qualcomm Support
Added myself as a co-maintainer. Updated the files to include the
Qualcomm SoC directory. Added linux-soc mailing list.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Stephen Boyd [Wed, 21 Jan 2015 19:22:09 +0000 (11:22 -0800)]
ARM: qcom: Drop unnecessary selects from ARCH_QCOM
We don't need to force gpiolib on everyone given that it isn't
required to actually boot the device and the multiplatform
Kconfig already selects ARCH_WANT_OPTIONAL_GPIOLIB. CLKSRC_OF is
already selected by CONFIG_ARCH_MULTIPLATFORM too, so we can drop
that here.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Stephen Boyd [Wed, 21 Jan 2015 19:21:15 +0000 (11:21 -0800)]
ARM: qcom: Fix SCM interface for big-endian kernels
The secure environment only runs in little-endian mode, so any
buffers shared with the secure environment should have their
contents converted to little-endian. We also mark such elements
with __le32 to allow sparse to catch such problems.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Stephen Boyd [Fri, 24 Oct 2014 00:35:07 +0000 (17:35 -0700)]
ARM: qcom: scm: Clarify boot interface
The secure world only knows about 32-bit wide physical addresses
for the boot API. Clarify the kernel interface by explicitly
stating a u32 instead of phys_addr_t which could be 32 or 64 bits
depending on LPAE or not.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Mikko Perttunen [Tue, 6 Jan 2015 10:52:58 +0000 (12:52 +0200)]
soc: tegra: Add thermal reset (thermtrip) support to PMC
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is supported on
Tegra30, Tegra114 and Tegra124. The thermal reset only works when
the thermal sensors are calibrated, so a soctherm driver is also
required.
The thermtrip event is triggered by the soctherm block, and all
soctherm sensors default to showing a temperature of zero Celsius
before they are initialized. Because of this, it is safe to initialize
thermtrip and soctherm in any order.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Mikko Perttunen [Tue, 6 Jan 2015 10:52:57 +0000 (12:52 +0200)]
ARM: tegra: Add PMC thermtrip programming to Jetson TK1 device tree
This adds the required information to reset the board during an overheating
situation to the Jetson TK1 device tree. The thermal reset is handled by the
PMC by sending an I2C message to the PMIC. The entries specify the I2C
message to be sent.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Mikko Perttunen [Tue, 6 Jan 2015 10:52:56 +0000 (12:52 +0200)]
of: Add descriptions of thermtrip properties to Tegra PMC bindings
Hardware-triggered thermal reset requires configuring the I2C
reset procedure. This configuration is read from the device tree,
so document the relevant properties in the binding documentation.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Lina Iyer [Thu, 4 Sep 2014 22:35:26 +0000 (16:35 -0600)]
ARM: qcom: Add SCM warmboot flags for quad core targets.
Quad core targets like APQ8074, APQ8064, APQ8084 need SCM support set up
warm boot addresses in the Secure Monitor. Extend the SCM flags to
support warmboot addresses for secondary cores.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Olof Johansson [Thu, 22 Jan 2015 01:19:05 +0000 (17:19 -0800)]
Merge tag 'renesas-soc3-for-v3.20' of git://git./linux/kernel/git/horms/renesas into next/soc
Merge "Third Round of Renesas ARM Based SoC Updates for v3.20" from Simon
Horman:
* Special-case PM domains with memory-controllers
* tag 'renesas-soc3-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: R-Mobile: Special-case PM domains with memory-controllers
ARM: shmobile: R-Mobile: Generalize adding/looking up special PM domains
ARM: shmobile: R-Mobile: Consolidate rmobile_pd_suspend_*()
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Thu, 22 Jan 2015 01:02:21 +0000 (17:02 -0800)]
Merge tag 'renesas-soc2-for-v3.20' of git://git./linux/kernel/git/horms/renesas into next/soc
Merge "Second Round of Renesas ARM Based SoC Updates for v3.20" from Simon
Horman:
* Add DT support for PM domains
* tag 'renesas-soc2-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: R-Mobile: Add DT support for PM domains
ARM: shmobile: R-Mobile: Store SYSC base address in rmobile_pm_domain
ARM: shmobile: R-Mobile: Use generic_pm_domain.attach_dev() for pm_clk setup
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 21 Jan 2015 23:23:24 +0000 (15:23 -0800)]
Merge tag 'sti-soc-for-v3.20-1' of git://git.stlinux.com/devel/kernel/linux-sti into next/soc
Merge "ARM: STi: SoC changes for v3.20, round 1" from Maxime Coquelin:
Highlights:
-----------
- Add support for STiH418 SoC
* tag 'sti-soc-for-v3.20-1' of git://git.stlinux.com/devel/kernel/linux-sti:
ARM: STi: Add STiH418 SoC support
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 21 Jan 2015 23:17:56 +0000 (15:17 -0800)]
Merge tag 'at91-cleanup2' of git://git./linux/kernel/git/nferre/linux-at91 into next/soc
Merge "at91: cleanup for 3.20 #2" from Nicolas Ferre:
Second batch of cleanup for 3.20:
- By reworking the PM code, we can remove the AT91 more specific initialization
- We are using DT for SRAM initialization now, so we can remove its explicit
mapping
- The PMC clock driver now hosts IDLE function for at91rm9200 with other
SoCs ones.
* tag 'at91-cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91: (37 commits)
ARM: at91: move at91rm9200_idle() to clk/at91/pmc.c
ARM: at91: remove unused at91_init_sram
ARM: at91: sama5d4: remove useless call to at91_init_sram
ARM: at91: remove useless map_io
ARM: at91: pm: prepare for multiplatform
ARM: at91: pm: add UDP and UHP checks to newer SoCs
ARM: at91: pm: use the mmio-sram pool to access SRAM
ARM: at91: pm: rework cpu detection
ARM: at91: dts: sama5d3: add ov2640 camera sensor support
ARM: at91: dts: sama5d3: change name of pinctrl of ISI_MCK
ARM: at91: dts: sama5d3: change name of pinctrl_isi_{power,reset}
ARM: at91: dts: sama5d3: move the isi mck pin to mb
ARM: at91: dts: sama5d3: add missing pins of isi
ARM: at91: dts: sama5d3: split isi pinctrl
ARM: at91: dts: sama5d3: add isi clock
ARM: at91/dt: ethernut5: use at91sam9xe.dtsi
ARM: at91/dt: Add a dtsi for at91sam9xe
ARM: at91/dt: add SRAM nodes
ARM: at91/dt: at91rm9200ek: enable RTC
ARM: at91/dt: rm9200: add RTC node
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Wang Long [Wed, 24 Dec 2014 03:10:02 +0000 (03:10 +0000)]
ARM: hisi: enable smp for HiP01
Enable smp for HiP01 board.
Signed-off-by: Wang Long <long.wanglong@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
[olof: split off the dts change to a separate commit]
Signed-off-by: Olof Johansson <olof@lixom.net>
Wang Long [Wed, 24 Dec 2014 03:10:01 +0000 (03:10 +0000)]
ARM: hisi: rename secondary_startup function
As hix5hd2 and hip01 has the same secondary_startup
so rename hix5hd2_secondary_startup to
to hisi_secondary_startup.
the hip01 will use hisi_secondary_startup for the
secondary core boot.
Signed-off-by: Wang Long <long.wanglong@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Wang Long [Wed, 24 Dec 2014 03:10:00 +0000 (03:10 +0000)]
ARM: hisi: rename smp_prepares_cpus function
As hix5hd2 and hip01 has the same .smp_prepare_cpus
in struct smp_operations, so rename hix5hd2_smp_prepare_cpus
to hisi_common_smp_prepare_cpus.
the hip01 will use hisi_common_smp_prepare_cpus in its
struct smp_operations.
Signed-off-by: Wang Long <long.wanglong@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Wang Long [Wed, 24 Dec 2014 03:09:57 +0000 (03:09 +0000)]
ARM: hisi: enable HiP01 SoC
Enable Hisilicon HiP01 SoC. This HiP01 SoC series support both
one core or dual cores and quad cores. The core is Cortex A9.
Signed-off-by: Wang Long <long.wanglong@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Wang Long [Wed, 24 Dec 2014 03:09:56 +0000 (03:09 +0000)]
ARM: debug: add HiP01 debug uart
Add the support of Hisilicon HiP01 debug uart.
The uart of hip01 is 8250 compatible.
Signed-off-by: Wang Long <long.wanglong@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 21 Jan 2015 22:29:06 +0000 (14:29 -0800)]
Merge tag 'new-atlas7mach-for-3.20' of git://git./linux/kernel/git/baohua/linux into next/soc
Merge "CSR new atlas7 machine, and delete old marco machine for 3.20" from
Barry Song:
drop CSR Marco machine and add Atlas7 new machine
This is the init support for CSR Atlas7 new SoC. Old Marco has never
shipped to customers and been dropped.
* tag 'new-atlas7mach-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux:
ARM: sirf: add Atlas7 machine support
ARM: sirf: move to debug_ll_io_init and drop map_io
ARM: sirf: move platsmp to support Atlas7 SoC
ARM: sirf: drop Marco machine
ARM: sirf: drop Marco support in reset controller module
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 21 Jan 2015 22:26:53 +0000 (14:26 -0800)]
Merge tag 'atlas7-lldebug-for-3.20' of git://git./linux/kernel/git/baohua/linux into next/soc
Merge "CSR atlas7 debug ports for 3.20" from Barry Song:
add debug ports for CSRatlas7 SoC
Because Marco chip has never shipped to customers and has been replaced
by Atlas7, so we do the below
- drop Marco's debug port
- add debug ports for Atlas7
* tag 'atlas7-lldebug-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux:
ARM: sirf: add two debug ports for CSRatlas7 SoC
ARM: sirf: drop Marco low-level debug port
Signed-off-by: Olof Johansson <olof@lixom.net>
Heiko Stuebner [Wed, 21 Jan 2015 09:41:56 +0000 (10:41 +0100)]
ARM: rockchip: remove cpu-core name from machine name
The Rockchip support is not limited to Cortex-A9 socs anymore and its
presence may confuse people reading /proc/cpuinfo. So remove the core
specific part.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Matthias Brugger [Wed, 14 Jan 2015 08:42:02 +0000 (09:42 +0100)]
ARM: mediatek: Low-level-debug for mt6592
This patch changes the description of the low-level-debug port. SoC mt8127 and
mt6592 have the same uart port and the same mapping. We just change the
description to add low-level-debug to mt6592.
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Yingjoe Chen [Tue, 16 Dec 2014 23:34:29 +0000 (07:34 +0800)]
ARM: mediatek: Add config options for mediatek SoCs.
The upcoming MTK pinctrl driver have a big pin table for each SoC
and we don't want to bloat the kernel binary if we don't need it.
Add config options so we can build for one SoC only.
Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Zhiwu Song [Sun, 4 Jan 2015 09:53:37 +0000 (17:53 +0800)]
ARM: sirf: add Atlas7 machine support
CSRatlas7 is next-gen auto SoC from CSR.
It could bring to customers most integrated SoC solution:
- World leading Bluetooth 4.0 and GNSS baseband
- Audio processing, analog CODEC and ADC by DSP
- Analog video input
- SDR accelerators
- CAN bus support by Cortex-M3
Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Barry Song [Sun, 4 Jan 2015 09:40:54 +0000 (17:40 +0800)]
ARM: sirf: move to debug_ll_io_init and drop map_io
This patch moves to debug_ll_io_init(), then finally drops CSR map_io()
machine callbacks.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Zhiwu Song [Thu, 25 Dec 2014 08:34:20 +0000 (16:34 +0800)]
ARM: sirf: move platsmp to support Atlas7 SoC
This patch breaks Marco SMP support, but Marco project has been dropped.
So it corrects cpu1 jump/flag address for Atlas7 and removes scu related
logic as scu doesn't expose in cortex-a7.
Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Barry Song [Sun, 4 Jan 2015 06:31:39 +0000 (14:31 +0800)]
ARM: sirf: drop Marco machine
Marco will not be supported any more. it has been replaced by CSR
Atlas7.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Barry Song [Sun, 4 Jan 2015 06:48:20 +0000 (14:48 +0800)]
ARM: sirf: drop Marco support in reset controller module
Marco will not be supported any more. It has been replaced by CSR
Atlas7.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Guo Zeng [Sun, 4 Jan 2015 09:40:54 +0000 (17:40 +0800)]
ARM: sirf: add two debug ports for CSRatlas7 SoC
this patch adds UART0 and UART1 as LLUART port, as the new Atlas7
registers layout are different, it also refines some names of old
hard-coded MARCOs and uses CONFIG_DEBUG_UART_PHYS/DEBUG_UART_VIRT
to define different base addresses for multiple ports.
Signed-off-by: Guo Zeng <Guo.Zeng@csr.com>
Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Shengjiu Wang [Fri, 16 Jan 2015 02:57:04 +0000 (10:57 +0800)]
ARM: clk-imx6q: refine esai_ipg's parent
esai_ipg clock's parent is ahb, not ipg.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Sebastian Andrzej Siewior [Tue, 13 Jan 2015 17:46:53 +0000 (18:46 +0100)]
ARM i.MX6q: unmap memory mapped at imx6q_opp_check_speed_grading()
imx6q_opp_check_speed_grading() remaps memory to the base variable and
never unmaps it. I can't see how this can be of any use later so here I
unmap it.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Thomas Petazzoni [Fri, 9 Jan 2015 16:59:04 +0000 (10:59 -0600)]
bus: mvebu-mbus: make sure SDRAM CS for DMA don't overlap the MBus bridge window
The mvebu-mbus driver reads the SDRAM window registers, and make the
information about the DRAM CS configuration available to device
drivers using the mv_mbus_dram_info() API. This information is used by
the DMA-capable device drivers to program their address decoding
windows.
Until now, we were basically providing the SDRAM window register
details as is. However, it turns out that the DMA capability of the
CESA cryptographic engine consists in doing DMA being the DRAM and the
crypto SRAM mapped as a MBus window. For this case, it is very
important that the SDRAM CS information does not overlap with the MBus
bridge window.
Therefore, this commit improves the mvebu-mbus driver to make sure we
adjust the SDRAM CS information so that it doesn't overlap with the
MBus bridge window. This problem was reported by Boris Brezillon,
while working on the mv_cesa driver for Armada 37x/38x/XP. We use the
memblock memory information to know where the usable RAM is located,
as this information is guaranteed to be correct on all SoC variants.
We could have used the MBus bridge window registers on Armada 370/XP,
but they are not really used on Armada 375/38x (Cortex-A9 based),
since the PL310 L2 filtering is used instead to discriminate between
RAM accesses and I/O accesses. Therefore, using the memblock
information is more generic and works accross the different platforms.
Reported-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
[Andrew Lunn <andrew@lunn.ch>: Fixed merge conflict]
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Michal Mazur [Tue, 30 Dec 2014 12:43:43 +0000 (13:43 +0100)]
bus: mvebu-mbus: fix support of MBus window 13 on Armada XP/375/38x
On Armada XP, 375 and 38x the MBus window 13 has the remap capability,
like windows 0 to 7. However, the mvebu-mbus driver isn't currently
taking into account this special case, which means that when window 13
is actually used, the remap registers are left to 0, making the device
using this MBus window unavailable.
To make things even more fun, the hardware designers have chosen to
put the window 13 remap registers in a completely custom location,
using a logic that differs from the one used for all other remappable
windows.
To solve this problem, this commit:
* Adds a SoC specific function to calculate offset of remap registers
to the mvebu_mbus_soc_data structure. This function,
->win_remap_offset(), returns the offset of the remap registers, or
MVEBU_MBUS_NO_REMAP if the window does not have the remap
capability. This new function replaces the previous integer field
num_remappable_wins, which was insufficient to encode the special
case of window 13.
* Adds an implementation of the ->win_remap_offset() function for the
various SoC families. Some have 2 first windows that are remapable,
some the 4 first, some the 8 first, and then the Armada XP/375/38x
case where the 8 first are remapable plus the special window
13. This is implemented in functions
generic_mbus_win_remap_2_offset(),
generic_mbus_win_remap_4_offset(),
generic_mbus_win_remap_8_offset() and
armada_xp_mbus_win_remap_offset() respectively.
* Change the code to use the ->win_remap_offset() function when
accessing the remap registers, and also to use a newly introduced
mvebu_mbus_window_is_remappable() helper function that tells
whether a given window is remapable or not.
* Separate Armada 370 from XP/375/38X because the window 13 of Armada
370 does not support the remap capability.
[Thomas: adapted for the mainline kernel, minor clarifications in the
code, reword the commit log.]
Signed-off-by: Michal Mazur <arg@semihalf.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
[Andrew Lunn <andrew@lunn.ch>: Undo the simple fix for stable]
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Thomas Petazzoni [Fri, 16 Jan 2015 16:11:29 +0000 (17:11 +0100)]
ARM: mvebu: use arm_coherent_dma_ops and re-enable hardware I/O coherency
Now that we have enabled automatic I/O synchronization barriers, we no
longer need any explicit barriers. We can therefore simplify
arch/arm/mach-mvebu/coherency.c by using the existing
arm_coherent_dma_ops instead of our custom mvebu_hwcc_dma_ops, and
re-enable hardware I/O coherency support.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
[Andrew Lunn <andrew@lunn.ch>: Remove forgotten comment]
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Thomas Petazzoni [Fri, 16 Jan 2015 16:11:28 +0000 (17:11 +0100)]
bus: mvebu-mbus: use automatic I/O synchronization barriers
Instead of using explicit I/O synchronization barriers shoehorned
inside the streaming DMA mappings API (in
arch/arm/mach-mvebu/coherency.c), we are switching to use automatic
I/O synchronization barrier.
The primary motivation for this change is that explicit I/O
synchronization barriers are not only needed for streaming DMA
mappings (which can easily be done by overriding the dma_map_ops), but
also for coherent DMA mappings (which is a lot less easy to do, since
the kernel assumes such mappings are coherent and don't require any
sort of cache maintenance operation to ensure the consistency of the
buffers).
Switching to automatic I/O synchronization barriers will also allow us
to use the existing arm_coherent_dma_ops instead of our custom
arm_dma_ops.
In order to use automatic I/O synchronization barriers, this commit
changes mvebu-mbus in two ways:
- It enables automatic I/O synchronization barriers in the 0x84
register of the MBus bridge, by enabling such barriers for all MBus
units. This enables automatic barriers for the on-SoC peripherals
that are doing DMA.
- It enables the SyncEnable bit in the MBus windows, so that PCIe
devices also use automatic I/O synchronization barrier.
This automatic synchronization barrier relies on the assumption that
at least one register of a given hardware unit is read before the
driver accesses the DMA mappings modified by this unit. This
assumption is guaranteed for PCI devices by vertue of the PCI
standard, and we can reasonably verify that this assumption is also
true for the limited number of platform drivers doing DMA used on
Marvell EBU platforms.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Andrew Lunn [Mon, 19 Jan 2015 22:00:15 +0000 (16:00 -0600)]
Merge branch 'mvebu/fixes-3' into mvebu/soc
Andrew Lunn [Sun, 18 Jan 2015 15:46:10 +0000 (09:46 -0600)]
bus: mvebu-mbus: fix support of MBus window 13
On Armada XP, 375 and 38x the MBus window 13 has the remap capability,
like windows 0 to 7. However, the mvebu-mbus driver isn't currently
taking into account this special case, which means that when window 13
is actually used, the remap registers are left to 0, making the device
using this MBus window unavailable.
As a minimal fix for stable, don't use window 13. A full fix will
follow later.
Fixes:
fddddb52a6c ("bus: introduce an Marvell EBU MBus driver")
Cc: <stable@vger.kernel.org> # v3.10+
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Olav Haugan [Tue, 5 Aug 2014 01:31:49 +0000 (18:31 -0700)]
ARM: qcom: scm: Add logging of actual return code from scm call
When an error occurs during an scm call the error returned is remapped so
we lose the original error code. This means that when an error occurs we
have no idea what actually failed within the secure environment.
Add a logging statement that will log the actual error code from scm call
allowing us to easily determine what caused the error to occur.
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Vikram Mulukutla [Tue, 5 Aug 2014 01:31:45 +0000 (18:31 -0700)]
ARM: qcom: scm: Flush the command buffer only instead of the entire cache
scm_call flushes the entire cache before calling into the secure world.
This is both a performance penalty as well as insufficient on SMP systems
where the CPUs possess a write-back L1 cache. Flush only the command and
response buffers instead, moving the responsibility of flushing any other
cached buffer (being passed to the secure world) to callers.
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Stephen Boyd [Tue, 5 Aug 2014 01:31:44 +0000 (18:31 -0700)]
ARM: qcom: scm: Get cacheline size from CTR
Instead of hardcoding the cacheline size as 32, get the cacheline size from
the CTR register.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Stephen Boyd [Tue, 5 Aug 2014 01:31:43 +0000 (18:31 -0700)]
ARM: qcom: scm: Fix incorrect cache invalidation
The cache invalidation in scm_call() correctly rounds down the start
address to invalidate the beginning of the cacheline but doesn't properly
round up the 'end' address to make it aligned. The last chunk of the
buffer won't be invalidated when 'end' is not cacheline size aligned so
make sure to invalidate the last few bytes in such situations. It also
doesn't do anything about outer caches so make sure to invalidate and flush
those as well.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Stephen Boyd [Mon, 22 Sep 2014 21:42:39 +0000 (14:42 -0700)]
ARM: qcom: Select ARCH_SUPPORTS_BIG_ENDIAN
We can run qcom platforms in big-endian mode. Select the option.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Stephen Boyd [Mon, 30 Jun 2014 21:49:39 +0000 (14:49 -0700)]
ARM: debug: msm: Support big-endian CPUs
If the CPU is in big-endian mode these macros will access the
hardware incorrectly. Reverse thins as necessary to fix this.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Stephen Boyd [Fri, 5 Sep 2014 22:51:56 +0000 (15:51 -0700)]
ARM: debug: Update MSM and QCOM DEBUG_LL help
Add another SoC address for apq8064 and use DEBUG_UART_VIRT
instead of DEBUG_UART_BASE because the former actually exists.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Thomas Petazzoni [Fri, 16 Jan 2015 16:11:27 +0000 (17:11 +0100)]
ARM: mvebu: completely disable hardware I/O coherency
The current hardware I/O coherency is known to cause problems with DMA
coherent buffers, as it still requires explicit I/O synchronization
barriers, which is not compatible with the semantics expected by the
Linux DMA coherent buffers API.
So, in order to have enough time to validate a new solution based on
automatic I/O synchronization barriers, this commit disables hardware
I/O coherency entirely. Future patches will re-enable it.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.8+
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Alexandre Belloni [Thu, 15 Jan 2015 14:59:31 +0000 (15:59 +0100)]
ARM: at91: move at91rm9200_idle() to clk/at91/pmc.c
Move at91rm9200_idle() along with at91sam9_idle() in clk/at91/pmc.c.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Thu, 15 Jan 2015 14:59:30 +0000 (15:59 +0100)]
ARM: at91: remove unused at91_init_sram
SRAM initialization is now done through the mmio-sram driver and
at91_init_sram() is not called anymore, remove it.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Thu, 15 Jan 2015 14:59:29 +0000 (15:59 +0100)]
ARM: at91: sama5d4: remove useless call to at91_init_sram
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Thu, 15 Jan 2015 14:59:28 +0000 (15:59 +0100)]
ARM: at91: remove useless map_io
Now that the SRAM is initialized by the mmio-sram driver, .map_io is useless.
remove it.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Thu, 15 Jan 2015 14:59:27 +0000 (15:59 +0100)]
ARM: at91: pm: prepare for multiplatform
Split at91_pm_init() in three variants that are called by the respective SoCs
.init_machine. This allows to remove the of_machine_is_compatible() calls and
move at91_pm_init() out of arch_initcall() which is required for multiplatform.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Thu, 15 Jan 2015 14:59:26 +0000 (15:59 +0100)]
ARM: at91: pm: add UDP and UHP checks to newer SoCs
Check UDP and UHP on sam9x5, sam9n12 and the sama5 series.
Check UHP on the sam9g45.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Thu, 15 Jan 2015 14:59:25 +0000 (15:59 +0100)]
ARM: at91: pm: use the mmio-sram pool to access SRAM
Now that the SRAM is part of a genpool, use it to allocate memory to use for the
slowclock implementation.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Thu, 15 Jan 2015 14:59:24 +0000 (15:59 +0100)]
ARM: at91: pm: rework cpu detection
Store SoC differences in a struct to remove cpu_is_* usage.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Nicolas Ferre [Fri, 16 Jan 2015 16:18:34 +0000 (17:18 +0100)]
Merge tag 'at91-dt' into at91-3.20-cleanup
Maxime COQUELIN [Fri, 9 Jan 2015 15:11:00 +0000 (16:11 +0100)]
ARM: STi: Add STiH418 SoC support
This patch adds support to STiH418 SoC.
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Geert Uytterhoeven [Wed, 14 Jan 2015 12:11:22 +0000 (13:11 +0100)]
ARM: shmobile: R-Mobile: Special-case PM domains with memory-controllers
Add a special case for PM domains containing a memory-controller.
Such a PM domain must not be turned off if memory is in use.
On sh73a0 PM domains A4BC0 and A4BC1 each contain an SDRAM Bus State
Controller (SBSC). On r8a73a4 PM domain A3BC contains two DDR Bus
Controllers (DBSC). In both cases, there are no other devices in these
PM domains, so they were eligible for power down, crashing the system.
On r8a7740 the DDR3 Bus State Controller (DBSC3) is located in A4S,
whose child domain A3SM contains the CPU core. Hence A4S is never turned
off, and no crash happened.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Geert Uytterhoeven [Wed, 14 Jan 2015 12:11:21 +0000 (13:11 +0100)]
ARM: shmobile: R-Mobile: Generalize adding/looking up special PM domains
Make adding special PM domains to an array, and looking them up
later, more generic, so it can be used for all special hardware blocks.
The type of PM domain is also stored, so rmobile_setup_pm_domain() can
use a switch() statement instead of a chain of if/else statements.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Geert Uytterhoeven [Wed, 14 Jan 2015 12:11:20 +0000 (13:11 +0100)]
ARM: shmobile: R-Mobile: Consolidate rmobile_pd_suspend_*()
Consolidate the identical rmobile_pd_suspend_*() routines that just
return -EBUSY to prevent a PM domain from being powered down into a
single rmobile_pd_suspend_busy().
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Josh Wu [Wed, 14 Jan 2015 02:41:54 +0000 (10:41 +0800)]
ARM: at91: dts: sama5d3: add ov2640 camera sensor support
According to v4l2 dt document, we add:
a camera host: ISI port.
a i2c camera sensor: ov2640 port.
to sama5d3xmb.dtsi.
The ov2640 node defines the pinctrls, clocks and refer to isi port.
The ISI node also has a reference to the ov2640 port.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Josh Wu [Sun, 4 Jan 2015 09:02:31 +0000 (17:02 +0800)]
ARM: at91: dts: sama5d3: change name of pinctrl of ISI_MCK
For sama5d3xmb board, the pins: pinctrl_isi_pck_as_mck is pck1, and
used to provide MCK for camera sensor.
We change its name to: pinctrl_pck1_as_isi_mck.
As we want camera sensor instead of ISI to configure the pck1 (ISI_MCK) pin.
So we remove this pinctrl from ISI DT node. It will be added in sensor's
DT node.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Josh Wu [Sun, 4 Jan 2015 09:02:30 +0000 (17:02 +0800)]
ARM: at91: dts: sama5d3: change name of pinctrl_isi_{power,reset}
For sama5d3xmb board, the pins: pinctrl_isi_{power,reset} is used to
power-down or reset camera sensor.
So we should let camera sensor instead of ISI to configure the pins.
This patch will change pinctrl name from pinctrl_isi_{power,reset} to
pinctrl_sensor_{power,reset}. And remove these two pinctrl from ISI's
DT node. We will add these two pinctrl to sensor's DT node.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Bo Shen [Sun, 4 Jan 2015 09:02:29 +0000 (17:02 +0800)]
ARM: at91: dts: sama5d3: move the isi mck pin to mb
The mck is decided by the board design, move it to mb related
dtsi file.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Bo Shen [Sun, 4 Jan 2015 09:02:28 +0000 (17:02 +0800)]
ARM: at91: dts: sama5d3: add missing pins of isi
The ISI has 12 data lines, add the missing two data lines.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Bo Shen [Sun, 4 Jan 2015 09:02:27 +0000 (17:02 +0800)]
ARM: at91: dts: sama5d3: split isi pinctrl
As the ISI has 12 data lines, however we only use 8 data lines with
sensor module. So, split the data line into two groups which make
it can be choosed depends on the hardware design.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Josh Wu [Sun, 4 Jan 2015 09:02:26 +0000 (17:02 +0800)]
ARM: at91: dts: sama5d3: add isi clock
Add ISI peripheral clock in sama5d3.dtsi.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Tue, 13 Jan 2015 18:12:26 +0000 (19:12 +0100)]
ARM: at91/dt: ethernut5: use at91sam9xe.dtsi
The ethernut5 is actually based on an at91sam9xe, use the correct dts include.
Cc: Martin Reimann <martin.reimann@egnite.de>
Cc: Tim Schendekehl <tim.schendekehl@egnite.de>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Tue, 13 Jan 2015 18:12:25 +0000 (19:12 +0100)]
ARM: at91/dt: Add a dtsi for at91sam9xe
at91sam9xe is slightly different from at91sam9260, in particular it has a
different SRAM size and location.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Tue, 13 Jan 2015 18:12:24 +0000 (19:12 +0100)]
ARM: at91/dt: add SRAM nodes
Add nodes for the SRAM available on atmel SoCs
For the at91sam9260 and the at91sam9g20, address mirroring is used to create a
single contiguous SRAM range instead of declaring two separate banks.
Also remove leftover TODOs in the sam9g45 file
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[nicolas.ferre@atmel.com: correct at91sam9rl sram size => 0x10000]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Tue, 13 Jan 2015 18:12:23 +0000 (19:12 +0100)]
ARM: at91/dt: at91rm9200ek: enable RTC
Enable the RTC on the at91rm9200ek.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Tue, 13 Jan 2015 18:12:22 +0000 (19:12 +0100)]
ARM: at91/dt: rm9200: add RTC node
Add a node for the RTC available on at91rm9200.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Tue, 13 Jan 2015 18:12:21 +0000 (19:12 +0100)]
ARM: at91/dt: at91sam9n12: Add RTC node
Add node for the RTC available on the at91sam9n12.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Mon, 12 Jan 2015 18:42:16 +0000 (19:42 +0100)]
ARM: at91: remove useless at91rm9200_set_type()
Since all rm9200 board files have been removed, there is no user of
at91rm9200_set_type() left. Remove it
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Mon, 12 Jan 2015 18:42:15 +0000 (19:42 +0100)]
ARM: at91: remove useless at91rm9200_dt_initialize()
at91rm9200_dt_initialize() is doing the same as at91_dt_initialize(), use that
one instead.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Mon, 12 Jan 2015 18:42:14 +0000 (19:42 +0100)]
ARM: at91: move debug-macro.S into the common space
Move debug-macro.S from include/mach/ to include/debug where all other common
debug macros are.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Mon, 12 Jan 2015 18:42:13 +0000 (19:42 +0100)]
ARM: at91: remove useless at91_sysirq_mask_rtx
The irq fixup from at91_sysirq_mask_rtc and at91_sysirq_mask_rtt is now handled
by aic_common_rtc_irq_fixup and aic_common_rtt_irq_fixup. Remove those useless
functions.
Also remove the now unused mach/at91_rtt.h header.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Mon, 12 Jan 2015 18:42:12 +0000 (19:42 +0100)]
ARM: at91: remove useless config MACH_AT91SAM9_DT
Now that at91sam9 SoCs are only supported through DT, remove
CONFIG_MACH_AT91SAM9_DT and use CONFIG_SOC_AT91SAM9 instead.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Mon, 12 Jan 2015 18:42:11 +0000 (19:42 +0100)]
ARM: at91: remove useless config MACH_AT91RM9200_DT
Now that rm9200 is only supported through DT, remove CONFIG_MACH_AT91RM9200_DT
and use CONFIG_SOC_AT91RM9200 instead.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Mon, 12 Jan 2015 18:42:10 +0000 (19:42 +0100)]
ARM: at91: remove unused mach/memory.h
CONFIG_NEED_MACH_MEMORY_H is not set by any at91 platform, remove mach/memory.h
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Boris Brezillon [Thu, 4 Dec 2014 14:26:09 +0000 (15:26 +0100)]
ARM: at91: remove useless header file includes
Since removal of !DT boards, asm/irq.h inclusion is not needed in these product
files.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Nicolas Ferre [Thu, 4 Dec 2014 14:09:47 +0000 (15:09 +0100)]
ARM: at91: remove unneeded header file
These GPIO pin descriptions are now moved with the pinctrl driver. We can
safely remove this useless header file.
Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>