OSDN Git Service
Fedor Sergeev [Wed, 17 Oct 2018 09:02:54 +0000 (09:02 +0000)]
[LoopPredication] add some simple stats
Just adding some useful statistics to LoopPredication pass
which was lacking any of these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344681
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Sjoerd Meijer [Wed, 17 Oct 2018 07:51:24 +0000 (07:51 +0000)]
[ARM] Follow up of rL344671, attempt to pacify a buildbot
It was rightfully complaining about an unpretty logical expression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344677
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Sjoerd Meijer [Wed, 17 Oct 2018 07:26:35 +0000 (07:26 +0000)]
[ARM][NFCI] Do not fuse VADD and VMUL, continued (1/2)
This is a follow up of rL342874, which stopped fusing muls and adds into VMLAs
for performance reasons on the Cortex-M4 and Cortex-M33. This is a serie of 2
patches, that is trying to achieve the same for VFMA. The second column in the
table below shows what we were generating before rL342874, the third column
what changed with rL342874, and the last column what we want to achieve with
these 2 patches:
--------------------------------------------------------
| Opt | < rL342874 | >= rL342874 | |
|------------------------------------------------------|
|-O3 | vmla | vmul | vmul |
| | | vadd | vadd |
|------------------------------------------------------|
|-Ofast | vfma | vfma | vmul |
| | | | vadd |
|------------------------------------------------------|
|-Oz | vmla | vmla | vmla |
--------------------------------------------------------
This patch 1/2, is a cleanup of the spaghetti predicate logic on the different
VMLA and VFMA codegen rules, so that we can make the final functional change in
patch 2/2. This also fixes a typo in the regression test added in rL342874.
Differential revision: https://reviews.llvm.org/D53314
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344671
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Sylvestre Ledru [Wed, 17 Oct 2018 06:35:10 +0000 (06:35 +0000)]
Document the behavior of option passing when using -DCLANG_ENABLE_BOOTSTRAP=On
Also document -DCLANG_BOOTSTRAP_PASSTHROUGH
Reviewers: ecbeckmann
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53018
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344669
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Lang Hames [Wed, 17 Oct 2018 03:34:09 +0000 (03:34 +0000)]
[BuildingAJIT] Update chapter 1 to use the ORCv2 APIs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344667
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Teresa Johnson [Wed, 17 Oct 2018 00:59:14 +0000 (00:59 +0000)]
New test requires x86-registered-target
New test added in r344658 also requires x86-registered-target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344662
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Teresa Johnson [Wed, 17 Oct 2018 00:19:21 +0000 (00:19 +0000)]
[ThinLTO] Fix test to require asserts
New test added in r344658 requires asserts due to -stats.
While here, augment it to test new global variable importing
message as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344660
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Leonard Chan [Wed, 17 Oct 2018 00:16:07 +0000 (00:16 +0000)]
[Sanitizer][PassManager] Fix for failing ASan tests on arm-linux-gnueabihf
Forgot to initialize the legacy pass in it's constructor.
Differential Revision: https://reviews.llvm.org/D53350
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344659
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Teresa Johnson [Tue, 16 Oct 2018 23:49:50 +0000 (23:49 +0000)]
[ThinLTO] Add importing stats to thin link
Summary:
Previously we could only get the number of imported functions and
variables from the backend. This adds stats to the thin link where the
importing is decided.
Reviewers: wmi
Subscribers: inglorion, dexonsmith, llvm-commits
Differential Revision: https://reviews.llvm.org/D53337
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344658
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Jonathan Metzman [Tue, 16 Oct 2018 23:43:57 +0000 (23:43 +0000)]
[SanitizerCoverage] Don't duplicate code to get section pointers
Summary:
Merge code used to get section start and section end pointers
for SanitizerCoverage constructors. This includes code that handles
getting the start pointers when targeting MSVC.
Reviewers: kcc, morehouse
Reviewed By: morehouse
Subscribers: kcc, hiraditya
Differential Revision: https://reviews.llvm.org/D53211
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344657
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Craig Topper [Tue, 16 Oct 2018 22:29:36 +0000 (22:29 +0000)]
[X86] Match (cmp (and (shr X, C), mask), 0) to BEXTR+TEST.
Without this we match the CMP+AND to a TEST and then match the SHR separately. I'm trusting analyzeCompare to remove the TEST during the peephole pass. Otherwise we need to check the flag users to see if they only use the Z flag.
This recovers a case lost by r344270.
Differential Revision: https://reviews.llvm.org/D53310
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344649
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David Bolvansky [Tue, 16 Oct 2018 21:18:31 +0000 (21:18 +0000)]
[InstCombine] Cleanup libfunc attribute inferring
Reviewers: efriedma
Reviewed By: efriedma
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53338
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344645
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Lang Hames [Tue, 16 Oct 2018 20:13:06 +0000 (20:13 +0000)]
[ORC] Make the VModuleKey optional, propagate it via MaterializationUnit and
MaterializationResponsibility.
VModuleKeys are intended to enable selective removal of modules from a JIT
session, however for a wide variety of use cases selective removal is not
needed and introduces unnecessary overhead. As of this commit, the default
constructed VModuleKey value is reserved as a "do not track" value, and
becomes the default when adding a new module to the JIT.
This commit also changes the propagation of VModuleKeys. They were passed
alongside the MaterializationResponsibity instance in XXLayer::emit methods,
but are now propagated as part of the MaterializationResponsibility instance
itself (and as part of MaterializationUnit when stored in a JITDylib).
Associating VModuleKeys with MaterializationUnits in this way should allow
for a thread-safe module removal mechanism in the future, even when a module
is in the process of being compiled, by having the
MaterializationResponsibility object check in on its VModuleKey's state
before commiting its results to the JITDylib.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344643
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Krasimir Georgiev [Tue, 16 Oct 2018 18:50:09 +0000 (18:50 +0000)]
Revert "[WebAssembly] LSDA info generation"
This reverts commit r344575.
Newly introduced test eh-lsda.ll.test fails with use-after-free under
ASAN build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344639
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Evandro Menezes [Tue, 16 Oct 2018 17:41:45 +0000 (17:41 +0000)]
[PATCH] [NFC][AArch64] Fix refactoring of macro fusion
Fix compiler error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344632
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Teresa Johnson [Tue, 16 Oct 2018 17:37:45 +0000 (17:37 +0000)]
[LTO] Call InitLLVM from llvm-lto2
Summary:
D45602 added this to most tools, including llvm-lto, but not to
llvm-lto2. Add it there and test that it works in both lto tools.
Reviewers: ruiu
Subscribers: mehdi_amini, inglorion, eraman, steven_wu, dexonsmith, llvm-commits
Differential Revision: https://reviews.llvm.org/D53330
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344631
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Leonard Chan [Tue, 16 Oct 2018 17:35:41 +0000 (17:35 +0000)]
[Intrinsic] Signed Saturation Addition Intrinsic
Add an intrinsic that takes 2 integers and perform saturation addition on them.
This is a part of implementing fixed point arithmetic in clang where some of
the more complex operations will be implemented as intrinsics.
Differential Revision: https://reviews.llvm.org/D53053
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344629
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Evandro Menezes [Tue, 16 Oct 2018 17:19:51 +0000 (17:19 +0000)]
[NFC][ARM] Refactor macro fusion
Simplify code for wildcards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344625
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Evandro Menezes [Tue, 16 Oct 2018 17:19:28 +0000 (17:19 +0000)]
[NFC][AArch64] Refactor macro fusion
Simplify API of checking functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344624
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Chris Lattner [Tue, 16 Oct 2018 16:54:10 +0000 (16:54 +0000)]
fix an out of date paragraph noticed by Bryce Lelbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344621
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Anna Thomas [Tue, 16 Oct 2018 15:46:26 +0000 (15:46 +0000)]
[LV] Teach vectorizer about variant value store into uniform address
Summary:
Teach vectorizer about vectorizing variant value stores to uniform
address. Similar to rL343028, we do not allow vectorization if we have
multiple stores to the same uniform address.
Cost model already has the change for considering the extract
instruction cost for a variant value store. See added test cases for how
vectorization is done.
The patch also contains changes to the ORE messages.
Reviewers: Ayal, mkuper, anemet, hsaito
Subscribers: rkruppe, llvm-commits
Differential Revision: https://reviews.llvm.org/D52656
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344613
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Sanjay Patel [Tue, 16 Oct 2018 15:26:08 +0000 (15:26 +0000)]
revert rL344609: [InstCombine] try harder to form select from logic ops
I noticed a missing check and added it at rL344610, but there actually
are codegen tests that will fail without that, so I'll edit those and
submit a fixed patch with more tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344612
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Sanjay Patel [Tue, 16 Oct 2018 14:44:50 +0000 (14:44 +0000)]
[InstCombine] make sure type is integer before calling ComputeNumSignBits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344610
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Sanjay Patel [Tue, 16 Oct 2018 14:35:21 +0000 (14:35 +0000)]
[InstCombine] try harder to form select from logic ops
This is part of solving PR37549:
https://bugs.llvm.org/show_bug.cgi?id=37549
The patterns shown here are a special case of something
that we already convert to select. Using ComputeNumSignBits()
catches that case (but not the more complicated motivating
patterns yet).
The backend has hooks/logic to convert back to logic ops
if that's better for the target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344609
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Ayal Zaks [Tue, 16 Oct 2018 14:25:02 +0000 (14:25 +0000)]
[LV] Add test checks when vectorizing loops under opt for size; NFC
Landing this as a separate part of https://reviews.llvm.org/D50480, recording
current behavior more accurately, to clarify subsequent diff ([LV] Vectorizing
loops of arbitrary trip count without remainder under opt for size).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344606
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Simon Pilgrim [Tue, 16 Oct 2018 10:06:15 +0000 (10:06 +0000)]
[LegalizeDAG] ExpandLegalINT_TO_FP - cleanup UINT_TO_FP i64 -> f64 expansion.
Use SrcVT/DestVT types, correct shift type and AND instead of ZERO_EXTEND_IN_REG.
Part of prep work for D52965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344602
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Max Kazantsev [Tue, 16 Oct 2018 09:58:09 +0000 (09:58 +0000)]
[NFC] Introduce ICFLoopSafetyInfo
This is an alternative implementation of LoopSafetyInfo that uses the implicit
control flow tracking to give precise answers on queries "whether or not this
block contains throwing instructions". This rules out false-positive answers on
LoopSafetyInfo's queries.
This patch only introduces the new implementation. It is not currently used in
any pass. The enabling patches will go separately, through review.
The plan is to completely replace all uses of LoopSafetyInfo with
ICFLoopSafetyInfo in the future, but to avoid introducing functional problems,
we will do it pass by pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344601
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Simon Pilgrim [Tue, 16 Oct 2018 09:50:16 +0000 (09:50 +0000)]
[X86] Fix Skylake ReadAfterLd for PADDrm etc.
Missed in rL343868 as due to their custom InstrRW.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344600
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Renato Golin [Tue, 16 Oct 2018 09:37:52 +0000 (09:37 +0000)]
[VPlan] Script to extract VPlan digraphs from log
The vectoriser's debug log prints VPlan digraphs, but it's a bit
cumbersome to extract them and render them into PNG images. This script
does exactly that, being careful enough to extract all individual plans,
name them appropriately and save in either .dot or .png files.
Example usage:
$ opt -O3 -debug-only=loop-vectorize file.ll -S -o /dev/null 2> debug.log
$ $LLVM_SRC/utils/extract_vplan.py < debug.log
Exporting VF1UF1 to DOT: VPlanVF1UF1.dot
Exporting VF24UF1 to DOT: VPlanVF24UF1.dot
$ $LLVM_SRC/utils/extract_vplan.py --png < debug.log
Exporting VF1UF1 to PNG via dot: VPlanVF1UF1.png
Exporting VF24UF1 to PNG via dot: VPlanVF24UF1.png
$ xdot VPlanVF1UF1.dot
Differential Revision: https://reviews.llvm.org/D53142
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344599
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Max Kazantsev [Tue, 16 Oct 2018 09:11:25 +0000 (09:11 +0000)]
[NFC] Remove obsolete method headerMayThrow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344596
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Max Kazantsev [Tue, 16 Oct 2018 08:31:05 +0000 (08:31 +0000)]
[NFC] Make LoopSafetyInfo abstract to allow alternative implementations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344592
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Aleksandar Beserminji [Tue, 16 Oct 2018 08:27:28 +0000 (08:27 +0000)]
[mips][micromips] Fix how values in .gcc_except_table are calculated
When a landing pad is calculated in a program that is compiled
for micromips, it will point to an even address. Such an error will
cause a segmentation fault, as the instructions in micromips are
aligned on odd addresses. This patch sets the last bit of the offset
where a landing pad is, to 1, which will effectively be
an odd address and point to the instruction exactly.
Differential Revision: https://reviews.llvm.org/D52985
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344591
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Max Kazantsev [Tue, 16 Oct 2018 08:07:14 +0000 (08:07 +0000)]
[NFC] Encapsulate work with BlockColors in LoopSafetyInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344590
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David Stenberg [Tue, 16 Oct 2018 08:06:48 +0000 (08:06 +0000)]
[DebugInfo][LCSSA] Rewrite pre-existing debug values outside loop
Summary:
Extend LCSSA so that debug values outside loops are rewritten to
use the PHI nodes that the pass creates.
This fixes PR39019. In that case, we ran LCSSA on a loop that
was later on vectorized, which left us with something like this:
for.cond.cleanup:
%add.lcssa = phi i32 [ %add, %for.body ], [ %34, %middle.block ]
call void @llvm.dbg.value(metadata i32 %add,
ret i32 %add.lcssa
for.body:
%add =
[...]
br i1 %exitcond, label %for.cond.cleanup, label %for.body
which later resulted in the debug.value becoming undef when
removing the scalar loop (and the location would have probably
been wrong for the vectorized case otherwise).
As we now may need to query the AvailableVals cache more than
once for a basic block, FindAvailableVals() in SSAUpdaterImpl is
changed so that it updates the cache for blocks that we do not
create a PHI node for, regardless of the block's number of
predecessors. The debug value in the attached IR reproducer
would not be properly rewritten without this.
Debug values residing in blocks where we have not inserted any
PHI nodes are currently left as-is by this patch. I'm not sure
what should be done with those uses.
Reviewers: mattd, aprantl, vsk, probinson
Reviewed By: mattd, aprantl
Subscribers: jmorse, gbedwell, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D53130
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344589
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Max Kazantsev [Tue, 16 Oct 2018 07:50:14 +0000 (07:50 +0000)]
[NFC] Move block throw check inside allLoopPathsLeadToBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344588
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Max Kazantsev [Tue, 16 Oct 2018 06:34:53 +0000 (06:34 +0000)]
[NFC] Turn isGuaranteedToExecute into a method
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344587
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Alexander Shaposhnikov [Tue, 16 Oct 2018 05:40:18 +0000 (05:40 +0000)]
[llvm-objcopy] Factor out Buffer
In this diff we move out the hierarchy of buffers from Object.h/Object.cpp
into separate files since it is not ELF-specific and will be reused later.
After this change Object.h/Object.cpp are almost exclusively ELF-specific.
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D53298
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344585
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Max Kazantsev [Tue, 16 Oct 2018 05:26:21 +0000 (05:26 +0000)]
[SCEV] Limit AddRec "simplifications" to avoid combinatorial explosions
SCEV's transform that turns `{A1,+,A2,+,...,+,An}<L> * {B1,+,B2,+,...,+,Bn}<L>` into
a single AddRec of size `2n+1` with complex combinatorial coefficients can easily
trigger exponential growth of the SCEV (in case if nothing gets folded and simplified).
We tried to restrain this transform using the option `scalar-evolution-max-add-rec-size`,
but its default value seems to be insufficiently small: the test attached to this patch
with default value of this option `16` has a SCEV of >3M symbols (when printed out).
This patch reduces the simplification limit. It is not a cure to combinatorial
explosions, but at least it reduces this corner case to something more or less
reasonable.
Differential Revision: https://reviews.llvm.org/D53282
Reviewed By: sanjoy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344584
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Sebastian Pop [Tue, 16 Oct 2018 00:42:07 +0000 (00:42 +0000)]
[hot-cold-split] fix failing testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344577
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Heejin Ahn [Tue, 16 Oct 2018 00:09:12 +0000 (00:09 +0000)]
[WebAssembly] LSDA info generation
Summary:
This adds support for LSDA (exception table) generation for wasm EH.
Wasm EH mostly follows the structure of Itanium-style exception tables,
with one exception: a call site table entry in wasm EH corresponds to
not a call site but a landing pad.
In wasm EH, the VM is responsible for stack unwinding. After an
exception occurs and the stack is unwound, the control flow is
transferred to wasm 'catch' instruction by the VM, after which the
personality function is called from the compiler-generated code. (Refer
to WasmEHPrepare pass for more information on this part.)
This patch:
- Changes wasm.landingpad.index intrinsic to take a token argument, to
make this 1:1 match with a catchpad instruction
- Stores landingpad index info and catch type info MachineFunction in
before instruction selection
- Lowers wasm.lsda intrinsic to an MCSymbol pointing to the start of an
exception table
- Adds WasmException class with overridden methods for table generation
- Adds support for LSDA section in Wasm object writer
Reviewers: dschuff, sbc100, rnk
Subscribers: mgorny, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52748
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344575
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Craig Topper [Mon, 15 Oct 2018 23:34:58 +0000 (23:34 +0000)]
[X86] Remove some isel patterns that shouldn't be possible.
These included a bitcast of a load from v4f32 to v2f64, but DAG combine should have already changed the type of the load to remove the cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344573
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Lang Hames [Mon, 15 Oct 2018 22:56:10 +0000 (22:56 +0000)]
[ORC] Rename ORC layers to make the "new" ORC layers the default.
This commit adds a 'Legacy' prefix to old ORC layers and utilities, and removes
the '2' suffix from the new ORC layers. If you wish to continue using the old
ORC layers you will need to add a 'Legacy' prefix to your classes. If you were
already using the new ORC layers you will need to drop the '2' suffix.
The legacy layers will remain in-tree until the new layers reach feature
parity with them. This will involve adding support for removing code from the
new layers, and ensuring that performance is comperable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344572
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Nicolai Haehnle [Mon, 15 Oct 2018 22:37:46 +0000 (22:37 +0000)]
StructurizeCFG,AMDGPU: Test case of a redundant phi and codegen consequences
Change-Id: I9681f9e41ca30f82576f3d1f965c3a550a34b171
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344569
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Chris Bieneman [Mon, 15 Oct 2018 22:36:59 +0000 (22:36 +0000)]
[CMake] Fix a missing LLVM_ENABLE_IDE from r344555
This is just one place I missed swapping CMAKE_CONFIGURATION_TYPES with LLVM_ENABLE_IDE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344568
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Lang Hames [Mon, 15 Oct 2018 22:36:22 +0000 (22:36 +0000)]
[ORC] Rename MultiThreadedSimpleCompiler to ConcurrentIRCompiler.
The new name is a better fit: This class does not actually spawn any new
threads for compilation, it is just safe to call from multiple threads
concurrently.
The "Simple" part of the name did not convey much either, so it was
dropped.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344567
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Lang Hames [Mon, 15 Oct 2018 22:27:03 +0000 (22:27 +0000)]
Change a TerminatorInst* to an Instruction* in HotColdSplitting.cpp.
r344558 added an assignment to a TerminatorInst* from
BasicBlock::getTerminatorInst(), but BasicBlock::getTerminatorInst() returns an
Instruction* rather than a TerminatorInst* since r344504 so this fails to
compile.
Changing the variable to an Instruction* should get the bots building again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344566
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Lang Hames [Mon, 15 Oct 2018 22:27:02 +0000 (22:27 +0000)]
[ORC] Switch to DenseMap/DenseSet for ORC symbol map/set types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344565
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Erik Pilkington [Mon, 15 Oct 2018 22:03:53 +0000 (22:03 +0000)]
NFC: Fix a -Wsign-conversion warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344564
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Craig Topper [Mon, 15 Oct 2018 21:51:32 +0000 (21:51 +0000)]
[X86] Fix a bad bitcast in the load form of vXi16 uniform shift patterns for EVEX encoded instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344563
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Craig Topper [Mon, 15 Oct 2018 21:51:29 +0000 (21:51 +0000)]
[X86] Add test cases showing failure to fold load into vpsrlw when EVEX encoded instructions are used.
There's a bad bitcast being used in the isel patterns for the vXi16 shift instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344562
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Craig Topper [Mon, 15 Oct 2018 21:51:26 +0000 (21:51 +0000)]
[X86] Disable the peephole pass on avx2-intrinsics-x86.ll and avx512bw-intrinsics.ll to ensure any load folding tests are testing isel not load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344561
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Craig Topper [Mon, 15 Oct 2018 21:51:22 +0000 (21:51 +0000)]
[X86] Regenerate avx2-intrinsics-x86.ll to compress the 32 vs 64 bit mode checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344560
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Sanjay Patel [Mon, 15 Oct 2018 21:43:53 +0000 (21:43 +0000)]
[InstCombine] add tests for bitwise logic --> select; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344559
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Sebastian Pop [Mon, 15 Oct 2018 21:43:11 +0000 (21:43 +0000)]
[hot-cold-split] fix static analysis of cold regions
Make the code of blockEndsInUnreachable to match the function
blockEndsInUnreachable in CodeGen/BranchFolding.cpp. I also have
added a note to make sure the code of this function will not be
modified unless the back-end version is also modified.
An early return before outlining has been added to avoid
outlining the full function body when the first block in the
function is marked cold.
The static analysis of cold code has been amended to avoid
marking the whole function as cold by back-propagation
because the back-propagation would mark blocks with return
statements as cold.
The patch adds debug statements to help discover these problems.
Differential Revision: https://reviews.llvm.org/D52904
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344558
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Chris Bieneman [Mon, 15 Oct 2018 21:20:02 +0000 (21:20 +0000)]
[CMake] Use LLVM_ENABLE_IDE instead of CMAKE_CONFIGURATION_TYPES
There are several places where we use CMAKE_CONFIGURATION_TYPES to determine if we are using an IDE generator and in turn decide not to generate some of the convenience targets (like all the install-* and check-llvm-* targets). This decision is made because IDEs don't always deal well with the thousands of targets LLVM can generate.
This approach does not work for Visual Studio 15's new CMake integration. Because VS15 uses a Ninja generator, it isn't a multi-configuration build, and generating all these extra targets mucks up the UI and adds little value.
With this change we still don't generate these targets by default for Visual Studio and Xcode generators, and LLVM_ENABLE_IDE becomes a switch that can be enabled on the VS15 CMake builds, to improve the IDE experience.
This is a re-land of r340435, with a few minor fix-ups. The issues causing the revert were addressed in r344218, r344219, and r344553.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344555
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Simon Pilgrim [Mon, 15 Oct 2018 21:15:58 +0000 (21:15 +0000)]
[AARCH64] Improve vector popcnt lowering with ADDLP
AARCH64 equivalent to D53257 - uses widening pairwise adds on vXi8 CTPOP to support i16/i32/i64 vectors.
This is a blocker for generic vector CTPOP expansion (P32655) - this will remove the aarch64 diff from D53258.
Differential Revision: https://reviews.llvm.org/D53259
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344554
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Chris Bieneman [Mon, 15 Oct 2018 21:14:19 +0000 (21:14 +0000)]
[CMake] Change the default value of LLVM_ENABLE_IDE
There really aren't any generator behaviors that we need to take `CMAKE_EXTRA_GENERATOR` into account for. Where we need to take different behaviors for IDEs is mostly in enabling or disabling certain build system features that are optional but trip up the IDE UIs. Like the generation of lots of utility targets.
By changing the LLVM_ENABLE_IDE default to only being on for multi-configuration generators, we allow gating where it will impact the UI presentation, while also supporting optionally disabling the generation if your tooling workflow encounters problems. Presently being able to manually disable extra target generation is useful for Visual Studio 2017's CMake integration where the IDE has trouble displaying and working with the large number of optional targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344553
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Konstantin Zhuravlyov [Mon, 15 Oct 2018 20:37:47 +0000 (20:37 +0000)]
AMDGPU: Generate .amdgcn_target for object code v3
Differential Revision: https://reviews.llvm.org/D53221
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344552
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Jordan Rupprecht [Mon, 15 Oct 2018 20:15:58 +0000 (20:15 +0000)]
[llvm-objcopy] NFC: update TODO test comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344550
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Vedant Kumar [Mon, 15 Oct 2018 19:22:20 +0000 (19:22 +0000)]
[CodeExtractor] Erase debug intrinsics in outlined thunks (fix PR22900)
Variable updates within the outlined function are invisible to
debuggers. This could be improved by defining a DISubprogram for the
new function. For the moment, simply erase the debug intrinsics instead.
This fixes verifier failures about function-local metadata being used in
the wrong function, seen while testing the hot/cold splitting pass.
rdar://
45142482
Differential Revision: https://reviews.llvm.org/D53267
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344545
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Lang Hames [Mon, 15 Oct 2018 18:34:36 +0000 (18:34 +0000)]
[ADT] Fix a bug in DenseSet's initializer_list constructor.
Without this fix, DenseSet crashes with an assertion if constructed with an
initializer_list whose length is not a power of two.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344542
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Sanjay Patel [Mon, 15 Oct 2018 18:05:34 +0000 (18:05 +0000)]
[SelectionDAG] allow FP binops in SimplifyDemandedVectorElts
This is intended to make the backend on par with functionality that was
added to the IR version of SimplifyDemandedVectorElts in:
rL343727
...and the original motivation is that we need to improve demanded-vector-elements
in several ways to avoid problems that would be exposed in D51553.
Differential Revision: https://reviews.llvm.org/D52912
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344541
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Sanjay Patel [Mon, 15 Oct 2018 16:54:07 +0000 (16:54 +0000)]
[DAGCombiner] allow undef elts in vector fmul matching
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344534
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Sanjay Patel [Mon, 15 Oct 2018 16:47:01 +0000 (16:47 +0000)]
[DAGCombiner] refactor folds for fadd (fmul X, -2.0), Y; NFCI
The transform doesn't work if the vector constant has undef elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344532
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Sanjay Patel [Mon, 15 Oct 2018 16:44:00 +0000 (16:44 +0000)]
[AArch64] add tests for fmul x, -2.0 with undef elts; NFC
Also, add tests with commuted operands. There was no coverage for that case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344531
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Sanjay Patel [Mon, 15 Oct 2018 15:56:39 +0000 (15:56 +0000)]
[DAGCombiner] allow undef elts in vector fma matching
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344528
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Sanjay Patel [Mon, 15 Oct 2018 15:47:37 +0000 (15:47 +0000)]
[x86] add tests for fma with undef elts; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344527
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Sanjay Patel [Mon, 15 Oct 2018 15:38:38 +0000 (15:38 +0000)]
[DAGCombiner] allow undef elts in vector fma matching
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344525
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Fedor Sergeev [Mon, 15 Oct 2018 15:36:08 +0000 (15:36 +0000)]
Revert "[NewPM] teach -passes= to emit meaningful error messages"
This reverts r344519 due to failures in pipeline-parsing test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344524
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Sanjay Patel [Mon, 15 Oct 2018 15:28:44 +0000 (15:28 +0000)]
[x86] add tests for fma with undef elts; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344523
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Lang Hames [Mon, 15 Oct 2018 15:26:47 +0000 (15:26 +0000)]
[ADT] Adds equality operators for DenseMap and DenseSet, and an initializer_list
constructor for DenseMap (DenseSet already had an initializer_list constructor).
These changes make it easier to migrate existing code that uses std::map and
std::set (which support initializer_list construction and equality comparison)
to DenseMap and DenseSet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344522
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Fedor Sergeev [Mon, 15 Oct 2018 15:00:18 +0000 (15:00 +0000)]
[NewPM] teach -passes= to emit meaningful error messages
Summary:
All the PassBuilder::parse interfaces now return descriptive StringError
instead of a plain bool. It allows to make -passes/aa-pipeline parsing
errors context-specific and thus less confusing.
TODO: ideally we should also make suggestions for misspelled pass names,
but that requires some extensions to PassBuilder.
Reviewed By: philip.pfaffe, chandlerc
Differential Revision: https://reviews.llvm.org/D53246
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344519
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Aleksandar Beserminji [Mon, 15 Oct 2018 14:39:12 +0000 (14:39 +0000)]
[mips][micromips] Fix overlaping FDEs error
When compiling static executable for micromips, CFI symbols
are incorrectly labeled as MICROMIPS, which cause
".eh_frame_hdr refers to overlapping FDEs." error.
This patch does not label CFI symbols as MICROMIPS, and FDEs do not
overlap anymore. This patch also exposes another bug, which is fixed
here: https://reviews.llvm.org/D52985
Differential Revision: https://reviews.llvm.org/D52987
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344516
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Aleksandar Beserminji [Mon, 15 Oct 2018 14:36:48 +0000 (14:36 +0000)]
[mips][micromips] Revert "Fix overlaping FDEs error"
This reverts r344511.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344515
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Simon Pilgrim [Mon, 15 Oct 2018 13:20:41 +0000 (13:20 +0000)]
[ARM][NEON] Improve vector popcnt lowering with PADDL (PR39281)
As I suggested on PR39281, this patch uses PADDL pairwise addition to widen from the vXi8 CTPOP result to the target vector type.
This is a blocker for moving more x86 code to generic vector CTPOP expansion (P32655 + D53258) - ARM's vXi64 CTPOP currently expands, which would generate a vXi64 MUL but ARM's custom lowering expands the general MUL case and vectors aren't well handled in LegalizeDAG - improving the CTPOP lowering was a lot easier than fixing the MUL lowering for this one case......
Differential Revision: https://reviews.llvm.org/D53257
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344512
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Aleksandar Beserminji [Mon, 15 Oct 2018 12:59:17 +0000 (12:59 +0000)]
[mips][micromips] Fix overlaping FDEs error
When compiling static executable for micromips, CFI symbols
are incorrectly labeled as MICROMIPS, which cause
".eh_frame_hdr refers to overlapping FDEs." error.
This patch does not label CFI symbols as MICROMIPS, and FDEs do not
overlap anymore. This patch also exposes another bug, which is fixed
here: https://reviews.llvm.org/D52985
Differential Revision: https://reviews.llvm.org/D52987
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344511
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Nicolai Haehnle [Mon, 15 Oct 2018 11:37:04 +0000 (11:37 +0000)]
AMDGPU: Test showing a scalar buffer load deficiency
Change-Id: I5b64a565f22a8482aa0712488d85e45163ac3d12
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344506
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Fedor Sergeev [Mon, 15 Oct 2018 10:46:35 +0000 (10:46 +0000)]
[NewPM] implement SCC printing for -print-before-all/-print-after-all
Removing deficiency of initial implementation of -print-before-all/-after-all
- it was effectively skipping IR printing for all the SCC passes.
Now LazyCallGraph:SCC gets its IR printed.
Reviewed By: skatkov
Differential Revision: https://reviews.llvm.org/D53270
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344505
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Chandler Carruth [Mon, 15 Oct 2018 10:42:50 +0000 (10:42 +0000)]
[TI removal] Make `getTerminator()` return a generic `Instruction`.
This removes the primary remaining API producing `TerminatorInst` which
will reduce the rate at which code is introduced trying to use it and
generally make it much easier to remove the remaining APIs across the
codebase.
Also clean up some of the stragglers that the previous mechanical update
of variables missed.
Users of LLVM and out-of-tree code generally will need to update any
explicit variable types to handle this. Replacing `TerminatorInst` with
`Instruction` (or `auto`) almost always works. Most of these edits were
made in prior commits using the perl one-liner:
```
perl -i -ple 's/TerminatorInst(\b.* = .*getTerminator\(\))/Instruction\1/g'
```
This also my break some rare use cases where people overload for both
`Instruction` and `TerminatorInst`, but these should be easily fixed by
removing the `TerminatorInst` overload.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344504
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Chandler Carruth [Mon, 15 Oct 2018 10:10:54 +0000 (10:10 +0000)]
[TI removal] Rework `InstVisitor` to support visiting instructions that
are terminators without relying on the specific `TerminatorInst` type.
This required cleaning up two users of `InstVisitor`s usage of
`TerminatorInst` as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344503
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Chandler Carruth [Mon, 15 Oct 2018 10:04:59 +0000 (10:04 +0000)]
[TI removal] Make variables declared as `TerminatorInst` and initialized
by `getTerminator()` calls instead be declared as `Instruction`.
This is the biggest remaining chunk of the usage of `getTerminator()`
that insists on the narrow type and so is an easy batch of updates.
Several files saw more extensive updates where this would cascade to
requiring API updates within the file to use `Instruction` instead of
`TerminatorInst`. All of these were trivial in nature (pervasively using
`Instruction` instead just worked).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344502
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Chandler Carruth [Mon, 15 Oct 2018 10:00:15 +0000 (10:00 +0000)]
[TI removal] Remove `TerminatorInst` from GVN.h and GVN.cpp.
This is the last interesting usage in all of LLVM's headers. The
remaining usages in headers are the core typesystem bits (Core.h,
instruction types, and InstVisitor) and as the return of
`BasicBlock::getTerminator`. The latter is the big remaining API point
that I'll remove after mass updates to user code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344501
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Chandler Carruth [Mon, 15 Oct 2018 09:47:26 +0000 (09:47 +0000)]
[TI removal] Remove `TerminatorInst` from SparsePropagation.h and
related code.
This is simple as we just need to replace the type and move to the
concept of visiting a "terminator" rather than a specific instruction
subclass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344500
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Chandler Carruth [Mon, 15 Oct 2018 09:34:31 +0000 (09:34 +0000)]
[TI removal] Remove a dead forward declaration of TerminatorInst. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344499
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Chandler Carruth [Mon, 15 Oct 2018 09:34:05 +0000 (09:34 +0000)]
[TI removal] Remove `TerminatorInst` from BasicBlockUtils.h
This requires updating a number of .cpp files to adapt to the new API.
I've just systematically updated all uses of `TerminatorInst` within
these files te `Instruction` so thta I won't have to touch them again in
the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344498
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Chandler Carruth [Mon, 15 Oct 2018 09:33:40 +0000 (09:33 +0000)]
[TI removal] Just use Instruction in the CFG printer code. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344497
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Guillaume Chatelet [Mon, 15 Oct 2018 09:21:21 +0000 (09:21 +0000)]
[llvm-exegesis] Fix missing std::move.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344496
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Chandler Carruth [Mon, 15 Oct 2018 09:17:38 +0000 (09:17 +0000)]
[TI removal] Remove a unnecessary use of `TerminatorInst` from an IR
header. NFC.
Part of the removal of `TerminatorInst` from the type hierarchy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344495
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Chandler Carruth [Mon, 15 Oct 2018 09:17:09 +0000 (09:17 +0000)]
[TI removal] Remove TerminatorInst as an input parameter from all public
LLVM APIs. There weren't very many.
We still have the instruction visitor, and APIs with TerminatorInst as
a return type or an output parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344494
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Guillaume Chatelet [Mon, 15 Oct 2018 09:09:19 +0000 (09:09 +0000)]
[llvm-exegesis][NFC] Return many CodeTemplates instead of one.
Summary: This is part one of the change where I simply changed the signature of the functions. More work need to be done to actually produce more than one CodeTemplate per instruction.
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D53209
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344493
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Bjorn Pettersson [Mon, 15 Oct 2018 08:36:03 +0000 (08:36 +0000)]
[TwoAddressInstructionPass] Replace subregister uses when processing tied operands
Summary:
TwoAddressInstruction pass typically rewrites
%1:short = foo %0.sub_lo:long
as
%1:short = COPY %0.sub_lo:long
%1:short = foo %1:short
when having tied operands.
If there are extra un-tied operands that uses the same reg and
subreg, such as the second and third inputs to fie here:
%1:short = fie %0.sub_lo:long, %0.sub_hi:long, %0.sub_lo:long
then there was a bug which replaced the register %0 also for
the un-tied operand, but without changing the subregister indices.
So we used to get:
%1:short = COPY %0.sub_lo:long
%1:short = fie %1, %1.sub_hi:short, %1.sub_lo:short
With this fix we instead get:
%1:short = COPY %0.sub_lo:long
%1:short = fie %1, %0.sub_hi:long, %1
Reviewers: arsenm, JesperAntonsson, kparzysz, MatzeB
Reviewed By: MatzeB
Subscribers: bjope, kparzysz, wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D36224
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344492
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Craig Topper [Mon, 15 Oct 2018 05:31:24 +0000 (05:31 +0000)]
[X86] Autogenerate checks. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344490
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Lang Hames [Mon, 15 Oct 2018 05:07:54 +0000 (05:07 +0000)]
[ORC] Simplify naming for JITDylib definition generators.
Renames:
JITDylib's setFallbackDefinitionGenerator method to setGenerator.
DynamicLibraryFallbackGenerator class to DynamicLibrarySearchGenerator.
ReexportsFallbackDefinitionGenerator to ReexportsGenerator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344489
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Craig Topper [Mon, 15 Oct 2018 01:51:58 +0000 (01:51 +0000)]
[X86] Move promotion of vector and/or/xor from legalization to DAG combine
Summary:
I've noticed that the bitcasts we introduce for these make computeKnownBits and computeNumSignBits not work well in LegalizeVectorOps. LegalizeVectorOps legalizes bottom up while LegalizeDAG legalizes top down. The bottom up strategy for LegalizeVectorOps means operands are legalized before their uses. So we promote and/or/xor before we legalize the operands that use them making computeKnownBits/computeNumSignBits in places like LowerTruncate suboptimal. I looked at changing LegalizeVectorOps to be top down as well, but that was more disruptive and caused some regressions. I also looked at just moving promotion of binops to LegalizeDAG, but that had a few issues one around matching AND,ANDN,OR into VSELECT because I had to create ANDN as vXi64, but the other nodes hadn't legalized yet, I didn't look too hard at fixing that.
This patch seems to produce better results overall than my other attempts. We now form broadcasts of constants better in some cases. For at least some of them the AND was being introduced in LegalizeDAG, promoted to vXi64, and the BUILD_VECTOR was also legalized there. I think we got bad ordering of that. Now the promotion is out of the legalizer so we handle this better.
In the longer term I think we really should evaluate whether we should be doing this promotion at all. It's really there to reduce isel pattern count, but I'm wondering if we'd be better served just eating the pattern cost or doing C++ based isel for vector and/or/xor in X86ISelDAGToDAG. The masked and/or/xor will definitely be difficult in patterns if a bitcast gets between the vselect and the and/or/xor node. That becomes a lot of permutations to cover.
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53107
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344487
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Craig Topper [Mon, 15 Oct 2018 01:51:53 +0000 (01:51 +0000)]
[X86] Add 128 MOVDDUP to the constant pool printing in X86AsmPrinter::EmitInstruction.
We use this instruction to broadcast a single 64-bit value to a v2i64/v2f64 vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344486
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Craig Topper [Mon, 15 Oct 2018 01:51:50 +0000 (01:51 +0000)]
[X86] Autogenerate complete checks. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344485
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Simon Pilgrim [Sun, 14 Oct 2018 20:14:33 +0000 (20:14 +0000)]
[InstCombine] Add PR27343 test cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344484
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Ayal Zaks [Sun, 14 Oct 2018 17:53:02 +0000 (17:53 +0000)]
[LV] Fix comments reported when not vectorizing single iteration loops; NFC
Landing this as a separate part of https://reviews.llvm.org/D50480, being a
seemingly unrelated change ([LV] Vectorizing loops of arbitrary trip count
without remainder under opt for size).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344483
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Simon Pilgrim [Sun, 14 Oct 2018 17:34:20 +0000 (17:34 +0000)]
[X86][AVX] Enable lowerVectorShuffleAsLanePermuteAndPermute v16i16/v32i8 shuffle lowering
Extends D53148 from v4f64 now that we have test coverage for v16i16/v32i8 shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344481
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Simon Pilgrim [Sun, 14 Oct 2018 16:49:04 +0000 (16:49 +0000)]
[ARM] Regenerate cttz tests
Improve codegen view as part of PR32655
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344479
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