OSDN Git Service
Bjorn Helgaas [Mon, 13 May 2019 23:34:44 +0000 (18:34 -0500)]
Merge branch 'remotes/lorenzo/pci/misc'
- Exit pcitest with error code when test fails (Jean-Jacques Hiblot)
- Fix leaked of_node references in dra7xx, uniphier, layerscape,
rockchip, aardvark, iproc, mediatek, rpadlpar (Wen Yang)
- Fix pcitest "help" option parsing (Kishon Vijay Abraham I)
- Fix Makefile bug that inadvertently removes pcitest.sh (Kishon Vijay
Abraham I)
- Check for alloc_workqueue() failure in endpoint test driver (Kangjie
Lu)
* remotes/lorenzo/pci/misc:
PCI: endpoint: Fix a potential NULL pointer dereference
tools: PCI: Handle pcitest.sh independently from pcitest
tools: PCI: Add 'h' in optstring of getopt()
PCI: mediatek: Fix a leaked reference by adding missing of_node_put()
PCI: iproc: Fix a leaked reference by adding missing of_node_put()
PCI: aardvark: Fix a leaked reference by adding missing of_node_put()
PCI: rockchip: Fix a leaked reference by adding missing of_node_put()
PCI: dwc: layerscape: Fix a leaked reference by adding missing of_node_put()
PCI: uniphier: Fix a leaked reference by adding missing of_node_put()
PCI: dwc: pci-dra7xx: Fix a leaked reference by adding missing of_node_put()
tools: PCI: Exit with error code when test fails
Bjorn Helgaas [Mon, 13 May 2019 23:34:44 +0000 (18:34 -0500)]
Merge branch 'remotes/lorenzo/pci/xilinx'
- Check for __get_free_pages() failure in xilinx (Kangjie Lu)
* remotes/lorenzo/pci/xilinx:
PCI: xilinx: Check for __get_free_pages() failure
Bjorn Helgaas [Mon, 13 May 2019 23:34:43 +0000 (18:34 -0500)]
Merge branch 'remotes/lorenzo/pci/tegra'
- Use DMA-API to get tegra MSI address to prevent device DMA from
generating unwanted MSIs (Vidya Sagar)
* remotes/lorenzo/pci/tegra:
PCI: tegra: Use the DMA-API to get the MSI address
Bjorn Helgaas [Mon, 13 May 2019 23:34:43 +0000 (18:34 -0500)]
Merge branch 'remotes/lorenzo/pci/rockchip'
- Fix rockchip bitwise operations that overflow type (Colin Ian King)
* remotes/lorenzo/pci/rockchip:
PCI: rockchip: Fix rockchip_pcie_ep_assert_intx() bitwise operations
Bjorn Helgaas [Mon, 13 May 2019 23:34:42 +0000 (18:34 -0500)]
Merge branch 'remotes/lorenzo/pci/rcar'
- Use BIT() when appropriate in rcar (Marek Vasut)
- Use u32 to match rcar hardware register widths (Marek Vasut)
- Use BITS_PER_BYTE when appropriate in rcar (Marek Vasut)
- Remove unnecessary casts in rcar (Marek Vasut)
- Fix 64-bit MSI target addresses in rcar (Marek Vasut)
- Check for __get_free_pages() failure in rcar (Kangjie Lu)
- Fix shadowed rcar "irq" variable (Wolfram Sang)
* remotes/lorenzo/pci/rcar:
PCI: rcar: Do not shadow the 'irq' variable
PCI: rcar: Fix a potential NULL pointer dereference
PCI: rcar: Fix 64bit MSI message address handling
PCI: rcar: Clean up debug messages
PCI: rcar: Replace (8 * n) with (BITS_PER_BYTE * n)
PCI: rcar: Replace various variable types with unsigned ones for register values
PCI: rcar: Replace unsigned long with u32/unsigned int in register accessors
PCI: rcar: Clean up remaining macros defining bits
# Conflicts:
# drivers/pci/controller/pcie-rcar.c
Bjorn Helgaas [Mon, 13 May 2019 23:34:41 +0000 (18:34 -0500)]
Merge branch 'remotes/lorenzo/pci/mediatek'
- Make mediatek clocks optional, not required (Chunfeng Yun)
- Remove unused mediatek mt2712 "num-lanes" DT property (Honghui Zhang)
* remotes/lorenzo/pci/mediatek:
arm64: dts: mt2712: Remove un-used property for PCIe
PCI: mediatek: Get optional clocks with devm_clk_get_optional()
Bjorn Helgaas [Mon, 13 May 2019 23:34:41 +0000 (18:34 -0500)]
Merge branch 'remotes/lorenzo/pci/keystone'
- Move IRQ register address computation inside macros (Kishon Vijay
Abraham I)
- Separate legacy IRQ and MSI configuration (Kishon Vijay Abraham I)
- Use hwirq, not virq, to get MSI IRQ number offset (Kishon Vijay Abraham
I)
- Squash ks_pcie_handle_msi_irq() into ks_pcie_msi_irq_handler() (Kishon
Vijay Abraham I)
- Add dwc support for platforms with custom MSI controllers (Kishon Vijay
Abraham I)
- Add keystone-specific MSI controller (Kishon Vijay Abraham I)
- Remove dwc host_ops previously used for keystone-specific MSI (Kishon
Vijay Abraham I)
- Skip dwc default MSI init if platform has custom MSI controller (Kishon
Vijay Abraham I)
- Implement .start_link() and .stop_link() for keystone endpoint support
(Kishon Vijay Abraham I)
- Add keystone "reg-names" DT binding (Kishon Vijay Abraham I)
- Squash ks_pcie_dw_host_init() into ks_pcie_add_pcie_port() (Kishon
Vijay Abraham I)
- Get keystone register resources from DT by name, not index (Kishon
Vijay Abraham I)
- Get DT resources in .probe() to prepare for endpoint support (Kishon
Vijay Abraham I)
- Add "ti,syscon-pcie-mode" DT property for PCIe mode configuration
(Kishon Vijay Abraham I)
- Explicitly set keystone to host mode (Kishon Vijay Abraham I)
- Document DT "atu" reg-names requirement for DesignWare core >= 4.80
(Kishon Vijay Abraham I)
- Enable dwc iATU unroll for endpoint mode as well as host mode (Kishon
Vijay Abraham I)
- Add dwc "version" to identify core >= 4.80 for ATU programming (Kishon
Vijay Abraham I)
- Don't build ARM32-specific keystone code on ARM64 (Kishon Vijay Abraham
I)
- Add DT binding for keystone PCIe RC in AM654 SoC (Kishon Vijay Abraham
I)
- Add keystone support for AM654 SoC PCIe RC (Kishon Vijay Abraham I)
- Reset keystone PHYs before enabling them (Kishon Vijay Abraham I)
- Make of_pci_get_max_link_speed() available to endpoint drivers as well
as host drivers (Kishon Vijay Abraham I)
- Add keystone support for DT "max-link-speed" property (Kishon Vijay
Abraham I)
- Add endpoint library support for BAR buffer alignment (Kishon Vijay
Abraham I)
- Make all dw_pcie_ep_ops structs const (Kishon Vijay Abraham I)
- Fix fencepost error in dw_pcie_ep_find_capability() (Kishon Vijay
Abraham I)
- Add dwc hooks for dbi/dbi2 that share the same address space (Kishon
Vijay Abraham I)
- Add keystone support for TI AM654x in endpoint mode (Kishon Vijay
Abraham I)
- Configure designware endpoints to advertise smallest resizable BAR
(1MB) (Kishon Vijay Abraham I)
- Align designware endpoint ATU windows for raising MSIs (Kishon Vijay
Abraham I)
- Add endpoint test support for TI AM654x (Kishon Vijay Abraham I)
- Fix endpoint test test_reg_bar issue (Kishon Vijay Abraham I)
* remotes/lorenzo/pci/keystone:
misc: pci_endpoint_test: Fix test_reg_bar to be updated in pci_endpoint_test
misc: pci_endpoint_test: Add support to test PCI EP in AM654x
PCI: designware-ep: Use aligned ATU window for raising MSI interrupts
PCI: designware-ep: Configure Resizable BAR cap to advertise the smallest size
PCI: keystone: Add support for PCIe EP in AM654x Platforms
dt-bindings: PCI: Add PCI EP DT binding documentation for AM654
PCI: dwc: Add callbacks for accessing dbi2 address space
PCI: dwc: Fix dw_pcie_ep_find_capability() to return correct capability offset
PCI: dwc: Add const qualifier to struct dw_pcie_ep_ops
PCI: endpoint: Add support to specify alignment for buffers allocated to BARs
PCI: keystone: Add support to set the max link speed from DT
PCI: OF: Allow of_pci_get_max_link_speed() to be used by PCI Endpoint drivers
PCI: keystone: Invoke phy_reset() API before enabling PHY
PCI: keystone: Add support for PCIe RC in AM654x Platforms
dt-bindings: PCI: Add PCI RC DT binding documentation for AM654
PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64
PCI: dwc: Fix ATU identification for designware version >= 4.80
PCI: dwc: Enable iATU unroll for endpoint too
dt-bindings: PCI: Document "atu" reg-names
PCI: keystone: Explicitly set the PCIe mode
dt-bindings: PCI: Add dt-binding to configure PCIe mode
PCI: keystone: Move resources initialization to prepare for EP support
PCI: keystone: Use platform_get_resource_byname() to get memory resources
PCI: keystone: Perform host initialization in a single function
dt-bindings: PCI: keystone: Add "reg-names" binding information
PCI: keystone: Cleanup error_irq configuration
PCI: keystone: Add start_link()/stop_link() dw_pcie_ops
PCI: dwc: Remove default MSI initialization for platform specific MSI chips
PCI: dwc: Remove Keystone specific dw_pcie_host_ops
PCI: keystone: Use Keystone specific msi_irq_chip
PCI: dwc: Add support to use non default msi_irq_chip
PCI: keystone: Cleanup ks_pcie_msi_irq_handler()
PCI: keystone: Use hwirq to get the MSI IRQ number offset
PCI: keystone: Add separate functions for configuring MSI and legacy interrupt
PCI: keystone: Cleanup interrupt related macros
# Conflicts:
# drivers/pci/controller/dwc/pcie-designware.h
Bjorn Helgaas [Mon, 13 May 2019 23:34:39 +0000 (18:34 -0500)]
Merge branch 'remotes/lorenzo/pci/iproc'
- Work around iproc CRS completion issues (Srinath Mannam)
- Allow smaller iproc outbound windows so driver can work on 32-bit
systems (Srinath Mannam)
- Use iproc-specific config read for PAXBv2 (not PAXB) (Srinath Mannam)
* remotes/lorenzo/pci/iproc:
PCI: iproc: Enable iProc config read for PAXBv2
PCI: iproc: Allow outbound configuration for 32-bit I/O region
PCI: iproc: Add CRS check in config read
Bjorn Helgaas [Mon, 13 May 2019 23:34:39 +0000 (18:34 -0500)]
Merge branch 'remotes/lorenzo/pci/imx'
- Simplify imx7d_pcie_wait_for_phy_pll_lock() by using
regmap_read_poll_timeout() (Andrey Smirnov)
- Drop imx6_pcie_wait_for_link() in favor of the more generic
dw_pcie_wait_for_link() (Andrey Smirnov)
- Return -ETIMEDOUT instead of -EINVAL from
imx6_pcie_wait_for_speed_change() (Andrey Smirnov)
- Remove unused PCIE_PL_PFLR_* constants from imx6 (Andrey Smirnov)
- Use shared PHY debug register definitions in imx6 (Andrey Smirnov)
- Use BIT() in imx6 (Andrey Smirnov)
- Simplify imx6 PHY bit operations (Andrey Smirnov)
- Simplify imx6 pcie_phy_poll_ack() (Andrey Smirnov)
- Use data types that match actual imx6 PHY register width (Andrey
Smirnov)
- Mark imx6 suspend support with drvdata flags instead of checking
variants (Andrey Smirnov)
- Sleep instead of delay in imx6_pcie_enable_ref_clk() (Andrey Smirnov)
* remotes/lorenzo/pci/imx:
PCI: imx6: Use usleep_range() in imx6_pcie_enable_ref_clk()
PCI: imx6: Use flags to indicate support for suspend
PCI: imx6: Restrict PHY register data to 16-bit
PCI: imx6: Simplify pcie_phy_poll_ack()
PCI: imx6: Simplify bit operations in PHY functions
PCI: imx6: Make use of BIT() in constant definitions
PCI: dwc: imx6: Share PHY debug register definitions
PCI: imx6: Remove PCIE_PL_PFLR_* constants
PCI: imx6: Return -ETIMEOUT from imx6_pcie_wait_for_speed_change()
PCI: imx6: Drop imx6_pcie_wait_for_link()
PCI: imx6: Simplify imx7d_pcie_wait_for_phy_pll_lock()
Bjorn Helgaas [Mon, 13 May 2019 23:34:38 +0000 (18:34 -0500)]
Merge branch 'pci/dwc'
- Use generic config space reader in qcom (Marc Gonzalez)
- Stop calling IRQ handler cleanup in dwc driver for invalid MSI IRQs
(Jisheng Zhang)
- Free dwc MSI target page when freeing MSI (Jisheng Zhang)
- Fix dwc MSI leak in host init error path (Jisheng Zhang)
- Use managed host bridge alloc to simplify dwc (Jisheng Zhang)
- Save dwc root pci_bus pointer for use by .remove() methods (Jisheng
Zhang)
- Allow imx6 asynchronous probing (Lucas Stach)
* pci/dwc:
PCI: imx6: Allow asynchronous probing
PCI: dwc: Save root bus for driver remove hooks
PCI: dwc: Use devm_pci_alloc_host_bridge() to simplify code
PCI: dwc: Free MSI in dw_pcie_host_init() error path
PCI: dwc: Free MSI IRQ page in dw_pcie_free_msi()
PCI: dwc: Fix dw_pcie_free_msi() if msi_irq is invalid
PCI: qcom: Use default config space read function
Bjorn Helgaas [Mon, 13 May 2019 23:34:37 +0000 (18:34 -0500)]
Merge branch 'remotes/lorenzo/pci/controller-fixes'
- Restore R-Car PCIe link early in resume (Kazufumi Ikeda)
- Fix Hyper-V PCI ejection memory leak (Dexuan Cui)
- Cleanup Hyper-V PCI slots on module unload (Dexuan Cui)
- Cleanup Hyper-V PCI slot on device removal to address a race (Dexuan
Cui)
* remotes/lorenzo/pci/controller-fixes:
PCI: hv: Add pci_destroy_slot() in pci_devices_present_work(), if necessary
PCI: hv: Add hv_pci_remove_slots() when we unload the driver
PCI: hv: Fix a memory leak in hv_eject_device_work()
PCI: rcar: Add the initialization of PCIe link in resume_noirq()
Bjorn Helgaas [Mon, 13 May 2019 23:34:36 +0000 (18:34 -0500)]
Merge branch 'pci/host/al'
- Add Amazon Annapurna Labs PCIe host controller driver (Jonathan
Chocron)
* pci/host/al:
PCI: al: Add Amazon Annapurna Labs PCIe host controller driver
Bjorn Helgaas [Mon, 13 May 2019 23:34:35 +0000 (18:34 -0500)]
Merge branch 'pci/virtualization'
- Mark ATS on AMD Stoney Radeon R7 GPU broken to avoid IOMMU issues
(Nikolai Kostrigin)
- Mark Atheros AR9462 to avoid bus reset that locks up host machine
(James Prestwood)
* pci/virtualization:
PCI: Mark Atheros AR9462 to avoid bus reset
PCI: Mark AMD Stoney Radeon R7 GPU ATS as broken
Bjorn Helgaas [Mon, 13 May 2019 23:34:35 +0000 (18:34 -0500)]
Merge branch 'pci/switchtec'
- Support all 255 PFF ports in switchtec driver (Wesley Sheng)
- Fix unintentional switchtec MRPC event masking that degraded firmware
update speed (Wesley Sheng)
* pci/switchtec:
switchtec: Fix unintended mask of MRPC event
switchtec: Increase PFF limit from 48 to 255
Bjorn Helgaas [Mon, 13 May 2019 23:34:34 +0000 (18:34 -0500)]
Merge branch 'pci/portdrv'
- Disable Link Management interrupt during suspend to prevent immediate
wakeup (Mika Westerberg)
* pci/portdrv:
PCI/LINK: Disable bandwidth notification interrupt during suspend
Bjorn Helgaas [Mon, 13 May 2019 23:34:33 +0000 (18:34 -0500)]
Merge branch 'pci/peer-to-peer'
- Add a whitelist of Root Complexes known to support peer-to-peer DMA
between Root Ports (Christian König)
* pci/peer-to-peer:
PCI/P2PDMA: Allow P2P DMA between any devices under AMD ZEN Root Complex
Bjorn Helgaas [Mon, 13 May 2019 23:34:32 +0000 (18:34 -0500)]
Merge branch 'pci/misc'
- Mark expected switch fall-throughs (Gustavo A. R. Silva)
- Remove unused pci_request_region_exclusive() (Johannes Thumshirn)
- Fix x86 PCI IRQ routing table memory leak (Wenwen Wang)
- Reset Lenovo ThinkPad P50 if firmware didn't do it on reboot (Lyude
Paul)
- Add and use pci_dev_id() helper to simplify PCI_DEVID() usage (touches
several places outside drivers/pci/) (Heiner Kallweit)
- Transition Mobiveil PCI maintenance to Karthikeyan M and Hou Zhiqiang
(Subrahmanya Lingappa)
* pci/misc:
MAINTAINERS: Add Karthikeyan Mitran and Hou Zhiqiang for Mobiveil PCI
platform/chrome: chromeos_laptop: use pci_dev_id() helper
stmmac: pci: Use pci_dev_id() helper
iommu/vt-d: Use pci_dev_id() helper
iommu/amd: Use pci_dev_id() helper
drm/amdkfd: Use pci_dev_id() helper
powerpc/powernv/npu: Use pci_dev_id() helper
r8169: use pci_dev_id() helper
PCI: Add pci_dev_id() helper
PCI: Reset Lenovo ThinkPad P50 nvgpu at boot if necessary
x86/PCI: Fix PCI IRQ routing table memory leak
PCI: Remove unused pci_request_region_exclusive()
PCI: Mark expected switch fall-throughs
Bjorn Helgaas [Mon, 13 May 2019 23:34:31 +0000 (18:34 -0500)]
Merge branch 'pci/msi'
- Remove unused mask_msi_irq(), unmask_msi_irq(), write_msi_msg(),
__write_msi_msg() (Bjorn Helgaas)
* pci/msi:
PCI/MSI: Remove unused mask_msi_irq() and unmask_msi_irq()
PCI/MSI: Remove unused __write_msi_msg() and write_msi_msg()
Bjorn Helgaas [Mon, 13 May 2019 23:34:31 +0000 (18:34 -0500)]
Merge branch 'pci/hotplug'
- Fix RPA and RPA DLPAR refcount issues (Tyrel Datwyler)
- Stop exporting pci_get_hp_params() (Alexandru Gagniuc)
- Simplify _HPP, _HPX parsing (Alexandru Gagniuc)
- Add support for _HPX Type 3 settings (Alexandru Gagniuc)
- Tell firmware we support _HPX Type 3 via _OSC (Alexandru Gagniuc)
* pci/hotplug:
PCI/ACPI: Advertise _HPX Type 3 support via _OSC
PCI/ACPI: Implement _HPX Type 3 Setting Record
PCI/ACPI: Remove the need for 'struct hotplug_params'
PCI/ACPI: Do not export pci_get_hp_params()
PCI: rpaphp: Get/put device node reference during slot alloc/dealloc
PCI: rpadlpar: Fix leaked device_node references in add/remove paths
Bjorn Helgaas [Mon, 13 May 2019 23:34:30 +0000 (18:34 -0500)]
Merge branch 'pci/enumeration'
- Enable PCIe services for host controller drivers that use managed host
bridge alloc (Jean-Philippe Brucker)
- Add quirk to clear PCIe Retrain Link bit to work around Pericom bridge
erratum (Stefan Mätje)
- Add "external-facing" DT property to identify cases where we require
IOMMU protection from untrusted devices (Jean-Philippe Brucker)
- Support fixed bus numbers from bridge Enhanced Allocation capabilities
(Subbaraya Sundeep)
* pci/enumeration:
PCI: Assign bus numbers present in EA capability for bridges
PCI: OF: Support "external-facing" property
dt-bindings: Add "external-facing" PCIe port property
PCI: Rework pcie_retrain_link() wait loop
PCI: Work around Pericom PCIe-to-PCI bridge Retrain Link erratum
PCI: Factor out pcie_retrain_link() function
PCI: Init PCIe feature bits for managed host bridge alloc
Bjorn Helgaas [Mon, 13 May 2019 23:34:29 +0000 (18:34 -0500)]
Merge branch 'pci/aer'
- Fix pci_aer_init() stub prototype for non-CONFIG_PCIEAER case (Jisheng
Zhang)
* pci/aer:
PCI/AER: Change pci_aer_init() stub to return void
Subrahmanya Lingappa [Tue, 7 May 2019 11:45:16 +0000 (07:45 -0400)]
MAINTAINERS: Add Karthikeyan Mitran and Hou Zhiqiang for Mobiveil PCI
Add Karthikeyan Mitran and Hou Zhiqiang as new maintainers of Mobiveil
controller driver.
Link: https://lore.kernel.org/linux-pci/1557229516-6870-1-git-send-email-l.subrahmanya@mobiveil.co.in
Signed-off-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
[bhelgaas: update names/email addresses to match usage in git history]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>
Lucas Stach [Thu, 4 Apr 2019 16:45:17 +0000 (18:45 +0200)]
PCI: imx6: Allow asynchronous probing
Establishing a PCIe link can take a while; allow asynchronous probing so
that link establishment can happen in the background while other devices
are being probed.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Jisheng Zhang [Fri, 29 Mar 2019 11:59:26 +0000 (11:59 +0000)]
PCI: dwc: Save root bus for driver remove hooks
Currently DWC host does not support the remove callback, but nothing
prevents us from supporting it.
Save the root bus for clean up work in driver remove code paths to allow
DWC host drivers to implement their remove hook as, eg:
static int foo_pcie_remove(struct platform_device *pdev)
{
...
pci_stop_root_bus(pp->root_bus);
pci_remove_root_bus(pp->root_bus);
dw_pcie_free_msi(pp);
...
}
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Jisheng Zhang [Fri, 29 Mar 2019 11:58:53 +0000 (11:58 +0000)]
PCI: dwc: Use devm_pci_alloc_host_bridge() to simplify code
Use devm_pci_alloc_host_bridge() to simplify the error code path. This
also fixes a leak in the dw_pcie_host_init() error path.
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
CC: stable@vger.kernel.org # v4.13+
Jisheng Zhang [Fri, 29 Mar 2019 11:57:54 +0000 (11:57 +0000)]
PCI: dwc: Free MSI in dw_pcie_host_init() error path
If we ever did MSI-related initializations, we need to call
dw_pcie_free_msi() in the error code path.
Remove the IS_ENABLED(CONFIG_PCI_MSI) check for MSI init because
pci_msi_enabled() already has a stub for !CONFIG_PCI_MSI.
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Jisheng Zhang [Fri, 29 Mar 2019 11:57:17 +0000 (11:57 +0000)]
PCI: dwc: Free MSI IRQ page in dw_pcie_free_msi()
To avoid a memory leak, free the page allocated for MSI IRQ in
dw_pcie_free_msi().
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Jisheng Zhang [Fri, 29 Mar 2019 11:56:25 +0000 (11:56 +0000)]
PCI: dwc: Fix dw_pcie_free_msi() if msi_irq is invalid
Check msi_irq variable before calling irq_set_chained_handler() and
irq_set_handler_data(), lest we call those functions for an invalid MSI
IRQ.
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Marc Gonzalez [Mon, 25 Mar 2019 15:42:55 +0000 (16:42 +0100)]
PCI: qcom: Use default config space read function
Move the device class fudge to a proper fixup function, and remove
qcom_pcie_rd_own_conf() which has become useless.
dw_pcie_setup_rc() already did the right thing, but it's broken
on older qcom chips, such as 8064.
Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
Christian König [Thu, 18 Apr 2019 11:58:59 +0000 (13:58 +0200)]
PCI/P2PDMA: Allow P2P DMA between any devices under AMD ZEN Root Complex
The PCI specs say that peer-to-peer DMA should be supported between any two
devices that have a common upstream PCI-to-PCI bridge. But devices under
different Root Ports don't share a common upstream bridge, and PCIe r4.0,
sec 1.3.1, says routing peer-to-peer transactions between Root Ports in the
same Root Complex is optional.
Many Root Complexes, including AMD ZEN, *do* support peer-to-peer DMA even
between Root Ports. Add a whitelist and allow peer-to-peer DMA if both
participants are attached to a Root Complex known to support it.
Link: https://lore.kernel.org/linux-pci/20190418115859.2394-1-christian.koenig@amd.com
Signed-off-by: Christian König <christian.koenig@amd.com>
[bhelgaas: changelog]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:47 +0000 (15:09 +0530)]
misc: pci_endpoint_test: Fix test_reg_bar to be updated in pci_endpoint_test
commit
834b90519925 ("misc: pci_endpoint_test: Add support for
PCI_ENDPOINT_TEST regs to be mapped to any BAR") while adding
test_reg_bar in order to map PCI_ENDPOINT_TEST regs to be mapped to any
BAR failed to update test_reg_bar in pci_endpoint_test, resulting in
test_reg_bar having invalid value when used outside probe.
Fix it.
Fixes:
834b90519925 ("misc: pci_endpoint_test: Add support for PCI_ENDPOINT_TEST regs to be mapped to any BAR")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:46 +0000 (15:09 +0530)]
misc: pci_endpoint_test: Add support to test PCI EP in AM654x
TI's AM654x PCIe EP has a restriction that BAR_0 is mapped to
application registers. "PCIe Inbound Address Translation" section in
AM65x Sitara Processors TRM (SPRUID7 – April 2018) describes BAR0 as
reserved.
Configure pci_endpoint_test to use BAR_2 instead.
Also set alignment to 64K since "PCIe Subsystem Address Translation"
section in TRM indicates minimum ATU window size is 64K.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:45 +0000 (15:09 +0530)]
PCI: designware-ep: Use aligned ATU window for raising MSI interrupts
Certain platforms like K2G reguires the outbound ATU window to be
aligned. The alignment size is already present in mem->page_size.
Use the alignment size present in mem->page_size to configure an
aligned ATU window. In order to raise an interrupt, CPU has to write
to address offset from the start of the window unlike before where
writes were always to the beginning of the ATU window.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:44 +0000 (15:09 +0530)]
PCI: designware-ep: Configure Resizable BAR cap to advertise the smallest size
Configure the Resizable BAR capability to advertise the smallest size
(1MB) for a couple of reasons:
- Host side resource allocation of BAR fails for larger sizes
- Endpoint function driver does not allocate memory for all supported
sizes in the Resizable BAR capability.
If and when there is a usecase required to add more flexibility using
the Resizable BAR capability, this can be revisited.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
[lorenzo.pieralisi@arm.com: updated commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:43 +0000 (15:09 +0530)]
PCI: keystone: Add support for PCIe EP in AM654x Platforms
Add PCIe EP support for AM654x Platforms in pci-keystone.c
Link: https://lore.kernel.org/linux-pci/20190325093947.32633-15-kishon@ti.com/
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
[lorenzo.pieralisi@arm.com: made dev_vdbg() call a comment]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Fri, 26 Apr 2019 12:46:20 +0000 (18:16 +0530)]
dt-bindings: PCI: Add PCI EP DT binding documentation for AM654
Add devicetree binding documentation for PCIe in EP mode present in
AM654 SoC.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Andrey Smirnov [Mon, 15 Apr 2019 00:46:32 +0000 (17:46 -0700)]
PCI: imx6: Use usleep_range() in imx6_pcie_enable_ref_clk()
imx6_pcie_enable_ref_clk() is never called in atomic context, so
there's no need to use udelay(). Replace it with usleep_range().
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Andrey Smirnov [Mon, 15 Apr 2019 00:46:31 +0000 (17:46 -0700)]
PCI: imx6: Use flags to indicate support for suspend
Now that driver data has flags variable that can be used to indicate
quirks/features supported we can switch the code to use it instead of
having a special function that does so based on variant alone. No
functional change intended.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Andrey Smirnov [Mon, 15 Apr 2019 00:46:30 +0000 (17:46 -0700)]
PCI: imx6: Restrict PHY register data to 16-bit
PHY registers on i.MX6 are 16-bit wide, so we can get rid of explicit
masking if we restrict pcie_phy_read()/pcie_phy_write() to use 'u16'
instead of 'int'. No functional change intended.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Andrey Smirnov [Mon, 15 Apr 2019 00:46:29 +0000 (17:46 -0700)]
PCI: imx6: Simplify pcie_phy_poll_ack()
Simplify pcie_phy_poll_ack() by incorporating shifting into constant
definition and convert the code to use 'bool'. No functional change
intended.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Andrey Smirnov [Mon, 15 Apr 2019 00:46:28 +0000 (17:46 -0700)]
PCI: imx6: Simplify bit operations in PHY functions
Simplify the code by incorporating left shifts into constant
definitions as well as using FIELD_PREP/GENMASK. No functional change
intended.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Andrey Smirnov [Mon, 15 Apr 2019 00:46:27 +0000 (17:46 -0700)]
PCI: imx6: Make use of BIT() in constant definitions
Avoid using explicit left shifts and convert various definitions to
use BIT() instead. No functional change intended.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Andrey Smirnov [Mon, 15 Apr 2019 00:46:26 +0000 (17:46 -0700)]
PCI: dwc: imx6: Share PHY debug register definitions
Both pcie-designware.c and pci-imx6.c contain custom definitions for
PHY debug registers R0/R1 and on top of that there's already a
definition for R0 in pcie-designware.h. Move all of the definitions to
pcie-designware.h. No functional change intended.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Andrey Smirnov [Mon, 15 Apr 2019 00:46:25 +0000 (17:46 -0700)]
PCI: imx6: Remove PCIE_PL_PFLR_* constants
Code using these constants was removed in commit
a71280722eeb ("PCI:
imx6: Remove LTSSM disable workaround"). No functional change
intended.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Andrey Smirnov [Mon, 15 Apr 2019 00:46:24 +0000 (17:46 -0700)]
PCI: imx6: Return -ETIMEOUT from imx6_pcie_wait_for_speed_change()
Change error code from -EINVAL to -ETIMEDOUT in
imx6_pcie_wait_for_speed_change() since that error code seems more
appropriate.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Andrey Smirnov [Mon, 15 Apr 2019 00:46:23 +0000 (17:46 -0700)]
PCI: imx6: Drop imx6_pcie_wait_for_link()
All calls to imx6_pcie_wait_for_link() share the same error path and
the state of PHY debug registers will already be printed there, so
there's no real reason we can't just use dw_pcie_wait_for_link(). Drop
imx6_pcie_wait_for_link() and replace it with dw_pcie_wait_for_link().
Suggested-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Andrey Smirnov [Mon, 15 Apr 2019 00:46:22 +0000 (17:46 -0700)]
PCI: imx6: Simplify imx7d_pcie_wait_for_phy_pll_lock()
Make use of regmap_read_poll_timeout() to simplify
imx7d_pcie_wait_for_phy_pll_lock(). No functional change intended.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Srinath Mannam [Fri, 26 Apr 2019 09:20:04 +0000 (14:50 +0530)]
PCI: iproc: Enable iProc config read for PAXBv2
iProc config read flag has to be enabled for PAXBv2 instead of PAXB.
Fixes:
f78e60a29d4f ("PCI: iproc: Reject unconfigured physical functions from PAXC")
Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Heiner Kallweit [Wed, 24 Apr 2019 19:17:19 +0000 (21:17 +0200)]
platform/chrome: chromeos_laptop: use pci_dev_id() helper
Use new helper pci_dev_id() to simplify the code.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-By: Benson Leung <bleung@chromium.org>
Heiner Kallweit [Wed, 24 Apr 2019 19:16:41 +0000 (21:16 +0200)]
stmmac: pci: Use pci_dev_id() helper
Use new helper pci_dev_id() to simplify the code.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Heiner Kallweit [Wed, 24 Apr 2019 19:16:10 +0000 (21:16 +0200)]
iommu/vt-d: Use pci_dev_id() helper
Use new helper pci_dev_id() to simplify the code.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Joerg Roedel <jroedel@suse.de>
Heiner Kallweit [Wed, 24 Apr 2019 19:15:25 +0000 (21:15 +0200)]
iommu/amd: Use pci_dev_id() helper
Use new helper pci_dev_id() to simplify the code.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Joerg Roedel <jroedel@suse.de>
Heiner Kallweit [Wed, 24 Apr 2019 19:14:55 +0000 (21:14 +0200)]
drm/amdkfd: Use pci_dev_id() helper
Use new helper pci_dev_id() to simplify the code.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Christian König <christian.koenig@amd.com>
Heiner Kallweit [Wed, 24 Apr 2019 19:14:25 +0000 (21:14 +0200)]
powerpc/powernv/npu: Use pci_dev_id() helper
Use new helper pci_dev_id() to simplify the code.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Heiner Kallweit [Wed, 24 Apr 2019 19:13:25 +0000 (21:13 +0200)]
r8169: use pci_dev_id() helper
Use new helper pci_dev_id() to simplify the code.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: David S. Miller <davem@davemloft.net>
Heiner Kallweit [Wed, 24 Apr 2019 19:11:58 +0000 (21:11 +0200)]
PCI: Add pci_dev_id() helper
In several places in the kernel we find PCI_DEVID used like this:
PCI_DEVID(dev->bus->number, dev->devfn)
Add a "pci_dev_id(struct pci_dev *dev)" helper to simplify callers.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Jonathan Chocron [Thu, 28 Mar 2019 11:57:56 +0000 (13:57 +0200)]
PCI: al: Add Amazon Annapurna Labs PCIe host controller driver
Add driver for Amazon's Annapurna Labs PCIe host controller. The
controller is based on DesignWare's IP.
The controller doesn't support accessing the Root Port's config space via
ECAM, so we obtain its base address via an AMZN0001 device.
Furthermore, the DesignWare PCIe controller doesn't filter out config
transactions sent to devices 1 and up on its bus, so they are filtered by
the driver.
All subordinate buses do support ECAM access.
Implementing specific PCI config access functions involves:
- Adding an init function to obtain the Root Port's base address from
an AMZN0001 device.
- Adding a new entry in the MCFG quirk array.
[bhelgaas: Note that there is no Kconfig option for this driver because it
is only intended for use with the generic ACPI host bridge driver. This
driver is only needed because the DesignWare IP doesn't completely support
ECAM access to the root bus.]
Link: https://lore.kernel.org/lkml/1553774276-24675-1-git-send-email-jonnyc@amazon.com
Co-developed-by: Vladimir Aerov <vaerov@amazon.com>
Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
Signed-off-by: Vladimir Aerov <vaerov@amazon.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Lyude Paul [Tue, 12 Feb 2019 22:02:30 +0000 (17:02 -0500)]
PCI: Reset Lenovo ThinkPad P50 nvgpu at boot if necessary
On ThinkPad P50 SKUs with an Nvidia Quadro M1000M instead of the M2000M
variant, the BIOS does not always reset the secondary Nvidia GPU during
reboot if the laptop is configured in Hybrid Graphics mode. The reason is
unknown, but the following steps and possibly a good bit of patience will
reproduce the issue:
1. Boot up the laptop normally in Hybrid Graphics mode
2. Make sure nouveau is loaded and that the GPU is awake
3. Allow the Nvidia GPU to runtime suspend itself after being idle
4. Reboot the machine, the more sudden the better (e.g. sysrq-b may help)
5. If nouveau loads up properly, reboot the machine again and go back to
step 2 until you reproduce the issue
This results in some very strange behavior: the GPU will be left in exactly
the same state it was in when the previously booted kernel started the
reboot. This has all sorts of bad side effects: for starters, this
completely breaks nouveau starting with a mysterious EVO channel failure
that happens well before we've actually used the EVO channel for anything:
nouveau 0000:01:00.0: disp: chid 0 mthd 0000 data
00000400 00001000 00000002
This causes a timeout trying to bring up the GR ctx:
nouveau 0000:01:00.0: timeout
WARNING: CPU: 0 PID: 12 at drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c:1547 gf100_grctx_generate+0x7b2/0x850 [nouveau]
Hardware name: LENOVO 20EQS64N0B/20EQS64N0B, BIOS N1EET82W (1.55 ) 12/18/2018
Workqueue: events_long drm_dp_mst_link_probe_work [drm_kms_helper]
...
nouveau 0000:01:00.0: gr: wait for idle timeout (en: 1, ctxsw: 0, busy: 1)
nouveau 0000:01:00.0: gr: wait for idle timeout (en: 1, ctxsw: 0, busy: 1)
nouveau 0000:01:00.0: fifo: fault 01 [WRITE] at
0000000000008000 engine 00 [GR] client 15 [HUB/SCC_NB] reason c4 [] on channel -1 [
0000000000 unknown]
The GPU never manages to recover. Booting without loading nouveau causes
issues as well, since the GPU starts sending spurious interrupts that cause
other device's IRQs to get disabled by the kernel:
irq 16: nobody cared (try booting with the "irqpoll" option)
...
handlers:
[<
000000007faa9e99>] i801_isr [i2c_i801]
Disabling IRQ #16
...
serio: RMI4 PS/2 pass-through port at rmi4-00.fn03
i801_smbus 0000:00:1f.4: Timeout waiting for interrupt!
i801_smbus 0000:00:1f.4: Transaction timeout
rmi4_f03 rmi4-00.fn03: rmi_f03_pt_write: Failed to write to F03 TX register (-110).
i801_smbus 0000:00:1f.4: Timeout waiting for interrupt!
i801_smbus 0000:00:1f.4: Transaction timeout
rmi4_physical rmi4-00: rmi_driver_set_irq_bits: Failed to change enabled interrupts!
This causes the touchpad and sometimes other things to get disabled.
Since this happens without nouveau, we can't fix this problem from nouveau
itself.
Add a PCI quirk for the specific P50 variant of this GPU. Make sure the
GPU is advertising NoReset- so we don't reset the GPU when the machine is
in Dedicated graphics mode (where the GPU being initialized by the BIOS is
normal and expected). Map the GPU MMIO space and read the magic 0x2240c
register, which will have bit 1 set if the device was POSTed during a
previous boot. Once we've confirmed all of this, reset the GPU and
re-disable it - bringing it back to a healthy state.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=203003
Link: https://lore.kernel.org/lkml/20190212220230.1568-1-lyude@redhat.com
Signed-off-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: nouveau@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Cc: Karol Herbst <kherbst@redhat.com>
Cc: Ben Skeggs <skeggsb@gmail.com>
Cc: stable@vger.kernel.org
Alexandru Gagniuc [Fri, 15 Mar 2019 19:29:40 +0000 (14:29 -0500)]
PCI/ACPI: Advertise _HPX Type 3 support via _OSC
_OSC now has a way to inform firmware that OS has the capability to
interpret _HPX Type 3 setting records. This was added by the following
PCI Firmware Specification ECN:
ECN: _HPX and PCIe Completion Timeout related _OSC Enhancements
Date: September 12, 2018
Affected Document: PCI Firmware Specification, Rev. 3.2
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Alexandru Gagniuc [Fri, 8 Feb 2019 16:24:13 +0000 (10:24 -0600)]
PCI/ACPI: Implement _HPX Type 3 Setting Record
The _HPX Type 3 Setting Record is intended to be more generic and allow
configuration of settings not possible with Type 2 records. For example,
firmware could ensure that the completion timeout value is set accordingly
throughout the PCI tree.
Implement support for _HPX Type 3 Setting Records, which were added in the
ACPI 6.3 spec.
Link: https://lore.kernel.org/lkml/20190208162414.3996-4-mr.nuke.me@gmail.com
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Alexandru Gagniuc [Fri, 19 Apr 2019 19:27:36 +0000 (14:27 -0500)]
PCI/ACPI: Remove the need for 'struct hotplug_params'
We used to first parse all the _HPP and _HPX tables before using the
information to program registers of PCIe devices. Up through HPX Type 2,
there was only one structure of each type, so we could cheat and store it
on the stack.
With HPX Type 3 we get an arbitrary number of entries, so the above model
doesn't scale that well. Instead of parsing all tables at once, parse and
program each entry separately. For _HPP and _HPX Types 0 through 2, this
is functionally equivalent. The change enables the upcoming _HPX Type 3 to
integrate more easily.
Link: https://lore.kernel.org/lkml/20190208162414.3996-3-mr.nuke.me@gmail.com
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[bhelgaas: fix build errors]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Alexandru Gagniuc [Fri, 8 Feb 2019 16:24:11 +0000 (10:24 -0600)]
PCI/ACPI: Do not export pci_get_hp_params()
pci_get_hp_params() is only used within drivers/pci, and there is no reason
to make it available outside of the PCI core, so stop exporting it.
Link: https://lore.kernel.org/lkml/20190208162414.3996-2-mr.nuke.me@gmail.com
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
James Prestwood [Mon, 7 Jan 2019 21:32:48 +0000 (13:32 -0800)]
PCI: Mark Atheros AR9462 to avoid bus reset
When using PCI passthrough with this device, the host machine locks up
completely when starting the VM, requiring a hard reboot. Add a quirk to
avoid bus resets on this device.
Fixes:
c3e59ee4e766 ("PCI: Mark Atheros AR93xx to avoid bus reset")
Link: https://lore.kernel.org/linux-pci/20190107213248.3034-1-james.prestwood@linux.intel.com
Signed-off-by: James Prestwood <james.prestwood@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org # v3.14+
Mika Westerberg [Mon, 15 Apr 2019 08:41:42 +0000 (11:41 +0300)]
PCI/LINK: Disable bandwidth notification interrupt during suspend
If the bandwidth notification interrupt is left unmasked when entering
suspend to idle, it triggers immediately bringing the system back to
working state.
To keep that from happening, disable the interrupt when entering system
sleep and enable it again during resume.
Reported-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Wesley Sheng [Mon, 15 Apr 2019 14:41:42 +0000 (22:41 +0800)]
switchtec: Fix unintended mask of MRPC event
When running application tool switchtec-user's `firmware update` and `event
wait` commands concurrently, sometimes the firmware update speed reduced
significantly.
It is because when the MRPC event happened after MRPC event occurrence
check but before the event mask loop reaches its header register in event
ISR, the MRPC event would be masked unintentionally. Since there's no
chance to enable it again except for a module reload, all the following
MRPC execution completion checks time out.
Fix this bug by skipping the mask operation for MRPC event in event ISR,
same as what we already do for LINK event.
Fixes:
52eabba5bcdb ("switchtec: Add IOCTLs to the Switchtec driver")
Signed-off-by: Wesley Sheng <wesley.sheng@microchip.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
Wesley Sheng [Mon, 15 Apr 2019 14:41:41 +0000 (22:41 +0800)]
switchtec: Increase PFF limit from 48 to 255
The Switchtec devices supports two PCIe Function Frameworks (PFFs) per
upstream port (one for the port itself and one for the management endoint),
and each PFF may have up to 255 ports. Previously the driver only
supported 48 of those ports, and the SWITCHTEC_IOCTL_EVENT_SUMMARY ioctl
only returned information about those 48.
Increase SWITCHTEC_MAX_PFF_CSR from 48 to 255 so the driver supports all
255 possible ports.
Rename SWITCHTEC_IOCTL_EVENT_SUMMARY and associated struct
switchtec_ioctl_event_summary to SWITCHTEC_IOCTL_EVENT_SUMMARY_LEGACY and
switchtec_ioctl_event_summary_legacy with so existing applications work
unchanged, supporting up to 48 ports.
Add replacement SWITCHTEC_IOCTL_EVENT_SUMMARY and struct
switchtec_ioctl_event_summary that new and recompiled applications support
up to 255 ports.
Signed-off-by: Wesley Sheng <wesley.sheng@microchip.com>
[bhelgaas: changelog]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
Wenwen Wang [Wed, 17 Apr 2019 14:18:50 +0000 (09:18 -0500)]
x86/PCI: Fix PCI IRQ routing table memory leak
In pcibios_irq_init(), the PCI IRQ routing table 'pirq_table' is first
found through pirq_find_routing_table(). If the table is not found and
CONFIG_PCI_BIOS is defined, the table is then allocated in
pcibios_get_irq_routing_table() using kmalloc(). Later, if the I/O APIC is
used, this table is actually not used. In that case, the allocated table
is not freed, which is a memory leak.
Free the allocated table if it is not used.
Signed-off-by: Wenwen Wang <wang6495@umn.edu>
[bhelgaas: added Ingo's reviewed-by, since the only change since v1 was to
use the irq_routing_table local variable name he suggested]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Ingo Molnar <mingo@kernel.org>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Johannes Thumshirn [Wed, 17 Apr 2019 08:23:56 +0000 (10:23 +0200)]
PCI: Remove unused pci_request_region_exclusive()
pci_request_region_exclusive() was introduced with commit
e8de1481fd71
("resource: allow MMIO exclusivity for device drivers") in 2.6.29 which
was released 2008.
It never had an in tree user since then, so after 11 years later let's
remove it.
Signed-off-by: Johannes Thumshirn <jthumshirn@suse.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Subbaraya Sundeep [Mon, 19 Nov 2018 13:14:32 +0000 (18:44 +0530)]
PCI: Assign bus numbers present in EA capability for bridges
The "Enhanced Allocation (EA) for Memory and I/O Resources" ECN, approved
23 October 2014, sec 6.9.1.2, specifies a second DW in the capability for
type 1 (bridge) functions to describe fixed secondary and subordinate bus
numbers. This ECN was included in the PCIe r4.0 spec, but sec 6.9.1.2 was
omitted, presumably by mistake.
Read fixed bus numbers from the EA capability for bridges.
Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com>
[bhelgaas: add pci_ea_fixed_busnrs() return value]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Vidya Sagar [Tue, 16 Apr 2019 10:51:44 +0000 (16:21 +0530)]
PCI: tegra: Use the DMA-API to get the MSI address
Since the upstream MSI memory writes are generated by downstream
devices, it is logically correct to have MSI target memory coming from
the DMA pool reserved for PCIe than from the general memory pool
reserved for CPU access to avoid PCIe DMA addresses coinciding with
MSI target address thereby raising unwanted MSI interrupts.
Enforce this behaviour by retrieving the MSI address through the DMA
API.
Limit the MSI target address to 32-bits to make it work for PCIe
endpoints that support only 32-bit MSI target address; endpoints that
support 64-bit MSI target address work with 32-bit MSI target
address too.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
[lorenzo.pieralisi@arm.com: updated commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:42 +0000 (15:09 +0530)]
PCI: dwc: Add callbacks for accessing dbi2 address space
Certain platforms like TI's AM654 do not have aseparate address space for
dbi2 instead they are accessed using the same address space as dbi
with some configuration bit set. In order to support such platforms,
add callbacks for accessing dbi2 address space.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:41 +0000 (15:09 +0530)]
PCI: dwc: Fix dw_pcie_ep_find_capability() to return correct capability offset
commit
beb4641a787d ("PCI: dwc: Add MSI-X callbacks handler") while
adding MSI-X callback handler, introduced dw_pcie_ep_find_capability()
and __dw_pcie_ep_find_next_cap() for finding the MSI and MSIX capability.
However if MSI or MSIX capability is the last capability (i.e there are
no additional items in the capabilities list and the Next Capability
Pointer is set to '0'), __dw_pcie_ep_find_next_cap will return '0'
even though MSI or MSIX capability may be present because of
incorrect ordering of the "next_cap_ptr" check. Fix it.
Fixes:
beb4641a787d ("PCI: dwc: Add MSI-X callbacks handler")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:40 +0000 (15:09 +0530)]
PCI: dwc: Add const qualifier to struct dw_pcie_ep_ops
Add const qualifier to struct dw_pcie_ep_ops member of
struct dw_pcie_ep.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:39 +0000 (15:09 +0530)]
PCI: endpoint: Add support to specify alignment for buffers allocated to BARs
The address that is allocated using pci_epf_alloc_space() is
directly written to the target address of the Inbound Address
Translation unit (ie the HW component implementing inbound address
decoding) on endpoint controllers.
Designware IP [1] has a configuration parameter (CX_ATU_MIN_REGION_SIZE
[2]) which has 64KB as default value and the lower 16 bits of the Base,
Limit and Target registers of the Inbound ATU are fixed to zero. If the
programmed memory address is not aligned to 64 KB boundary this causes
memory corruption.
Modify pci_epf_alloc_space() API to take alignment size as argument in
order to allocate buffers to be mapped to BARs with an alignment that
suits the platform where they are used.
Add an 'align' parameter to epc_features which can be used by platform
drivers to specify the BAR allocation alignment requirements and use
this while invoking pci_epf_alloc_space().
[1] "I/O and MEM Match Modes" section in DesignWare Cores PCI Express
Controller Databook version 4.90a
[2] http://www.ti.com/lit/ug/spruid7c/spruid7c.pdf
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:38 +0000 (15:09 +0530)]
PCI: keystone: Add support to set the max link speed from DT
PCIe in TI's AM654 devices is by default configured to work in GEN3 mode.
However PCIe does not work reliably in GEN3 mode because of SERDES
configuration.
Add support to set the link speed to GEN1, GEN2 or GEN3 based on
"max-link-speed" DT property with GEN2 as the default speed if
"max-link-speed" is absent.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:37 +0000 (15:09 +0530)]
PCI: OF: Allow of_pci_get_max_link_speed() to be used by PCI Endpoint drivers
of_pci_get_max_link_speed() is built only if CONFIG_PCI is enabled.
Make of_pci_get_max_link_speed() to be also used by PCI Endpoint
controllers with just CONFIG_PCI_ENDPOINT enabled.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:36 +0000 (15:09 +0530)]
PCI: keystone: Invoke phy_reset() API before enabling PHY
SERDES connected to the PCIe controller in AM654 requires
power on reset enable (POR_EN) to be set in the SERDES. The
SERDES driver sets POR_EN in the reset ops and it has to be
invoked before init or enable ops. In order for SERDES driver
to set POR_EN, invoke the phy_reset() API in pci-keystone driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:35 +0000 (15:09 +0530)]
PCI: keystone: Add support for PCIe RC in AM654x Platforms
Add PCIe RC support for AM654x Platforms in pci-keystone.c
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:34 +0000 (15:09 +0530)]
dt-bindings: PCI: Add PCI RC DT binding documentation for AM654
Add devicetree binding documentation for PCIe in RC mode present in
AM654 SoC.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:33 +0000 (15:09 +0530)]
PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64
hook_fault_code() is an ARM32 specific API for hooking into data abort.
AM65X platforms (that integrate ARM v8 cores and select CONFIG_ARM64 as
arch) rely on pci-keystone.c but on them the enumeration of a
non-present BDF does not trigger a bus error, so the fixup exception
provided by calling hook_fault_code() is not needed and can be guarded
with CONFIG_ARM.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
[lorenzo.pieralisi@arm.com: commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:32 +0000 (15:09 +0530)]
PCI: dwc: Fix ATU identification for designware version >= 4.80
Synopsys designware version >= 4.80 uses a separate register space
for programming ATU. The current code identifies if there exists a
separate register space by accessing the register address of ATUs
in designware version < 4.80. Accessing this address results in
abort in the case of K2G.
Fix it here by adding "version" member to struct dw_pcie. This should be
set by platform specific drivers and designware core will use it to
identify if the platform has a separate ATU space. For platforms which
have not populated the version member, the old method of identification
will still be used.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:31 +0000 (15:09 +0530)]
PCI: dwc: Enable iATU unroll for endpoint too
iatu_unroll_enabled flag is set only for Designware in host mode.
However iATU unroll can be applicable for endpoint mode too. Set
iatu_unroll_enabled flag in dw_pcie_setup() which is common for
both host mode and endpoint mode.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:30 +0000 (15:09 +0530)]
dt-bindings: PCI: Document "atu" reg-names
Document "atu" reg-names required to get the register space for ATU in
Synopsys designware core version >= 4.80.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:29 +0000 (15:09 +0530)]
PCI: keystone: Explicitly set the PCIe mode
Explicitly set the PCIe mode to BOOTCFG_DEVCFG instead of always
relying on the default values. This is required when EP mode has to
be explicitly written to BOOTCFG_DEVCFG register.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:28 +0000 (15:09 +0530)]
dt-bindings: PCI: Add dt-binding to configure PCIe mode
Add "ti,syscon-pcie-mode" dt-binding to hold phandle to the syscon
register that should be used to configure PCIe in RC mode or EP mode.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:27 +0000 (15:09 +0530)]
PCI: keystone: Move resources initialization to prepare for EP support
Move platform_get_resource() calls for resources that are applicable to
both host and endpoint mode (ie "dbics" and "app") from
ks_add_pcie_port() to the probe() callback, in preparation for adding
endpoint support to pci-keystone driver.
No functional change intended.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Colin Ian King [Sat, 30 Mar 2019 15:09:10 +0000 (15:09 +0000)]
PCI: rockchip: Fix rockchip_pcie_ep_assert_intx() bitwise operations
Currently the bitwise operations on the u16 variable 'status' with
the setting ROCKCHIP_PCIE_EP_CMD_STATUS_IS are incorrect because
ROCKCHIP_PCIE_EP_CMD_STATUS_IS is 1UL<<19 which is wider than the
u16 variable.
Fix this by making status a u32.
Fixes:
cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Mukesh Ojha <mojha@codeaurora.org>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
Kangjie Lu [Fri, 15 Mar 2019 05:07:10 +0000 (00:07 -0500)]
PCI: endpoint: Fix a potential NULL pointer dereference
In case alloc_workqueue() fails, return -ENOMEM to avoid
potential NULL pointer dereferences.
Signed-off-by: Kangjie Lu <kjlu@umn.edu>
[lorenzo.pieralisi@arm.com: commit log and code update]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Jisheng Zhang [Fri, 12 Apr 2019 06:43:06 +0000 (06:43 +0000)]
PCI/AER: Change pci_aer_init() stub to return void
Commit
60ed982a4e78 ("PCI/AER: Move internal declarations to
drivers/pci/pci.h") changed pci_aer_init() to return "void", but didn't
change the stub for when CONFIG_PCIEAER isn't enabled. Change the stub to
match.
Fixes:
60ed982a4e78 ("PCI/AER: Move internal declarations to drivers/pci/pci.h")
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org # v4.19+
Honghui Zhang [Mon, 18 Mar 2019 08:27:55 +0000 (16:27 +0800)]
arm64: dts: mt2712: Remove un-used property for PCIe
The "num-lanes" property for PCIe is not used, remove it.
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Jean-Philippe Brucker [Thu, 11 Apr 2019 12:40:27 +0000 (13:40 +0100)]
PCI: OF: Support "external-facing" property
Set the "untrusted" attribute to any PCIe port that has an
"external-facing" device tree property. Any device downstream of this port
will inherit the attribute and have only the strictest IOMMU protection.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Jean-Philippe Brucker [Thu, 11 Apr 2019 12:40:26 +0000 (13:40 +0100)]
dt-bindings: Add "external-facing" PCIe port property
Provide a way for the firmware to tell the OS which devices are external to
the machine and therefore untrusted. The property can describe for example
Thunderbolt and other user-accessible ports, which should always have the
strongest IOMMU protection.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Grant Likely <grant.likely@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Nikolai Kostrigin [Mon, 8 Apr 2019 10:37:25 +0000 (13:37 +0300)]
PCI: Mark AMD Stoney Radeon R7 GPU ATS as broken
ATS is broken on the Radeon R7 GPU (at least for Stoney Ridge based laptop)
and causes IOMMU stalls and system failure. Disable ATS on these devices
to make them usable again with IOMMU enabled.
Thanks to Joerg Roedel <jroedel@suse.de> for help.
[bhelgaas: In the email thread mentioned below, Alex suspects the real
problem is in sbios or iommu, so it may affect only certain systems, and it
may affect other devices in those systems as well. However, per Joerg we
lack the ability to debug further, so this quirk is the best we can do for
now.]
Link: https://bugzilla.kernel.org/show_bug.cgi?id=194521
Link: https://lore.kernel.org/lkml/20190408103725.30426-1-nickel@altlinux.org
Fixes:
9b44b0b09dec ("PCI: Mark AMD Stoney GPU ATS as broken")
Signed-off-by: Nikolai Kostrigin <nickel@altlinux.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Joerg Roedel <jroedel@suse.de>
CC: stable@vger.kernel.org
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:26 +0000 (15:09 +0530)]
PCI: keystone: Use platform_get_resource_byname() to get memory resources
Use platform_get_resource_byname() instead of platform_get_resource()
which uses an index to get memory resources. While at that get the memory
resource defined specifically for configuration space instead of
deriving the configuration space address from dbics address space.
Since the pci-keystone driver has never worked in the mainline kernel,
DT backward compatibility is not an issue.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:25 +0000 (15:09 +0530)]
PCI: keystone: Perform host initialization in a single function
No functional change. Instead of having two functions
ks_pcie_add_pcie_port() and ks_pcie_dw_host_init() for initializing
host, have a single function to perform all the host initialization.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:24 +0000 (15:09 +0530)]
dt-bindings: PCI: keystone: Add "reg-names" binding information
Add "reg-names" binding information in order for device tree node
to be populated with the correct register strings.
This will break old DT compatibility. However Keystone PCI has never
worked in upstream kernel due to lack of SERDES support, so, before
SERDES support is added, cleanup the Keystone PCI dt-bindings.
This new binding will also be used by PCI in AM654 platform.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:23 +0000 (15:09 +0530)]
PCI: keystone: Cleanup error_irq configuration
pci-keystone driver uses irq_of_parse_and_map() to get irq number of
error_irq.
Use platform_get_irq() instead and move platform_get_irq() and
request_irq() of error_irq from ks_pcie_add_pcie_port to ks_pcie_probe
since error_irq is common to both RC mode and EP mode.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Mon, 25 Mar 2019 09:39:22 +0000 (15:09 +0530)]
PCI: keystone: Add start_link()/stop_link() dw_pcie_ops
Add start_link()/stop_link() dw_pcie_ops and invoke ks_pcie_start_link()
directly from host_init. start_link()/stop_link() ops are required for
adding EP mode support.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Kishon Vijay Abraham I [Thu, 4 Apr 2019 11:06:09 +0000 (16:36 +0530)]
tools: PCI: Handle pcitest.sh independently from pcitest
Handling pcitest.sh along with pcitest (obtained by compiling
pcitest.c) results in pcitest.sh getting removed inadvertently
while "make -C tools/pci clean".
Fix it by handling pcitest.sh independently of pcitest.
Fixes:
1ce78ce09430 ("tools: PCI: Change pcitest compiling process")
Reported-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Kishon Vijay Abraham I [Thu, 4 Apr 2019 11:06:08 +0000 (16:36 +0530)]
tools: PCI: Add 'h' in optstring of getopt()
'h' is a valid option character for the pcitest tool used to print
the pcitest usage.
Add 'h' in optstring of getopt() in order to get rid of "pcitest:
invalid option -- 'h'" warning.
While at that remove unncessary case '?'.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>