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Ian Rogers [Wed, 25 Jun 2014 05:48:01 +0000 (22:48 -0700)]
Weaken condition to dump a thread's stack in a debug build.
If the current thread isn't suspended its also ok to dump the stack.
Bug:
14229281
Change-Id: I2810ea79bc4330bb6e9616436d74076b5997c20b
Ian Rogers [Wed, 25 Jun 2014 05:27:36 +0000 (05:27 +0000)]
Merge "x86_64: Fix wide argument increment"
Ian Rogers [Wed, 25 Jun 2014 05:11:55 +0000 (05:11 +0000)]
Merge "x86_64: int-to-long should ensure that int in kCoreReg"
Serguei Katkov [Tue, 24 Jun 2014 17:25:35 +0000 (00:25 +0700)]
x86_64: int-to-long should ensure that int in kCoreReg
it is possible that int in xmm so implementation of int-to-long
should ensure that src in core reg before usage of move with
sign extension which does not support xmm case.
Change-Id: Ibab9df7564f0f1c1f3e1f5ff67c38f1a5e3cdb69
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Ian Rogers [Wed, 25 Jun 2014 04:45:01 +0000 (04:45 +0000)]
Merge "Fix various test dependencies."
Ian Rogers [Wed, 25 Jun 2014 04:34:09 +0000 (21:34 -0700)]
Fix various test dependencies.
Change-Id: I2e4761f4cc061f74319a7b64ebe67c553d5297df
Chao-ying Fu [Tue, 24 Jun 2014 20:24:36 +0000 (13:24 -0700)]
x86_64: Fix wide argument increment
This patch fixes to always increment the index for a wide argument,
and fixes the index upper bound.
Otherwise, the mapping may be incorrect.
Change-Id: I0116d8fd0a0a5c1270a23129c73a9e3651132977
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Ian Rogers [Tue, 24 Jun 2014 23:48:11 +0000 (23:48 +0000)]
Merge "Multilib ART host."
Ian Rogers [Tue, 17 Jun 2014 15:21:54 +0000 (08:21 -0700)]
Multilib ART host.
Build ART for the host as a multilib project with dalvikvm32 and dalvikvm64
running as 32 or 64-bit repsectfully. Note, currently multilib host builds
are not the default, you make the so by setting BUILD_HOST_64bit=1.
Extend tests to execute in both 32 and 64-bit modes. By default both 32 and
64-bit tests are run, add 32 or 64 to the end of a test name to run it in
purely that flavor.
Given the extra spam, modify oat tests to only generate console output when
the test fails.
Change the test harness so that common commands are run when a test should be
skipped, when it passes or when it fails. Use these commands to generate a
summary of passing, skipped and failing tests. Tests will be skipped if they
are known to be broken or if a test has already failed. Setting the variable
TEST_ART_KEEP_GOING=true will force working tests not to be skipped.
In this change all tests running on the optimizing compiler are marked broken
due to breakages running them in a multilib environment.
Break apart Android.common.mk into its constituent parts, along with other
pieces of reorganization.
Stylistic nit, we refer to make rule targets as targets thereby overloading
the term target. While consistent with make's terminology, its confusing with
the Android notion of target. I've switched to just calling targets rules to
avoid confusion in host tests.
Change-Id: I5190fc3de46800a949fbb06b3f4c258ca89ccde9
Andreas Gampe [Tue, 24 Jun 2014 23:27:32 +0000 (23:27 +0000)]
Merge "AArch64: Add memcmp.S for Arm64."
Hiroshi Yamauchi [Tue, 24 Jun 2014 22:34:17 +0000 (22:34 +0000)]
Merge "Add more read barriers to the class linker."
Hiroshi Yamauchi [Tue, 24 Jun 2014 21:31:37 +0000 (14:31 -0700)]
Add more read barriers to the class linker.
This change makes it possible to concurrently scan the remaining roots
in the class linker (the non-class-table roots that are visited by
ClassLinker::VisitRoots()) by adding read barriers.
Bug:
12687968
Change-Id: I66fecf7a303eee7537429e018f38da8270b18c67
Mathieu Chartier [Tue, 24 Jun 2014 22:30:11 +0000 (22:30 +0000)]
Merge "More advanced timing loggers."
Mathieu Chartier [Fri, 20 Jun 2014 17:37:54 +0000 (10:37 -0700)]
More advanced timing loggers.
The new timing loggers have lower overhead since they only push into
a vector. The new format has two types, a start timing and a stop
timing. You can thing of these as brackets associated with a
timestamp. It uses these to construct various statistics when needed,
such as: Total time, exclusive time, and nesting depth.
Changed PrettyDuration to have a default of 3 digits after the decimal
point.
Exaple of a GC dump with exclusive / total times and indenting:
I/art (23546): GC iteration timing logger [Exclusive time] [Total time]
I/art (23546): 0ms InitializePhase
I/art (23546): 0.305ms/167.746ms MarkingPhase
I/art (23546): 0ms BindBitmaps
I/art (23546): 0ms FindDefaultSpaceBitmap
I/art (23546): 0ms/1.709ms ProcessCards
I/art (23546): 0.183ms ImageModUnionClearCards
I/art (23546): 0.916ms ZygoteModUnionClearCards
I/art (23546): 0.610ms AllocSpaceClearCards
I/art (23546): 1.373ms AllocSpaceClearCards
I/art (23546): 0.305ms/6.318ms MarkRoots
I/art (23546): 2.106ms MarkRootsCheckpoint
I/art (23546): 0.153ms MarkNonThreadRoots
I/art (23546): 4.287ms MarkConcurrentRoots
I/art (23546): 43.461ms UpdateAndMarkImageModUnionTable
I/art (23546): 0ms/112.712ms RecursiveMark
I/art (23546): 112.712ms ProcessMarkStack
I/art (23546): 0.610ms/2.777ms PreCleanCards
I/art (23546): 0.305ms/0.855ms ProcessCards
I/art (23546): 0.153ms ImageModUnionClearCards
I/art (23546): 0.610ms ZygoteModUnionClearCards
I/art (23546): 0.610ms AllocSpaceClearCards
I/art (23546): 0.549ms AllocSpaceClearCards
I/art (23546): 0.549ms MarkRootsCheckpoint
I/art (23546): 0.610ms MarkNonThreadRoots
I/art (23546): 0ms MarkConcurrentRoots
I/art (23546): 0.610ms ScanGrayImageSpaceObjects
I/art (23546): 0.305ms ScanGrayZygoteSpaceObjects
I/art (23546): 0.305ms ScanGrayAllocSpaceObjects
I/art (23546): 1.129ms ScanGrayAllocSpaceObjects
I/art (23546): 0ms ProcessMarkStack
I/art (23546): 0ms/0.977ms (Paused)PausePhase
I/art (23546): 0.244ms ReMarkRoots
I/art (23546): 0.672ms (Paused)ScanGrayObjects
I/art (23546): 0ms (Paused)ProcessMarkStack
I/art (23546): 0ms/0.610ms SwapStacks
I/art (23546): 0.610ms RevokeAllThreadLocalAllocationStacks
I/art (23546): 0ms PreSweepingGcVerification
I/art (23546): 0ms/10.621ms ReclaimPhase
I/art (23546): 0.610ms/0.702ms ProcessReferences
I/art (23546): 0.214ms/0.641ms EnqueueFinalizerReferences
I/art (23546): 0.427ms ProcessMarkStack
I/art (23546): 0.488ms SweepSystemWeaks
I/art (23546): 0.824ms/9.400ms Sweep
I/art (23546): 0ms SweepMallocSpace
I/art (23546): 0.214ms SweepZygoteSpace
I/art (23546): 0.122ms SweepMallocSpace
I/art (23546): 6.226ms SweepMallocSpace
I/art (23546): 0ms SweepMallocSpace
I/art (23546): 2.144ms SweepLargeObjects
I/art (23546): 0.305ms SwapBitmaps
I/art (23546): 0ms UnBindBitmaps
I/art (23546): 0.275ms FinishPhase
I/art (23546): GC iteration timing logger: end, 178.971ms
Change-Id: Ia55b65609468f212b3cd65cda66b843da42be645
Mathieu Chartier [Tue, 24 Jun 2014 22:00:32 +0000 (22:00 +0000)]
Merge "Add logging to monitor deflation."
Mathieu Chartier [Tue, 24 Jun 2014 18:21:59 +0000 (11:21 -0700)]
Add logging to monitor deflation.
Change-Id: I0251ff19e0a3c3b9edc7c7e296f15eb3229f8f7c
Mathieu Chartier [Tue, 24 Jun 2014 01:35:59 +0000 (01:35 +0000)]
Merge "Use reader lock of bulk free lock when not freeing."
Mathieu Chartier [Tue, 24 Jun 2014 00:53:09 +0000 (17:53 -0700)]
Use reader lock of bulk free lock when not freeing.
Should help reduce contention observed in systrace.
Change-Id: Iadb81728d4ba797c3a68acea795b15d7f212e89b
Dave Allison [Mon, 23 Jun 2014 22:34:11 +0000 (22:34 +0000)]
Merge "Fix implicit check option handling for non-cross-compiles"
Dave Allison [Mon, 23 Jun 2014 21:46:53 +0000 (14:46 -0700)]
Fix implicit check option handling for non-cross-compiles
This fixes an issue where the compiler was not being told to
generate implicit checks but the runtime was expecting them.
Bug:
15747876
Change-Id: I65e7475bac245c44d5094eb666d67bc1af327ab1
Brian Carlstrom [Tue, 24 Jun 2014 19:16:20 +0000 (19:16 +0000)]
Merge "Fixed ImageWriter timings not being written out."
Alex Light [Tue, 24 Jun 2014 17:27:40 +0000 (10:27 -0700)]
Fixed ImageWriter timings not being written out.
During host runs of dex2oat the timings for ImageWriter would not be
written out.
Change-Id: I74ce8bae724d1e732a6a1efb1c82804473081693
Andreas Gampe [Tue, 24 Jun 2014 18:44:29 +0000 (18:44 +0000)]
Merge "Revert "ART: Split out more cases of Load/StoreRef, volatile as parameter""
Andreas Gampe [Tue, 24 Jun 2014 18:42:06 +0000 (18:42 +0000)]
Revert "ART: Split out more cases of Load/StoreRef, volatile as parameter"
This reverts commit
2689fbad6b5ec1ae8f8c8791a80c6fd3cf24144d.
Breaks the build.
Change-Id: I9faad4e9a83b32f5f38b2ef95d6f9a33345efa33
Andreas Gampe [Tue, 24 Jun 2014 17:29:59 +0000 (17:29 +0000)]
Merge "ART: Split out more cases of Load/StoreRef, volatile as parameter"
Andreas Gampe [Tue, 24 Jun 2014 21:52:18 +0000 (21:52 +0000)]
Merge "Revert "Revert "ART: Split out more cases of Load/StoreRef, volatile as parameter"""
Andreas Gampe [Tue, 24 Jun 2014 18:46:29 +0000 (18:46 +0000)]
Revert "Revert "ART: Split out more cases of Load/StoreRef, volatile as parameter""
This reverts commit
de68676b24f61a55adc0b22fe828f036a5925c41.
Fixes an API comment, and differentiates between inserting and appending.
Change-Id: I0e9a21bb1d25766e3cbd802d8b48633ae251a6bf
Dave Allison [Tue, 24 Jun 2014 16:08:12 +0000 (16:08 +0000)]
Merge "Add some more instruction support to optimizing compiler."
Dave Allison [Tue, 17 Jun 2014 03:44:29 +0000 (20:44 -0700)]
Add some more instruction support to optimizing compiler.
This adds a few more DEX instructions to the optimizing compiler's
builder (constants, moves, if_xx, etc).
Also:
* Changes the codegen for IF_XX instructions to use a condition
rather than comparing a value against 0.
* Fixes some instructions in the ARM disassembler.
* Fixes PushList and PopList in the thumb2 assembler.
* Switches the assembler for the optimizing compiler to thumb2
rather than ARM.
Change-Id: Iaafcd02243ccc5b03a054ef7a15285b84c06740f
Sebastien Hertz [Tue, 24 Jun 2014 14:16:32 +0000 (14:16 +0000)]
Merge "Use GCC on ARM64"
Calin Juravle [Tue, 24 Jun 2014 10:57:35 +0000 (10:57 +0000)]
Merge "Log profile info only on debug builds."
Calin Juravle [Tue, 24 Jun 2014 10:56:44 +0000 (10:56 +0000)]
Merge "Always compile leafs during profile based compilation."
Dave Allison [Tue, 24 Jun 2014 01:56:51 +0000 (01:56 +0000)]
Merge "Move trampolines to thumb2 instead of ARM"
Andreas Gampe [Mon, 23 Jun 2014 20:23:04 +0000 (13:23 -0700)]
ART: Split out more cases of Load/StoreRef, volatile as parameter
Splits out more cases of ref registers being loaded or stored. For
code clarity, adds volatile as a flag parameter instead of a separate
method.
On ARM64, continue cleanup. Add flags to print/fatal on size mismatches.
Change-Id: I30ed88433a6b4ff5399aefffe44c14a5e6f4ca4e
Dave Allison [Mon, 23 Jun 2014 20:19:59 +0000 (13:19 -0700)]
Move trampolines to thumb2 instead of ARM
Currently the entrypoint trampolines are compiled using the ARM32 assembler.
This changes that to use the thumb2 assembler for consistency with the
other compiled code.
Bug:
15455279
Change-Id: I6bacdf359e2ae4c0967fb5cd9dc694af11f802ec
Calin Juravle [Mon, 23 Jun 2014 14:22:29 +0000 (15:22 +0100)]
Log profile info only on debug builds.
Change-Id: I80cce951bf4cce988c9ab8373be3e335860eadf3
Calin Juravle [Mon, 23 Jun 2014 13:40:31 +0000 (14:40 +0100)]
Always compile leafs during profile based compilation.
Bug:
12877748
Change-Id: Idbee9eaa87c419454728de195bdbdd9b0e6b7b50
Bill Buzbee [Mon, 23 Jun 2014 20:16:10 +0000 (20:16 +0000)]
Merge "x86_64: Correct fix for cmp-long"
Serguei Katkov [Mon, 23 Jun 2014 06:23:38 +0000 (13:23 +0700)]
x86_64: Correct fix for cmp-long
We cannot rely on the sign of the sub instruction because
LONG_MAX - LONG_MIN = -1 and the sign will indicate that
LONG_MAX < KONG_MIN and it is incorrect.
The fix also contains small improvement for load wide constant.
Change-Id: I74df70d7c198cebff5cad8c1d5614c1d29b79a1b
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Ian Rogers [Mon, 23 Jun 2014 21:09:35 +0000 (21:09 +0000)]
Merge "Mac doesn't define MAP_ANONYMOUS"
Ian Rogers [Mon, 23 Jun 2014 21:07:03 +0000 (14:07 -0700)]
Mac doesn't define MAP_ANONYMOUS
Fix mac build.
Change-Id: I607e8fff227259fbf27e468193a705c8c3fc1b59
Andreas Gampe [Mon, 23 Jun 2014 16:04:54 +0000 (16:04 +0000)]
Merge "Revert "Revert "ART: Fix StoreValue to use RefDisp when necessary."""
Andreas Gampe [Mon, 23 Jun 2014 15:39:00 +0000 (15:39 +0000)]
Revert "Revert "ART: Fix StoreValue to use RefDisp when necessary.""
This reverts commit
e98297bafe84e2ac15eb73739f27826fcaae1203.
No matter if holding a reference or not, the store needs to be tagged
as updating a Dalvik register.
Change-Id: Icb80e1b6f82103cff33ee971faaaa02f9ad4a683
Ian Rogers [Mon, 23 Jun 2014 15:11:25 +0000 (15:11 +0000)]
Merge "Limit the size of files created by run-test to 2MB."
Ian Rogers [Sun, 22 Jun 2014 05:58:05 +0000 (22:58 -0700)]
Limit the size of files created by run-test to 2MB.
In MemMap::MapAnonymous on the host, avoid creating ashmem regions that are
backed by files, when the size of the file will be greater than the ulimit.
Change-Id: I7cbf2ac59bf5869ed85850bea8d71898f3b7e1c7
Ian Rogers [Sun, 22 Jun 2014 05:31:52 +0000 (05:31 +0000)]
Merge "X86 Dis: Add missing mov byte; Add size suffixes"
Mark Mendell [Thu, 19 Jun 2014 01:02:29 +0000 (21:02 -0400)]
X86 Dis: Add missing mov byte; Add size suffixes
Yet another instruction not disassembled properly.
Add 'b', 'w', 'q' to opcodes to diffferentiate between various versions
and make it more understandable.
Change-Id: Ib794aac660bc8bc4900bfa49eab5aed682996adc
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
Ian Rogers [Mon, 23 Jun 2014 14:54:11 +0000 (14:54 +0000)]
Merge "Revert "ART: Fix StoreValue to use RefDisp when necessary.""
Ian Rogers [Sun, 22 Jun 2014 07:47:53 +0000 (07:47 +0000)]
Revert "ART: Fix StoreValue to use RefDisp when necessary."
This reverts commit
596bea8f6331fe8ad6eb456afa1f7dfe1b92e09c.
Change-Id: I1942bfc5127e8a631c5b24d107d304c7cd994e78
Ian Rogers [Sat, 21 Jun 2014 23:15:24 +0000 (23:15 +0000)]
Merge "Use command line android root in dex2oat to find image."
Bill Buzbee [Sat, 21 Jun 2014 14:59:51 +0000 (14:59 +0000)]
Merge "x86_64: Enable some optimizations"
Bill Buzbee [Sat, 21 Jun 2014 14:59:44 +0000 (14:59 +0000)]
Merge "x86_64: Fix fp-to-core conversion"
Bill Buzbee [Sat, 21 Jun 2014 14:59:34 +0000 (14:59 +0000)]
Merge "x86_64: Fix comp-long"
Serguei Katkov [Fri, 20 Jun 2014 11:17:16 +0000 (18:17 +0700)]
x86_64: Fix comp-long
If result and source are the same VR then implementation does
a wrong thing clearing dest in the beginning.
Change-Id: I66d97a828aa38121676561858119ccd44aaa4d50
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Andreas Gampe [Fri, 20 Jun 2014 19:48:12 +0000 (12:48 -0700)]
ART: Fix StoreValue to use RefDisp when necessary.
Split from https://android-review.googlesource.com/#/c/98605
Change-Id: Ib3a03428ddbec659591b838404bbfa1553fe18e9
Sebastien Hertz [Mon, 23 Jun 2014 08:02:59 +0000 (08:02 +0000)]
Merge "More verbose logs for JDWP events"
Sebastien Hertz [Fri, 11 Apr 2014 14:01:17 +0000 (16:01 +0200)]
More verbose logs for JDWP events
Logs more information about the JDWP event being reported with VLOG(jdwp). This
helps mainly when debugging JDWP with -verbose:jdwp option.
Change-Id: I49495bdab03dbcbdc0b6c00a8df718bfedbad91d
Serguei Katkov [Fri, 20 Jun 2014 09:45:52 +0000 (16:45 +0700)]
x86_64: Fix fp-to-core conversion
Long max value cannot be represented with double precision
and check fp against max_long does not guard invocation of
conversion instruction. As a result conversion ends up with
min long instead of max long.
The patch changes the guard check to not allow conversion
instruction for max long.
Change-Id: Ied761051ec27cf6c833040c25a2c61ab9fcea414
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Serban Constantinescu [Thu, 19 Jun 2014 13:27:52 +0000 (14:27 +0100)]
AArch64: Add memcmp.S for Arm64.
This patch adds a copy of bionic's memcmp.S to ART. A later patch
modifies this to memcmp16_arm64.S.
Change-Id: I18ddd43ea05a9828a741617fd2a87d2fa9a04449
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
Sebastien Hertz [Fri, 20 Jun 2014 10:22:11 +0000 (12:22 +0200)]
Use GCC on ARM64
This automatically enables the computed-goto interpreter as default.
Bug:
15763315
Bug:
15405621
Change-Id: I4f6ed5f7cad96333bc8dc1029e9b90ba1b6916df
buzbee [Fri, 20 Jun 2014 19:45:44 +0000 (19:45 +0000)]
Merge "Quick compiler: enable Arm64 compilation"
buzbee [Thu, 19 Jun 2014 23:08:48 +0000 (16:08 -0700)]
Quick compiler: enable Arm64 compilation
Change-Id: I19058defaff1c60b4b6b4d1ad82e0a42d50506a6
Andreas Gampe [Sat, 21 Jun 2014 01:38:46 +0000 (01:38 +0000)]
Merge "ART: Method verifier must check invoke-virtuals for non-zero args"
Andreas Gampe [Fri, 20 Jun 2014 01:13:29 +0000 (18:13 -0700)]
ART: Method verifier must check invoke-virtuals for non-zero args
Compiler checks rely on all instructions, not just reachable ones,
so add two new verifier flags.
Bug:
15755602
Change-Id: Ia9c2146cf82d94ce4d69fb6f7be6450137bb84bd
Mathieu Chartier [Fri, 20 Jun 2014 20:01:28 +0000 (20:01 +0000)]
Merge "Shared single GC iteration accounting for all GCs."
Mathieu Chartier [Sun, 15 Jun 2014 22:15:43 +0000 (15:15 -0700)]
Shared single GC iteration accounting for all GCs.
Previously, each garbage collector had data that was only used
during collection. Since only one collector can be running at any
given time, we can make this data be shared between all collectors.
This reduces memory usage since we don't need to have redundant
information for each GC types. Also reduced how much code is required
to sweep spaces.
Bug:
9969166
Change-Id: I31caf0ee4d572f75e0c66863fe7db12c08ae08e7
Andreas Gampe [Fri, 20 Jun 2014 05:58:42 +0000 (05:58 +0000)]
Merge "ART: Do not try to pretty-print method in dex file"
Andreas Gampe [Fri, 20 Jun 2014 03:24:22 +0000 (20:24 -0700)]
ART: Do not try to pretty-print method in dex file
The code is called in verification when it is not clear yet whether
structures are valid. Simplify warning message.
Bug:
15754233
Change-Id: I85858a71143f41444ce9f00536d901c268afe547
Andreas Gampe [Fri, 20 Jun 2014 03:39:07 +0000 (03:39 +0000)]
Merge "ART: Method verifier needs to check 2-reg values"
Bill Buzbee [Fri, 20 Jun 2014 19:42:30 +0000 (19:42 +0000)]
Merge "ART: Fix register overlap checks in CopyArgumentRegs"
Andreas Gampe [Fri, 20 Jun 2014 18:34:17 +0000 (11:34 -0700)]
ART: Fix register overlap checks in CopyArgumentRegs
This is a make-shift CL. Expect this to be replaced by a reworked
implementation.
Change-Id: Ia74697d1436efd2971bc4c791fabed66d2e9d72d
Hiroshi Yamauchi [Fri, 20 Jun 2014 19:30:53 +0000 (19:30 +0000)]
Merge "Add more read barriers for JNI roots."
Hiroshi Yamauchi [Wed, 18 Jun 2014 20:47:35 +0000 (13:47 -0700)]
Add more read barriers for JNI roots.
To make it possible to concurrently scan the JNI global roots (that
is, the roots visited by JavaVMExt::VisitRoots()), add read barriers
to the indirect reference table and the reference table.
Also, add read barriers to the jmethodID/jfieldID decode routines
(ScopedObjectAccessAlreadyRunnable::DecodeField/DecodeMethod) so that
we can concurrently handle (encoded) fields and methods.
Bug:
12687968
Change-Id: I3df4e4e622a572ff0ea8d44b2dc70a4d6b3ba058
Andreas Gampe [Fri, 20 Jun 2014 19:53:56 +0000 (19:53 +0000)]
Merge "ART: ReadFully needs to fail when EOF"
Andreas Gampe [Fri, 20 Jun 2014 17:45:30 +0000 (10:45 -0700)]
ART: ReadFully needs to fail when EOF
Besides an explicit error, we should stop trying when we unexpectedly
reach the end of the file.
Change-Id: I16d601e1b5bcbc39cb8c4dd7fd3dbb7d69016579
Andreas Gampe [Fri, 20 Jun 2014 19:53:22 +0000 (19:53 +0000)]
Merge "ART: Fix StoreValue to use RefDisp when necessary."
Andreas Gampe [Fri, 20 Jun 2014 00:29:48 +0000 (17:29 -0700)]
ART: Method verifier needs to check 2-reg values
The method verifier did not check against the second register
for a J or D parameter from a method signature.
The register line had a wrong DCHECK that did not catch this even
in debug mode.
Bug:
15751498
Change-Id: Ic6af08bf4704b3ab0f308dd9f0da28691a4cb024
buzbee [Thu, 19 Jun 2014 23:05:02 +0000 (23:05 +0000)]
Merge "Quick compiler: remove Arm64 "EXPERIMENTAL" filter"
buzbee [Thu, 19 Jun 2014 22:04:12 +0000 (15:04 -0700)]
Quick compiler: remove Arm64 "EXPERIMENTAL" filter
Support for the compilation of all dex opcodes should now exist.
We'll go ahead and leave the filter code in for a new weeks, as it
may be handy if we need a quick workaround.
Change-Id: I8f1857136d78347b7d2337db2c793ad41ad45cb9
Bill Buzbee [Thu, 19 Jun 2014 21:44:43 +0000 (21:44 +0000)]
Merge "x86_64: Several fixes required for enabling promotion"
Bill Buzbee [Thu, 19 Jun 2014 21:17:44 +0000 (21:17 +0000)]
Merge "x86_64: Fix neg_double"
Andreas Gampe [Thu, 19 Jun 2014 20:43:58 +0000 (20:43 +0000)]
Merge "ART: Log information when skipping method during compilation"
Andreas Gampe [Thu, 19 Jun 2014 18:34:06 +0000 (11:34 -0700)]
ART: Log information when skipping method during compilation
Add a reason for skipping a method to the log.
Change-Id: I3b31ee64cce6b531b25397f646cdfee650704ad6
Bill Buzbee [Thu, 19 Jun 2014 20:18:35 +0000 (20:18 +0000)]
Merge "x86_64: Enable core.oat/boot.oat compilation"
Alexei Zavjalov [Wed, 18 Jun 2014 10:18:36 +0000 (17:18 +0700)]
x86_64: Fix neg_double
In a case, when src and dest regs are the same, previous
implementation of the neg_double bytecode returns an
incorrect result.
This implementation uses shifts and xor and works for both
cases.
Change-Id: I137d9a90298ec225d80435d35558da8abb69cd01
Signed-off-by: Alexei Zavjalov <alexei.zavjalov@intel.com>
Andreas Gampe [Thu, 19 Jun 2014 06:56:51 +0000 (06:56 +0000)]
Merge "ART: Implicit checks in the compiler are independent from Runtime"
Andreas Gampe [Tue, 17 Jun 2014 23:36:07 +0000 (16:36 -0700)]
ART: Implicit checks in the compiler are independent from Runtime
When cross-compiling, those flags are independent. This is an
initial CL that helps bypass fatal failures when cross-compiling,
as not all architectures support (and have turned on) implicit
checks.
The actual transport for the target architecture when it is
different from the runtime needs to be implemented in a follow-up
CL.
Bug:
15703710
Change-Id: Idc881a9a4abfd38643b862a491a5af9b8841f693
Andreas Gampe [Thu, 19 Jun 2014 06:42:33 +0000 (06:42 +0000)]
Merge "ART: Reserve 8B for float literals on ARM64"
Andreas Gampe [Thu, 19 Jun 2014 06:19:07 +0000 (23:19 -0700)]
ART: Reserve 8B for float literals on ARM64
This is a cludge to make sure literal pools will be 8B aligned.
A better approach would be post-processing - that way we could
pack the floats.
Change-Id: Ia9c6f53e0f6e37b4be79e1efe7f14feb49f2052b
Andreas Gampe [Thu, 19 Jun 2014 02:39:37 +0000 (02:39 +0000)]
Merge "ART: Change rrr add and sub for ARM64"
Andreas Gampe [Thu, 19 Jun 2014 00:45:32 +0000 (17:45 -0700)]
ART: Change rrr add and sub for ARM64
OpRegRegImm will fall back to loading a constant into a register
and then doing the operation with three registers. That is, for
example, the case when we allocate large stack frames. However,
the currently chosen operations are add/sub shifted, which does
*not* allow to specify SP (x31 will be interpreted as xzr). Switch
to add/sub extended. There won't be a practical difference, as we
do not call with anything other than 0 shift.
Change-Id: I2b78df9f044d2963e3e890777c855b339952f9f4
Ian Rogers [Wed, 18 Jun 2014 23:24:40 +0000 (23:24 +0000)]
Merge "Assign a lower Locklevel for Mutexes used in QuasiAtomic operations. This fixes the CompilerDriverTest on MIPS. The test was failing when Transaction::Abort() acquired intern_table_lock_ and log_lock_ and subsequently performed QuasiAtomic operations."
Andreas Gampe [Thu, 19 Jun 2014 02:39:21 +0000 (02:39 +0000)]
Merge "ART: Target-dependent stack overflow, less check elision"
Andreas Gampe [Thu, 19 Jun 2014 00:01:15 +0000 (17:01 -0700)]
ART: Target-dependent stack overflow, less check elision
Refactor the separate stack overflow reserved sizes from thread.h
into instruction_set.h and make sure they're used in the compiler.
Refactor the decision on when to elide stack overflow checks:
especially with large interpreter stack frames, it is not a good
idea to elide checks when the frame size is even close to the
reserved size. Currently enforce checks when the frame size is
>= 2KB, but make sure that frame sizes 1KB and below will elide
the checks (number from experience).
Bug:
15728765
Change-Id: I016bfd3d8218170cbccbd123ed5e2203db167c06
Ian Rogers [Wed, 18 Jun 2014 23:56:39 +0000 (23:56 +0000)]
Merge "Ensure classes are initialized rather than initializing."
Ian Rogers [Wed, 18 Jun 2014 23:07:20 +0000 (16:07 -0700)]
Ensure classes are initialized rather than initializing.
A class can be being initialized on a different thread, in that case other
threads should block trying to access the class. The initializing state shows
the class is being initialized but not that its safe for other threads to
access. Change occurances of IsInitializing to IsInitialized primarily in
slow-path code.
Bug:
15347354
Change-Id: Ib586d0a385be6086a890dfbf8868d76f16767fac
Andreas Gampe [Thu, 19 Jun 2014 17:23:37 +0000 (17:23 +0000)]
Merge "ART: Start implementation of OpRegRegRegExtend for ARM64"
Andreas Gampe [Thu, 19 Jun 2014 08:10:07 +0000 (01:10 -0700)]
ART: Start implementation of OpRegRegRegExtend for ARM64
We need a sign-extending add for packed-switch and sparse-switch,
as the 32b values are signed offsets. This starts an implementation
that is sufficient for the use cases.
Change-Id: Ib5bae24b902077346a97d5e9e061533f9cdfcdb0
Dmitry Petrochenko [Fri, 13 Jun 2014 07:51:01 +0000 (14:51 +0700)]
x86_64: Enable some optimizations
Except kLoadStoreElimination and kPromoteRegs.
Change-Id: Iaebf6652641fe32c9e9b21469e4f898af2d67250
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
Dmitry Petrochenko [Fri, 13 Jun 2014 08:15:32 +0000 (15:15 +0700)]
x86_64: Enable core.oat/boot.oat compilation
This patch enabled compilation of image.
Change-Id: Idacce4a3898964d3a05762925dba236d7254a254
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>