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6 years ago[AMDGPU] Add gfx902 product names
Tony Tye [Sat, 14 Apr 2018 01:58:10 +0000 (01:58 +0000)]
[AMDGPU] Add gfx902 product names

Differential Revision: https://reviews.llvm.org/D45609

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330081 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[WebAssembly] Fix a bug in MachineBasicBlock::findDebugLoc() call
Heejin Ahn [Sat, 14 Apr 2018 00:12:12 +0000 (00:12 +0000)]
[WebAssembly] Fix a bug in MachineBasicBlock::findDebugLoc() call

Summary:
InsertPos is within the bacic block `Header`, so `findDebugLoc()` should
be called on not `MBB` but `Header` instead.

Reviewers: yurydelendik

Subscribers: jfb, dschuff, aprantl, sbc100, jgravelle-google, sunfish, JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D45648

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330079 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Add the bizarro movsww and movzww mnemonics for the disassembler.
Craig Topper [Fri, 13 Apr 2018 23:57:54 +0000 (23:57 +0000)]
[X86] Add the bizarro movsww and movzww mnemonics for the disassembler.

The destination size of the movzx/movsx instruction is controlled by the normal operand size mechanisms. Only the input type is fixed.

This means that a 0x66 prefix on the encoding for zext/sext 16->32 should really produce a 16->16 instruction. Functionally this is equivalent to a GR16->GR16 move since bits 16 and above will be preserved. So nothing is actually extended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330078 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoMachO: trap unreachable instructions
Tim Northover [Fri, 13 Apr 2018 22:25:20 +0000 (22:25 +0000)]
MachO: trap unreachable instructions

Debugability is more important than saving 4 bytes to let us to fall
through to nonense.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330073 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine][NFC] masked-merge: add 'and' tests, too.
Roman Lebedev [Fri, 13 Apr 2018 21:57:01 +0000 (21:57 +0000)]
[InstCombine][NFC] masked-merge: add 'and' tests, too.

(and plain 'or', for completeness sake.)

After submitting D45631, i have realized that it will *already*
affect 'and' pattern, and it was obvious that there were no
good test patterns to show that.

Since the masked-merge.ll is getting kinda big,
unify naming schemes a bit, and split into 'xor'/'and'/'or'
testfiles, with the only difference being the last operation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330072 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[DebugInfo][OPT] NFC follow-up on "Fixing a couple of DI duplication bugs of CloneModule"
Roman Tereshin [Fri, 13 Apr 2018 21:23:11 +0000 (21:23 +0000)]
[DebugInfo][OPT] NFC follow-up on "Fixing a couple of DI duplication bugs of CloneModule"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330070 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[DebugInfo][OPT] Fixing a couple of DI duplication bugs of CloneModule
Roman Tereshin [Fri, 13 Apr 2018 21:22:24 +0000 (21:22 +0000)]
[DebugInfo][OPT] Fixing a couple of DI duplication bugs of CloneModule

As demonstrated by the regression tests added in this patch, the
following cases are valid cases:

1. A Function with no DISubprogram attached, but various debug info
  related to its instructions, coming, for instance, from an inlined
  function, also defined somewhere else in the same module;
2. ... or coming exclusively from the functions inlined and eliminated
  from the module entirely.

The ValueMap shared between CloneFunctionInto calls within CloneModule
needs to contain identity mappings for all of the DISubprogram's to
prevent them from being duplicated by MapMetadata / RemapInstruction
calls, this is achieved via DebugInfoFinder collecting all the
DISubprogram's. However, CloneFunctionInto was missing calls into
DebugInfoFinder for functions w/o DISubprogram's attached, but still
referring DISubprogram's from within (case 1). This patch fixes that.

The fix above, however, exposes another issue: if a module contains a
DISubprogram referenced only indirectly from other debug info
metadata, but not attached to any Function defined within the module
(case 2), cloning such a module causes a DICompileUnit duplication: it
will be moved in indirecty via a DISubprogram by DebugInfoFinder first
(because of the first bug fix described above), without being
self-mapped within the shared ValueMap, and then will be copied during
named metadata cloning. So this patch makes sure DebugInfoFinder
visits DICompileUnit's referenced from DISubprogram's as it goes w/o
re-processing llvm.dbg.cu list over and over again for every function
cloned, and makes sure that CloneFunctionInto self-maps
DICompileUnit's referenced from the entire function, not just its own
DISubprogram attached that may also be missing.

The most convenient way of tesing CloneModule I found is to rely on
CloneModule call from `opt -run-twice`, instead of writing tedious
unit tests. That feature has a couple of properties that makes it hard
to use for this purpose though:

1. CloneModule doesn't copy source filename, making `opt -run-twice`
  report it as a difference.
2. `opt -run-twice` does the second run on the original module, not
  its clone, making the result of cloning completely invisible in opt's
  actual output with and without `-run-twice` both, which directly
  contradicts `opt -run-twice`s own error message.

This patch fixes this as well.

Reviewed By: aprantl

Reviewers: loladiro, GorNishanov, espindola, echristo, dexonsmith

Subscribers: vsk, debug-info, JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D45593

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330069 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Hexagon] Initial instruction cost model for auto-vectorization
Krzysztof Parzyszek [Fri, 13 Apr 2018 20:46:50 +0000 (20:46 +0000)]
[Hexagon] Initial instruction cost model for auto-vectorization

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330065 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRevert r329956, "AArch64: Introduce a DAG combine for folding offsets into addresses."
Peter Collingbourne [Fri, 13 Apr 2018 20:21:00 +0000 (20:21 +0000)]
Revert r329956, "AArch64: Introduce a DAG combine for folding offsets into addresses."

Caused a hang and eventually an assertion failure in LTO builds
of 7zip-benchmark on aarch64 iOS targets.
http://green.lab.llvm.org/green/job/lnt-ctmark-aarch64-O3-flto/2024/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330063 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[LV] Introduce TTI::getMinimumVF
Krzysztof Parzyszek [Fri, 13 Apr 2018 20:16:32 +0000 (20:16 +0000)]
[LV] Introduce TTI::getMinimumVF

The function getMinimumVF(ElemWidth) will return the minimum VF for
a vector with elements of size ElemWidth bits. This value will only
apply to targets for which TTI::shouldMaximizeVectorBandwidth returns
true. The value of 0 indicates that there is no minimum VF.

Differential Revision: https://reviews.llvm.org/D45271

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330062 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[DebugInfo] Change std::sort to llvm::sort in response to r327219
Mandeep Singh Grang [Fri, 13 Apr 2018 19:50:51 +0000 (19:50 +0000)]
[DebugInfo] Change std::sort to llvm::sort in response to r327219

r327219 added wrappers to std::sort which randomly shuffle the container before
sorting.  This will help in uncovering non-determinism caused due to undefined
sorting order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of
std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to
llvm::sort.  Refer the comments section in D44363 for a list of all the
required patches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330061 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Power9] Add the TLS store instructions to the Power 9 model
Stefan Pintilie [Fri, 13 Apr 2018 19:49:58 +0000 (19:49 +0000)]
[Power9] Add the TLS store instructions to the Power 9 model

The Power 9 scheduler model should now include the TLS instructions.
We can now, once again, mark the model as complete.
From now on, if instructions are added to Power 9 but are not
added to the model the build should produce an error. Hopefully
that will alert the developer who is adding new instructions
that they should also be added to the scheulder model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330060 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Transforms] Change std::sort to llvm::sort in response to r327219
Mandeep Singh Grang [Fri, 13 Apr 2018 19:47:57 +0000 (19:47 +0000)]
[Transforms] Change std::sort to llvm::sort in response to r327219

Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.

Reviewers: kcc, pcc, danielcdh, jmolloy, sanjoy, dberlin, ruiu

Reviewed By: ruiu

Subscribers: ruiu, llvm-commits

Differential Revision: https://reviews.llvm.org/D45142

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330059 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[MC] Change std::sort to llvm::sort in response to r327219
Mandeep Singh Grang [Fri, 13 Apr 2018 19:47:01 +0000 (19:47 +0000)]
[MC] Change std::sort to llvm::sort in response to r327219

Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.

Reviewers: grosbach, void, ruiu

Reviewed By: ruiu

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45138

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330058 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ProfileData] Change std::sort to llvm::sort in response to r327219
Mandeep Singh Grang [Fri, 13 Apr 2018 19:46:36 +0000 (19:46 +0000)]
[ProfileData] Change std::sort to llvm::sort in response to r327219

Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.

Reviewers: bogner, vsk, eraman, ruiu

Reviewed By: ruiu

Subscribers: ruiu, llvm-commits

Differential Revision: https://reviews.llvm.org/D45139

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330057 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[CostModel][X86] Add some specific cpu targets to the cost models
Simon Pilgrim [Fri, 13 Apr 2018 19:30:15 +0000 (19:30 +0000)]
[CostModel][X86] Add some specific cpu targets to the cost models

We're mostly testing with generic isa attributes, but PR36550 will require testing of specific target's scheduler models as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330056 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[CostModel][X86] Split fma arith costs tests from other fp tests
Simon Pilgrim [Fri, 13 Apr 2018 19:12:32 +0000 (19:12 +0000)]
[CostModel][X86] Split fma arith costs tests from other fp tests

Was proving cumbersome to test with/without fma

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330054 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[LTO] Change std::sort to llvm::sort in response to r327219
Mandeep Singh Grang [Fri, 13 Apr 2018 19:12:20 +0000 (19:12 +0000)]
[LTO] Change std::sort to llvm::sort in response to r327219

Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer D44363 for a list of all the required patches.

Reviewers: pcc, mehdi_amini, ruiu

Reviewed By: ruiu

Subscribers: ruiu, inglorion, eraman, llvm-commits

Differential Revision: https://reviews.llvm.org/D45137

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330053 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[CostModel][X86] Regenerate latency/codesize cost tests
Simon Pilgrim [Fri, 13 Apr 2018 18:56:58 +0000 (18:56 +0000)]
[CostModel][X86] Regenerate latency/codesize cost tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330052 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[CostModel][X86] Regenerate cast conversion cost tests
Simon Pilgrim [Fri, 13 Apr 2018 18:56:05 +0000 (18:56 +0000)]
[CostModel][X86] Regenerate cast conversion cost tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330051 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[CostModel][X86] Regenerate masked intrinsic cost tests
Simon Pilgrim [Fri, 13 Apr 2018 18:54:16 +0000 (18:54 +0000)]
[CostModel][X86] Regenerate masked intrinsic cost tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330050 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoDefine InitLLVM to do common initialization all at once.
Rui Ueyama [Fri, 13 Apr 2018 18:26:06 +0000 (18:26 +0000)]
Define InitLLVM to do common initialization all at once.

We have a few functions that virtually all command wants to run on
process startup/shutdown. This patch adds InitLLVM class to do that
all at once, so that we don't need to copy-n-paste boilerplate code
to each llvm command's main() function.

Differential Revision: https://reviews.llvm.org/D45602

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330046 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agohwasan: add -fsanitize=kernel-hwaddress flag
Andrey Konovalov [Fri, 13 Apr 2018 18:05:21 +0000 (18:05 +0000)]
hwasan: add -fsanitize=kernel-hwaddress flag

This patch adds -fsanitize=kernel-hwaddress flag, that essentially enables
-hwasan-kernel=1 -hwasan-recover=1 -hwasan-match-all-tag=0xff.

Differential Revision: https://reviews.llvm.org/D45046

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330044 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine][NFC] masked-merge: commutativity tests: ensure the ordering.
Roman Lebedev [Fri, 13 Apr 2018 17:15:55 +0000 (17:15 +0000)]
[InstCombine][NFC] masked-merge: commutativity tests: ensure the ordering.

This was intended since initially, but i did not really think
about it, and did not know how to force that. Now that the
xor->or fold is working (patch upcoming), this came up
to improve the test coverage.

A followup for rL330003, rL330007
https://bugs.llvm.org/show_bug.cgi?id=6773

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330039 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAdd PPC64_GLINK dynamic tag.
Sean Fertile [Fri, 13 Apr 2018 16:42:48 +0000 (16:42 +0000)]
Add PPC64_GLINK dynamic tag.

Add support for the PPC64_GLINK dynamic tag which is used in the ElfV2 abi.

Differential Revision: https://reviews.llvm.org/D45574

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330038 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[mips] Materialize constants for multiplication
Simon Dardis [Fri, 13 Apr 2018 16:09:07 +0000 (16:09 +0000)]
[mips] Materialize constants for multiplication

Previously, the MIPS backend would alwyas break down constant multiplications
into a series of shifts, adds, and subs. This patch changes that so the cost of
doing so is estimated.

The cost is estimated against worst case constant materialization and retrieving
the results from the HI/LO registers.

For cases where the value type of the multiplication is not legal, the cost of
legalization is estimated and is accounted for before performing the
optimization of breaking down the constant

This resolves PR36884.

Thanks to npl for reporting the issue!

Reviewers: abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D45316

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330037 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Remove remaining itinerary support from instructions and target (PR37093)
Simon Pilgrim [Fri, 13 Apr 2018 15:37:56 +0000 (15:37 +0000)]
[X86] Remove remaining itinerary support from instructions and target (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330035 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ARM] FP16 vmaxnm/vminnm scalar instructions
Sjoerd Meijer [Fri, 13 Apr 2018 15:34:26 +0000 (15:34 +0000)]
[ARM] FP16 vmaxnm/vminnm scalar instructions

This adds code generation support for the FP16 vmaxnm/vminnm scalar
instructions.

Differential Revision: https://reviews.llvm.org/D44675

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330034 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRevert r330027: "[llvm-exegesis] re-enable failing tests after r330026."
Clement Courbet [Fri, 13 Apr 2018 15:19:16 +0000 (15:19 +0000)]
Revert r330027: "[llvm-exegesis] re-enable failing tests after r330026."

The tests are still failing on some bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330033 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-mca] Ensure that instructions with a schedule read-advance are always issued...
Andrea Di Biagio [Fri, 13 Apr 2018 15:19:07 +0000 (15:19 +0000)]
[llvm-mca] Ensure that instructions with a schedule read-advance are always issued in the right order.

Normally, the Scheduler prioritizes older instructions over younger instructions
during the instruction issue stage. In one particular case where a dependent
instruction had a schedule read-advance associated to one of the input operands,
this rule was not correctly applied.

This patch fixes the issue and adds a test to verify that we don't regress that
particular case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330032 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ARC] Add LImm support for J/JL
Yan Luo [Fri, 13 Apr 2018 15:10:34 +0000 (15:10 +0000)]
[ARC] Add LImm support for J/JL

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330031 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Generalize X86FixupLEAs to work with TargetSchedModel
Simon Pilgrim [Fri, 13 Apr 2018 15:09:39 +0000 (15:09 +0000)]
[X86] Generalize X86FixupLEAs to work with TargetSchedModel

Similar to rL329834, don't rely on itinerary scheduler model to determine latencies for LEA thresholds, use the generic TargetSchedModel::computeInstrLatency call.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330030 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[profile] Fix binary format reader error propagation.
Mircea Trofin [Fri, 13 Apr 2018 15:04:36 +0000 (15:04 +0000)]
[profile] Fix binary format reader error propagation.

Summary:
This was originally part of rL328132, and led to the discovery
of the issues addressed in rL328987. Re-landing.

Reviewers: xur, davidxl, bkramer

Reviewed By: bkramer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45545

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330029 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-exegesis] re-enable failing tests after r330026.
Clement Courbet [Fri, 13 Apr 2018 14:50:10 +0000 (14:50 +0000)]
[llvm-exegesis] re-enable failing tests after r330026.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330027 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-exegesis] Fix use after free.
Clement Courbet [Fri, 13 Apr 2018 14:46:48 +0000 (14:46 +0000)]
[llvm-exegesis] Fix use after free.

Reviewers: gchatelet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D45625

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330026 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRemove comment reference to itineraries. NFCI.
Simon Pilgrim [Fri, 13 Apr 2018 14:42:48 +0000 (14:42 +0000)]
Remove comment reference to itineraries. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330025 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AArch64][SVE] Asm: Support for contiguous LD1 (scalar+imm) load instructions
Sander de Smalen [Fri, 13 Apr 2018 14:41:36 +0000 (14:41 +0000)]
[AArch64][SVE] Asm: Support for contiguous LD1 (scalar+imm) load instructions

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: rengolin

Subscribers: tschuett, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D45618

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330024 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86][AVX512] UNPCKL/H PS and PD should be scheduled with WriteFShuffle not WriteFAdd
Simon Pilgrim [Fri, 13 Apr 2018 14:41:05 +0000 (14:41 +0000)]
[X86][AVX512] UNPCKL/H PS and PD should be scheduled with WriteFShuffle not WriteFAdd

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330023 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Remove remaining OpndItins/SizeItins from all instruction defs (PR37093)
Simon Pilgrim [Fri, 13 Apr 2018 14:36:59 +0000 (14:36 +0000)]
[X86] Remove remaining OpndItins/SizeItins from all instruction defs (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330022 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRemove comment references to itineraries. NFCI.
Simon Pilgrim [Fri, 13 Apr 2018 14:31:57 +0000 (14:31 +0000)]
Remove comment references to itineraries. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330021 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-exegesis][NFC] Add more logging in case target creation fails.
Clement Courbet [Fri, 13 Apr 2018 14:29:52 +0000 (14:29 +0000)]
[llvm-exegesis][NFC] Add more logging in case target creation fails.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330020 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRemove out of data comment. NFCI.
Simon Pilgrim [Fri, 13 Apr 2018 14:24:06 +0000 (14:24 +0000)]
Remove out of data comment. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330019 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[PostRASink]Add register dependency check for implicit operands
Jun Bum Lim [Fri, 13 Apr 2018 14:23:09 +0000 (14:23 +0000)]
[PostRASink]Add register dependency check for implicit operands

Summary:
This change extend the register dependency check for implicit operands in Copy instructions.
Fixes PR36902.

Reviewers: thegameg, sebpop, uweigand, jnspaulsson, gberry, mcrosier, qcolombet, MatzeB

Reviewed By: thegameg

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D44958

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330018 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine][NFC] Regenerate logical-select.ll test
Roman Lebedev [Fri, 13 Apr 2018 14:07:29 +0000 (14:07 +0000)]
[InstCombine][NFC] Regenerate logical-select.ll test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330017 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-exegesis] Create test files in temporary directory.
Clement Courbet [Fri, 13 Apr 2018 13:37:07 +0000 (13:37 +0000)]
[llvm-exegesis] Create test files in temporary directory.

Currently the test fails in sandboxed environnements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330015 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AArch64][SVE] Asm: Support for contiguous ST1 (scalar+imm) store instructions.
Sander de Smalen [Fri, 13 Apr 2018 12:56:14 +0000 (12:56 +0000)]
[AArch64][SVE] Asm: Support for contiguous ST1 (scalar+imm) store instructions.

Summary:
Added instructions for contiguous stores, ST1, with scalar+imm addressing
modes and corresponding tests. The patch also adds parsing of
'mul vl' as needed for the VL-scaled immediate.

This is patch [6/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: rengolin

Subscribers: tschuett, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D45432

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330014 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Remove OpndItins/SizeItins from all sse instruction defs (PR37093)
Simon Pilgrim [Fri, 13 Apr 2018 12:50:31 +0000 (12:50 +0000)]
[X86] Remove OpndItins/SizeItins from all sse instruction defs (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330013 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[NEON] Support intrinsic for scalar and vector versions of the VRINTN instruction
Ivan A. Kosarev [Fri, 13 Apr 2018 12:45:12 +0000 (12:45 +0000)]
[NEON] Support intrinsic for scalar and vector versions of the VRINTN instruction

Differential Revision: https://reviews.llvm.org/D45514

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330011 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoPartially revert r330008.
Clement Courbet [Fri, 13 Apr 2018 12:43:55 +0000 (12:43 +0000)]
Partially revert r330008.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330010 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[llvm-exegesis] Run unit tests on more platforms.
Clement Courbet [Fri, 13 Apr 2018 12:20:30 +0000 (12:20 +0000)]
[llvm-exegesis] Run unit tests on more platforms.

Summary:
 - Target-independent tests are run all the time.
 - Tests that codegen X86 code are run when X86 is in build targets.
 - Tests that run X86 jitted code are run only on X86 hosts.

Reviewers: gchatelet

Subscribers: mgorny, llvm-commits, tschuett

Differential Revision: https://reviews.llvm.org/D45614

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330008 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine][NFC] Add last few tests with constant mask for masked merge folding.
Roman Lebedev [Fri, 13 Apr 2018 12:00:00 +0000 (12:00 +0000)]
[InstCombine][NFC] Add last few tests with constant mask for masked merge folding.

A followup for rL330003
https://bugs.llvm.org/show_bug.cgi?id=6773

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330007 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[NFC] fix trivial typos in comments
Hiroshi Inoue [Fri, 13 Apr 2018 11:37:06 +0000 (11:37 +0000)]
[NFC] fix trivial typos in comments

"the the" -> "the", "we we" -> "we", etc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330006 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine][NFC] Add tests for masked merge folding.
Roman Lebedev [Fri, 13 Apr 2018 10:56:35 +0000 (10:56 +0000)]
[InstCombine][NFC] Add tests for masked merge folding.

https://bugs.llvm.org/show_bug.cgi?id=6773

As discussed there, some backends may want to undo this fold
(x86+bmi for scalars, x86+sse for vectors, ...)
https://bugs.llvm.org/show_bug.cgi?id=37104

https://rise4fun.com/Alive/JXt

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330003 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[InstCombine]: foldSelectICmpAndAnd(): and is commutative
Roman Lebedev [Fri, 13 Apr 2018 09:57:57 +0000 (09:57 +0000)]
[InstCombine]: foldSelectICmpAndAnd(): and is commutative

Summary:
The fold added in D45108 did not account for the fact that
the and instruction is commutative, and if the mask is a variable,
the mask variable and the fold variable may be swapped.

I have noticed this by accident when looking into [[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]]

This extends/generalizes that fold, so it is handled too.

Reviewers: spatel, craig.topper

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45539

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330001 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AArch64][SVE] Asm: Add support for parsing and printing SVE vector lists.
Sander de Smalen [Fri, 13 Apr 2018 09:11:53 +0000 (09:11 +0000)]
[AArch64][SVE] Asm: Add support for parsing and printing SVE vector lists.

Summary:
Added Z_(b|h|s|d) vector list RegisterOperands along with support to
add/print the vector lists.

This is patch [5/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: fhahn

Subscribers: tschuett, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45431

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330000 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Introduce cldemote instruction
Gabor Buella [Fri, 13 Apr 2018 07:35:08 +0000 (07:35 +0000)]
[X86] Introduce cldemote instruction

Hint to hardware to move the cache line containing the
address to a more distant level of the cache without
writing back to memory.

Reviewers: craig.topper, zvi

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D45256

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329992 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Support] Fix building for Windows on ARM
Martin Storsjo [Fri, 13 Apr 2018 06:38:02 +0000 (06:38 +0000)]
[Support] Fix building for Windows on ARM

The commit in SVN r310001 that added support for this actually didn't
use the right struct field for the frame pointer - for ARM, there is
no register named Fp in the CONTEXT struct. On Windows, the R11
register is used as frame pointer.

Differential Revision: https://reviews.llvm.org/D45590

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329991 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Remove the pmuldq/pmuldq intrinsics and replace with native IR.
Craig Topper [Fri, 13 Apr 2018 06:07:18 +0000 (06:07 +0000)]
[X86] Remove the pmuldq/pmuldq intrinsics and replace with native IR.

This completes the work started in r329604 and r329605 when we changed clang to no longer use the intrinsics.

We lost some InstCombine SimplifyDemandedBit optimizations through this change as we aren't able to fold 'and', bitcast, shuffle very well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329990 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoEnable debug fission for thinLTO linked via gold-plugin
Yunlian Jiang [Fri, 13 Apr 2018 05:03:28 +0000 (05:03 +0000)]
Enable debug fission for thinLTO linked via gold-plugin

Summary: This enables debug fission on implicit ThinLTO when linked with gold. It will put the .dwo files in a directory specified by user.

Reviewers: tejohnson, pcc, dblaikie

Reviewed By: pcc

Subscribers: JDevlieghere, mehdi_amini, inglorion

Differential Revision: https://reviews.llvm.org/D44792

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329988 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[CallSiteSplit] Fix comment. NFC
Xin Tong [Fri, 13 Apr 2018 04:35:38 +0000 (04:35 +0000)]
[CallSiteSplit] Fix comment. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329987 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFix another bot failure from r329951.
Erik Pilkington [Fri, 13 Apr 2018 02:53:26 +0000 (02:53 +0000)]
Fix another bot failure from r329951.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329986 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AMDGPU] Update relocation record description
Tony Tye [Fri, 13 Apr 2018 01:01:27 +0000 (01:01 +0000)]
[AMDGPU] Update relocation record description

Document which relocation records are static and dynamic.

Differential Revision: https://reviews.llvm.org/D45587

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329981 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[lit] Remove duplicate to_string method
Aaron Smith [Thu, 12 Apr 2018 23:45:15 +0000 (23:45 +0000)]
[lit] Remove duplicate to_string method

There are two versions of to_string used by TestRunner.py. The one defined
in TestRunner.py and the one defined in utils/lit/lit/util.py. The util.py
version is superior to the TestRunner.py version.

This change removes the duplicate to_string in TestRunner.py in favor of
always using the version from util.py. Beside removing duplicate code, this
makes it easier to debug TestRunner.py since only one version of to_string
is used.

Patch by Stella Stamenova!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329972 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Remove unused MoveLoadStoreItins/ShiftOpndItins schedule class wrappers.
Simon Pilgrim [Thu, 12 Apr 2018 22:57:34 +0000 (22:57 +0000)]
[X86] Remove unused MoveLoadStoreItins/ShiftOpndItins schedule class wrappers.

Was being used to move around empty/unused itineraries...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329970 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFree a pointer, fix a bot.
Erik Pilkington [Thu, 12 Apr 2018 22:54:47 +0000 (22:54 +0000)]
Free a pointer, fix a bot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329969 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Remove x86 InstrItinClass entries (PR37093)
Simon Pilgrim [Thu, 12 Apr 2018 22:44:47 +0000 (22:44 +0000)]
[X86] Remove x86 InstrItinClass entries (PR37093)

This removes the last of the x86 schedule itineraries, I'm intending to cleanup the remaining uses of NoItinerary/OpndItins/etc. before resolving PR37093.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329967 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[CachePruning] Clarify the per-directory entry limit on Linux ext4.
Fangrui Song [Thu, 12 Apr 2018 22:27:38 +0000 (22:27 +0000)]
[CachePruning] Clarify the per-directory entry limit on Linux ext4.

Summary:
508   root node entries (root_limit)
510   internal node entries (node_limit)

For a filename with 40 bytes, its sizeof(ext4_dir_entry_2) = 48, a linear directory can contain at most floor(4096/48)=85 of them.
The real per-directory entry limit should be 508*510*85 = 22021800
The limit varies with the average length of filenames.

However, the Linux ext4 code does not try rebalancing the htree, so we will not be able to create filenames in a full leaf node. This is demonstrated with the following example, certain filenames cannot be used while others can:

  % touch d/0000000000000000000000000000000000816a6f
  touch: cannot touch 'd/0000000000000000000000000000000000816a6f': No
  space left on device
  % touch d/0000000000000000000000000000000000816a70
  # succeeded

Reviewers: pcc

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45546

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329966 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[DAGCombiner] simplify code; NFC
Sanjay Patel [Thu, 12 Apr 2018 22:14:58 +0000 (22:14 +0000)]
[DAGCombiner] simplify code; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329964 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[PowerPC] add fsub-fneg test; NFC
Sanjay Patel [Thu, 12 Apr 2018 22:14:23 +0000 (22:14 +0000)]
[PowerPC] add fsub-fneg test; NFC

This is a test for a transform that was suggested in the post-commit
mailing list thread for rL329821. The target in question is not in
trunk, so PPC gets to stand in for it because it's the only in-tree
target that sets 'isFPExtFree()' to 'true'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329963 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoDon't call skipModule for CFI lowering passes.
Eli Friedman [Thu, 12 Apr 2018 22:04:11 +0000 (22:04 +0000)]
Don't call skipModule for CFI lowering passes.

opt-bisect shouldn't skip these passes; they lower intrinsics which
no other pass can handle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329961 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ProfileSummary] Remove repeated cutoffs; NFCI
George Burgess IV [Thu, 12 Apr 2018 21:38:43 +0000 (21:38 +0000)]
[ProfileSummary] Remove repeated cutoffs; NFCI

I'm told the repeat of "500000, 600000," is accidental, and should be
removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329959 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoLet llvm-diff correctly deal with Undef/ConstantAggregateZero/ConstantVector/IndirectBr
Brian Gesiak [Thu, 12 Apr 2018 21:28:04 +0000 (21:28 +0000)]
Let llvm-diff correctly deal with Undef/ConstantAggregateZero/ConstantVector/IndirectBr

Summary:
llvm-diff incorrectly reports that there's a diff when input IR contains undef/zeroinitializer/constantvector/indirectbr.
(This happens even if two identical files are given, e.g. `llvm-diff x.ll x.ll`)

This is fix to the bug report https://bugs.llvm.org/show_bug.cgi?id=33623 .

Reviewers: dexonsmith, rjmccall

Reviewed By: rjmccall

Subscribers: chenwj, mgrang, llvm-commits

Differential Revision: https://reviews.llvm.org/D34856

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329957 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoAArch64: Introduce a DAG combine for folding offsets into addresses.
Peter Collingbourne [Thu, 12 Apr 2018 21:23:55 +0000 (21:23 +0000)]
AArch64: Introduce a DAG combine for folding offsets into addresses.

This is a code size win in code that takes offseted addresses
frequently, such as C++ constructors that typically need to compute
an offseted address of a vtable. This reduces the size of Chromium
for Android's .text section by 108KB.

Differential Revision: https://reviews.llvm.org/D45199

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329956 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[DebugInfo] Create merged locations for instructions other than calls
Vedant Kumar [Thu, 12 Apr 2018 20:58:24 +0000 (20:58 +0000)]
[DebugInfo] Create merged locations for instructions other than calls

This lifts a restriction on DILocation::getMergedLocation(), allowing it
to create merged locations for instructions other than calls.

Instruction::applyMergedLocation() now defaults to creating merged
locations for all instructions.

The default behavior of getMergedLocation() is unchanged: callers which
invoke it directly are unaffected.

This change will enable a follow-up Mem2Reg fix which improves crash
reporting.

Differential Revision: https://reviews.llvm.org/D45396

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329955 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ProfileSummary] Move a vector we're about to destroy anyway; NFC
George Burgess IV [Thu, 12 Apr 2018 20:54:05 +0000 (20:54 +0000)]
[ProfileSummary] Move a vector we're about to destroy anyway; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329954 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Remove InstrItinClass entries from all x86 instruction defs (PR37093)
Simon Pilgrim [Thu, 12 Apr 2018 20:47:34 +0000 (20:47 +0000)]
[X86] Remove InstrItinClass entries from all x86 instruction defs (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329953 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[demangler] Add a partial demangling API for LLDB.
Erik Pilkington [Thu, 12 Apr 2018 20:41:38 +0000 (20:41 +0000)]
[demangler] Add a partial demangling API for LLDB.

This parses a mangled name into an AST (typically an intermediate stage in
itaniumDemangle) and provides some functions to query certain properties or
print certain parts of the demangled name.

Differential revision: https://reviews.llvm.org/D44668

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329951 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[demangler] NFC: Some refactoring to support partial demangling.
Erik Pilkington [Thu, 12 Apr 2018 20:41:06 +0000 (20:41 +0000)]
[demangler] NFC: Some refactoring to support partial demangling.

I'm committing this to libcxxabi too so that the two demanglers remain as
simular as possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329950 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[WebAssembly] libObject: Don't include the name the size of custom sections
Sam Clegg [Thu, 12 Apr 2018 20:31:12 +0000 (20:31 +0000)]
[WebAssembly] libObject: Don't include the name the size of custom sections

Differential Revision: https://reviews.llvm.org/D45579

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329947 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Remove InstrItinClass entries from SSE/AVX instructions defs (PR37093)
Simon Pilgrim [Thu, 12 Apr 2018 19:59:35 +0000 (19:59 +0000)]
[X86] Remove InstrItinClass entries from SSE/AVX instructions defs (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329945 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ORC] Use insert rather than emplace.
Lang Hames [Thu, 12 Apr 2018 19:54:41 +0000 (19:54 +0000)]
[ORC] Use insert rather than emplace.

Hopefully this will fix the build failure at
http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/9028

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329944 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoSimplify; NFCI
George Burgess IV [Thu, 12 Apr 2018 19:48:05 +0000 (19:48 +0000)]
Simplify; NFCI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329943 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Remove explicit SSE/AVX schedule itineraries from defs (PR37093)
Simon Pilgrim [Thu, 12 Apr 2018 19:25:07 +0000 (19:25 +0000)]
[X86] Remove explicit SSE/AVX schedule itineraries from defs (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329940 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0
Sameer AbuAsal [Thu, 12 Apr 2018 19:22:40 +0000 (19:22 +0000)]
[RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0

Summary:
GCC compresses the pseudo instruction "mv rd, rs",  which is an alias of
"addi rd, rs, 0", to "c.mv rd, rs".

In LLVM we rely on the canonical MC instruction (MCInst) to do our compression
checks and since there is no rule to compress "addi rd, rs, 0" --> "c.mv
rd, rs" we lose this compression opportunity to gcc.

 In this patch we fix that by adding an addi to c.mv compression pattern, the
 instruction "mv rd, rs" will be compressed to "c.mv rd, rs" just like
 gcc does.

Patch by Zhaoshi Zheng (zzheng) and Sameer (sabuasal).

Reviewers: asb, apazos, zzheng, mgrang, shiva0217

Reviewed By: asb

Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, llvm-commits

Differential Revision: https://reviews.llvm.org/D45583

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329939 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Remove remaining gpr schedule itineraries (PR37093)
Simon Pilgrim [Thu, 12 Apr 2018 18:46:15 +0000 (18:46 +0000)]
[X86] Remove remaining gpr schedule itineraries (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329938 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Introduce LLVM wbinvd intrinsic
Gabor Buella [Thu, 12 Apr 2018 18:38:18 +0000 (18:38 +0000)]
[X86] Introduce LLVM wbinvd intrinsic

A previously missing intrinsic for an old instruction.

Reviewers: craig.topper, echristo

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D45312

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329936 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoFix a typo in a comment; NFC
George Burgess IV [Thu, 12 Apr 2018 18:36:01 +0000 (18:36 +0000)]
Fix a typo in a comment; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329935 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[ORC] Plumb error notifications through the VSO interface.
Lang Hames [Thu, 12 Apr 2018 18:35:08 +0000 (18:35 +0000)]
[ORC] Plumb error notifications through the VSO interface.

This allows materializers to notify the VSO that they were unable to
resolve or finalize symbols.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329934 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Remove gpr shift/extension schedule itineraries (PR37093)
Simon Pilgrim [Thu, 12 Apr 2018 18:25:38 +0000 (18:25 +0000)]
[X86] Remove gpr shift/extension schedule itineraries (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329933 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Power9]Legalize and emit code for converting (Un)Signed DWord to Quad-Precision
Lei Huang [Thu, 12 Apr 2018 18:00:14 +0000 (18:00 +0000)]
[Power9]Legalize and emit code for converting (Un)Signed DWord to Quad-Precision

Legalize and emit code for:

  * xscvsdqp
  * xscvudqp

Differential Revision: https://reviews.llvm.org/D45230

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329931 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[MCJIT] Remove the anchor from mcjit.
Benjamin Kramer [Thu, 12 Apr 2018 17:28:30 +0000 (17:28 +0000)]
[MCJIT] Remove the anchor from mcjit.

This is a layering violation. LTO shouldn't depend on MCJIT. The right
fix for this is moving the class somewhere else.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329929 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[MIPS GlobalISel] remove superfluous #includes (NFC)
Petar Jovanovic [Thu, 12 Apr 2018 17:01:46 +0000 (17:01 +0000)]
[MIPS GlobalISel] remove superfluous #includes (NFC)

Remove superfluous #includes.
Minor code style change in MipsCallLowering::lowerFormalArguments().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329926 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AArch64] Move AFI->setRedZone(false) to top of emitPrologue
Jessica Paquette [Thu, 12 Apr 2018 16:16:18 +0000 (16:16 +0000)]
[AArch64] Move AFI->setRedZone(false) to top of emitPrologue

AFI->setRedZone(false) was put in the wrong place before, and so it only fired
on functions that didn't have stack frames. This moves that to the top of
emitPrologue to make sure that every function without a redzone has it set
correctly.

This also adds a function representing one of the early exit cases (GHC calling
convention) to the MachineOutliner noredzone test to ensure that we can outline
from functions like these, where we never use a redzone.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329922 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agorevert r328921 - [DAGCombine] (float)((int) f) --> ftrunc (PR36617)
Sanjay Patel [Thu, 12 Apr 2018 15:27:01 +0000 (15:27 +0000)]
revert r328921 - [DAGCombine] (float)((int) f) --> ftrunc (PR36617)

This change is exposing UB in source code - as was warned/predicted. :)
See D44909 for discussion. Reverting while we figure out how to fix things.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329920 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[Pipeliner] Use std::stable_sort when ordering NodeSets
Krzysztof Parzyszek [Thu, 12 Apr 2018 15:11:11 +0000 (15:11 +0000)]
[Pipeliner] Use std::stable_sort when ordering NodeSets

There are cases when individual NodeSets can be equal with respect to
the ordering criteria. Since they are stored in an ordered container,
use stable_sort to preserve the relative order of equal NodeSets.

This should remove non-determinism discovered by shuffling done in
llvm::sort with expensive checks enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329915 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[mips] Correct the predicates of the load/store (double)word for coprocessor 3.
Simon Dardis [Thu, 12 Apr 2018 14:41:38 +0000 (14:41 +0000)]
[mips] Correct the predicates of the load/store (double)word for coprocessor 3.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329913 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[X86] Remove AES/CLMUL/CRC32/LDDQU/MOVNT/POPCNT/SHA schedule itineraries (PR37093)
Simon Pilgrim [Thu, 12 Apr 2018 14:31:42 +0000 (14:31 +0000)]
[X86] Remove AES/CLMUL/CRC32/LDDQU/MOVNT/POPCNT/SHA schedule itineraries (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329912 91177308-0d34-0410-b5e6-96231b3b80d8

6 years agoRevert "Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." one more time."
Benjamin Kramer [Thu, 12 Apr 2018 13:52:02 +0000 (13:52 +0000)]
Revert "Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." one more time."

This reverts commit r329865. Causes stage2/stage3 miscompare.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329910 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[AArch64][AsmParser] Unify 'addVectorListOperands' functions.
Sander de Smalen [Thu, 12 Apr 2018 13:19:32 +0000 (13:19 +0000)]
[AArch64][AsmParser] Unify 'addVectorListOperands' functions.

Summary:
Merged 'addVectorList64Operands' and 'addVectorList128Operands' into a
generic 'addVectorListOperands', which can be easily extended to work
for SVE vectors.

This is patch [4/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: rengolin

Subscribers: kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45430

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329909 91177308-0d34-0410-b5e6-96231b3b80d8

6 years ago[CodeGen] Allow printing MachineMemOperands with less context in SDAGDumper
Francis Visoiu Mistrih [Thu, 12 Apr 2018 12:59:50 +0000 (12:59 +0000)]
[CodeGen] Allow printing MachineMemOperands with less context in SDAGDumper

Don't assume SelectionDAG is non-null as the targets can use it with a
null pointer.

Differential Revision: https://reviews.llvm.org/D44611

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329908 91177308-0d34-0410-b5e6-96231b3b80d8