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David Bolvansky [Thu, 13 Jun 2019 18:13:03 +0000 (18:13 +0000)]
[NFC] Updated testcase for D54411/rL363284
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363285
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David Bolvansky [Thu, 13 Jun 2019 18:11:32 +0000 (18:11 +0000)]
[Codegen] Merge tail blocks with no successors after block placement
Summary:
I found the following case having tail blocks with no successors merging opportunities after block placement.
Before block placement:
bb0:
...
bne a0, 0, bb2:
bb1:
mv a0, 1
ret
bb2:
...
bb3:
mv a0, 1
ret
bb4:
mv a0, -1
ret
The conditional branch bne in bb0 is opposite to beq.
After block placement:
bb0:
...
beq a0, 0, bb1
bb2:
...
bb4:
mv a0, -1
ret
bb1:
mv a0, 1
ret
bb3:
mv a0, 1
ret
After block placement, that appears new tail merging opportunity, bb1 and bb3 can be merged as one block. So the conditional constraint for merging tail blocks with no successors should be removed. In my experiment for RISC-V, it decreases code size.
Author of original patch: Jim Lin
Reviewers: haicheng, aheejin, craig.topper, rnk, RKSimon, Jim, dmgreen
Reviewed By: Jim, dmgreen
Subscribers: xbolva00, dschuff, javed.absar, sbc100, jgravelle-google, aheejin, kito-cheng, dmgreen, PkmX, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D54411
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363284
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Stanislav Mekhanoshin [Thu, 13 Jun 2019 16:31:51 +0000 (16:31 +0000)]
[AMDGPU] ImmArg and SourceOfDivergence for permlane/dpp
Added missing ImmArg and SourceOfDivergence to the crosslane
intrinsics.
Differential Revision: https://reviews.llvm.org/D63216
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363276
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Cameron McInally [Thu, 13 Jun 2019 15:54:20 +0000 (15:54 +0000)]
[NFC][CodeGen] Add unary FNeg tests to X86/avx512-intrinsics-fast-isel.ll
Patch 2 of n.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363275
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Joseph Tremoulet [Thu, 13 Jun 2019 15:24:11 +0000 (15:24 +0000)]
[EarlyCSE] Ensure equal keys have the same hash value
Summary:
The logic in EarlyCSE that looks through 'not' operations in the
predicate recognizes e.g. that `select (not (cmp sgt X, Y)), X, Y` is
equivalent to `select (cmp sgt X, Y), Y, X`. Without this change,
however, only the latter is recognized as a form of `smin X, Y`, so the
two expressions receive different hash codes. This leads to missed
optimization opportunities when the quadratic probing for the two hashes
doesn't happen to collide, and assertion failures when probing doesn't
collide on insertion but does collide on a subsequent table grow
operation.
This change inverts the order of some of the pattern matching, checking
first for the optional `not` and then for the min/max/abs patterns, so
that e.g. both expressions above are recognized as a form of `smin X, Y`.
It also adds an assertion to isEqual verifying that it implies equal
hash codes; this fires when there's a collision during insertion, not
just grow, and so will make it easier to notice if these functions fall
out of sync again. A new flag --earlycse-debug-hash is added which can
be used when changing the hash function; it forces hash collisions so
that any pair of values inserted which compare as equal but hash
differently will be caught by the isEqual assertion.
Reviewers: spatel, nikic
Reviewed By: spatel, nikic
Subscribers: lebedev.ri, arsenm, craig.topper, efriedma, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62644
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363274
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Michael Liao [Thu, 13 Jun 2019 14:11:09 +0000 (14:11 +0000)]
Fix GCC compiler warning. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363269
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Simon Pilgrim [Thu, 13 Jun 2019 14:05:37 +0000 (14:05 +0000)]
[X86] Use fresh MemOps when emitting VAARG64
Previously it copied over MachineMemOperands verbatim which caused MOV32rm to have store flags set, and MOV32mr to have load flags set. This fixes some assertions being thrown with EXPENSIVE_CHECKS on.
Committed on behalf of @luke (Luke Lau)
Differential Revision: https://reviews.llvm.org/D62726
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363268
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David Stenberg [Thu, 13 Jun 2019 14:02:55 +0000 (14:02 +0000)]
Remove ';' after namespace's closing bracket [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363267
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James Henderson [Thu, 13 Jun 2019 13:58:44 +0000 (13:58 +0000)]
[docs][llvm-symbolizer] Fix formatting issue with --functions
Reviewed by: rupprecht
Differential Revision: https://reviews.llvm.org/D63195
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363266
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Diogo N. Sampaio [Thu, 13 Jun 2019 13:56:19 +0000 (13:56 +0000)]
[FIX] Forces shrink wrapping to consider any memory access as aliasing with the stack
Summary:
Relate bug: https://bugs.llvm.org/show_bug.cgi?id=37472
The shrink wrapping pass prematurally restores the stack, at a point where the stack might still be accessed.
Taking an exception can cause the stack to be corrupted.
As a first approach, this patch is overly conservative, assuming that any instruction that may load or store could access
the stack.
Reviewers: dmgreen, qcolombet
Reviewed By: qcolombet
Subscribers: simpal01, efriedma, eli.friedman, javed.absar, llvm-commits, eugenis, chill, carwil, thegameg
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63152
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363265
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James Henderson [Thu, 13 Jun 2019 13:53:16 +0000 (13:53 +0000)]
[docs][llvm-dwarfdump] Add missing options and behaviour to documentation
This fixes https://bugs.llvm.org/show_bug.cgi?id=42185.
llvm-dwarfdump's documentation was missing a number of options and other
behaviours. This change tries to fix up the documentation by adding
these missing items.
Reviewed by: JDevlieghere
Differential Revision: https://reviews.llvm.org/D63217
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363264
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Eugene Leviant [Thu, 13 Jun 2019 13:25:20 +0000 (13:25 +0000)]
Extra error checking to ARMAttributeParser
The patch checks for subsection length as discussed in D63191
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363260
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Jeremy Morse [Thu, 13 Jun 2019 13:11:57 +0000 (13:11 +0000)]
[NFC] Sink a function call into LiveDebugValues::process
This was requested in D62904, which I successfully missed. This is just
a refactor and shouldn't change any behaviour.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363259
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Simon Tatham [Thu, 13 Jun 2019 13:11:13 +0000 (13:11 +0000)]
[ARM] Set up infrastructure for MVE vector instructions.
This commit prepares the way to start adding the main collection of
MVE instructions, which operate on the 128-bit vector registers.
The most obvious thing that's needed, and the simplest, is to add the
MQPR register class, which is like the existing QPR except that it has
fewer registers in it.
The more complicated part: MVE defines a system of vector predication,
in which instructions operating on 128-bit vector registers can be
constrained to operate on only a subset of the lanes, using a system
of prefix instructions similar to the existing Thumb IT, in that you
have one prefix instruction which designates up to 4 following
instructions as subject to predication, and within that sequence, the
predicate can be inverted by means of T/E suffixes ('Then' / 'Else').
To support instructions of this type, we've added two new Tablegen
classes `vpred_n` and `vpred_r` for standard clusters of MC operands
to add to a predicated instruction. Both include a flag indicating how
the instruction is predicated at all (options are T, E and 'not
predicated'), and an input register field for the register controlling
the set of active lanes. They differ from each other in that `vpred_r`
also includes an input operand for the previous value of the output
register, for instructions that leave inactive lanes unchanged.
`vpred_n` lacks that extra operand; it will be used for instructions
that don't preserve inactive lanes in their output register (either
because inactive lanes are zeroed, as the MVE load instructions do, or
because the output register isn't a vector at all).
This commit also adds the family of prefix instructions themselves
(VPT / VPST), and all the machinery needed to work with them in
assembly and disassembly (e.g. generating the 't' and 'e' mnemonic
suffixes on disassembled instructions within a predicated block)
I've added a couple of demo instructions that derive from the new
Tablegen base classes and use those two operand clusters. The bulk of
the vector instructions will come in followup commits small enough to
be manageable. (One exception is that I've added the full version of
`isMnemonicVPTPredicable` in the AsmParser, because it seemed
pointless to carefully split it up.)
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62669
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363258
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Simon Pilgrim [Thu, 13 Jun 2019 12:58:55 +0000 (12:58 +0000)]
[CodeGen] Add getMachineMemOperand + MachineMemOperand::Flags allocator helper wrapper. NFCI.
Pre-commit for D62726 on behalf of @luke (Luke Lau)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363257
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Jeremy Morse [Thu, 13 Jun 2019 12:51:57 +0000 (12:51 +0000)]
[DebugInfo] Honour variable fragments in LiveDebugValues
This patch makes the LiveDebugValues pass consider fragments when propagating
DBG_VALUE insts between blocks, fixing PR41979. Fragment info for a variable
location is added to the open-ranges key, which allows distinct fragments to be
tracked separately. To handle overlapping fragments things become slightly
funkier. To avoid excessive searching for overlaps in the data-flow part of
LiveDebugValues, this patch:
* Pre-computes pairings of fragments that overlap, for each DILocalVariable
* During data-flow, whenever something happens that causes an open range to
be terminated (via erase), any fragments pre-determined to overlap are
also terminated.
The effect of which is that when encountering a DBG_VALUE fragment that
overlaps others, the overlapped fragments do not get propagated to other
blocks. We still rely on later location-list building to correctly handle
overlapping fragments within blocks.
It's unclear whether a mixture of DBG_VALUEs with and without fragmented
expressions are legitimate. To avoid suprises, this patch interprets a
DBG_VALUE with no fragment as overlapping any DBG_VALUE _with_ a fragment.
Differential Revision: https://reviews.llvm.org/D62904
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363256
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Dmitry Preobrazhensky [Thu, 13 Jun 2019 12:46:37 +0000 (12:46 +0000)]
[AMDGPU][MC] Enabled constant expressions as operands of s_getreg/s_setreg
See bug 40820: https://bugs.llvm.org/show_bug.cgi?id=40820
Reviewers: artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D61125
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363255
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Eugene Leviant [Thu, 13 Jun 2019 12:33:26 +0000 (12:33 +0000)]
[ThinLTO][Bitcode] Add 'entrycount' to FS_COMBINED_PROFILE. NFC
Differential revision: https://reviews.llvm.org/D63078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363254
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Simon Pilgrim [Thu, 13 Jun 2019 11:42:32 +0000 (11:42 +0000)]
[X86][AVX] Add broadcast(v4f64 hadd) test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363252
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Simon Pilgrim [Thu, 13 Jun 2019 11:26:21 +0000 (11:26 +0000)]
[X86][SSE] Avoid assert for broadcast(horiz-op()) cases for non-f64 cases.
Based on fuzz test from @craig.topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363251
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Simon Pilgrim [Thu, 13 Jun 2019 10:41:56 +0000 (10:41 +0000)]
[X86][SSE] Add tests for underaligned nt stores
Test both 'unaligned' (which we should scalarize) and 'subvector aligned' (which we should split)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363249
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Chris Jackson [Thu, 13 Jun 2019 10:39:36 +0000 (10:39 +0000)]
[llvm-nm] Additional lit tests for command line options
Differential Revision: https://reviews.llvm.org/D62955
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363248
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Simon Pilgrim [Thu, 13 Jun 2019 10:30:12 +0000 (10:30 +0000)]
[X86][SSE] Add SSE4A nt store tests on X86 as well as X64
We should be able to use MOVNTSD (f64) instead of MOVNTI (i32) to reduce the number of ops 32-bit targets
Pulled out of D63246
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363247
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Nikola Prica [Thu, 13 Jun 2019 10:23:26 +0000 (10:23 +0000)]
[DebugInfo] Move Value struct out of DebugLocEntry as DbgValueLoc (NFC)
Since the DebugLocEntry::Value is used as part of DwarfDebug and
DebugLocEntry make it as the separate class.
Reviewers: aprantl, dstenb
Reviewed By: aprantl
Differential Revision: https://reviews.llvm.org/D63213
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363246
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Jeremy Morse [Thu, 13 Jun 2019 10:03:17 +0000 (10:03 +0000)]
[DebugInfo] Use FrameDestroy to extend stack locations to end-of-function
We aim to ignore changes in variable locations during the prologue and
epilogue of functions, to avoid using space documenting location changes
that aren't visible. However in D61940 / r362951 this got ripped out as
the previous implementation was unsound.
Instead, use the FrameDestroy flag to identify when we're in the epilogue
of a function, and ignore variable location changes accordingly. This fits
in with existing code that examines the FrameSetup flag.
Some variable locations get shuffled in modified tests as they now cover
greater ranges, which is what would be expected. Some additional
single-location variables are generated too. Two tests are un-xfailed,
they were only xfailed due to r362951 deleting functionality they depended
on.
Apparently some out-of-tree backends don't accurately maintain FrameDestroy
flags -- if you're an out-of-tree maintainer and see changes in variable
locations disappear due to a faulty FrameDestroy flag, it's safe to back
this change out. The impact is just slightly more debug info than necessary.
Differential Revision: https://reviews.llvm.org/D62314
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363245
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Simon Tatham [Thu, 13 Jun 2019 10:01:52 +0000 (10:01 +0000)]
[ARM] Refactor handling of IT mask operands.
During assembly, the mask operand to an IT instruction (storing the
sequence of T/E for 'Then' and 'Else') is parsed out of the mnemonic
into a representation that encodes 'Then' and 'Else' in the same way
regardless of the condition code. At some point during encoding it has
to be converted into the instruction encoding used in the
architecture, in which the mask encodes a sequence of replacement
low-order bits for the condition code, so that which bit value means
'then' and which 'else' depends on whether the original condition code
had its low bit set.
Previously, that transformation was done by processInstruction(), half
way through assembly. So an MCOperand storing an IT mask would
sometimes store it in one format, and sometimes in the other,
depending on where in the assembly pipeline you were. You can see this
in diagnostics from `llvm-mc -debug -triple=thumbv8a -show-inst`, for
example: if you give it an instruction such as `itete eq`, you'd see
an `<MCOperand Imm:5>` in a diagnostic become `<MCOperand Imm:11>` in
the final output.
Having the same data structure store values with time-dependent
semantics is confusing already, and it will get more confusing when we
introduce the MVE VPT instruction which reuses the Then/Else bitmask
idea in a different context. So I'm refactoring: now, all `ARMOperand`
and `MCOperand` representations of an IT mask work exactly the same
way, namely, 0 means 'Then' and 1 means 'Else', regardless of what
original predicate is being referred to. The architectural encoding of
IT that depends on the original condition is now constructed at the
point when we turn the `MCOperand` into the final instruction bit
pattern, and decoded similarly in the disassembler.
The previous condition-independent parse-time format used 0 for Else
and 1 for Then. I've taken the opportunity to flip the sense of it
while I'm changing all of this anyway, because it seems to me more
natural to use 0 for 'leave the starting condition unchanged' and 1
for 'invert it', as if those bits were an XOR mask.
Reviewers: ostannard
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63219
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363244
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Eugene Leviant [Thu, 13 Jun 2019 09:56:14 +0000 (09:56 +0000)]
[llvm-objcopy] Implement IHEX reader
This is the final part of IHEX format support in llvm-objcopy
Differential revision: https://reviews.llvm.org/D62583
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363243
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Sander de Smalen [Thu, 13 Jun 2019 09:37:38 +0000 (09:37 +0000)]
Improve reduction intrinsics by overloading result value.
This patch uses the mechanism from D62995 to strengthen the
definitions of the reduction intrinsics by letting the scalar
result/accumulator type be overloaded from the vector element type.
For example:
; The LLVM LangRef specifies that the scalar result must equal the
; vector element type, but this is not checked/enforced by LLVM.
declare i32 @llvm.experimental.vector.reduce.or.i32.v4i32(<4 x i32> %a)
This patch changes that into:
declare i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> %a)
Which has the type-constraint more explicit and causes LLVM to check
the result type with the vector element type.
Reviewers: RKSimon, arsenm, rnk, greened, aemerson
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D62996
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363240
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Owen Reynolds [Thu, 13 Jun 2019 09:02:33 +0000 (09:02 +0000)]
Revert [llvm-ar][test] Add to MRI test coverage
This reverts 363232 due to mru-utf8.test buildbot test failure
Differential Revision: https://reviews.llvm.org/D63197
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363239
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Sam Parker [Thu, 13 Jun 2019 08:32:56 +0000 (08:32 +0000)]
[NFC] Simplify Call query
Use getIntrinsicID() directly from IntrinsicInst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363235
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Sam Parker [Thu, 13 Jun 2019 08:28:46 +0000 (08:28 +0000)]
[ARM][TTI] Scan for existing loop intrinsics
TTI should report that it's not profitable to generate a hardware loop
if it, or one of its child loops, has already been converted.
Differential Revision: https://reviews.llvm.org/D63212
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363234
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Sander de Smalen [Thu, 13 Jun 2019 08:19:33 +0000 (08:19 +0000)]
[IntrinsicEmitter] Extend argument overloading with forward references.
Extend the mechanism to overload intrinsic arguments by using either
backward or forward references to the overloadable arguments.
In for example:
def int_something : Intrinsic<[LLVMPointerToElt<0>],
[llvm_anyvector_ty], []>;
LLVMPointerToElt<0> is a forward reference to the overloadable operand
of type 'llvm_anyvector_ty' and would allow intrinsics such as:
declare i32* @llvm.something.v4i32(<4 x i32>);
declare i64* @llvm.something.v2i64(<2 x i64>);
where the result pointer type is deduced from the element type of the
first argument.
If the returned pointer is not a pointer to the element type, LLVM will
give an error:
Intrinsic has incorrect return type!
i64* (<4 x i32>)* @llvm.something.v4i32
Reviewers: RKSimon, arsenm, rnk, greened
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D62995
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363233
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Owen Reynolds [Thu, 13 Jun 2019 07:45:12 +0000 (07:45 +0000)]
[llvm-ar][test] Add to MRI test coverage
This change adds tests to cover existing MRI script functionality.
Differential Revision: https://reviews.llvm.org/D63197
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363232
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Craig Topper [Thu, 13 Jun 2019 07:11:02 +0000 (07:11 +0000)]
[X86] Correct instruction operands in evex-to-vex-compress.mir to be closer to real instructions.
$noreg was being used way more than it should have. We also had
xmm registers in addressing modes.
Mostly found by hacking the machine verifier to do some stricter
checking that happened to work for this test, but not sure if
generally applicable for other tests or other targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363231
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Shawn Landden [Thu, 13 Jun 2019 05:26:17 +0000 (05:26 +0000)]
[SimplifyCFG] reverting preliminary Switch patches again
This reverts 363226 and 363227, both NFC intended
I swear I fixed the test case that is failing, and ran
the tests, but I will look into it again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363229
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Shawn Landden [Thu, 13 Jun 2019 05:01:44 +0000 (05:01 +0000)]
[SimpligyCFG] NFC intended, remove GCD that was only used for powers of two
and replace with an equilivent countTrailingZeros.
GCD is much more expensive than this, with repeated division.
This depends on D60823
Differential Revision: https://reviews.llvm.org/D61151
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363227
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Shawn Landden [Thu, 13 Jun 2019 04:51:35 +0000 (04:51 +0000)]
[SimplifyCFG] NFC, update Switch tests to better examine successive patches
Also add baseline tests to show effect of later patches.
There were a couple of regressions here that were never caught,
but my patch set that this is a preparation to will fix them.
Differential Revision: https://reviews.llvm.org/D61150
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363226
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Craig Topper [Thu, 13 Jun 2019 04:10:08 +0000 (04:10 +0000)]
[X86] Add tests for some the special cases in EVEX to VEX to the evex-to-vex-compress.mir test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363224
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Shawn Landden [Thu, 13 Jun 2019 02:47:47 +0000 (02:47 +0000)]
[SimplifyCFG] revert the last commit.
I ran ALL the test suite locally, so I will look into this...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363223
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Shawn Landden [Thu, 13 Jun 2019 02:24:24 +0000 (02:24 +0000)]
[SimplifyCFG] NFC, update Switch tests to HEAD so I can
see if my changes change anything
Also add baseline tests to show effect of later patches.
Differential Revision: https://reviews.llvm.org/D61150
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363222
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Tom Stellard [Thu, 13 Jun 2019 02:09:32 +0000 (02:09 +0000)]
X86: Clean up pass initialization
Summary:
- Remove redundant initializations from pass constructors that were
already being initialized by LLVMInitializeX86Target().
- Add initialization function for the FPS pass.
Reviewers: craig.topper
Reviewed By: craig.topper
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63218
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363221
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David L. Jones [Thu, 13 Jun 2019 02:04:45 +0000 (02:04 +0000)]
Revert r361811: 'Re-commit r357452 (take 2): "SimplifyCFG SinkCommonCodeFromPredecessors ...'
We have observed some failures with internal builds with this revision.
- Performance regressions:
- llvm's SingleSource/Misc evalloop shows performance regressions (although these may be red herrings).
- Benchmarks for Abseil's SwissTable.
- Correctness:
- Failures for particular libicu tests when building the Google AppEngine SDK (for PHP).
hwennborg has already been notified, and is aware of reproducer failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363220
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Dinar Temirbulatov [Thu, 13 Jun 2019 00:19:50 +0000 (00:19 +0000)]
[SLP] Update propagate_ir_flags.ll test to check that we do retain the common subset, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363218
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Philip Reames [Wed, 12 Jun 2019 23:39:49 +0000 (23:39 +0000)]
[Tests] Highlight impact of multiple exit LFTR (D62625) as requested by reviewer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363217
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Cameron McInally [Wed, 12 Jun 2019 22:50:44 +0000 (22:50 +0000)]
[NFC][CodeGen] Add unary FNeg tests to X86/avx512-intrinsics-fast-isel.ll
Patch 1 of n.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363215
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Mircea Trofin [Wed, 12 Jun 2019 22:02:07 +0000 (22:02 +0000)]
[llvm] Expose DWARFDebugLine::LineTable::getFileNameEntry
Summary:
This is useful for scenarios where Prologue was directly used and DWARF
5 awareness is required. The current alternative would be to either
duplicate the logic in getFileNameEntry, or to use getFileNameByIndex.
The latter isn't quite an in-place replacement - it performs some
processing, and it produces a string instead of a StringRef, meaning
the caller needs to handle its lifetime.
Reviewers: tamur, dblaikie, JDevlieghere
Reviewed By: tamur, JDevlieghere
Subscribers: aprantl, llvm-commits
Tags: #llvm, #debug-info
Differential Revision: https://reviews.llvm.org/D63228
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363210
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Sanjay Patel [Wed, 12 Jun 2019 21:30:06 +0000 (21:30 +0000)]
[x86] add tests for vector shifts; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363203
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Serge Guelton [Wed, 12 Jun 2019 21:08:19 +0000 (21:08 +0000)]
Sanitize llvm-extract -help output
Filter out irrelevant options
New output:
OVERVIEW: llvm extractor
USAGE: llvm-extract [options] <input bitcode file>
OPTIONS:
Generic Options:
--help - Display available options (--help-hidden for more)
--help-list - Display list of available options (--help-list-hidden for more)
--version - Display the version of this program
llvm-extract Options:
--alias=<alias> - Specify alias to extract
--bb=<function:bb> - Specify <function, basic block> pairs to extract
--delete - Delete specified Globals from Module
-f - Enable binary output on terminals
--func=<function> - Specify function to extract
--glob=<global> - Specify global to extract
-o=<filename> - Specify output filename
--ralias=<ralias> - Specify alias(es) to extract using a regular expression
--recursive - Recursively extract all called functions
--rfunc=<rfunction> - Specify function(s) to extract using a regular expression
--rglob=<rglobal> - Specify global(s) to extract using a regular expression
Differential Revision: https://reviews.llvm.org/D62511
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363201
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Cameron McInally [Wed, 12 Jun 2019 20:56:59 +0000 (20:56 +0000)]
[NFC][CodeGen] Add unary FNeg tests to X86/avx512vl-intrinsics-fast-isel.ll
Patch 3 of 3 for X86/avx512vl-intrinsics-fast-isel.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363200
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Jordan Rupprecht [Wed, 12 Jun 2019 20:16:22 +0000 (20:16 +0000)]
[llvm-readobj] Fix output interleaving issue caused by using multiple streams at the same time.
Summary:
Use llvm::fouts() as the default stream for outputing. No new stream
should be constructed to output at the same time.
https://bugs.llvm.org/show_bug.cgi?id=42140
Reviewers: jhenderson, grimar, MaskRay, phosek, rupprecht
Reviewed By: rupprecht
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63115
Patch by Yuanfang Chen!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363198
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Philip Reames [Wed, 12 Jun 2019 19:52:05 +0000 (19:52 +0000)]
[IndVars] Extend diagnostic -replexitval flag w/ability to bypass hard use hueristic
Note: This does mean that "always" is now more powerful than it was.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363196
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Cameron McInally [Wed, 12 Jun 2019 19:39:42 +0000 (19:39 +0000)]
[NFC][CodeGen] Add unary FNeg tests to X86/avx512vl-intrinsics-fast-isel.ll
Patch 2 of 3 for X86/avx512vl-intrinsics-fast-isel.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363194
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Philip Reames [Wed, 12 Jun 2019 19:23:10 +0000 (19:23 +0000)]
[Tests] Autogen RLEV test and add tests for a future enhancement
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363193
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Philip Reames [Wed, 12 Jun 2019 19:04:51 +0000 (19:04 +0000)]
[Tests] Add tests to highlight sibling loop optimization order issue for exit rewriting
The issue addressed in r363180 is more broadly relevant. For the moment, we don't actually get any of these cases because we a) restrict SCEV formation due to SCEExpander needing to preserve LCSSA, and b) don't iterate between loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363192
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Stanislav Mekhanoshin [Wed, 12 Jun 2019 18:44:11 +0000 (18:44 +0000)]
[AMDGPU] more gfx1010 tests. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363190
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Jordan Rupprecht [Wed, 12 Jun 2019 18:41:27 +0000 (18:41 +0000)]
[llvm-ar][test] Relax lit directory assumptions in thin-archive.test
Summary: thin-archive.test assumes the Output/<testname> structure that lit creates. Rewrite the test in a way that still tests the same thing (creating via relative path and adding via absolute path) but doesn't assume this specific lit structure, making it possible to run in a lit emulator.
Reviewers: gbreynoo
Reviewed By: gbreynoo
Subscribers: llvm-commits, bkramer
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62930
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363189
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Stanislav Mekhanoshin [Wed, 12 Jun 2019 18:02:41 +0000 (18:02 +0000)]
[AMDGPU] gfx1010 dpp16 and dpp8
Differential Revision: https://reviews.llvm.org/D63203
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363186
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Stanislav Mekhanoshin [Wed, 12 Jun 2019 17:52:51 +0000 (17:52 +0000)]
[AMDGPU] gfx1010 premlane instructions
Differential Revision: https://reviews.llvm.org/D63202
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363185
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Simon Atanasyan [Wed, 12 Jun 2019 17:52:05 +0000 (17:52 +0000)]
[Mips] Add s.d instruction alias for Mips1
Add support for s.d instruction for Mips1 which expands into two swc1
instructions.
Patch by Mirko Brkusanin.
Differential Revision: https://reviews.llvm.org/D63199
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363184
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Shoaib Meenai [Wed, 12 Jun 2019 17:37:01 +0000 (17:37 +0000)]
[llvm-lipo] Update llvm-lipo docs for -archs flag
The information for -archs flag is added to llvm-lipo.rst.
Patch by Anusha Basana <anusha.basana@gmail.com>
Differential Revision: https://reviews.llvm.org/D63100
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363182
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Simon Pilgrim [Wed, 12 Jun 2019 17:28:48 +0000 (17:28 +0000)]
[X86][SSE] Avoid unnecessary stack codegen in NT merge-consecutive-stores codegen tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363181
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Philip Reames [Wed, 12 Jun 2019 17:21:47 +0000 (17:21 +0000)]
[SCEV] Teach computeSCEVAtScope benefit from one-input Phi. PR39673
SCEV does not propagate arguments through one-input Phis so as to make it easy for the SCEV expander (and related code) to preserve LCSSA. It's not entirely clear this restriction is neccessary, but for the moment it exists. For this reason, we don't analyze single-entry phi inputs. However it is possible that when an this input leaves the loop through LCSSA Phi, it is a provable constant. Missing that results in an order of optimization issue in loop exit value rewriting where we miss some oppurtunities based on order in which we visit sibling loops.
This patch teaches computeSCEVAtScope about this case. We can generalize it later, but so far we can only replace LCSSA Phis with their constant loop-exiting values. We should probably also add similiar logic directly in the SCEV construction path itself.
Patch by: mkazantsev (with revised commit message by me)
Differential Revision: https://reviews.llvm.org/D58113
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363180
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Simon Pilgrim [Wed, 12 Jun 2019 17:14:03 +0000 (17:14 +0000)]
[TargetLowering] Add MachineMemOperand::Flags to allowsMemoryAccess tests (PR42123)
As discussed on D62910, we need to check whether particular types of memory access are allowed, not just their alignment/address-space.
This NFC patch adds a MachineMemOperand::Flags argument to allowsMemoryAccess and allowsMisalignedMemoryAccesses, and wires up calls to pass the relevant flags to them.
If people are happy with this approach I can then update X86TargetLowering::allowsMisalignedMemoryAccesses to handle misaligned NT load/stores.
Differential Revision: https://reviews.llvm.org/D63075
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363179
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Simon Pilgrim [Wed, 12 Jun 2019 16:38:20 +0000 (16:38 +0000)]
[X86][AVX] Fold concat(vpermilps(x,c),vpermilps(y,c)) -> vpermilps(concat(x,y),c)
Handles PSHUFD/PSHUFLW/PSHUFHW (AVX2) + VPERMILPS (AVX1).
An extra AVX1 PSHUFD->VPERMILPS combine will be added in a future commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363178
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Sanjay Patel [Wed, 12 Jun 2019 15:29:40 +0000 (15:29 +0000)]
[InstCombine] add tests for fmin/fmax libcalls; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363175
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Sam Parker [Wed, 12 Jun 2019 15:28:00 +0000 (15:28 +0000)]
Revert rL363156.
The patch was to fix buildbots, but rL363157 should now be fixing it
in a cleaner way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363174
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David Bolvansky [Wed, 12 Jun 2019 15:01:36 +0000 (15:01 +0000)]
[NFC[ Updated tests for D54411
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363173
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Nico Weber [Wed, 12 Jun 2019 14:24:43 +0000 (14:24 +0000)]
gn build: Add SystemZ target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363170
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Matt Arsenault [Wed, 12 Jun 2019 14:23:33 +0000 (14:23 +0000)]
StackProtector: Use PointerMayBeCaptured
This was using its own, outdated list of possible captures. This was
at minimum not catching cmpxchg and addrspacecast captures.
One change is now any volatile access is treated as capturing. The
test coverage for this pass is quite inadequate, but this required
removing volatile in the lifetime capture test.
Also fixes some infrastructure issues to allow running just the IR
pass.
Fixes bug 42238.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363169
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Matt Arsenault [Wed, 12 Jun 2019 14:23:28 +0000 (14:23 +0000)]
AMDGPU/GlobalISel: Fix using illegal situations in tests
These were using illegal copies as the side effecting use, so make
them legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363168
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Mikael Holmen [Wed, 12 Jun 2019 14:19:22 +0000 (14:19 +0000)]
[ARM] Fix compiler warning
Without this fix clang 3.6 complains with:
../lib/Target/ARM/ARMAsmPrinter.cpp:1473:18: error: variable 'BranchTarget' is used uninitialized whenever 'if' condition is false [-Werror,-Wsometimes-uninitialized]
} else if (MI->getOperand(1).isSymbol()) {
^~~~~~~~~~~~~~~~~~~~~~~~~~~~
../lib/Target/ARM/ARMAsmPrinter.cpp:1479:22: note: uninitialized use occurs here
MCInst.addExpr(BranchTarget);
^~~~~~~~~~~~
../lib/Target/ARM/ARMAsmPrinter.cpp:1473:14: note: remove the 'if' if its condition is always true
} else if (MI->getOperand(1).isSymbol()) {
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../lib/Target/ARM/ARMAsmPrinter.cpp:1465:33: note: initialize the variable 'BranchTarget' to silence this warning
const MCExpr *BranchTarget;
^
= nullptr
1 error generated.
Discussed here:
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20190610/661417.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363166
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Matt Arsenault [Wed, 12 Jun 2019 14:05:58 +0000 (14:05 +0000)]
LoopVersioning: Respect convergent
This changes the standalone pass only. Arguably the utility class
itself should assert there are no convergent calls. However, a target
pass with additional context may still be able to version a loop if
all of the dynamic conditions are sufficiently uniform.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363165
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Anton Afanasyev [Wed, 12 Jun 2019 13:51:44 +0000 (13:51 +0000)]
[MIR] Skip hoisting to basic block which may throw exception or return
Summary:
Fix hoisting to basic block which are not legal for hoisting cause
it can be terminated by exception or it is return block.
Reviewers: john.brawn, RKSimon, MatzeB
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63148
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363164
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Sanjay Patel [Wed, 12 Jun 2019 13:51:33 +0000 (13:51 +0000)]
[InstCombine] add tests for fcmp+select with FMF (minnum/maxnum); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363163
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Matt Arsenault [Wed, 12 Jun 2019 13:50:47 +0000 (13:50 +0000)]
LoopLoadElim: Respect convergent
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363162
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Jeremy Morse [Wed, 12 Jun 2019 13:41:56 +0000 (13:41 +0000)]
[DebugInfo] Add a test that fell out of an earlier commit
r362951 was supposed to contain this test, however it didn't get committed
due to operator error. This was originally part of D59431.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363161
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Matt Arsenault [Wed, 12 Jun 2019 13:34:19 +0000 (13:34 +0000)]
LoopDistribute/LAA: Respect convergent
This case is slightly tricky, because loop distribution should be
allowed in some cases, and not others. As long as runtime dependency
checks don't need to be introduced, this should be OK. This is further
complicated by the fact that LoopDistribute partially ignores if LAA
says that vectorization is safe, and then does its own runtime pointer
legality checks.
Note this pass still does not handle noduplicate correctly, as this
should always be forbidden with it. I'm not going to bother trying to
fix it, as it would require more effort and I think noduplicate should
be removed.
https://reviews.llvm.org/D62607
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363160
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Nico Weber [Wed, 12 Jun 2019 13:25:58 +0000 (13:25 +0000)]
gn build: Add Mips target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363159
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Matt Arsenault [Wed, 12 Jun 2019 13:15:59 +0000 (13:15 +0000)]
LoopDistribute/LAA: Add tests to catch regressions
I broke 2 of these with a patch, but were not covered by existing
tests.
https://reviews.llvm.org/D63035
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363158
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Sam Parker [Wed, 12 Jun 2019 12:54:19 +0000 (12:54 +0000)]
[NFC] Add HardwareLoops lit.local.cfg file
Set Transforms/HardwareLoops/ARM/ tests as unsupported if there isn't
an arm target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363157
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Sam Parker [Wed, 12 Jun 2019 12:47:35 +0000 (12:47 +0000)]
Attempt to fix non-Arm buildbots
Adding REQUIRES: arm to failing tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363156
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Nico Weber [Wed, 12 Jun 2019 12:46:46 +0000 (12:46 +0000)]
Fix a Wunused-lambda-capture warning.
The capture was added in the first commit of https://reviews.llvm.org/D61934
when it was used. In the reland, the use was removed but the capture
wasn't removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363155
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Nico Weber [Wed, 12 Jun 2019 12:41:03 +0000 (12:41 +0000)]
gn build: add RISCV target
Patch from David L. Jones <dlj@google.com>, with minor tweaks by me.
Differential Revision: https://reviews.llvm.org/D61821
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363154
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Simon Pilgrim [Wed, 12 Jun 2019 12:40:03 +0000 (12:40 +0000)]
[X86][AVX] Tests showing missing concat(shuffle,shuffle) -> shuffle(concat) folds. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363153
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Nico Weber [Wed, 12 Jun 2019 12:27:04 +0000 (12:27 +0000)]
gn build: Merge r363122
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363152
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Ben Dunbobbin [Wed, 12 Jun 2019 12:17:49 +0000 (12:17 +0000)]
[Legacy LTO] Fix build bots: r363140: Fix export name
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363151
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Sam Parker [Wed, 12 Jun 2019 12:00:42 +0000 (12:00 +0000)]
[ARM] Implement TTI::isHardwareLoopProfitable
Implement the backend target hook to drive the HardwareLoops pass.
The low-overhead branch extension for Arm M-class cores is flexible
enough that we don't have to ensure correctness at this point, except
checking that the loop counter variable can be stored in LR - a
32-bit register. For it to be profitable, we want to avoid loops that
contain function calls, or any other instruction that alters the PC.
This implementation uses TargetLoweringInfo, to query type and
operation actions, looks at intrinsic calls and also performs some
manual checks for remainder/division and FP operations.
I think this should be a good base to start and extra details can be
filled out later.
Differential Revision: https://reviews.llvm.org/D62907
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363149
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Ayke van Laethem [Wed, 12 Jun 2019 11:59:09 +0000 (11:59 +0000)]
[bindings/go][NFC] Format code with go fmt
Run go fmt (version 1.12) over the Go bindings. This cleans up lots of
inconsistencies in the code, it does not change the code in a functional
way.
Differential Revision: https://reviews.llvm.org/D63057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363148
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Sam Parker [Wed, 12 Jun 2019 11:53:55 +0000 (11:53 +0000)]
[NFC][SCEV] Add NoWrapFlag argument to InsertBinOp
'Use wrap flags in InsertBinop' (rL362687) was reverted due to
miscompiles. This patch introduces the previous change to pass
no-wrap flags but now only FlagAnyWrap is passed.
Differential Revision: https://reviews.llvm.org/D61934
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363147
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James Henderson [Wed, 12 Jun 2019 11:41:43 +0000 (11:41 +0000)]
[docs][llvm-symbolizer] Fix typo and grammar error
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363145
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Nico Weber [Wed, 12 Jun 2019 11:32:43 +0000 (11:32 +0000)]
Share /machine: handling code with llvm-cvtres too
r363016 let lld-link and llvm-lib share the /machine: parsing code.
This lets llvm-cvtres share it as well.
Making llvm-cvtres depend on llvm-lib seemed a bit strange (it doesn't
need llvm-lib's dependencies on BinaryFormat and BitReader) and I
couldn't find a good place to put this code. Since it's just a few
lines, put it in lib/Object for now.
Differential Revision: https://reviews.llvm.org/D63120
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363144
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Xing GUO [Wed, 12 Jun 2019 11:24:22 +0000 (11:24 +0000)]
[DOC] Fix `load` instructions' syntax, function definition.
Summary: In this patch, I updated `load` instruction syntax and fixed function definition. Besides, I re-named some variables to make them obey SSA rule.
Reviewers: MaskRay
Reviewed By: MaskRay
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63186
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363142
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Simon Pilgrim [Wed, 12 Jun 2019 11:08:29 +0000 (11:08 +0000)]
[XCore] CombineSTORE - Use allowsMemoryAccess wrapper. NFCI.
Noticed in D63075 - there was a allowsMisalignedMemoryAccesses call to check for unaligned loads and a check for aligned legal type loads - which is exactly what allowsMemoryAccess does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363141
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Ben Dunbobbin [Wed, 12 Jun 2019 11:07:56 +0000 (11:07 +0000)]
[ThinLTO]LTO]Legacy] Fix dependent libraries support by adding querying of the IRSymtab
Dependent libraries support for the legacy api was committed in a
broken state (see: https://reviews.llvm.org/D60274). This was missed
due to the painful nature of having to integrate the changes into a
linker in order to test. This change implements support for dependent
libraries in the legacy LTO api:
- I have removed the current api function, which returns a single
string, and added functions to access each dependent library
specifier individually.
- To reduce the testing pain, I have made the api functions as thin as
possible to maximize coverage from llvm-lto.
- When doing ThinLTO the system linker will load the modules lazily
when scanning the input files. Unfortunately, when modules are
lazily loaded there is no access to module level named metadata. To
fix this I have added api functions that allow querying the IRSymtab
for the dependent libraries. I hope to expand the api in the future
so that, eventually, all the information needed by a client linker
during scan can be retrieved from the IRSymtab.
Differential Revision: https://reviews.llvm.org/D62935
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363140
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James Henderson [Wed, 12 Jun 2019 10:48:33 +0000 (10:48 +0000)]
[docs] Fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363138
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Simon Pilgrim [Wed, 12 Jun 2019 10:46:50 +0000 (10:46 +0000)]
[XCore] LowerLOAD/LowerSTORE - Use allowsMemoryAccess wrapper. NFCI.
Noticed in D63075 - there was a allowsMisalignedMemoryAccesses call to check for unaligned loads and a check for aligned legal type loads - which is exactly what allowsMemoryAccess does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363137
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James Henderson [Wed, 12 Jun 2019 10:44:41 +0000 (10:44 +0000)]
[llvm-nm] Fix docs and help text for --print-size
The --print-size help text and documentation claimed that the size was
printed instead of the address, but this is incorrect. It is printed as
well as the address. This patch fixes this issue.
Reviewed by: MaskRay, mtrent, ruiu
Differential Revision: https://reviews.llvm.org/D63142
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363136
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Orlando Cazalet-Hyams [Wed, 12 Jun 2019 08:34:51 +0000 (08:34 +0000)]
Revert "[DebugInfo@O2][LoopVectorize] pr39024: Vectorized code linenos step through loop even after completion"
This reverts commit
1a0f7a2077b70c9864faa476e15b048686cf1ca7.
See phabricator thread for D60831.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363132
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Dylan McKay [Wed, 12 Jun 2019 08:31:07 +0000 (08:31 +0000)]
[AVR] Fix the 'avr-tiny.ll' and 'avr25.ll' subtarget feature tests
When these tests were originally written, the middle end would introduce
an unnecessary copy from r24:r23->GPR16->r24:r23, and these tests
mistakenly relied on it.
The most optimal codegen for the functions in the test cases before this patch
would be NOPs. This is because the first i16 argument always gets the same register
allocation as an i16 return value in the AVR calling convention.
These tests broke in r362963 when the codegen was improved and the
redundant copy was eliminated. After this, the test functions
were lowered to their optimal form - a 'ret' and nothing else.
This patch prepends an extra i16 operand to each of the test functions
so that a 16-bit copy must be inserted for the program to be correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363131
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Sjoerd Meijer [Wed, 12 Jun 2019 08:28:35 +0000 (08:28 +0000)]
[AArch64] Merge globals when optimising for size
Extern global merging is good for code-size. There's definitely potential for
performance too, but there's one regression in a benchmark that needs
investigating, so that's why we enable it only when we optimise for size for
now.
Patch by Ramakota Reddy and Sjoerd Meijer.
Differential Revision: https://reviews.llvm.org/D61947
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363130
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