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Renato Golin [Wed, 3 Jul 2013 20:56:33 +0000 (20:56 +0000)]
Add platform specific tests doc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185581
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Tilmann Scheller [Wed, 3 Jul 2013 20:38:01 +0000 (20:38 +0000)]
ARM: Prevent ARMAsmParser::shouldOmitCCOutOperand() from misidentifying certain Thumb2 add immediate T3 encodings.
Before the fix Thumb2 instructions of type "add rD, rN, #imm" (T3 encoding, see ARM ARM A8.8.4) with rD and rN both being low registers (r0-r7) were classified as having the T4 encoding.
The T4 encoding doesn't have a cc_out operand so for above instructions the operand gets erroneously removed, corrupting the token stream and leading to parse errors later in the process.
This bug prevented "add r1, r7, #0xcbcbcbcb" from being assembled correctly.
Fixes <rdar://problem/
14224440>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185575
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Eric Christopher [Wed, 3 Jul 2013 20:36:36 +0000 (20:36 +0000)]
Move typedefs inside the class that they belong to.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185573
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Chad Rosier [Wed, 3 Jul 2013 18:38:08 +0000 (18:38 +0000)]
Use an RWMutex instead of a Mutex in PassRegistry.
Patch by Alex Crichton <alex@crichton.co>. Approved by Chris Lattner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185566
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Ulrich Weigand [Wed, 3 Jul 2013 18:29:47 +0000 (18:29 +0000)]
[PowerPC] Support lmw/stmw in the asm parser
This adds support for the load/store multiple instructions,
currently used by the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185564
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Ulrich Weigand [Wed, 3 Jul 2013 17:59:07 +0000 (17:59 +0000)]
[PowerPC] Use mtocrf when available
Just as with mfocrf, it is also preferable to use mtocrf instead of
mtcrf when only a single CR register is to be written.
Current code however always emits mtcrf. This probably does not matter
when using an external assembler, since the GNU assembler will in fact
automatically replace mtcrf with mtocrf when possible. It does create
inefficient code with the integrated assembler, however.
To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and
uses those instead of MTCRF/MTCRF8 everything. Just as done in the
MFOCRF patch committed as 185556, these patterns will be converted
back to MTCRF if MTOCRF is not available on the machine.
As a side effect, this allows to modify the MTCRF pattern to accept
the full range of mask operands for the benefit of the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185561
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Ulrich Weigand [Wed, 3 Jul 2013 17:05:42 +0000 (17:05 +0000)]
[PowerPC] Always use mfocrf if available
When accessing just a single CR register, it is always preferable to
use mfocrf instead of mfcr, if the former is available on the CPU.
Current code makes that distinction in many, but not all places
where a single CR register value is retrieved. One missing
location is PPCRegisterInfo::lowerCRSpilling.
To fix this and make this simpler in the future, this patch changes
the bulk of the back-end to always assume mfocrf is available and
simply generate it when needed.
On machines that actually do not support mfocrf, the instruction
is replaced by mfcr at the very end, in EmitInstruction.
This has the additional benefit that we no longer need the
MFCRpseud hack, since before EmitInstruction we always have
a MFOCRF instruction pattern, which already models data flow
as required.
The patch also adds the MFOCRF8 version of the instruction,
which was missing so far.
Except for the PPCRegisterInfo::lowerCRSpilling case, no change
in generated code intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185556
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Rafael Espindola [Wed, 3 Jul 2013 16:41:29 +0000 (16:41 +0000)]
Prefix failing commands with not to make clear they are expected to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185554
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Rafael Espindola [Wed, 3 Jul 2013 16:35:26 +0000 (16:35 +0000)]
Remove another old test.
It was only passing because 'grep andpd' was not finding any andpd, but
we don't fail if part of a pipe fails.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185552
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Rafael Espindola [Wed, 3 Jul 2013 16:30:01 +0000 (16:30 +0000)]
Remove test for the old EH system. It doesn't parse anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185551
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Rafael Espindola [Wed, 3 Jul 2013 16:27:55 +0000 (16:27 +0000)]
Fix test: It was missing run lines and llvm-dis has no -disable-verify option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185550
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Rafael Espindola [Wed, 3 Jul 2013 15:57:14 +0000 (15:57 +0000)]
Add support for gnu archives with a string table and no symtab.
While there, use early returns to reduce nesting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185547
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Rafael Espindola [Wed, 3 Jul 2013 15:46:03 +0000 (15:46 +0000)]
Make llvm-nm return 1 on error.
This is a small compatibility improvement with gnu nm and makes llvm-nm more
useful as a testing tool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185546
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Ulrich Weigand [Wed, 3 Jul 2013 15:13:30 +0000 (15:13 +0000)]
[PowerPC] Remove dead code from PPCDAGToDAGISel::SelectSETCC
The subroutine getCRIdxForSetCC has a parameter "Other" and comment:
If this returns with Other != -1, then the returned comparison
is an or of two simpler comparisons.
However for at least the last five years this routine has never
returned a value of Other != -1; these cases are now handled
differently to begin with.
This patch removes the parameter and the code in SelectSETCC that
attempted to handle the Other != -1 case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185541
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Craig Topper [Wed, 3 Jul 2013 15:07:05 +0000 (15:07 +0000)]
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185540
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Craig Topper [Wed, 3 Jul 2013 14:48:37 +0000 (14:48 +0000)]
Fix regular expression used by 'make update' to only look for 'I' and '?' at the start of svn info results and to check for spaces after 'I' instead of just after '?'.
Previously it was able to match 'I' anywhere in the filenames of the svn info results instead of just files that where ignored or unknown to svn. This would cause 'make update' to infinitely recurse if a file was modified with I anywhere in its name since svn info would return a Path pointing to the llvm root for those files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185539
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Evgeniy Stepanov [Wed, 3 Jul 2013 14:39:14 +0000 (14:39 +0000)]
[msan] Unpoison stack allocations and undef values in blacklisted functions.
This changes behavior of -msan-poison-stack=0 flag from not poisoning stack
allocations to actively unpoisoning them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185538
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Ulrich Weigand [Wed, 3 Jul 2013 12:51:09 +0000 (12:51 +0000)]
[PowerPC] Make specialized AltiVec patterns isCodeGenOnly
A couple of AltiVec patterns are just specialized forms of the
generic instruction pattern, and should therefore be marked
isCodeGenOnly to avoid confusing the asm parser:
VCFSX_0, VCTUXS_0, VCFUX_0, VCTSXS_0, and V_SETALLONES.
Noticed by inspection of the generated PPCGenAsmMatcher.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185533
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Ulrich Weigand [Wed, 3 Jul 2013 12:32:41 +0000 (12:32 +0000)]
[PowerPC] Support mtspr/mfspr in the asm parser
This adds support for the generic forms of mtspr/mfspr
for the asm parser. The compiler will continue to use
the specialized patters for mtlr etc. since those are
needed to correctly describe data flow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185532
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Richard Sandiford [Wed, 3 Jul 2013 10:10:02 +0000 (10:10 +0000)]
[SystemZ] Fold more spills
Add a mapping from register-based <INSN>R instructions to the corresponding
memory-based <INSN>. Use it to cut down on the number of spill loads.
Some instructions extend their operands from smaller fields, so this
required a new TSFlags field to say how big the unextended operand is.
This optimisation doesn't trigger for C(G)R and CL(G)R because in practice
we always combine those instructions with a branch. Adding a test for every
other case probably seems excessive, but it did catch a missed optimisation
for DSGF (fixed in r185435).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185529
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Mihai Popa [Wed, 3 Jul 2013 09:21:44 +0000 (09:21 +0000)]
This corrects the implementation of Thumb ADR instruction. There are three issues:
1. it should accept only 4-byte aligned addresses
2. the maximum offset should be 1020
3. it should be encoded with the offset scaled by two bits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185528
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Tim Northover [Wed, 3 Jul 2013 09:20:36 +0000 (09:20 +0000)]
ARM: relax the atomic release barrier to "dmb ishst" on Swift
Swift cores implement store barriers that are stronger than the ARM
specification but weaker than general barriers. They are, in fact, just about
enough to provide the ordering needed for atomic operations with release
semantics.
This patch makes use of that quirk.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185527
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Richard Sandiford [Wed, 3 Jul 2013 09:19:58 +0000 (09:19 +0000)]
[SystemZ] Rename mapping table fields
Rename Function->DispKey and PairType->DispSize. I'd originally used
"Function" because I thought it might be useful for other InstMappings.
However, it turns out that having two very similar instructions with the
same Function makes it pretty useless for anything other than the displacement
size key. Other InstMappings will want the key to be defined for only one
instruction in the pair.
No behavioural change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185526
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Richard Sandiford [Wed, 3 Jul 2013 09:11:00 +0000 (09:11 +0000)]
[SystemZ] Fix caller-allocated save slot FIXME
Get rid of some old code (and associated FIXME) for handling the
caller-allocated register save area. No behavioural change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185525
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Eric Christopher [Wed, 3 Jul 2013 08:26:07 +0000 (08:26 +0000)]
Remove unused field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185523
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Eric Christopher [Wed, 3 Jul 2013 08:13:55 +0000 (08:13 +0000)]
Constify a few functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185520
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Richard Osborne [Wed, 3 Jul 2013 07:49:03 +0000 (07:49 +0000)]
[XCore] Whitespace fixes, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185519
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Richard Osborne [Wed, 3 Jul 2013 07:48:50 +0000 (07:48 +0000)]
[XCore] Add ISel pattern for LDWCP
Patch by Robert Lytton.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185518
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Craig Topper [Wed, 3 Jul 2013 05:18:47 +0000 (05:18 +0000)]
Use SmallVectorImpl::const_iterator instead of SmallVector to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185514
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Craig Topper [Wed, 3 Jul 2013 05:16:59 +0000 (05:16 +0000)]
Use SmallVectorImpl instead of SmallVector as method argument to avoid specifying vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185513
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Craig Topper [Wed, 3 Jul 2013 05:11:49 +0000 (05:11 +0000)]
Use SmallVectorImpl instead of SmallVector for iterators and references to avoid specifying the vector size unnecessarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185512
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Eric Christopher [Wed, 3 Jul 2013 05:01:24 +0000 (05:01 +0000)]
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector
to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185511
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Craig Topper [Wed, 3 Jul 2013 04:42:33 +0000 (04:42 +0000)]
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185509
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Craig Topper [Wed, 3 Jul 2013 04:40:27 +0000 (04:40 +0000)]
Introduce some typedefs for DenseMaps containing SmallVectors so the vector size doesn't have to repeated when creating iterators for the DenseMap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185508
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Craig Topper [Wed, 3 Jul 2013 04:30:58 +0000 (04:30 +0000)]
Return SmallVectorImpl& instead of SmallVector& in a couple places to avoid having to specify the vector size in multiple places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185507
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Craig Topper [Wed, 3 Jul 2013 04:27:31 +0000 (04:27 +0000)]
Add a space between type and variable name. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185506
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Craig Topper [Wed, 3 Jul 2013 04:24:43 +0000 (04:24 +0000)]
Use SmallVectorImpl& instead of SmallVector& to avoid needlessly respecifying the small vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185505
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Craig Topper [Wed, 3 Jul 2013 04:17:25 +0000 (04:17 +0000)]
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185504
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Michael Gottesman [Wed, 3 Jul 2013 04:15:22 +0000 (04:15 +0000)]
Change the gettimeofday test to only test on a posix platform.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185503
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Michael Gottesman [Wed, 3 Jul 2013 04:00:54 +0000 (04:00 +0000)]
Added support in FunctionAttrs for adding relevant function/argument attributes for the posix call gettimeofday.
This implies annotating it as nounwind and its arguments as nocapture. To be
conservative, we do not annotate the arguments with noalias since some platforms
do not have restrict on the declaration for gettimeofday.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185502
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Michael Gottesman [Wed, 3 Jul 2013 04:00:51 +0000 (04:00 +0000)]
Added posix function gettimeofday to LibFunc::Func for all platforms but Windows.
*NOTE* In a recent version of posix, they added the restrict keyword to the
arguments for this function. From some spelunking it seems that on some
platforms, the call has restrict on its arguments and others it does not. Thus I
left off the restrict keyword from the function prototype in the comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185501
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Eric Christopher [Wed, 3 Jul 2013 02:23:53 +0000 (02:23 +0000)]
Avoid doing a lot of computation when we have multiple ranges and
avoid adding information for the debug_inlined section when it isn't
going to be emitted anyhow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185500
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NAKAMURA Takumi [Wed, 3 Jul 2013 02:20:49 +0000 (02:20 +0000)]
SystemZInstrInfo.cpp: Tweak an assertion. [-Wunused-variable]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185499
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Eric Christopher [Wed, 3 Jul 2013 01:57:28 +0000 (01:57 +0000)]
Move iterator to where it's used and update comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185498
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Eric Christopher [Wed, 3 Jul 2013 01:57:26 +0000 (01:57 +0000)]
Move instance variable before experimental section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185497
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Eric Christopher [Wed, 3 Jul 2013 01:57:23 +0000 (01:57 +0000)]
Fix typo to make grep for DW_AT_comp_dir work without case-insensitive
grep.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185496
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Eric Christopher [Wed, 3 Jul 2013 01:57:20 +0000 (01:57 +0000)]
Remove unnecessary forward declare.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185495
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Eric Christopher [Wed, 3 Jul 2013 01:22:29 +0000 (01:22 +0000)]
Add a helpful comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185492
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Eric Christopher [Wed, 3 Jul 2013 01:08:30 +0000 (01:08 +0000)]
addConstantValue, addConstantFPValue never returned anything but
true, so remove the return value and propagate accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185490
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Manman Ren [Wed, 3 Jul 2013 00:16:11 +0000 (00:16 +0000)]
Trying to fix the bots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185489
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Manman Ren [Tue, 2 Jul 2013 23:40:10 +0000 (23:40 +0000)]
Debug Info: use module flag to set up Dwarf version.
Correctly handles ref_addr depending on the Dwarf version. Emit Dwarf with
version from module flag.
TODO: turn on/off features depending on the Dwarf version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185484
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Eric Christopher [Tue, 2 Jul 2013 21:36:07 +0000 (21:36 +0000)]
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185480
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Michael Gottesman [Tue, 2 Jul 2013 21:32:56 +0000 (21:32 +0000)]
Fixed typo in LangRef where we were using _'' to quote instead of the correct _.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185479
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Ulrich Weigand [Tue, 2 Jul 2013 21:31:59 +0000 (21:31 +0000)]
[PowerPC] PR16512 - Support TLS call sequences in the asm parser
This patch now adds support for recognizing TLS call sequences in
the asm parser. This needs a new pattern BL8_TLS, which is like
BL8_NOP_TLS except without nop. That pattern is used for the
asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185478
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Ulrich Weigand [Tue, 2 Jul 2013 21:31:04 +0000 (21:31 +0000)]
[PowerPC] Rework TLS call operand processing
As part of the global-dynamic and local-dynamic TLS sequences, we need
to use a special form of the call instruction:
bl __tls_get_addr(sym@tlsld)
bl __tls_get_addr(sym@tlsgd)
which generates two fixups. The current implementation of this causes
problems with recognizing this form in the asm parser. To fix this,
this patch reworks operand processing for this special form by using
a single operand to hold both __tls_get_addr and sym@tlsld and defining
a print method to output the above form, and an encoding method to
generate the two fixups.
As a side simplification, the patch replaces the two instruction
patterns BL8_NOP_TLSGD and BL8_NOP_TLSLD by a single BL8_NOP_TLS,
since the patterns already operate in an identical fashion (whether
we have a local-dynamic or global-dynamic symbol is already encoded
in the symbol modifier).
No change in code generation intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185477
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Ulrich Weigand [Tue, 2 Jul 2013 21:29:06 +0000 (21:29 +0000)]
[PowerPC] Remove VK_PPC_TLSGD and VK_PPC_TLSLD
The PowerPC-specific modifiers VK_PPC_TLSGD and VK_PPC_TLSLD
correspond exactly to the generic modifiers VK_TLSGD and VK_TLSLD.
This causes some confusion with the asm parser, since VK_PPC_TLSGD
is output as @tlsgd, which is then read back in as VK_TLSGD.
To avoid this confusion, this patch removes the PowerPC-specific
modifiers and uses the generic modifiers throughout. (The only
drawback is that the generic modifiers are printed in upper case
while the usual convention on PowerPC is to use lower-case modifiers.
But this is just a cosmetic issue.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185476
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Benjamin Kramer [Tue, 2 Jul 2013 21:17:31 +0000 (21:17 +0000)]
SystemZ: Fold variable into assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185475
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Jyotsna Verma [Tue, 2 Jul 2013 19:21:43 +0000 (19:21 +0000)]
Add 'REQUIRES: object-emission' to DebugInfo/inlined-arguments.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185465
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Ulrich Weigand [Tue, 2 Jul 2013 18:47:35 +0000 (18:47 +0000)]
[PowerPC] Support TLS variables in debug info
This adds an implementation of getDebugThreadLocalSymbol for
(64-bit) PowerPC. This needs to return a generic MCExpr
since on ppc64, we need to add a bias of 0x8000 to the
value returned by the R_PPC64_DTPREL64 relocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185461
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Ulrich Weigand [Tue, 2 Jul 2013 18:47:09 +0000 (18:47 +0000)]
[DebugInfo] Allow getDebugThreadLocalSymbol to return MCExpr
This allows getDebugThreadLocalSymbol to return a generic MCExpr
instead of just a MCSymbolRefExpr.
This is in preparation for supporting debug info for TLS variables
on PowerPC, where we need to describe the variable location using
a more complex expression than just MCSymbolRefExpr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185460
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Ulrich Weigand [Tue, 2 Jul 2013 18:46:46 +0000 (18:46 +0000)]
[DebugInfo] Hold generic MCExpr in AddrPool
This changes the AddrPool infrastructure to enable it to hold
generic MCExpr expressions, not just MCSymbolRefExpr.
This is in preparation for supporting debug info for TLS variables
on PowerPC, where we need to describe the variable location using
a more complex expression than just MCSymbolRefExpr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185459
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Ulrich Weigand [Tue, 2 Jul 2013 18:46:26 +0000 (18:46 +0000)]
[DebugInfo] Introduce DIEExpr variant of DIEValue to hold MCExpr values
This partially reverts r185202 and restores DIELabel to hold plain
MCSymbol references. Instead, we add a new subclass DIEExpr of
DIEValue that can hold generic MCExpr references.
This is in preparation for supporting debug info for TLS variables
on PowerPC, where we need to describe the variable location using
a more complex expression than just MCSymbolRefExpr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185458
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Manman Ren [Tue, 2 Jul 2013 18:37:35 +0000 (18:37 +0000)]
Debug Info: cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185456
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Jakob Stoklund Olesen [Tue, 2 Jul 2013 17:31:58 +0000 (17:31 +0000)]
Revert (most of) r185393 and r185395.
"Remove floating point computations form SpillPlacement.cpp."
These commits caused test failures in lencod on clang-native-arm-lnt.
I suspect these changes are only exposing an existing issue, but
reverting anyway to keep the bots passing while we investigate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185447
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Benjamin Kramer [Tue, 2 Jul 2013 17:24:00 +0000 (17:24 +0000)]
Hexagon: Avoid unused variable warnings in Release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185445
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David Blaikie [Tue, 2 Jul 2013 16:48:10 +0000 (16:48 +0000)]
Fix -Wsign-compare warning and remove windows-style line endings introduced by r185421
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185443
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Michael Gottesman [Tue, 2 Jul 2013 15:50:05 +0000 (15:50 +0000)]
[APFloat] Swap an early out check so we do not dereference str.end().
Originally if D.firstSigDigit == str.end(), we will have already dereferenced
D.firstSigDigit in the first predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185437
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Rafael Espindola [Tue, 2 Jul 2013 15:49:13 +0000 (15:49 +0000)]
Remove address spaces from MC.
This is dead code since PIC16 was removed in 2010. The result was an odd mix,
where some parts would carefully pass it along and others would assert it was
zero (most of the object streamer for example).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185436
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Richard Sandiford [Tue, 2 Jul 2013 15:40:22 +0000 (15:40 +0000)]
[SystemZ] Use DSGFR over DSGR in more cases
Fixes some cases where we were using full 64-bit division for (sdiv i32, i32)
and (sdiv i64, i32).
The "32" in "SDIVREM32" just refers to the second operand. The first operand
of all *DIVREM*s is a GR128.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185435
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Richard Sandiford [Tue, 2 Jul 2013 15:28:56 +0000 (15:28 +0000)]
[SystemZ] Use MVC to spill loads and stores
Try to use MVC when spilling the destination of a simple load or the source
of a simple store. As explained in the comment, this doesn't yet handle
the case where the load or store location is also a frame index, since
that could lead to two simultaneous scavenger spills, something the
backend can't handle yet. spill-02.py tests that this restriction kicks in,
but unfortunately I've not yet found a case that would fail without it.
The volatile trick I used for other scavenger tests doesn't work here
because we can't use MVC for volatile accesses anyway.
I'm planning on relaxing the restriction later, hopefully with a test
that does trigger the problem...
Tests @f8 and @f9 also showed that L(G)RL and ST(G)RL were wrongly
classified as SimpleBDX{Load,Store}. It wouldn't be easy to test for
that bug separately, which is why I didn't split out the fix as a
separate patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185434
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Richard Sandiford [Tue, 2 Jul 2013 14:56:45 +0000 (14:56 +0000)]
[SystemZ] Add the MVC instruction
This is the first use of D(L,B) addressing, which required a fair bit
of surgery. For that reason, the patch just adds the instruction
definition and the associated assembler and disassembler support.
A later patch will actually make use of it for codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185433
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Richard Osborne [Tue, 2 Jul 2013 14:46:34 +0000 (14:46 +0000)]
[XCore] Fix instruction selection for zext, mkmsk instructions.
r182680 replaced CountLeadingZeros_32 with a template function
countLeadingZeros that relies on using the correct argument type to give
the right result. The type passed in the XCore backend after this
revision was incorrect in a couple of places.
Patch by Robert Lytton.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185430
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Logan Chien [Tue, 2 Jul 2013 12:43:27 +0000 (12:43 +0000)]
Fix ARM EHABI compact model 1 and 2 without handlerdata.
According to ARM EHABI section 9.2, if the
__aeabi_unwind_cpp_pr1() or __aeabi_unwind_cpp_pr2() is
used, then the handler data must be emitted after the unwind
opcodes. The handler data consists of several words, and
should be terminated by zero.
In case that the .handlerdata directive is not specified by
the programmer, we should emit zero to terminate the handler
data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185422
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Elena Demikhovsky [Tue, 2 Jul 2013 12:24:22 +0000 (12:24 +0000)]
Fixed alignment of code sections in the JIT mode. Added a test to the JITMemoryManager.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185421
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Tim Northover [Tue, 2 Jul 2013 09:58:53 +0000 (09:58 +0000)]
DAGCombiner: fix use-counting issue when forming zextload
DAGCombiner was counting all uses of a load node when considering whether it's
worth combining into a zextload. Really, it wants to ignore the chain and just
count real uses.
rdar://problem/
13896307
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185419
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Hal Finkel [Tue, 2 Jul 2013 05:21:11 +0000 (05:21 +0000)]
Revert r185257 (InstCombine: Be more agressive optimizing 'udiv' instrs with 'select' denoms)
I'm reverting this commit because:
1. As discussed during review, it needs to be rewritten (to avoid creating and
then deleting instructions).
2. This is causing optimizer crashes. Specifically, I'm seeing things like
this:
While deleting: i1 %
Use still stuck around after Def is destroyed: <badref> = select i1 <badref>, i32 0, i32 1
opt: /src/llvm-trunk/lib/IR/Value.cpp:79: virtual llvm::Value::~Value(): Assertion `use_empty() && "Uses remain when a value is destroyed!"' failed.
I'd guess that these will go away once we're no longer creating/deleting
instructions here, but just in case, I'm adding a regression test.
Because the code is bring rewritten, I've just XFAIL'd the original regression test. Original commit message:
InstCombine: Be more agressive optimizing 'udiv' instrs with 'select' denoms
Real world code sometimes has the denominator of a 'udiv' be a
'select'. LLVM can handle such cases but only when the 'select'
operands are symmetric in structure (both select operands are a constant
power of two or a left shift, etc.). This falls apart if we are dealt a
'udiv' where the code is not symetric or if the select operands lead us
to more select instructions.
Instead, we should treat the LHS and each select operand as a distinct
divide operation and try to optimize them independently. If we can
to simplify each operation, then we can replace the 'udiv' with, say, a
'lshr' that has a new select with a bunch of new operands for the
select.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185415
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Nick Lewycky [Tue, 2 Jul 2013 05:02:56 +0000 (05:02 +0000)]
Add missing break statements. Noticed by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185414
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Tobias Grosser [Tue, 2 Jul 2013 04:15:28 +0000 (04:15 +0000)]
Fix typo in comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185413
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Hal Finkel [Tue, 2 Jul 2013 03:39:34 +0000 (03:39 +0000)]
Cleanup PPC Altivec registers in CSR lists and improve VRSAVE handling
There are a couple of (small) related changes here:
1. The printed name of the VRSAVE register has been changed from VRsave to
vrsave in order to match the name accepted by GNU binutils.
2. Support for parsing vrsave has been added to the asm parser (it seems that
there was no test case specifically covering this code, so I've added one).
3. The list of Altivec registers, which was common to all calling conventions,
has been separated out. This allows us to define the base CSR lists, and then
lists for each ABI with Altivec included. This allows SjLj, for example, to
work correctly on non-Altivec targets without using unnatural definitions of
the NoRegs CSR list.
4. VRSAVE is now always reserved on non-Darwin targets and all Altivec
registers are reserved when Altivec is disabled.
With these changes, it is now possible to compile a function containing
__builtin_unwind_init() on Linux/PPC64 with debugging information. This did not
work previously because GNU binutils assumes that all .cfi_offset offsets will
be 8-byte aligned on PPC64 (and errors out if you provide a non-8-byte-aligned
offset). This is not true for the vrsave register, however, because this
register is used only on Darwin, GCC does not bother printing a .cfi_offset
entry for it (even though there is a slot in the stack frame for it as
specified by the ABI). This change allows us to do the same: we will also not
print .cfi_offset directives for vrsave.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185409
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Tobias Grosser [Tue, 2 Jul 2013 03:28:10 +0000 (03:28 +0000)]
IRVerifier: Correctly check attribute types
Add missing parenthesis such that all and not only the very first attribute
is checked.
Testing this piece of code is not possible with an LLVM-IR test file, as the
LLVM-IR parser has a similar check such that the wrong IR does not even arrive
at the verifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185408
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Akira Hatanaka [Tue, 2 Jul 2013 00:00:02 +0000 (00:00 +0000)]
[mips] Add new InstrItinClasses for move from/to coprocessor instructions and
floating point loads and stores.
No changes in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185399
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David Blaikie [Mon, 1 Jul 2013 23:55:52 +0000 (23:55 +0000)]
PR14728: DebugInfo: TLS variables with -gsplit-dwarf
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185398
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Michael Gottesman [Mon, 1 Jul 2013 23:54:08 +0000 (23:54 +0000)]
[APFloat] Ensure that we can properly parse strings that do not have null terminators.
rdar://
14323230
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185397
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Richard Trieu [Mon, 1 Jul 2013 23:42:53 +0000 (23:42 +0000)]
Fix up some asserts that are within an if statement. This removes the need
for assert(0 && "text").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185396
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Jakob Stoklund Olesen [Mon, 1 Jul 2013 23:36:37 +0000 (23:36 +0000)]
Tweak some comments that referred to the old bias computations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185395
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Ulrich Weigand [Mon, 1 Jul 2013 23:33:29 +0000 (23:33 +0000)]
[PowerPC] Add support for TLS data relocations
This adds support for TLS data relocations and modifiers:
.quad target@dtpmod
.quad target@tprel
.quad target@dtprel
Currently exploited by the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185394
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Jakob Stoklund Olesen [Mon, 1 Jul 2013 23:19:39 +0000 (23:19 +0000)]
Remove floating point computations form SpillPlacement.cpp.
Patch by Benjamin Kramer!
Use the BlockFrequency class instead of floats in the Hopfield network
computations. This rescales the node Bias field from a [-2;2] float
range to two block frequencies BiasN and BiasP pulling in opposite
directions. This construct has a more predictable behavior when block
frequencies saturate.
The per-node scaling factors are no longer necessary, assuming the block
frequencies around a bundle are consistent.
This patch can cause the register allocator to make different spilling
decisions. The differences should be small.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185393
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Richard Trieu [Mon, 1 Jul 2013 23:06:23 +0000 (23:06 +0000)]
Change if (cond) ... else llvm_unreachable("text") to assert(cond && "text") ...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185392
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Ulrich Weigand [Mon, 1 Jul 2013 22:27:57 +0000 (22:27 +0000)]
[PowerPC] Fix 32-bit PowerPC TLS relocs
Some TLS relocs were copied incorrectly from ppc64 to ppc32,
and some were missing completely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185390
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David Blaikie [Mon, 1 Jul 2013 21:45:25 +0000 (21:45 +0000)]
PR16493: DebugInfo with TLS on PPC crashing due to invalid relocation
Restrict the current TLS support to X86 ELF for now. Test that we don't
produce it on PPC & we can flesh that test case out with the right thing
once someone implements it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185389
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Ulrich Weigand [Mon, 1 Jul 2013 21:40:54 +0000 (21:40 +0000)]
[PowerPC] Support all condition register logical instructions
This adds support for all missing condition register logical
instructions and extended mnemonics to the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185387
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Chad Rosier [Mon, 1 Jul 2013 21:31:10 +0000 (21:31 +0000)]
Add a newline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185385
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Manman Ren [Mon, 1 Jul 2013 21:02:01 +0000 (21:02 +0000)]
Debug Info: clean up usage of Verify.
No functionality change. It should suffice to check the type of a debug info
metadata, instead of calling Verify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185383
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Bill Schmidt [Mon, 1 Jul 2013 20:52:27 +0000 (20:52 +0000)]
Index: test/CodeGen/PowerPC/reloc-align.ll
===================================================================
--- test/CodeGen/PowerPC/reloc-align.ll (revision 0)
+++ test/CodeGen/PowerPC/reloc-align.ll (revision 0)
@@ -0,0 +1,34 @@
+; RUN: llc -mcpu=pwr7 -O1 < %s | FileCheck %s
+
+; This test verifies that the peephole optimization of address accesses
+; does not produce a load or store with a relocation that can't be
+; satisfied for a given instruction encoding. Reduced from a test supplied
+; by Hal Finkel.
+
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+%struct.S1 = type { [8 x i8] }
+
+@main.l_1554 = internal global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 -1, i8 -6, i8 57, i8 62, i8 -48, i8 0, i8 58, i8 80 }, align 1
+
+; Function Attrs: nounwind readonly
+define signext i32 @main() #0 {
+entry:
+ %call = tail call fastcc signext i32 @func_90(%struct.S1* byval bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @main.l_1554 to %struct.S1*))
+; CHECK-NOT: ld {{[0-9]+}}, main.l_1554@toc@l
+ ret i32 %call
+}
+
+; Function Attrs: nounwind readonly
+define internal fastcc signext i32 @func_90(%struct.S1* byval nocapture %p_91) #0 {
+entry:
+ %0 = bitcast %struct.S1* %p_91 to i64*
+ %bf.load = load i64* %0, align 1
+ %bf.shl = shl i64 %bf.load, 26
+ %bf.ashr = ashr i64 %bf.shl, 54
+ %bf.cast = trunc i64 %bf.ashr to i32
+ ret i32 %bf.cast
+}
+
+attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
Index: lib/Target/PowerPC/PPCAsmPrinter.cpp
===================================================================
--- lib/Target/PowerPC/PPCAsmPrinter.cpp (revision 185327)
+++ lib/Target/PowerPC/PPCAsmPrinter.cpp (working copy)
@@ -679,7 +679,26 @@ void PPCAsmPrinter::EmitInstruction(const MachineI
OutStreamer.EmitRawText(StringRef("\tmsync"));
return;
}
+ break;
+ case PPC::LD:
+ case PPC::STD:
+ case PPC::LWA: {
+ // Verify alignment is legal, so we don't create relocations
+ // that can't be supported.
+ // FIXME: This test is currently disabled for Darwin. The test
+ // suite shows a handful of test cases that fail this check for
+ // Darwin. Those need to be investigated before this sanity test
+ // can be enabled for those subtargets.
+ if (!Subtarget.isDarwin()) {
+ unsigned OpNum = (MI->getOpcode() == PPC::STD) ? 2 : 1;
+ const MachineOperand &MO = MI->getOperand(OpNum);
+ if (MO.isGlobal() && MO.getGlobal()->getAlignment() < 4)
+ llvm_unreachable("Global must be word-aligned for LD, STD, LWA!");
+ }
+ // Now process the instruction normally.
+ break;
}
+ }
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this);
OutStreamer.EmitInstruction(TmpInst);
Index: lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelDAGToDAG.cpp (revision 185327)
+++ lib/Target/PowerPC/PPCISelDAGToDAG.cpp (working copy)
@@ -1530,6 +1530,14 @@ void PPCDAGToDAGISel::PostprocessISelDAG() {
if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
SDLoc dl(GA);
const GlobalValue *GV = GA->getGlobal();
+ // We can't perform this optimization for data whose alignment
+ // is insufficient for the instruction encoding.
+ if (GV->getAlignment() < 4 &&
+ (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD ||
+ StorageOpcode == PPC::LWA)) {
+ DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n");
+ continue;
+ }
ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags);
} else if (ConstantPoolSDNode *CP =
dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185380
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Chad Rosier [Mon, 1 Jul 2013 20:49:23 +0000 (20:49 +0000)]
[ARMAsmParser] Sort the ARM register lists based on the encoding value, not the
tablegen enum values. This should be the last fix due to fallout from r185094.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185379
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Lang Hames [Mon, 1 Jul 2013 20:47:47 +0000 (20:47 +0000)]
Make PBQP require/preserve MachineLoopInfo - the spiller requires it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185378
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Sean Silva [Mon, 1 Jul 2013 20:45:12 +0000 (20:45 +0000)]
[docs] Amend confusing title
"Writing an LLVM Compiler Backend" can be misinterpreted as meaning
"backend" in the sense of "using LLVM as a backend for your compiler for
your new language". This new name is less ambiguous.
As a bonus, this brings the title in line with the file name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185377
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Akira Hatanaka [Mon, 1 Jul 2013 20:39:53 +0000 (20:39 +0000)]
[mips] Reverse the order of source operands of shift and rotate instructions that
have three register operands.
No intended functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185376
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Ulrich Weigand [Mon, 1 Jul 2013 20:39:50 +0000 (20:39 +0000)]
[PowerPC] Also add "msync" alias
This adds an alias for "msync" (which is used on Book E
systems instead of "sync").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185375
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Akira Hatanaka [Mon, 1 Jul 2013 20:31:44 +0000 (20:31 +0000)]
[mips] Increase the number of floating point control registers available to 32.
Create a dedicated register class for floating point condition code registers and
move FCC0 from register class CCR to the new register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185373
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