OSDN Git Service
Jake Ehrlich [Thu, 25 Jan 2018 22:15:14 +0000 (22:15 +0000)]
[llvm-objcopy] Add --add-gnu-debuglink
This change adds support for --add-gnu-debuglink to llvm-objcopy
Differential Revision: https://reviews.llvm.org/D41731
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323477
91177308-0d34-0410-b5e6-
96231b3b80d8
Paul Robinson [Thu, 25 Jan 2018 22:02:36 +0000 (22:02 +0000)]
[DWARFv5] Support DW_FORM_line_strp in llvm-dwarfdump.
This form is like DW_FORM_strp, but points to .debug_line_str instead
of .debug_str as the string section. It's intended to be used from
the line-table header, and allows string-pooling of directory and
filenames across compilation units.
Differential Revision: https://reviews.llvm.org/D42553
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323476
91177308-0d34-0410-b5e6-
96231b3b80d8
Easwaran Raman [Thu, 25 Jan 2018 22:02:29 +0000 (22:02 +0000)]
[SyntheticCounts] Rewrite the code using only graph traits.
Summary:
The intent of this is to allow the code to be used with ThinLTO. In
Thinlink phase, a traditional Callgraph can not be computed even though
all the necessary information (nodes and edges of a call graph) is
available. This is due to the fact that CallGraph class is closely tied
to the IR. This patch first extends GraphTraits to add a CallGraphTraits
graph. This is then used to implement a version of counts propagation
on a generic callgraph.
Reviewers: davidxl
Subscribers: mehdi_amini, tejohnson, llvm-commits
Differential Revision: https://reviews.llvm.org/D42311
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323475
91177308-0d34-0410-b5e6-
96231b3b80d8
Joel Jones [Thu, 25 Jan 2018 21:55:39 +0000 (21:55 +0000)]
[AArch64] Enable aggressive FMA on T99 and provide AArch64 options for others.
This patch enables aggressive FMA by default on T99, and provides a -mllvm
option to enable the same on other AArch64 micro-arch's (-mllvm
-aarch64-enable-aggressive-fma).
Test case demonstrating the effects on T99 is included.
Patch by: steleman (Stefan Teleman)
Differential Revision: https://reviews.llvm.org/D40696
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323474
91177308-0d34-0410-b5e6-
96231b3b80d8
Vedant Kumar [Thu, 25 Jan 2018 21:37:07 +0000 (21:37 +0000)]
[Debug] Add dbg.value intrinsics for PHIs created during LCSSA.
This patch is an enhancement to propagate dbg.value information when
Phis are created on behalf of LCSSA. I noticed a case where a value
carried across a loop was reported as <optimized out>.
Specifically this case:
int bar(int x, int y) {
return x + y;
}
int foo(int size) {
int val = 0;
for (int i = 0; i < size; ++i) {
val = bar(val, i); // Both val and i are correct
}
return val; // <optimized out>
}
In the above case, after all of the interesting computation completes
our value is reported as "optimized out." This change will add a
dbg.value to correct this.
This patch also moves the dbg.value insertion routine from
LoopRotation.cpp into Local.cpp, so that we can share it in both places
(LoopRotation and LCSSA).
Patch by Matt Davis!
Differential Revision: https://reviews.llvm.org/D42551
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323472
91177308-0d34-0410-b5e6-
96231b3b80d8
Vedant Kumar [Thu, 25 Jan 2018 21:37:05 +0000 (21:37 +0000)]
[Debug] Add a utility to propagate dbg.value to new PHIs, NFC
This simply moves an existing utility to Utils for reuse.
Split out of: https://reviews.llvm.org/D42551
Patch by Matt Davis!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323471
91177308-0d34-0410-b5e6-
96231b3b80d8
Evgeniy Stepanov [Thu, 25 Jan 2018 21:28:51 +0000 (21:28 +0000)]
[asan] Fix kernel callback naming in instrumentation module.
Right now clang uses "_n" suffix for some user space callbacks and "N" for the matching kernel ones. There's no need for this and it actually breaks kernel build with inline instrumentation. Use the same callback names for user space and the kernel (and also make them consistent with the names GCC uses).
Patch by Andrey Konovalov.
Differential Revision: https://reviews.llvm.org/D42423
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323470
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 25 Jan 2018 21:23:57 +0000 (21:23 +0000)]
[X86] Teach Intel syntax InstPrinter to print lock prefixes that have been parsed from the asm parser.
The asm parser puts the lock prefix in the MCInst flags so we need to check that in addition to TSFlags. This matches what the ATT printer does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323469
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 25 Jan 2018 21:23:51 +0000 (21:23 +0000)]
[X86] Combine two unnecessarily complicated ifs that had the same body. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323468
91177308-0d34-0410-b5e6-
96231b3b80d8
Aaron Ballman [Thu, 25 Jan 2018 21:08:23 +0000 (21:08 +0000)]
Revert r322132; it appears to be an accidental commit, based on the commit message. The original author of the commit has not commented on whether this was accidental or purposeful, so if this revert is in error, the author can re-commit with an actual commit message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323466
91177308-0d34-0410-b5e6-
96231b3b80d8
Aaron Ballman [Thu, 25 Jan 2018 21:03:38 +0000 (21:03 +0000)]
Reverting r323463 as it appears to be an accidental commit. Regardless, it broke a lot of build bots, so reverting back to green.
http://lab.llvm.org:8011/builders/lldb-amd64-ninja-netbsd8/builds/9294
http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/24084
http://lab.llvm.org:8011/builders/clang-ppc64le-linux-lnt/builds/9567
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323465
91177308-0d34-0410-b5e6-
96231b3b80d8
Jake Ehrlich [Thu, 25 Jan 2018 20:24:17 +0000 (20:24 +0000)]
tmp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323463
91177308-0d34-0410-b5e6-
96231b3b80d8
Easwaran Raman [Thu, 25 Jan 2018 19:27:17 +0000 (19:27 +0000)]
Re-land "[ThinLTO] Add call edges' relative block frequency to per-module summary."
It was reverted after buildbot regressions.
Original commit message:
This allows relative block frequency of call edges to be passed
to the thinlink stage where it will be used to compute synthetic
entry counts of functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323460
91177308-0d34-0410-b5e6-
96231b3b80d8
Shoaib Meenai [Thu, 25 Jan 2018 19:16:46 +0000 (19:16 +0000)]
[CMake] Fix Bug Report URL
It looks like this hasn't been updated since bugzilla moved.
Patch by Colden Cullen.
Differential Revision: https://reviews.llvm.org/D42496
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323457
91177308-0d34-0410-b5e6-
96231b3b80d8
Vedant Kumar [Thu, 25 Jan 2018 18:20:19 +0000 (18:20 +0000)]
Revert "asan: add kernel inline instrumentation test"
This reverts commit r323451. It breaks this bot:
http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/24077
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323454
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Thu, 25 Jan 2018 18:07:27 +0000 (18:07 +0000)]
[Hexagon] SETEQ and SETNE are valid integer condition codes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323452
91177308-0d34-0410-b5e6-
96231b3b80d8
Vedant Kumar [Thu, 25 Jan 2018 18:05:44 +0000 (18:05 +0000)]
asan: add kernel inline instrumentation test
Patch by Andrey Konovalov!
Differential Revision: https://reviews.llvm.org/D42473
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323451
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Thu, 25 Jan 2018 17:28:12 +0000 (17:28 +0000)]
Revert "[SLP] Fix for PR32086: Count InsertElementInstr of the same elements as shuffle."
This reverts commit r323441 to fix buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323447
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Thu, 25 Jan 2018 17:24:22 +0000 (17:24 +0000)]
[ADT] Make moving Optional not reset the Optional it moves from.
This brings it in line with std::optional. My recent changes to
make Optional of trivial types trivially copyable introduced
diverging behavior depending on the type, which is bad. Now all
types have the same moving behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323445
91177308-0d34-0410-b5e6-
96231b3b80d8
George Rimar [Thu, 25 Jan 2018 17:23:27 +0000 (17:23 +0000)]
[LTO] - Introduce GlobalResolution::Prevailing flag.
It is NFC refactoring change that will make
D42107 a bit smaller.
Differential revision: https://reviews.llvm.org/D42528
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323444
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam McCall [Thu, 25 Jan 2018 16:55:48 +0000 (16:55 +0000)]
Give scope_exit helper correct move semantics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323442
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Thu, 25 Jan 2018 16:45:18 +0000 (16:45 +0000)]
[SLP] Fix for PR32086: Count InsertElementInstr of the same elements as shuffle.
Summary:
If the same value is going to be vectorized several times in the same
tree entry, this entry is considered to be a gather entry and cost of
this gather is counter as cost of InsertElementInstrs for each gathered
value. But we can consider these elements as ShuffleInstr with
SK_PermuteSingle shuffle kind.
Reviewers: spatel, RKSimon, mkuper, hfinkel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323441
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 25 Jan 2018 16:38:56 +0000 (16:38 +0000)]
[X86] Apply clang-format to detectUSatPattern. NFCI.
Cleanup from D42544
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323439
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Thu, 25 Jan 2018 16:36:53 +0000 (16:36 +0000)]
Revert "[Hexagon] Replace EmitFunctionEntryCode with a DAG preprocessing code"
This reverts r323374. The fix needs a different approach.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323438
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Thu, 25 Jan 2018 16:34:36 +0000 (16:34 +0000)]
[InstCombine] narrow masked zexted binops (PR35792)
This is guarded by shouldChangeType(), so the tests show that
we don't do the fold if the narrower type is not legal. Note
that there is a proposal (D42424) that would change the results
for the specific cases shown in these tests. That difference is
also discussed in PR35792:
https://bugs.llvm.org/show_bug.cgi?id=35792
Alive proofs for the cases handled here as well as the bitwise
logic binops that we should already do better on:
https://rise4fun.com/Alive/c97
https://rise4fun.com/Alive/Lc5E
https://rise4fun.com/Alive/kdf
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323437
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Thu, 25 Jan 2018 16:03:44 +0000 (16:03 +0000)]
[InstCombine] add tests for PR35792; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323436
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Thu, 25 Jan 2018 15:20:29 +0000 (15:20 +0000)]
Revert "[SLP] Fix for PR32086: Count InsertElementInstr of the same elements as shuffle."
This reverts commit r323430 to fix buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323432
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Thu, 25 Jan 2018 15:01:36 +0000 (15:01 +0000)]
[SLP] Fix for PR32086: Count InsertElementInstr of the same elements as shuffle.
Summary:
If the same value is going to be vectorized several times in the same
tree entry, this entry is considered to be a gather entry and cost of
this gather is counter as cost of InsertElementInstrs for each gathered
value. But we can consider these elements as ShuffleInstr with
SK_PermuteSingle shuffle kind.
Reviewers: spatel, RKSimon, mkuper, hfinkel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323430
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 25 Jan 2018 14:56:21 +0000 (14:56 +0000)]
[X86][SSE] Add tests for vector truncation with signed saturation
AVX512 isn't using X86ISD::VTRUNCS and SSE/AVX isn't using PACKSS/PACKUS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323428
91177308-0d34-0410-b5e6-
96231b3b80d8
Hans Wennborg [Thu, 25 Jan 2018 14:43:10 +0000 (14:43 +0000)]
Update build_llvm_package.bat
I moved to a new machine and had to adjust a few things:
- Use %USERNAME% instead of %USER% (not sure why %USER% didn't work anymore)
- Update paths for using Python 3.6 instead of 3.5
- Skip building OpenMP which seems broken on Windows
- Work around new vsdevcmd.bat changing paths:
https://developercommunity.visualstudio.com/content/problem/26780/vsdevcmdbat-changes-the-current-working-directory.html
- Build stage-0 compiler with MinSizeRel to work around VS 2017 bug:
https://developercommunity.visualstudio.com/content/problem/139043/miscompile-in-trivial-c-program-with-155-preview-2.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323427
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 25 Jan 2018 14:28:55 +0000 (14:28 +0000)]
[X86][SSE] Add tests for vector truncation with unsigned saturation
AVX512 tends to do a good job, but there are some missed opportunities with SSE/AVX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323422
91177308-0d34-0410-b5e6-
96231b3b80d8
Zvi Rackover [Thu, 25 Jan 2018 14:07:33 +0000 (14:07 +0000)]
X86 Tests: Add AVX+XOP config to SDIV combine tests
As pointed out in D42479, XOP also needs to be covered as it supports
vector shifts with variable shift amount.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323418
91177308-0d34-0410-b5e6-
96231b3b80d8
Amjad Aboud [Thu, 25 Jan 2018 12:06:32 +0000 (12:06 +0000)]
Another try to commit 323321 (aggressive instruction combine).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323416
91177308-0d34-0410-b5e6-
96231b3b80d8
George Rimar [Thu, 25 Jan 2018 11:45:02 +0000 (11:45 +0000)]
[LTO] - Get rid of friend 'computeDeadSymbols'. NFC.
computeDeadSymbols accessed isLive() which was not public
before. It does not make much sence to keep isLive() private
because flags are available via flags() public member anyways.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323415
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Devlieghere [Thu, 25 Jan 2018 11:19:08 +0000 (11:19 +0000)]
[Dwarf] Add dsymutil Atom extensions. NFC
This patch extends the atom types used by the Apple accelerator tables
with two dsymutil extensions:
- DW_ATOM_type_type_flags
- DW_ATOM_qual_name_hash
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323414
91177308-0d34-0410-b5e6-
96231b3b80d8
Mikael Holmen [Thu, 25 Jan 2018 10:09:26 +0000 (10:09 +0000)]
[GlobalOpt] Emit fragments using field offsets from struct layout
Summary:
When creating the debug fragments for a SRA'd struct, use the fields'
offsets, taken from the struct layout, as the offsets for the resulting
fragments. This fixes an issue where GlobalOpt would emit fragments with
incorrect offsets for padded fields.
This should solve PR36016.
Patch by David Stenberg.
Reviewers: aprantl
Reviewed By: aprantl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42489
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323411
91177308-0d34-0410-b5e6-
96231b3b80d8
Igor Laevsky [Thu, 25 Jan 2018 09:22:18 +0000 (09:22 +0000)]
[FuzzMutate] Inst deleter doesn't work with PhiNodes
Differential Revision: https://reviews.llvm.org/D42412
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323409
91177308-0d34-0410-b5e6-
96231b3b80d8
Eugene Leviant [Thu, 25 Jan 2018 08:35:52 +0000 (08:35 +0000)]
[IRMover] Add comment and fix test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323407
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 25 Jan 2018 06:57:42 +0000 (06:57 +0000)]
[X86] Expand IMUL/MUL instregexs in Intel scheduler models. Add load latency to some of them in SkylakeClient model.
The regular expressions and the imul names caused some instructions to be matched by multiple regexs creating unpredictable results.
This changes them all to use explicit instrs instead.
While doing this I also found that some instructions in Skylake were missing load latency so I fixed that too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323406
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 25 Jan 2018 06:57:39 +0000 (06:57 +0000)]
[X86] Expand IMUL/MUL instregexs in Znver1 scheduler to show what's actually implemented.
The IMUL instruction names mixed with the prefix matching of the instregex lead to some strange matches. The worst being that several memory instructions are using the register form latency.
I don't know what the right answer is, so I've left TODOs and will try to work with the AMD folks to get this cleaned up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323405
91177308-0d34-0410-b5e6-
96231b3b80d8
Don Hinton [Thu, 25 Jan 2018 04:55:18 +0000 (04:55 +0000)]
[cmake] Set cmake policy CMP0068 to suppress warnings on OSX
Set cmake policy CMP0068=NEW, if available, and set
"CMAKE_BUILD_WITH_INSTALL_NAME_DIR=On" globally to
maintain current behavior.
This is needed to suppress warnings on OSX starting with cmake version
3.9.6.
Differential Revision: https://reviews.llvm.org/D42463
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323404
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 25 Jan 2018 04:45:32 +0000 (04:45 +0000)]
[X86] Name the MMX phaddd instruction with 3 Ds instead of just 2. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323403
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 25 Jan 2018 04:45:30 +0000 (04:45 +0000)]
[X86] Remove 64/128/256 from MMX/SSE/AVX instruction names for overall consistency. NFC
MMX instrutions all start with MMX_ so the 64 isn't needed for disambigutation.
SSE/AVX1 instructions are assumed 128-bit so we don't need to say 128.
AVX2 instructions should use a Y to indicate 256-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323402
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 25 Jan 2018 04:45:28 +0000 (04:45 +0000)]
[X86] Remove unnecessary '_alt' and '_Int' from scheduler model regular expressions.
These were treated as optional suffixes, but the regular expressions are already prefix matches so this is unnecessary. It breaks the binary search optimization in tablegen due to the top level question mark.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323401
91177308-0d34-0410-b5e6-
96231b3b80d8
Aditya Nandakumar [Thu, 25 Jan 2018 02:53:06 +0000 (02:53 +0000)]
Add support for pattern matching MachineInsts.
https://reviews.llvm.org/D42439
Add Instcombine like matchers for MachineInstructions. There are only
globalISel matchers for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323400
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Thu, 25 Jan 2018 01:43:00 +0000 (01:43 +0000)]
[ORC] Refactor the various lookupFlags methods to return the flags map via the
first argument.
This makes lookupFlags more consistent with lookup (which takes the query as the
first argument) and composes better in practice, since lookups are usually
linearly chained: Each lookupFlags can populate the result map based on the
symbols not found in the previous lookup. (If the maps were returned rather than
passed by reference there would have to be a merge step at the end).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323398
91177308-0d34-0410-b5e6-
96231b3b80d8
Aditya Nandakumar [Thu, 25 Jan 2018 01:16:14 +0000 (01:16 +0000)]
[GISel]: Fix modules build by including <cassert>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323394
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Thu, 25 Jan 2018 01:05:29 +0000 (01:05 +0000)]
[ORC] Try to silence compiler error at
http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/17264
NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323393
91177308-0d34-0410-b5e6-
96231b3b80d8
Aditya Nandakumar [Thu, 25 Jan 2018 00:41:58 +0000 (00:41 +0000)]
[GISel]: Implement GlobalISel combiner API.
https://reviews.llvm.org/D41373
The various components are
GICombinerHelper contains transformations that are common to all
targets. Targets can pick and choose which transformations (at
function/opcode granularity) each pass uses via configuring a
GICombinerInfo.
GICombiner contains some common code and it does the traversal,
driving of combines, worklist management and iterating until
convergence.
GICombinerInfo is an interface with a virtual method called combine.
The combiner info will allow targets to pick and choose (or
implement their own specific combines). CombineInfos can make
use of available combines in GICombineHelper to configure the
transformations for a particular pass. Currently this approach allows
cherry picking transformations from helpers (at function/opcode
granularity) and also allows early returning on specific
transformations. Targets also get to prioritize whether target specific
combines run before/after the opt-in generic combines. Ideally we would
like this part to be configured by both C++ and Tablegen. The
CombinerInfo also has a field which indicates how to deal with
IllegalOps (ie - should we allow to create them/or legalize them?).
A CombinerPass would configure a CombinerInfo, create the GICombiner
with the Info, and call
GICombiner::combineMachineInstrs(MachineFunction&).
This organization is very similar to the GISelLegalizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323392
91177308-0d34-0410-b5e6-
96231b3b80d8
Volkan Keles [Thu, 25 Jan 2018 00:18:52 +0000 (00:18 +0000)]
[GlobalISel][TableGen] Fix the statistics for emitted patters
Collected statistics for the number of patterns emitted can be
incorrect because rules can be grouped if OptimizeMatchTable
is enabled. Increase the counter in RuleMatcher::emit(...)
to avoid that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323391
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Wed, 24 Jan 2018 23:09:07 +0000 (23:09 +0000)]
[ORC] Add helpers for building orc::SymbolResolvers from legacy findSymbol-style
functions/methods that return JITSymbols.
lookupFlagsWithLegacyFn takes a SymbolNameSet and a legacy lookup function and
returns a LookupFlagsResult. It uses the legacy lookup function to search for
each symbol. If found, getFlags is called on the symbol and the flags added to
the SymbolFlags map. If not found, the symbol is added to the SymbolsNotFound
set.
lookupWithLegacyFn takes an AsynchronousSymbolQuery, a SymbolNameSet and a
legacy lookup function. Each symbol in the SymbolNameSet is searched for via the
legacy lookup function. If it is found, its getAddress function is called
(triggering materialization if it has not happened already) and the resulting
mapping stored in the query. If it is not found the symbol is added to the
unresolved symbols set which is returned at the end of the function. If an
error occurs during legacy lookup or materialization it is passed to the
query via setFailed and the function returns immediately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323388
91177308-0d34-0410-b5e6-
96231b3b80d8
Amara Emerson [Wed, 24 Jan 2018 22:40:25 +0000 (22:40 +0000)]
[GlobalISel] Add a requires: asserts to a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323384
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Wed, 24 Jan 2018 22:35:11 +0000 (22:35 +0000)]
[TableGen] Add a way of getting the number of generic opcodes without including modular CodeGen headers.
This is a bit of a hack, but removes a cycle that broke modular builds
of LLVM. Of course the cycle is still there in form of a dependency
on the .def file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323383
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 24 Jan 2018 21:36:45 +0000 (21:36 +0000)]
[InstCombine] fix datalayout in test file
The only part of the datalayout that should matter for these tests
is the part that specifies the legal int widths ('n*'). But there
was a bug - that part of the string was not correctly separated with
the expected '-' character, so we were testing as if there were no
legal int widths at all. Removed the leading cruft so we have some
legal ints to test with.
I noticed this while testing a potential change to the way we
transform shifts and sexts in D42424.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323377
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Wed, 24 Jan 2018 21:21:10 +0000 (21:21 +0000)]
[ORC] Add a LambdaSymbolResolver convenience class and docs for SymbolResolver.
This patch adds a LambdaSymbolResolver convenience utility that can create an
orc::SymbolResolver from a pair of function objects that supply the behavior for
the lookupFlags and lookup methods.
This class plays the same role for orc::SymbolResolver as the legacy
LambdaResolver class plays for LegacyJITSymbolResolver, and will replace the
latter class once all ORC APIs are migrated to orc::SymbolResolver.
This patch also adds some documentation for the orc::SymbolResolver class as
this was left out of the original commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323375
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Wed, 24 Jan 2018 21:19:51 +0000 (21:19 +0000)]
[Hexagon] Replace EmitFunctionEntryCode with a DAG preprocessing code
The code in EmitFunctionEntryCode needs to know the maximum stack
alignment, but it runs very early in the selection process (before
lowering). The final stack alignment may change during lowering, so
the code needs to be moved to where the alignment is known.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323374
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Sanders [Wed, 24 Jan 2018 20:43:21 +0000 (20:43 +0000)]
[globalisel] Fix long lines from r323342
They would be fixed in a later patch but they shouldn't have been introduced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323372
91177308-0d34-0410-b5e6-
96231b3b80d8
Amara Emerson [Wed, 24 Jan 2018 20:35:37 +0000 (20:35 +0000)]
[AArch64][GlobalISel] Fall back during AArch64 isel if we have a volatile load.
The tablegen imported patterns for sext(load(a)) don't check for single uses
of the load or delete the original after matching. As a result two loads are
left in the generated code. This particular issue will be fixed by adding
support for a G_SEXTLOAD opcode in future.
There are however other potential issues around this that wouldn't be fixed by
a G_SEXTLOAD, so until we have a proper solution we don't try to handle volatile
loads at all in the AArch64 selector.
Fixes/works around PR36018.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323371
91177308-0d34-0410-b5e6-
96231b3b80d8
Amara Emerson [Wed, 24 Jan 2018 19:59:29 +0000 (19:59 +0000)]
[GlobalISel] Don't fall back to FastISel.
Apparently checking the pass structure isn't enough to ensure that we don't fall
back to FastISel, as it's set up as part of the SelectionDAGISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323369
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 24 Jan 2018 19:20:02 +0000 (19:20 +0000)]
[X86][SSE] Aggressively use PMADDWD for v4i32 multiplies with 17 or more leading zeros
As discussed in D41484, PMADDWD for 'zero extended' vXi32 is nearly always a better option than PMULLD:
On SNB it will result in code that isn't any faster, but not any slower so we may as well keep it.
On KNL it only has half the throughput, so I've disabled it on there - ideally there'd be a better way than this.
Differential Revision: https://reviews.llvm.org/D42258
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323367
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Wed, 24 Jan 2018 19:11:24 +0000 (19:11 +0000)]
Simplify. NFC.
Thanks to Teresa Johnson for the suggestion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323365
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 24 Jan 2018 19:09:11 +0000 (19:09 +0000)]
[X86][SSE] Add slow-pmulld attribute (silvermont-style) test
Requested by @zvi on D42258
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323364
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Wed, 24 Jan 2018 18:36:51 +0000 (18:36 +0000)]
Revert "[SLP] Fix for PR32086: Count InsertElementInstr of the same elements as shuffle."
This reverts commit r323348 because of the broken buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323359
91177308-0d34-0410-b5e6-
96231b3b80d8
Easwaran Raman [Wed, 24 Jan 2018 18:15:29 +0000 (18:15 +0000)]
Revert "[ThinLTO] Add call edges' relative block frequency to per-module summary."
Causes buildbot regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323358
91177308-0d34-0410-b5e6-
96231b3b80d8
Paul Robinson [Wed, 24 Jan 2018 18:15:08 +0000 (18:15 +0000)]
Fix up and document controlling ccache via CMake options.
Patch by Matthew Davis!
Differential Revision: https://reviews.llvm.org/D41757
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323357
91177308-0d34-0410-b5e6-
96231b3b80d8
Geoff Berry [Wed, 24 Jan 2018 18:09:53 +0000 (18:09 +0000)]
[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
Summary:
Move reserveRegisterTuples into AMDGPURegisterInfo and use it in
R600RegisterInfo::getReservedRegs and
R600InstrInfo::reserveIndirectRegisters to ensure that all super
registers of reserved registers are also marked as reserved.
Before this change, under certain circumstances, the registers %t1_x and
%t1_xyzw would be marked as reserved, but %t1_xy and %t1_xyz would not
be, leading to the register allocator sometimes assigning a register to
%t1_xy, which is invalid since %t1_x is reserved.
Reviewers: arsenm, tstellar, MatzeB, qcolombet
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D42448
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323356
91177308-0d34-0410-b5e6-
96231b3b80d8
Nicolai Haehnle [Wed, 24 Jan 2018 18:02:05 +0000 (18:02 +0000)]
Revert r321751, "StructurizeCFG: Fix broken backedge detection"
It causes regressions in various OpenGL test suites.
Keep the test cases introduced by r321751 as XFAIL, and add a test case
for the regression.
Change-Id: I90b4cc354f68cebe5fcef1f2422dc8fe1c6d3514
Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=36015
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323355
91177308-0d34-0410-b5e6-
96231b3b80d8
Weiming Zhao [Wed, 24 Jan 2018 18:00:57 +0000 (18:00 +0000)]
[ARM] Expand long shifts for Thumb1 to __aeabi_ calls
Summary: For long shifts, the inlined version takes about 20 instructions on Thumb1. To avoid the code bloat, expand to __aeabi_ calls if target is Thumb1.
Reviewers: samparker
Reviewed By: samparker
Subscribers: samparker, aemerson, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D42401
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323354
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 24 Jan 2018 17:58:57 +0000 (17:58 +0000)]
[X86] Fix some inconsistencies in the itineraries and Sched for (V)PEXTRW/(V)PINSRW
The weirdest being that PEXTRWrr was tagged as a memory operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323353
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 24 Jan 2018 17:58:51 +0000 (17:58 +0000)]
[X86] Adjust names of PINSRW/PEXTRW intructions between MMX/SSE/AVX/AVX512 for consistency and to maybe enable more regular expression compaction in the scheduler models. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323352
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 24 Jan 2018 17:58:42 +0000 (17:58 +0000)]
[X86] Remove '(_REV)?' from a bunch of scheduler regular expressions. NFC
The regexs are treated as a prefix match already so the checking for optional text at the end provides no value. Instead it prevents the binary search optimization in tablegen from kicking in due to the top level question mark.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323351
91177308-0d34-0410-b5e6-
96231b3b80d8
Easwaran Raman [Wed, 24 Jan 2018 17:51:23 +0000 (17:51 +0000)]
[ThinLTO] Add call edges' relative block frequency to per-module summary.
Summary:
This allows relative block frequency of call edges to be passed to the
thinlink stage where it will be used to compute synthetic entry counts
of functions.
Reviewers: tejohnson, pcc
Subscribers: mehdi_amini, llvm-commits, inglorion
Differential Revision: https://reviews.llvm.org/D42212
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323349
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Wed, 24 Jan 2018 17:50:53 +0000 (17:50 +0000)]
[SLP] Fix for PR32086: Count InsertElementInstr of the same elements as shuffle.
Summary:
If the same value is going to be vectorized several times in the same
tree entry, this entry is considered to be a gather entry and cost of
this gather is counter as cost of InsertElementInstrs for each gathered
value. But we can consider these elements as ShuffleInstr with
SK_PermuteSingle shuffle kind.
Reviewers: spatel, RKSimon, mkuper, hfinkel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323348
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Wed, 24 Jan 2018 17:48:11 +0000 (17:48 +0000)]
[Hexagon] Run late copy propagation and dead code elimination passes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323346
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Wed, 24 Jan 2018 17:36:08 +0000 (17:36 +0000)]
Handle R_386_PLT32 in RuntimeDyldELF.
This should fix the 32 bit buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323344
91177308-0d34-0410-b5e6-
96231b3b80d8
Zvi Rackover [Wed, 24 Jan 2018 17:22:00 +0000 (17:22 +0000)]
InstSimplify: If divisor element is undef simplify to undef
Summary:
If any vector divisor element is undef, we can arbitrarily choose it be
zero which would make the div/rem an undef value by definition.
Reviewers: spatel, reames
Reviewed By: spatel
Subscribers: magabari, llvm-commits
Differential Revision: https://reviews.llvm.org/D42485
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323343
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Sanders [Wed, 24 Jan 2018 17:17:46 +0000 (17:17 +0000)]
[globalisel] Introduce LegalityQuery to better encapsulate the legalizer decisions. NFC.
Summary:
`getAction(const InstrAspect &) const` breaks encapsulation by exposing
the smaller components that are used to decide how to legalize an
instruction.
This is a problem because we need to change the implementation of
LegalizerInfo so that it's able to describe particular type combinations
rather than just cartesian products of types.
For example, declaring the following
setAction({..., 0, s32}, Legal)
setAction({..., 0, s64}, Legal)
setAction({..., 1, s32}, Legal)
setAction({..., 1, s64}, Legal)
currently declares these type combinations as legal:
{s32, s32}
{s64, s32}
{s32, s64}
{s64, s64}
but we currently have no means to say that, for example, {s64, s32} is
not legal. Some operations such as G_INSERT/G_EXTRACT/G_MERGE_VALUES/
G_UNMERGE_VALUES has relationships between the types that are currently
described incorrectly.
Additionally, G_LOAD/G_STORE currently have no means to legalize non-atomics
differently to atomics. The necessary information is in the MMO but we have no
way to use this in the legalizer. Similarly, there is currently no way for the
register type and the memory type to differ so there is no way to cleanly
represent extending-load/truncating-store in a way that can't be broken by
optimizers (resulting in illegal MIR).
This patch introduces LegalityQuery which provides all the information
needed by the legalizer to make a decision on whether something is legal
and how to legalize it.
Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar, volkan, reames, bogner
Reviewed By: bogner
Subscribers: bogner, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D42244
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323342
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Devlieghere [Wed, 24 Jan 2018 16:53:14 +0000 (16:53 +0000)]
[NFC] Make magic number for DJB hash function customizable.
This allows us to specify the magic number for the DJB hash function.
This feature is needed by dsymutil to emit Apple types accelerator
table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323341
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Devlieghere [Wed, 24 Jan 2018 16:16:43 +0000 (16:16 +0000)]
[dsymutil] Make NonRelocatableStringPool a wrapper around DwarfStringPoolEntry. NFC
This is needed in order to use our StringPool entries in the Apple
accelerator tables.
As this is NFC we rely on the existing tests for correctness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323339
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 24 Jan 2018 15:20:37 +0000 (15:20 +0000)]
[ValueTracking] add recursion depth param to matchSelectPattern
We're getting bug reports:
https://bugs.llvm.org/show_bug.cgi?id=35807
https://bugs.llvm.org/show_bug.cgi?id=35840
https://bugs.llvm.org/show_bug.cgi?id=36045
...where we blow up the stack in value tracking because other passes are sending
in selects that have an operand that is itself the select.
We don't currently have a reliable way to avoid analyzing dead code that may take
non-standard forms, so bail out when things go too far.
This mimics the recursion depth limitations in other parts of value tracking.
Unfortunately, this pushes the underlying problems for other passes (jump-threading,
simplifycfg, correlated-propagation) into hiding. If someone wants to uncover those
again, the first draft of this patch on Phab would do that (it would assert rather
than bail out).
Differential Revision: https://reviews.llvm.org/D42442
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323331
91177308-0d34-0410-b5e6-
96231b3b80d8
Zvi Rackover [Wed, 24 Jan 2018 15:02:16 +0000 (15:02 +0000)]
X86 Tests: Add more sdiv combine cases. NFC
Add cases with vector non-splat pow2 contant divider.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323329
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 24 Jan 2018 14:59:02 +0000 (14:59 +0000)]
Regenerate shuffle sink test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323328
91177308-0d34-0410-b5e6-
96231b3b80d8
Amjad Aboud [Wed, 24 Jan 2018 14:48:49 +0000 (14:48 +0000)]
Reverted 323321.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323326
91177308-0d34-0410-b5e6-
96231b3b80d8
Pablo Barrio [Wed, 24 Jan 2018 14:13:47 +0000 (14:13 +0000)]
[AArch64] Avoid unnecessary vector byte-swapping in big-endian
Summary:
Loads/stores of some NEON vector types are promoted to other vector
types with different lane sizes but same vector size. This is not a
problem in little-endian but, when in big-endian, it requires
additional byte reversals required to preserve the lane ordering
while keeping the right endianness of the data inside each lane.
For example:
%1 = load <4 x half>, <4 x half>* %p
results in the following assembly:
ld1 { v0.2s }, [x1]
rev32 v0.4h, v0.4h
This patch changes the promotion of these loads/stores so that the
actual vector load/store (LD1/ST1) takes care of the endianness
correctly and there is no need for further byte reversals. The
previous code now results in the following assembly:
ld1 { v0.4h }, [x1]
Reviewers: olista01, SjoerdMeijer, efriedma
Reviewed By: efriedma
Subscribers: aemerson, rengolin, javed.absar, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D42235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323325
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Wed, 24 Jan 2018 14:07:37 +0000 (14:07 +0000)]
[Hexagon] Remove unused HexagonISD opcodes, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323324
91177308-0d34-0410-b5e6-
96231b3b80d8
Sander de Smalen [Wed, 24 Jan 2018 13:35:54 +0000 (13:35 +0000)]
[DebugInfo] Emit DWARF reference for DIVariable 'count' in DISubrange
Summary:
This patch implements the codegen of DWARF debug info for non-constant
'count' fields for DISubrange.
This is patch [2/3] in a series to extend LLVM's DISubrange Metadata
node to support debugging of C99 variable length arrays and vectors with
runtime length like the Scalable Vector Extension for AArch64. It is
also a first step towards representing more complex cases like arrays
in Fortran.
Reviewers: echristo, pcc, aprantl, dexonsmith, clayborg, kristof.beyls, dblaikie
Reviewed By: aprantl
Subscribers: fhahn, aemerson, rengolin, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D41696
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323323
91177308-0d34-0410-b5e6-
96231b3b80d8
Amjad Aboud [Wed, 24 Jan 2018 12:42:42 +0000 (12:42 +0000)]
[InstCombine] Introducing Aggressive Instruction Combine pass (-aggressive-instcombine).
Combine expression patterns to form expressions with fewer, simple instructions.
This pass does not modify the CFG.
For example, this pass reduce width of expressions post-dominated by TruncInst
into smaller width when applicable.
It differs from instcombine pass in that it contains pattern optimization that
requires higher complexity than the O(1), thus, it should run fewer times than
instcombine pass.
Differential Revision: https://reviews.llvm.org/D38313
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323321
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 24 Jan 2018 11:41:09 +0000 (11:41 +0000)]
[X86][SSE] Avoid calls to combineX86ShufflesRecursively that can't combine to target shuffles (PR32037)
Don't bother making recursive calls to combineX86ShufflesRecursively if we have more shuffle source operands than will be combined together with the remaining recursive depth.
See https://bugs.llvm.org/show_bug.cgi?id=32037#c26 and https://bugs.llvm.org/show_bug.cgi?id=32037#c27 for the reduction in compile times from this patch.
Differential Revision: https://reviews.llvm.org/D42378
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323320
91177308-0d34-0410-b5e6-
96231b3b80d8
Malcolm Parsons [Wed, 24 Jan 2018 10:33:39 +0000 (10:33 +0000)]
Fix typos of occurred and occurrence
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323318
91177308-0d34-0410-b5e6-
96231b3b80d8
Sander de Smalen [Wed, 24 Jan 2018 10:30:23 +0000 (10:30 +0000)]
Fixes Sphinx issue ('undefined label') introduced in r323313.
(and also slightly reformatted the related lines to look better in
the rendered HTML)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323317
91177308-0d34-0410-b5e6-
96231b3b80d8
Igor Laevsky [Wed, 24 Jan 2018 09:57:17 +0000 (09:57 +0000)]
[llvm-opt-fuzzer] Add couple of popular passes
Differential Revision: https://reviews.llvm.org/D42410
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323314
91177308-0d34-0410-b5e6-
96231b3b80d8
Sander de Smalen [Wed, 24 Jan 2018 09:56:07 +0000 (09:56 +0000)]
[Metadata] Extend 'count' field of DISubrange to take a metadata node
Summary:
This patch extends the DISubrange 'count' field to take either a
(signed) constant integer value or a reference to a DILocalVariable
or DIGlobalVariable.
This is patch [1/3] in a series to extend LLVM's DISubrange Metadata
node to support debugging of C99 variable length arrays and vectors with
runtime length like the Scalable Vector Extension for AArch64. It is
also a first step towards representing more complex cases like arrays
in Fortran.
Reviewers: echristo, pcc, aprantl, dexonsmith, clayborg, kristof.beyls, dblaikie
Reviewed By: aprantl
Subscribers: rnk, probinson, fhahn, aemerson, rengolin, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D41695
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323313
91177308-0d34-0410-b5e6-
96231b3b80d8
Sven van Haastregt [Wed, 24 Jan 2018 09:53:47 +0000 (09:53 +0000)]
[DAGCombiner] Bail out if vector size is not a multiple
For the included test case, the DAG transformation
concat_vectors(scalar, undef) -> scalar_to_vector(sclr)
would attempt to create a v2i32 vector for a v9i8
concat_vector. Bail out to avoid creating a bitcast with
mismatching sizes later on.
Differential Revision: https://reviews.llvm.org/D42379
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323312
91177308-0d34-0410-b5e6-
96231b3b80d8
David Chisnall [Wed, 24 Jan 2018 09:53:01 +0000 (09:53 +0000)]
[Doc] Guideline on adding exception handling support for a target
Summary:
This is the first attempt to write down a guideline on adding exception handling support for a target. The content basically bases on the discussion on [1]. If you guys know who is exception handling expert, please add him as the reviewer. Thanks.
[1] http://lists.llvm.org/pipermail/llvm-dev/2018-January/120405.html
Reviewers: t.p.northover, theraven, nemanjai
Reviewed By: theraven
Subscribers: sdardis, llvm-commits
Differential Revision: https://reviews.llvm.org/D42178
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323311
91177308-0d34-0410-b5e6-
96231b3b80d8
Max Kazantsev [Wed, 24 Jan 2018 07:51:41 +0000 (07:51 +0000)]
[NFC] Remove overconfident assert from IRCE
This patch removes assert that SCEV is able to prove that a value is
non-negative. In fact, SCEV can sometimes be unable to do this because
its cache does not update properly. This assert will be returned once this
problem is resolved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323309
91177308-0d34-0410-b5e6-
96231b3b80d8
Martin Storsjo [Wed, 24 Jan 2018 06:40:11 +0000 (06:40 +0000)]
[ARM] Call __chkstk for dynamic stack allocation in all windows environments
This matches what MSVC does for alloca() function calls on ARM.
Even if MSVC doesn't support VLAs at the language level, it does
support the alloca function.
On the clang level, both the _alloca() (when emulating MSVC, which is
what the alloca() function expands to) and __builtin_alloca() builtin
functions, and VLAs, map to the same LLVM IR "alloca" function - so
within LLVM they're not distinguishable from each other.
Differential Revision: https://reviews.llvm.org/D42292
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323308
91177308-0d34-0410-b5e6-
96231b3b80d8
Martin Storsjo [Wed, 24 Jan 2018 06:40:04 +0000 (06:40 +0000)]
[GlobalMerge] Don't merge dllexport globals
Merging such globals loses the dllexport attribute. Add a test
to check that normal globals still are merged.
Differential Revision: https://reviews.llvm.org/D42127
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323307
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 24 Jan 2018 05:32:51 +0000 (05:32 +0000)]
[X86] Move 'Y' to correct place in FMA4 regular expression in Znver1 scheduler model.
I think these instructions used to be named differently and the regular expression reflected that. I guess we must have correct itinerary information that made this not matter for the scheduler test?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323305
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 24 Jan 2018 05:14:39 +0000 (05:14 +0000)]
[X86] Rename 256-bit VFRCZ instructions to have the Y before the rr/rm to match other instructions. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323304
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 24 Jan 2018 05:14:33 +0000 (05:14 +0000)]
[X86] Remove redundant regular expression from the Znver1 scheduler model. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323303
91177308-0d34-0410-b5e6-
96231b3b80d8