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Eric Engestrom [Mon, 28 Jan 2019 18:13:55 +0000 (18:13 +0000)]
gitlab-ci: add meson gallium ST "Other" build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 18:09:24 +0000 (18:09 +0000)]
gitlab-ci: add meson gallium ST Clover (LLVM 7.0) build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 18:07:31 +0000 (18:07 +0000)]
gitlab-ci: add meson gallium ST Clover (LLVM 6.0) build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 18:05:22 +0000 (18:05 +0000)]
gitlab-ci: add meson gallium ST Clover (LLVM 5.0) build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 17:47:09 +0000 (17:47 +0000)]
gitlab-ci: add meson gallium "other drivers" build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 17:45:26 +0000 (17:45 +0000)]
gitlab-ci: add meson gallium RadeonSI build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 17:42:59 +0000 (17:42 +0000)]
gitlab-ci: add meson gallium SWR build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 17:38:17 +0000 (17:38 +0000)]
gitlab-ci: add meson loader/classic DRI build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 16:33:22 +0000 (16:33 +0000)]
gitlab-ci: add scons SWR build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 28 Jan 2019 16:30:36 +0000 (16:30 +0000)]
gitlab-ci: add scons llvm 3.5 build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Wed, 23 Jan 2019 15:46:10 +0000 (15:46 +0000)]
gitlab-ci: add a scons no-llvm build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 21 Jan 2019 09:42:37 +0000 (09:42 +0000)]
gitlab-ci: add a make vulkan build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Sun, 20 Jan 2019 11:26:53 +0000 (11:26 +0000)]
gitlab-ci: add a meson vulkan build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Sun, 20 Jan 2019 11:21:45 +0000 (11:21 +0000)]
gitlab-ci: add ubuntu container
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Marek Olšák [Thu, 31 Jan 2019 15:59:48 +0000 (10:59 -0500)]
radeonsi: use local ws variable in si_need_dma_space
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 22 Jan 2019 22:29:19 +0000 (17:29 -0500)]
radeonsi: don't leak an index buffer if draw_vbo fails
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 30 Jan 2019 19:29:36 +0000 (14:29 -0500)]
radeonsi: make allocator_zeroed_memory unmappable and use bigger buffers
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 29 Jan 2019 00:49:56 +0000 (19:49 -0500)]
radeonsi: clear allocator_zeroed_memory with SDMA
so that it can be used in parallel IBs.
This also removes the SO_FILLED_SIZE hack.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 23 Jan 2019 16:34:48 +0000 (11:34 -0500)]
radeonsi: initialize textures using DCC to black when possible
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Jonathan Marek [Tue, 5 Feb 2019 19:08:12 +0000 (14:08 -0500)]
freedreno: a2xx: fix fast clear
Fixes:
912a9c8d
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Eric Engestrom [Sat, 2 Feb 2019 11:38:45 +0000 (11:38 +0000)]
egl: use coherent variable names
`EGLDisplay` variables (the opaque Khronos type) have mostly been
consistently called `dpy`, as this is the name used in the Khronos
specs.
However, `_EGLDisplay` variables (our internal struct) have been
randomly called `dpy` when there was no local variable clash with
`EGLDisplay`s, and `disp` otherwise.
Let's be consistent and use `dpy` for the Khronos type, and `disp`
for our struct.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Eric Anholt <eric@anholt.net>
Alyssa Rosenzweig [Tue, 5 Feb 2019 02:00:12 +0000 (02:00 +0000)]
meson: Remove panfrost from default driver list
Until the kernel side matures and the full driver is upstreamed, to
avoid end-user surprises, Panfrost should only be built for the
adventurous.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Anholt <eric@anholt.net>
Eric Anholt [Mon, 4 Feb 2019 20:07:41 +0000 (12:07 -0800)]
v3d: Whitespace consistency fix.
Eric Anholt [Mon, 4 Feb 2019 18:35:40 +0000 (10:35 -0800)]
v3d: Fix copy-propagation of input unpacks.
I had a single function for "does this do float input unpacking" with two
major flaws: It was missing the most common thing to try to copy propagate
a f32 input nunpack to (the VFPACK to an FP16 render target) along with
several other ALU ops, and also would try to propagate an f32 unpack into
a VFMUL which only does f16 unpacks.
instructions in affected programs: 659232 -> 655895 (-0.51%)
uniforms in affected programs: 132613 -> 135336 (2.05%)
and a couple of programs increase their thread counts.
The uniforms hit appears to be a pattern in generated code of doing (-a >=
a) comparisons, which when a is abs(b) can result in the abs instruction
being copy propagated once but not fully DCEed.
Eric Anholt [Tue, 5 Feb 2019 01:15:36 +0000 (17:15 -0800)]
v3d: Fix input packing of .l for rounding/fdx/fdy.
Avoids a regression in
dEQP-GLES3.functional.shaders.derivate.fwidth.texture.* once we start
copy-propagating more input packs.
Eric Anholt [Mon, 4 Feb 2019 19:18:55 +0000 (11:18 -0800)]
v3d: Fix pack/unpack of VFPACK operand unpacks.
We want to be able to copy propagate our texture unpacks into the vfpack.
Eric Anholt [Sat, 2 Feb 2019 01:18:41 +0000 (17:18 -0800)]
v3d: Fix dumping of shaders with alpha test.
We were trying to print a NULL entry from the table.
Eric Anholt [Fri, 1 Feb 2019 21:13:48 +0000 (13:13 -0800)]
v3d: Store the actual mask of color buffers present in the key.
If you only bound rt 1+, we'd still emit a write to the rt0 that isn't
present (noticed while debugging an
ext_framebuffer_multisample-alpha-to-coverage-no-draw-buffer-zero
regression in another change).
Eric Anholt [Sat, 2 Feb 2019 00:41:56 +0000 (16:41 -0800)]
v3d: Fix precompile of FRAG_RESULT_DATA1 and higher outputs.
I was just leaving the other MRT targets than DATA0 out, by accident.
Kristian H. Kristensen [Tue, 5 Feb 2019 22:13:51 +0000 (14:13 -0800)]
st/nir: Use src/ relative include path for autotools
Fixes:
cdc53fa81cbeb80373eac33ef7695d9025caf14b
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Kenneth Graunke [Wed, 23 Jan 2019 10:04:01 +0000 (02:04 -0800)]
gallium: Add a PIPE_CAP_NIR_COMPACT_ARRAYS capability bit.
Iris would like to use compact arrays for tesslevels and clip/cull
distances. radeonsi will likely want to switch to these at some point,
since it'll be necessary for GL_ARB_gl_spirv support, but it's not ready
for them just yet.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Kenneth Graunke [Wed, 23 Jan 2019 10:44:28 +0000 (02:44 -0800)]
st/nir: Call nir_lower_clip_cull_distance_arrays().
Today, st always sets LowerCombinedClipCullDistance, causing the GLSL IR
lowering to run, giving us vec4[2] arrays. I would like to disable this
and instead run the NIR lowering so that we get compact float[] arrays
instead.
Calling the new pass is a noop if the GLSL IR pass has already run, so
it's safe to call the pass unconditionally.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Kenneth Graunke [Thu, 5 Jul 2018 21:34:27 +0000 (14:34 -0700)]
nir: Avoid splitting compact arrays into per-element variables.
Compact arrays are used for special variables like clip and cull
distances, or tessellation levels. Drivers using compact arrays
assume that these values will always be actual arrays. We don't
want to turn a float[1] gl_CullDistance into a single float; that
would confuse drivers.
Today, i965 uses compact arrays, and Gallium drivers use
nir_lower_io_arrays_to_elements, so we haven't had any overlap
that would demonstrate the issue. Iris will use both.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Kenneth Graunke [Wed, 23 Jan 2019 09:15:05 +0000 (01:15 -0800)]
nir: Avoid clip/cull distance lowering multiple times.
A couple places in st/nir assume that cull distances have been lowered
away, so it will need to call this lowering pass for drivers which opt
out of the GLSL IR lowering. The Intel backend also calls this pass,
for i965 and anv. We need to only do it once.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Kenneth Graunke [Wed, 23 Jan 2019 10:36:44 +0000 (02:36 -0800)]
nir: Bail on clip/cull distance lowering if GLSL IR already did it.
We have a GLSL IR pass to convert clip/cull distance float[] arrays
into vec4[2] arrays. In
ff281e6204, we attempted to skip this pass
if the GLSL IR lowering had already run. But, that code was not quite
right, as we forgot to strip away the per-vertex IO array layer for
geometry and tessellation shader varyings.
If the GLSL IR pass has run, the variables will not be marked as
"compact". So we can simply check that and bail.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Kenneth Graunke [Wed, 23 Jan 2019 09:55:45 +0000 (01:55 -0800)]
compiler: Mark clip/cull distance arrays as compact before lowering.
nir_lower_clip_cull_distance_arrays() marks the combined clip/cull
distance array as compact. However, when translating in from GLSL
or SPIR-V, we were not marking the original float[] arrays as compact.
We should do so. That way, we can detect these corner cases properly.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Kenneth Graunke [Sat, 2 Feb 2019 08:43:42 +0000 (00:43 -0800)]
nir: Record info->fs.pixel_center_integer in lower_system_values
radeonsi uses a system value for gl_FragCoord rather than an input var.
These get translated into load_frag_coord NIR intrinsics, which lose the
pixel_center_integer and origin_upper_left decorations. To cope with
this, Tim added a shader_info field for pixel_center_integer, and made
glsl_to_nir set it accordingly.
prog_to_nir also needs to handle these fragcoord conventions. Instead
of duplicating the logic to set the info field, just move it to
nir_lower_system_values so it'll happen regardless of who makes the NIR.
(For what it's worth, we don't need an info flag for origin_upper_left,
because radeonsi lowers origin conventions in nir_lower_wpos_ytransform
before nir_lower_system_values destroys the variable and qualifiers.)
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Fri, 1 Feb 2019 05:52:50 +0000 (21:52 -0800)]
program: Extend prog_to_nir handle system values.
Some drivers, such as radeonsi, use a system value for gl_FragCoord
rather than an input variable. In this case, our Mesa IR will have
a PROGRAM_SYSTEM_VALUE register, which we need to translate.
This makes prog_to_nir work for Gallium drivers which expose the
PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL capability bit.
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Fri, 1 Feb 2019 06:02:55 +0000 (22:02 -0800)]
program: Use u_bit_scan64 in prog_to_nir.
We can simply iterate the bits rather than using util_last_bit and
checking each one up until that point.
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Fri, 2 Nov 2018 09:39:58 +0000 (02:39 -0700)]
st/mesa: Add NIR versions of the PBO upload/download shaders.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Rob Clark <robdclark@gmail.com>
Tested-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Sun, 4 Nov 2018 23:42:02 +0000 (15:42 -0800)]
st/mesa: Add a NIR version of the OES_draw_texture built-in shaders.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Rob Clark <robdclark@gmail.com>
Tested-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Fri, 2 Nov 2018 09:24:00 +0000 (02:24 -0700)]
st/mesa: Add NIR versions of the clear shaders.
We implement the basic VS and FS, as well as the VS that does layered
clears by writing gl_Layer from the vertex shader. Drivers which need
a geometry shader for writing layer continue falling back to TGSI, as
I didn't need this and so didn't bother implementing it. (We certainly
could, however, if people want to add it in the future.)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Rob Clark <robdclark@gmail.com>
Tested-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Mon, 17 Sep 2018 02:08:07 +0000 (19:08 -0700)]
st/mesa: Add NIR versions of the drawpixels Z/stencil fragment shaders.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Rob Clark <robdclark@gmail.com>
Tested-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Sun, 4 Nov 2018 06:46:29 +0000 (23:46 -0700)]
st/mesa: Add a NIR version of the drawpixels/bitmap VS copy shader.
This provides a native NIR version of the DrawPixels/Bitmap passthrough
vertex shader.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Rob Clark <robdclark@gmail.com>
Tested-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Tue, 30 Oct 2018 05:30:06 +0000 (22:30 -0700)]
st/nir: Make new helpers for constructing built-in NIR shaders.
The state tracker generates several built-in shaders in order to
perform scissored clears, upload/download PBOs, and so on. These
are currently constructed using TGSI, using ureg and u_simple_shader.
I want to have NIR versions of these shaders, for my Gallium driver
that has a NIR backend but no TGSI support. To that end, we'll want
a few helpers to help construct simple shaders.
This patch adds two new helpers:
- st_nir_finish_builtin_shader() takes a manually constructed NIR
shader, applies lowering passes (like st_link_nir would do for GLSL),
and constructs the pipe_shader_state.
- st_nir_make_passthrough_shader() makes a simple passthrough shader,
which copies inputs to outputs. This is similar to u_simple_shaders.
v2: Set info->fs.untyped_color_outputs for vc4/v3d (thanks Eric!).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Rob Clark <robdclark@gmail.com>
Tested-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Tue, 30 Oct 2018 05:41:18 +0000 (22:41 -0700)]
st/nir: Move varying setup code to a helper function.
I want to reuse this for built-in shaders.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Rob Clark <robdclark@gmail.com>
Tested-by: Eric Anholt <eric@anholt.net>
Jason Ekstrand [Sun, 3 Feb 2019 15:32:32 +0000 (09:32 -0600)]
nir/deref: Drop zero ptr_as_array derefs
They are effectively (&x)[0] or *&x which does nothing.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Eric Anholt [Tue, 5 Feb 2019 18:22:30 +0000 (10:22 -0800)]
nir: Move V3D's "the shader was TGSI, ignore FS output types" flag to NIR.
Ken's rework of mesa/st builtins to NIR means that we'll have more NIR
shaders with color output types that are mismatched with the render target
types. Since this is behavior that GLSL doesn't require, add it as a
shader_info option so the driver can know that it needs to ignore the FS
output's base type in favor of the actual render target's. This prevents
needing additional variants in several mesa/st paths (clear, pbo upload,
pbo download), given that the driver already has to handle the variants
for any TGSI being passed to it (from u_blitter, for example).
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Emil Velikov [Tue, 5 Feb 2019 12:09:45 +0000 (12:09 +0000)]
anv: wire up the state_pool_padding test
Cc: Jason Ekstrand <jason@jlekstrand.net>
Fixes:
927ba12b53c ("anv/tests: Adding test for the state_pool padding.")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com><Paste>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Karol Herbst [Thu, 13 Dec 2018 19:19:45 +0000 (20:19 +0100)]
nvc0/ir: replace cvt instructions with add to improve shader performance
gives me an performance boost of 0.2% in pixmark_piano on my gk106, gm204 and
gp107.
reduces the amount of generated convert instructions by roughly 30% in
shader-db.
v2: only for 32 bit operations
move some common code out of the switch
handle OP_SAT with modifiers
v3: only for registers and const memory
rework if clauses
merge isCvt into this patch
v4: merge isCvt into its use
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Bart Oldeman [Sun, 3 Feb 2019 02:57:10 +0000 (02:57 +0000)]
gallium-xlib: query MIT-SHM before using it.
When Mesa is compiled for gallium-xlib using e.g.
./configure --enable-glx=gallium-xlib --disable-dri --disable-gbm
-disable-egl
and is used by an X server (usually remotely via SSH X11 forwarding)
that does not support MIT-SHM such as XMing or MobaXterm, OpenGL
clients report error messages such as
Xlib: extension "MIT-SHM" missing on display "localhost:11.0".
ad infinitum.
The reason is that the code in src/gallium/winsys/sw/xlib uses
MIT-SHM without checking for its existence, unlike the code
in src/glx/drisw_glx.c and src/mesa/drivers/x11/xm_api.c.
I copied the same check using XQueryExtension, and tested with
glxgears on MobaXterm.
This issue was reported before here:
https://lists.freedesktop.org/archives/mesa-users/2016-July/001183.html
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Cc: <mesa-stable@lists.freedesktop.org>
Alok Hota [Thu, 7 Jun 2018 18:14:48 +0000 (13:14 -0500)]
swr/rast: update SWR rasterizer shader stats
Primarily refactoring internal stats types
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Michel Dänzer [Mon, 4 Feb 2019 17:53:52 +0000 (18:53 +0100)]
loader/dri3: Use strlen instead of sizeof for creating VRR property atom
sizeof counts the terminating null character as well, so that also
contributed to the ID computed for the X11 atom. But the convention is
for only the non-null characters to contribute to the atom ID.
Fixes:
2e12fe425fe3 "loader/dri3: Enable adaptive_sync via
_VARIABLE_REFRESH property"
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Jonathan Marek [Tue, 29 Jan 2019 14:09:07 +0000 (09:09 -0500)]
nir: add missing vec opcodes in lower_bool_to_float
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Gert Wollny [Sat, 2 Feb 2019 12:17:16 +0000 (13:17 +0100)]
mesa: release references to image textures when a context is destroyed
When a texture is still bound as an image and the context it was bound in
is destroyed but not the texture, then the texture will still hold the
resource and will not be freed when it is finally destroyed. Hence, release
these references when the context is destroyed.
This leak was triggered by virglrenderer:
https://gitlab.freedesktop.org/virgl/virglrenderer/issues/86
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Gert Wollny [Thu, 31 Jan 2019 13:50:41 +0000 (14:50 +0100)]
radeonsi: release tokens after creating the shader program
ureg_get_tokens clears the reference to the tokens, and create_compute_state makes
a copy, hence the tokens must be explicitely released.
Fixes: Direct leak of 256 byte(s) in 1 object(s) allocated from:
#0 0x7ff729cf3c60 in realloc (/usr/lib64/gcc/x86_64-pc-linux-gnu/7.3.0/libasan.so+0xdbc60)
#1 0x7ff721b1240c in tokens_expand ../../samba/mesa/src/gallium/auxiliary/tgsi/tgsi_ureg.c:234
#2 0x7ff721b1c9c0 in get_tokens ../../samba/mesa/src/gallium/auxiliary/tgsi/tgsi_ureg.c:257
#3 0x7ff721b1c9c0 in copy_instructions ../../samba/mesa/src/gallium/auxiliary/tgsi/tgsi_ureg.c:2040
#4 0x7ff721b1c9c0 in ureg_finalize ../../samba/mesa/src/gallium/auxiliary/tgsi/tgsi_ureg.c:2090
#5 0x7ff721b1e919 in ureg_get_tokens ../../samba/mesa/src/gallium/auxiliary/tgsi/tgsi_ureg.c:2167
#6 0x7ff721f8b35a in si_create_dma_compute_shader ../../samba/mesa/src/gallium/drivers/radeonsi/si_shaderlib_tgsi.c:219
#7 0x7ff722043ed9 in si_compute_do_clear_or_copy ../../samba/mesa/src/gallium/drivers/radeonsi/si_compute_blit.c:156
#8 0x7ff7220448d3 in si_clear_buffer ../../samba/mesa/src/gallium/drivers/radeonsi/si_compute_blit.c:247
#9 0x7ff7220350e8 in vi_dcc_clear_level ../../samba/mesa/src/gallium/drivers/radeonsi/si_clear.c:274
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Caio Marcelo de Oliveira Filho [Thu, 31 Jan 2019 21:18:19 +0000 (13:18 -0800)]
isl: assert that Gen8+ don't have bit6_swizzling
v2: Rewrite the condition to more clearly match the comment. (Jordan)
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Caio Marcelo de Oliveira Filho [Thu, 31 Jan 2019 21:29:40 +0000 (13:29 -0800)]
anv: skip bit6 swizzle detection in Gen8+
It is always false on Gen8+. Also, move the variable definition near
its use.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Caio Marcelo de Oliveira Filho [Thu, 31 Jan 2019 21:28:24 +0000 (13:28 -0800)]
i965: skip bit6 swizzle detection in Gen8+
It is always false on Gen8+.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Caio Marcelo de Oliveira Filho [Sat, 26 Jan 2019 09:05:14 +0000 (01:05 -0800)]
nir: keep the phi order when splitting blocks
All things being equal is better to keep the original order. Since
the new block is empty, push the phis in order to tail.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Daniel Schürmann <daniel.schuermann@campus.tu-berlin.de>
Ilia Mirkin [Tue, 5 Feb 2019 04:33:09 +0000 (23:33 -0500)]
nv50,nvc0: add explicit settings for recent caps
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Alyssa Rosenzweig [Wed, 30 Jan 2019 01:11:31 +0000 (01:11 +0000)]
panfrost: Implement Midgard shader toolchain
This patch implements the free Midgard shader toolchain: the assembler,
the disassembler, and the NIR-based compiler. The assembler is a
standalone inaccessible Python script for reference purposes. The
disassembler and the compiler are implemented in C, accessible via the
standalone `midgard_compiler` binary. Later patches will use these
interfaces from the driver for online compilation.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Rob Clark <robdclark@gmail.com>
Acked-by: Eric Anholt <eric@anholt.net>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
Alyssa Rosenzweig [Tue, 29 Jan 2019 05:46:07 +0000 (05:46 +0000)]
panfrost: Initial stub for Panfrost driver
This patch adds an initial stub for the Gallium driver, containing
simple screen functions and the majority of the driver headers but no
actual functionality. It further adds the winsys glue for linking in
this stub driver via kmsro on Rockchip/Amlogic boards.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Rob Clark <robdclark@gmail.com>
Acked-by: Eric Anholt <eric@anholt.net>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
Marek Olšák [Sat, 26 Jan 2019 01:39:40 +0000 (20:39 -0500)]
radeonsi: fix crashing performance counters (division by zero)
Fixes:
e2b9329f17 "radeonsi: move remaining perfcounter code into si_perfcounter.c"
Marek Olšák [Wed, 23 Jan 2019 21:54:28 +0000 (16:54 -0500)]
radeonsi: handle render_condition_enable in si_compute_clear_render_target
Sonny Jiang [Mon, 21 Jan 2019 23:16:40 +0000 (18:16 -0500)]
radeonsi: use compute for clear_render_target when possible
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Kenneth Graunke [Fri, 1 Feb 2019 00:54:43 +0000 (16:54 -0800)]
st/mesa: Set pipe_image_view::shader_access in PBO readpixels.
Commit
8b626a22b24089edf90cb1b06e5b1895bb36c61b introduced a new
pipe_image_view::shader_access field, indicating the access mode
specified in the shader. st/mesa's built-in PBO download shader
creates a write-only image buffer, so we should flag it as such.
Nobody uses this field yet (Iris will), so we don't need to backport
this fix to stable branches.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Rodrigo Vivi [Sat, 2 Feb 2019 08:03:04 +0000 (00:03 -0800)]
intel: Add more PCI Device IDs for Coffee Lake and Ice Lake.
Align with kernel commits:
5e0f5a58b167 ("drm/i915/cfl: Adding another PCI Device ID.")
03ca3cf8e9aa ("drm/i915/icl: Adding few more device IDs for Ice Lake")
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Danylo Piliaiev [Fri, 1 Feb 2019 10:21:38 +0000 (12:21 +0200)]
anv: Fix VK_EXT_transform_feedback working with varyings packed in PSIZ
Transform feedback did not set correct SO_DECL.ComponentMask for
varyings packed in VARYING_SLOT_PSIZ:
gl_Layer - VARYING_SLOT_LAYER in VARYING_SLOT_PSIZ.y
gl_ViewportIndex - VARYING_SLOT_VIEWPORT in VARYING_SLOT_PSIZ.z
gl_PointSize - VARYING_SLOT_PSIZ in VARYING_SLOT_PSIZ.w
Fixes:
36ee2fd61c8f94 "anv: Implement the basic form of VK_EXT_transform_feedback"
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Danylo Piliaiev [Thu, 31 Jan 2019 13:56:21 +0000 (15:56 +0200)]
radv: Handle VK_ATTACHMENT_UNUSED in CmdClearAttachment
From the Vulkan 1.0.98 spec for vkCmdClearAttachments:
"If any attachment to be cleared in the current subpass is VK_ATTACHMENT_UNUSED,
then the clear has no effect on that attachment."
"If the aspectMask member of any element of pAttachments contains
VK_IMAGE_ASPECT_COLOR_BIT, then the colorAttachment member of that
element must either refer to a color attachment which is VK_ATTACHMENT_UNUSED,
or must be a valid color attachment."
"If the aspectMask member of any element of pAttachments contains
VK_IMAGE_ASPECT_DEPTH_BIT, then the current subpass' depth/stencil attachment
must either be VK_ATTACHMENT_UNUSED, or must have a depth component"
"If the aspectMask member of any element of pAttachments contains
VK_IMAGE_ASPECT_STENCIL_BIT, then the current subpass' depth/stencil attachment
must either be VK_ATTACHMENT_UNUSED, or must have a stencil component"
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Danylo Piliaiev [Thu, 31 Jan 2019 13:49:35 +0000 (15:49 +0200)]
anv: Handle VK_ATTACHMENT_UNUSED in colorAttachment
From the Vulkan 1.0.98 spec for vkCmdClearAttachments:
"If the aspectMask member of any element of pAttachments contains
VK_IMAGE_ASPECT_COLOR_BIT, then the colorAttachment member of that
element must either refer to a color attachment which is VK_ATTACHMENT_UNUSED,
or must be a valid color attachment."
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Samuel Pitoiset [Tue, 29 Jan 2019 21:19:04 +0000 (22:19 +0100)]
radv: don't flush src stages when dstStageMask == BOTTOM_OF_PIPE
Original patch by Fredrik Höglund.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 29 Jan 2019 21:19:03 +0000 (22:19 +0100)]
radv: do not set preserveAttachments for internal render passes
We don't use that.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 29 Jan 2019 21:19:02 +0000 (22:19 +0100)]
radv: drop useless checks when resolving subpass color attachments
The Vulkan spec says:
"If pResolveAttachments is not NULL, for each resolve attachment
that does not have the value VK_ATTACHMENT_UNUSED, the
corresponding color attachment must not have the value
VK_ATTACHMENT_UNUSED."
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 29 Jan 2019 21:19:01 +0000 (22:19 +0100)]
radv: execute external subpass barriers after ending subpasses
Outgoing dependencies (ie. external) should happen after the subpass.
This doesn't change anything for subpass resolves as we already
make sure that attachments are shader readable.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 29 Jan 2019 21:19:00 +0000 (22:19 +0100)]
radv: accumulate all ingoing external dependencies to the first subpass
In case two or more subpasses declare ingoing external dependencies.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 29 Jan 2019 21:18:59 +0000 (22:18 +0100)]
radv: handle subpass dependencies correctly
The different masks should be accumulated. For example if two
subpasses declare an outgoing dependency (ie. dst ==
VK_SUBPASS_EXTERNAL).
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 29 Jan 2019 21:18:58 +0000 (22:18 +0100)]
radv: track if subpasses have color attachments
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 29 Jan 2019 21:18:57 +0000 (22:18 +0100)]
radv: add radv_render_pass_add_subpass_dep() helper
To share common code that handles subpass dependencies.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 29 Jan 2019 21:18:56 +0000 (22:18 +0100)]
radv: move some render pass things to radv_render_pass_compile()
radv_render_pass_compile() is common to vkCreateRenderPass()
and vkCreateRenderPass2().
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 29 Jan 2019 21:18:54 +0000 (22:18 +0100)]
radv: handle final layouts at end of every subpass and render pass
That shouldn't change anything as we check if the last
subpass id is the final subpass.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 29 Jan 2019 21:18:53 +0000 (22:18 +0100)]
radv: determine the last subpass id for every attachments
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 29 Jan 2019 21:18:52 +0000 (22:18 +0100)]
radv: use the new attachments array when starting subpasses
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 29 Jan 2019 21:18:51 +0000 (22:18 +0100)]
radv: store the list of attachments for every subpass
This reworks how the depth stencil attachment is used for
simplicity. This also introduces radv_render_pass_compile()
helper that will be used for further optimizations.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 29 Jan 2019 21:18:50 +0000 (22:18 +0100)]
radv: move subpass image transitions to radv_cmd_buffer_begin_subpass()
Instead of doing them in radv_cmd_buffer_set_subpass().
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 29 Jan 2019 21:18:49 +0000 (22:18 +0100)]
radv: add radv_cmd_buffer_begin_subpass() helper
To unify some code in BeginRenderPass() and NextSubpass().
Based on Intel ANV driver.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 29 Jan 2019 21:18:48 +0000 (22:18 +0100)]
radv: remove useless MAYBE_UNUSED in CmdBeginRenderPass()
Trivial.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 29 Jan 2019 21:18:47 +0000 (22:18 +0100)]
radv: remove unused radv_render_pass_attachment::view_mask
Trivial.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 29 Jan 2019 21:18:46 +0000 (22:18 +0100)]
radv: bail out when no image transitions will be performed
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Marek Olšák [Thu, 24 Jan 2019 00:48:26 +0000 (19:48 -0500)]
meson: drop the xcb-xrandr version requirement
autotools doesn't have any requirement. This fixes meson on Ubuntu 16.04.
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Eric Engestrom [Sun, 16 Sep 2018 14:22:29 +0000 (15:22 +0100)]
wsi/display: add comment
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Keith Packard <keithp@keithp.com>
Jason Ekstrand [Sat, 2 Feb 2019 14:41:19 +0000 (08:41 -0600)]
relnotes: Add VK_EXT_buffer_device_address
Jason Ekstrand [Sat, 19 Jan 2019 14:54:32 +0000 (08:54 -0600)]
anv: Implement VK_EXT_buffer_device_address
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Mon, 26 Nov 2018 21:15:04 +0000 (15:15 -0600)]
intel/fs: Implement nir_intrinsic_global_atomic_*
eviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Fri, 16 Nov 2018 16:13:51 +0000 (10:13 -0600)]
intel/fs: Use SENDS for A64 writes on gen9+
eviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Wed, 14 Nov 2018 23:13:57 +0000 (17:13 -0600)]
intel/fs: Implement load/store_global with A64 untyped messages
eviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 15 Jan 2019 16:53:44 +0000 (10:53 -0600)]
intel/fs: Do the grf127 hack on SIMD8 instructions in SIMD16 mode
Previously, we only applied the fix to shaders with a dispatch mode of
SIMD8 but the code it relies on for SIMD16 mode only applies to SIMD16
instructions. If you have a SIMD8 instruction in a SIMD16 shader,
neither would trigger and the restriction could still be hit.
Fixes:
232ed8980217dd "i965/fs: Register allocator shoudn't use grf127..."
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Thu, 15 Nov 2018 04:38:23 +0000 (22:38 -0600)]
intel/fs: Properly handle 64-bit types in LOAD_PAYLOAD
By just assigning dst.type to src[i].type, we ensure that the offset at
the end of the loop actually offsets it by the right number of
registers. Otherwise, we'll get into a case where we copy with a Q type
and then offset with a D type and things get out of sync.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 15 Jan 2019 04:21:48 +0000 (22:21 -0600)]
intel/fs/cse: Split create_copy_instr into three cases
Previously, we tried to combine all cases where the instruction being
CSE'd writes to more than one MOV worth of registers into one case with
a bit of special casing for LOAD_PAYLOAD. This commit splits things so
that LOAD_PAYLOAD is entirely it's own case. This makes tweaking the
LOAD_PAYLOAD case simpler in the next commit.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Wed, 14 Nov 2018 21:40:43 +0000 (15:40 -0600)]
intel/nir: Add global support to lower_mem_access_bit_sizes
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>