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Yi Kong [Thu, 17 Jul 2014 10:50:20 +0000 (10:50 +0000)]
Port memory barriers intrinsics to AArch64
Memory barrier __builtin_arm_[dmb, dsb, isb] intrinsics are required to
implement their corresponding ACLE and MSVC intrinsics.
This patch ports ARM dmb, dsb, isb intrinsic to AArch64.
Differential Revision: http://reviews.llvm.org/D4520
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213247
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Daniel Sanders [Thu, 17 Jul 2014 10:10:04 +0000 (10:10 +0000)]
[mips] .reginfo is 8 byte aligned on N32.
Differential Revision: http://reviews.llvm.org/D4540
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213246
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Daniel Sanders [Thu, 17 Jul 2014 10:02:08 +0000 (10:02 +0000)]
[mips] Correct ELF e_flags for the N32 ABI when using a mips-* triple rather than a mips64-* triple
Summary:
Generally speaking, mips-* vs mips64-* should not be used to make decisions
about the content or format of the ELF. This should be based on the ABI
and CPU in use. For example, `mips-linux-gnu-clang -mips64r2 -mabi=64`
should produce an ELF64 as should `mips64-linux-gnu-clang -mabi=64`.
Conversely, `mips64-linux-gnu-clang -mabi=n32` should produce an ELF32 as
should `mips-linux-gnu-clang -mips64r2 -mabi=n32`.
This patch fixes the e_flags but leaves the ELF32 vs ELF64 issue for now
since there is no apparent way to base this decision on the ABI and CPU.
Differential Revision: http://reviews.llvm.org/D4539
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213244
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Daniel Sanders [Thu, 17 Jul 2014 09:57:23 +0000 (09:57 +0000)]
[mips] Correct .MIPS.abiflags for -mfpxx on MIPS32r6
Summary:
The cpr1_size field describes the minimum register width to run the program
rather than the size of the registers on the target. MIPS32r6 was acting
as if -mfp64 has been given because it starts off with 64-bit FPU registers.
Differential Revision: http://reviews.llvm.org/D4538
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213243
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Daniel Sanders [Thu, 17 Jul 2014 09:52:56 +0000 (09:52 +0000)]
[mips] Fix ELF e_flags related to -mabicalls and -mplt.
Summary:
These options are not implemented yet but we act as if they are always
given.
The integrated assembler is driven by the clang driver so the e_flag test
cases should match the e_flags emitted by GCC+GAS rather than GAS
by itself.
Differential Revision: http://reviews.llvm.org/D4536
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213242
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Yi Kong [Thu, 17 Jul 2014 09:43:27 +0000 (09:43 +0000)]
Fix the prefix for arm64 triple
Triple.cpp still returns "arm64" as prefix for arm64 triple, causing Clang not
being able to select the correct GCCBuiltin IR.
This patch changes the value to correct prefix "aarch64". Regression test will
be added in the coming patch.
Differential Revision: http://reviews.llvm.org/D4516
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213240
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Evgeniy Stepanov [Thu, 17 Jul 2014 09:10:37 +0000 (09:10 +0000)]
[msan] Avoid redundant origin stores.
Origin is meaningless for fully initialized values. Avoid
storing origin for function arguments that are known to
be always initialized (i.e. shadow is a compile-time null
constant).
This is not about correctness, but purely an optimization.
Seems to affect compilation time of blacklisted functions
significantly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213239
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Suyog Sarda [Thu, 17 Jul 2014 06:28:15 +0000 (06:28 +0000)]
Move ashr optimization from InstCombineShift to InstSimplify.
Refactor code, no functionality change, test case moved from instcombine to instsimplify.
Differential Revision: http://reviews.llvm.org/D4102
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213231
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Matt Arsenault [Thu, 17 Jul 2014 06:19:06 +0000 (06:19 +0000)]
Use range for
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213230
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Matt Arsenault [Thu, 17 Jul 2014 06:13:41 +0000 (06:13 +0000)]
R600: Short circuit alloca check if address space isn't private.
Skip calling GetUnderlyingObject in cases where it obviously
isn't from an alloca. This should only be a compile time improvement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213229
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Suyog Sarda [Thu, 17 Jul 2014 06:09:34 +0000 (06:09 +0000)]
Fix Typo (first commit to test commit access)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213228
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Eric Fiselier [Thu, 17 Jul 2014 05:53:00 +0000 (05:53 +0000)]
[lit] Add --show-unsupported flag to LIT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213227
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Saleem Abdulrasool [Thu, 17 Jul 2014 03:08:50 +0000 (03:08 +0000)]
MC: make WinEH opcode an opaque value
This makes the opcode an opaque value (unsigned int) rather than the
enumeration. This permits the use of target specific operands.
Split out the generic type into a MCWinEH header and add a supporting
MCWin64EH::Instruction to abstract out the selection of the opcode and
construction of the actual instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213221
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Hal Finkel [Thu, 17 Jul 2014 01:28:25 +0000 (01:28 +0000)]
Improve BasicAA CS-CS queries (redux)
This reverts, "r213024 - Revert r212572 "improve BasicAA CS-CS queries", it
causes PR20303." with a fix for the bug in pr20303. As it turned out, the
relevant code was both wrong and over-conservative (because, as with the code
it replaced, it would return the overall ModRef mask even if just Ref had been
implied by the argument aliasing results). Hopefully, this correctly fixes both
problems.
Thanks to Nick Lewycky for reducing the test case for pr20303 (which I've
cleaned up a little and added in DSE's test directory). The BasicAA test has
also been updated to check for this error.
Original commit message:
BasicAA contains knowledge of certain intrinsics, such as memcpy and memset,
and uses that information to form more-accurate answers to CallSite vs. Loc
ModRef queries. Unfortunately, it did not use this information when answering
CallSite vs. CallSite queries.
Generically, when an intrinsic takes one or more pointers and the intrinsic is
marked only to read/write from its arguments, the offset/size is unknown. As a
result, the generic code that answers CallSite vs. CallSite (and CallSite vs.
Loc) queries in AA uses UnknownSize when forming Locs from an intrinsic's
arguments. While BasicAA's CallSite vs. Loc override could use more-accurate
size information for some intrinsics, it did not do the same for CallSite vs.
CallSite queries.
This change refactors the intrinsic-specific logic in BasicAA into a generic AA
query function: getArgLocation, which is overridden by BasicAA to supply the
intrinsic-specific knowledge, and used by AA's generic implementation. This
allows the intrinsic-specific knowledge to be used by both CallSite vs. Loc and
CallSite vs. CallSite queries, and simplifies the BasicAA implementation.
Currently, only one function, Mac's memset_pattern16, is handled by BasicAA
(all the rest are intrinsics). As a side-effect of this refactoring, BasicAA's
getModRefBehavior override now also returns OnlyAccessesArgumentPointees for
this function (which is an improvement).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213219
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Jingyue Wu [Wed, 16 Jul 2014 23:25:00 +0000 (23:25 +0000)]
Partially revert r210444 due to performance regression
Summary:
Converting outermost zext(a) to sext(a) causes worse code when the
computation of zext(a) could be reused. For example, after converting
... = array[zext(a)]
... = array[zext(a) + 1]
to
... = array[sext(a)]
... = array[zext(a) + 1],
the program computes sext(a), which is actually unnecessary. I added one
test in split-gep-and-gvn.ll to illustrate this scenario.
Also, with r211281 and r211084, we annotate more "nuw" tags to
computation involving CUDA intrinsics such as threadIdx.x. These
annotations help with splitting GEP a lot, rendering the benefit we get
from this reverted optimization only marginal.
Test Plan: make check-all
Reviewers: eliben, meheff
Reviewed By: meheff
Subscribers: jholewinski, llvm-commits
Differential Revision: http://reviews.llvm.org/D4542
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213209
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Sanjay Patel [Wed, 16 Jul 2014 22:40:28 +0000 (22:40 +0000)]
Fixed formatting, removed bug reference, renamed testcase
Thanks to Duncan Exon Smith for reviewing and cleanup suggestions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213205
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Juergen Ributzka [Wed, 16 Jul 2014 22:20:51 +0000 (22:20 +0000)]
[FastISel] Local values shouldn't be alive across an inline asm call with side effects.
This fixes an issue where a local value is defined before and used after an
inline asm call with side effects.
This fix simply flushes the local value map, which updates the insertion point
for the inline asm call to be above any previously defined local values.
This fixes <rdar://problem/
17694203>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213203
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Lang Hames [Wed, 16 Jul 2014 22:02:20 +0000 (22:02 +0000)]
[MCJIT] Improve a RuntimeDyldChecker diagnostic.
When a RuntimeDyldChecker test requests an invalid operand for an instruction,
print the decoded instruction to aid diagnosis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213202
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Hal Finkel [Wed, 16 Jul 2014 21:22:46 +0000 (21:22 +0000)]
Fix a typo in the inalloca description
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213200
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Sanjay Patel [Wed, 16 Jul 2014 21:08:10 +0000 (21:08 +0000)]
trivial fix for PR20314
Make sure that the AddrInst is an Instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213197
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Sanjay Patel [Wed, 16 Jul 2014 20:18:49 +0000 (20:18 +0000)]
Remove Atom references in description.
Any CPU can run this pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213190
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Manuel Jacob [Wed, 16 Jul 2014 20:13:45 +0000 (20:13 +0000)]
Utilize CastInst::CreatePointerBitCastOrAddrSpaceCast here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213189
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Chris Bieneman [Wed, 16 Jul 2014 20:13:31 +0000 (20:13 +0000)]
[RegisterCoalescer] Moving the RegisterCoalescer subtarget hook onto the TargetRegisterInfo instead of the TargetSubtargetInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213188
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Justin Holewinski [Wed, 16 Jul 2014 19:45:35 +0000 (19:45 +0000)]
[NVPTX] Honor alignment on vector loads/stores
We were not considering the stated alignment on vector loads/stores,
leading us to generate vector instructions even when we do not have
sufficient alignment.
Now, for IR like:
%1 = load <4 x float>, <4 x float>* %ptr, align 4
we will generate correct, conservative PTX like:
ld.f32 ... [%ptr]
ld.f32 ... [%ptr+4]
ld.f32 ... [%ptr+8]
ld.f32 ... [%ptr+12]
Or if we have an alignment of 8 (for example), we can
generate code like:
ld.v2.f32 ... [%ptr]
ld.v2.f32 ... [%ptr+8]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213186
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Alexey Samsonov [Wed, 16 Jul 2014 18:11:31 +0000 (18:11 +0000)]
CHECK-LABEL-ize one test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213177
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Kevin Enderby [Wed, 16 Jul 2014 17:38:26 +0000 (17:38 +0000)]
Add the "-x" flag to llvm-nm for Mach-O files that prints the fields of a symbol in hex.
(generally use for debugging the tools). This is same functionality as darwin’s
nm(1) "-x" flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213176
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David Blaikie [Wed, 16 Jul 2014 17:09:21 +0000 (17:09 +0000)]
Remove unnecessary/redundant std::move
(run returns unique_ptr by value already)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213174
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Alp Toker [Wed, 16 Jul 2014 16:50:34 +0000 (16:50 +0000)]
Track clang r213171
The clang rewriter is now a core facility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213173
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Chris Bieneman [Wed, 16 Jul 2014 16:27:31 +0000 (16:27 +0000)]
Added documentation for SizeMultiplier in the ARM subtarget hook for register coalescing. Also fixed some 80 col violations.
No functional code changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213169
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Justin Holewinski [Wed, 16 Jul 2014 16:26:58 +0000 (16:26 +0000)]
[NVPTX] Rename registers %fl -> %fd and %rl -> %rd
This matches the internal behavior of NVIDIA tools like libnvvm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213168
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Tim Northover [Wed, 16 Jul 2014 15:37:24 +0000 (15:37 +0000)]
CodeGen: don't form illegail EXTLOAD operations.
It turns out that in most cases (the main exception being i1-related
types) once these operations are formed we cannot separate them and
the targets end up having to deal with them whether they want to or
not.
This is not a good situation, and a more reasonable default can be
formed by ackowledging this and having targets leave them as Legal.
Only x86 seems to be affected (other targets don't even try marking
the operation Expand).
Mostly there's no visible change here yet, but it will be useful to
have truly expanded EXTLOADS for MVT::f16 softening support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213162
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Tim Northover [Wed, 16 Jul 2014 15:37:08 +0000 (15:37 +0000)]
Convert test to CHECK-LABEL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213161
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Daniel Sanders [Wed, 16 Jul 2014 15:34:07 +0000 (15:34 +0000)]
[mips][fp64a] Temporarily disable odd-numbered double-precision registers when using the FP64A ABI.
Summary:
A few instructions (mostly cvt.d.w and similar) are causing problems with
-mfp64 and -mno-odd-spreg and it looks like fixing it properly may
take several weeks. In the meantime, let's disable the odd-numbered
double-precision registers so that the generated code is at least valid.
The problem is that instructions like cvt.d.w read from the 32-bit low
subregister of a double-precision FPU register. This often leads to the compiler
to inserting moves to transfer a GPR32 to a FGR32 using mtc1. Such moves
violate the rules against 32-bit writes to odd-numbered FPU registers imposed
by -mno-odd-spreg. By disabling the odd-numbered double-precision registers, it
becomes impossible for the 32-bit low subregister to be odd-numbered.
This fixes numerous test-suite failures when compiling for the FP64A ABI
('-mfp64 -mno-odd-spreg'). There is no LLVM test case because it's difficult to
test that odd-numbered FPU registers are not allocatable. Instead, we depend on
the assembler (GAS and -fintegrated-as) raising errors when the rules are
violated.
Differential Revision: http://reviews.llvm.org/D4532
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213160
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Andrea Di Biagio [Wed, 16 Jul 2014 11:29:39 +0000 (11:29 +0000)]
[X86] Add a check for 'isMOVHLPSMask' within method 'isShuffleMaskLegal'.
Before this change, method 'isShuffleMaskLegal' didn't know that shuffles
implementing a 'movhlps' operation were perfectly legal for SSE targets.
This patch adds the missing check for 'isMOVHLPSMask' inside method
'isShuffleMaskLegal' to fix the problem.
The reason why it is important to do this is because the DAGCombiner
conservatively avoids combining a pair of shuffles if the resulting shuffle
node has an illegal mask. Before this patch, shuffles with a MOVHLPS mask were
wrongly considered not to be legal. This was the root cause of some poor-code
generation bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213137
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Justin Bogner [Wed, 16 Jul 2014 08:18:58 +0000 (08:18 +0000)]
unittests: Actually test reverse iterators in Path tests
This re-enables some #if 0'd code (since 2010) in the Path unittests
and makes at least a weak effort at testing sys::path's rbegin/rend.
This change was inspired by some test failures near uses of rbegin and
rend here:
http://lab.llvm.org:8011/builders/clang-x86_64-linux-vg/builds/3209
The "valgrind was whining" comment looked promising in terms of a
simpler to debug case of the same errors. However, it appears that the
valgrind complaints the comment was referring to are distinct from the
ones in the frontend, since this updated test isn't complaining for me
under valgrind.
In any case, the disabled tests weren't helping anybody.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213125
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Reid Kleckner [Wed, 16 Jul 2014 01:34:27 +0000 (01:34 +0000)]
Roundtrip the inalloca bit on allocas through bitcode
This was an oversight in the original support. As it is, I stuffed this
bit into the alignment. The alignment is stored in log2 form, so it
doesn't need more than 5 bits, given that Value::MaximumAlignment is 1
<< 29.
Reviewers: nicholas
Differential Revision: http://reviews.llvm.org/D3943
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213118
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Manuel Jacob [Wed, 16 Jul 2014 01:34:21 +0000 (01:34 +0000)]
Fix comment in InstCombiner::visitAddrSpaceCast.
In the original version of the patch the behaviour was like described in
the comment. This behaviour was changed before committing it without
updating the comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213117
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Hans Wennborg [Wed, 16 Jul 2014 00:52:11 +0000 (00:52 +0000)]
Perform wildcard expansion in Process::GetArgumentVector on Windows (PR17098)
On Windows, wildcard expansion isn't performed by the shell, but left to the
program itself. The common way to do this is to link with setargv.obj, which
performs the expansion on argc/argv before main is entered. However, we don't
use argv in Clang on Windows, but instead call GetCommandLineW so we can handle
unicode arguments. This means we have to do wildcard expansion ourselves.
A test case will be added on the Clang side.
Differential Revision: http://reviews.llvm.org/D4529
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213114
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Tyler Nowicki [Wed, 16 Jul 2014 00:36:00 +0000 (00:36 +0000)]
Emit warnings if vectorization is forced and fails.
This patch modifies the existing DiagnosticInfo system to create a generic base
class that is inherited to produce diagnostic-based warnings. This is used by
the loop vectorizer to trigger a warning when vectorization is forced and
fails. Several tests have been added to verify this behavior.
Reviewed by: Arnold Schwaighofer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213110
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Juergen Ributzka [Wed, 16 Jul 2014 00:01:22 +0000 (00:01 +0000)]
Remove TLI from isInTailCallPosition's arguments. NFC.
There is no need to pass on TLI separately to the function. As Eric pointed out
the Target Machine already provides everything we need.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213108
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Matt Arsenault [Tue, 15 Jul 2014 23:50:10 +0000 (23:50 +0000)]
R600/SI: Allow using f32 rcp / rsq when denormals not handled.
These are precise enough to use for OpenCL unless denormals
are handled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213107
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David Majnemer [Tue, 15 Jul 2014 23:01:10 +0000 (23:01 +0000)]
X86: Simplify X86WindowsTargetObjectFile::getSectionForConstant
There exists a helper function to abstract away the various differences
between ConstantVector, ConstantDataVector, ConstantAggregateZero, etc.
Use it to simplify X86WindowsTargetObjectFile::getSectionForConstant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213104
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Sanjay Patel [Tue, 15 Jul 2014 22:39:58 +0000 (22:39 +0000)]
Move Post RA Scheduling flag bit into SchedMachineModel
Refactoring; no functional changes intended
Removed PostRAScheduler bits from subtargets (X86, ARM).
Added PostRAScheduler bit to MCSchedModel class.
This bit is set by a CPU's scheduling model (if it exists).
Removed enablePostRAScheduler() function from TargetSubtargetInfo and subclasses.
Fixed the existing enablePostMachineScheduler() method to use the MCSchedModel (was just returning false!).
Added methods to TargetSubtargetInfo to allow overrides for AntiDepBreakMode, CriticalPathRCs, and OptLevel for PostRAScheduling.
Added enablePostRAScheduler() function to PostRAScheduler class which queries the subtarget for the above values.
Preserved existing scheduler behavior for ARM, MIPS, PPC, and X86:
a. ARM overrides the CPU's postRA settings by enabling postRA for any non-Thumb or Thumb2 subtarget.
b. MIPS overrides the CPU's postRA settings by enabling postRA for everything.
c. PPC overrides the CPU's postRA settings by enabling postRA for everything.
d. X86 is the only target that actually has postRA specified via sched model info.
Differential Revision: http://reviews.llvm.org/D4217
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213101
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Peter Collingbourne [Tue, 15 Jul 2014 22:13:19 +0000 (22:13 +0000)]
[dfsan] Introduce further optimization to reduce the number of union queries.
Specifically, do not compute a union if it is statically known that one
shadow set subsumes the other.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213100
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Alp Toker [Tue, 15 Jul 2014 22:11:54 +0000 (22:11 +0000)]
CMake: avoid a reconfigure loop from r213091
Removing the native CMakeCache.txt causes the target to get re-run needlessly
on some systems. We'll want another solution for that part of the fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213099
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Matt Arsenault [Tue, 15 Jul 2014 21:44:37 +0000 (21:44 +0000)]
R600/SI: Fix select on i1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213096
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David Blaikie [Tue, 15 Jul 2014 21:06:37 +0000 (21:06 +0000)]
Try out FileCheck's new (in r212810) -implicit-check-not in a DebugInfo test.
Just tried this on a few tests and this was the only one that was
easily ported to use the new feature, so we'll go with that for now.
Hopefully can act as inspiration/reminder for other tests.
Not all debug info tests need to check for every DW_TAG or NULL child
terminator, but perhaps they should (just to ensure they don't accidentally
end up with tags nested inside other tags without the test failing, for example)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213092
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Alp Toker [Tue, 15 Jul 2014 21:04:12 +0000 (21:04 +0000)]
CMake: fix cross-compilation with external source directories
This adds support for building native artifacts when cross-compiling using the
popular side-by-side source directory layout (no symlinks, no nested
repositories).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213091
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Duncan P. N. Exon Smith [Tue, 15 Jul 2014 20:24:56 +0000 (20:24 +0000)]
ADT: Add MapVector::remove_if
Add a `MapVector::remove_if()` that erases items in bulk in linear time,
as opposed to quadratic time for repeated calls to `MapVector::erase()`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213090
91177308-0d34-0410-b5e6-
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Matt Arsenault [Tue, 15 Jul 2014 20:18:31 +0000 (20:18 +0000)]
R600/SI: Implement less wrong f32 fdiv
Assuming single precision denormals and accurate sqrt/div are not
reported, this passes the OpenCL conformance test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213089
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Matt Arsenault [Tue, 15 Jul 2014 20:18:24 +0000 (20:18 +0000)]
R600: Add predicate for UnsafeFPMath
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213088
91177308-0d34-0410-b5e6-
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Matt Arsenault [Tue, 15 Jul 2014 20:10:27 +0000 (20:10 +0000)]
R600: Remove intrinsics that appear to be unused
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213087
91177308-0d34-0410-b5e6-
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Lang Hames [Tue, 15 Jul 2014 19:35:22 +0000 (19:35 +0000)]
[RuntimeDyld] Revert r211652 - MachO object GDB registration support.
The registration scheme used in r211652 violated the read-only contract of
MemoryBuffer. This caused crashes in llvm-rtdyld where macho objects were backed
by read-only mmap'd memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213086
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Duncan P. N. Exon Smith [Tue, 15 Jul 2014 18:32:30 +0000 (18:32 +0000)]
ADT: Fix MapVector::erase()
Actually update the changed indexes in the map portion of `MapVector`
when erasing from the middle. Add a unit test that checks for this.
Note that `MapVector::erase()` is a linear time operation (it was and
still is). I'll commit a new method in a moment called
`MapVector::remove_if()` that deletes multiple entries in linear time,
which should be slightly less painful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213084
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Duncan P. N. Exon Smith [Tue, 15 Jul 2014 18:06:56 +0000 (18:06 +0000)]
ADT: Add "end namespace" comment
This keeps clang-format from deleting the preceding newline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213082
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Chris Bieneman [Tue, 15 Jul 2014 17:18:41 +0000 (17:18 +0000)]
[RegisterCoalescer] Add new subtarget hook allowing targets to opt-out of coalescing.
The coalescer is very aggressive at propagating constraints on the register classes, and the register allocator doesn’t know how to split sub-registers later to recover. This patch provides an escape valve for targets that encounter this problem to limit coalescing.
This patch also implements such for ARM to lower register pressure when using lots of large register classes. This works around PR18825.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213078
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Tilmann Scheller [Tue, 15 Jul 2014 16:33:24 +0000 (16:33 +0000)]
[AArch64] Add negative tests for the SIMD & FP LDP instructions.
LDP is unpredictable if the registers in the pair are identical, these tests check that we don't assemble instructions like that and error out instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213074
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Cameron McInally [Tue, 15 Jul 2014 16:24:24 +0000 (16:24 +0000)]
Revert r213070. It's breaking the build in MCELFStreamer::EmitInstToData(...).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213073
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Jan Vesely [Tue, 15 Jul 2014 15:51:09 +0000 (15:51 +0000)]
R600: Implement zero undef variants of ctlz/cttz
v2: use ffbh/l if available
v3: Rebase on top of Matt's SI patches
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <tom@stellard.net>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213072
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Daniel Sanders [Tue, 15 Jul 2014 15:31:39 +0000 (15:31 +0000)]
[mips] Correct .MIPS.abiflags fp_abi field for -mfpxx and without .module
Summary: Previously all the test cases set it after initialization with '.module fp=xx'.
Differential Revision: http://reviews.llvm.org/D4489
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213071
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Cameron McInally [Tue, 15 Jul 2014 15:03:32 +0000 (15:03 +0000)]
Add x86 patterns to match a specific add-with-carry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213070
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Andrea Di Biagio [Tue, 15 Jul 2014 13:26:28 +0000 (13:26 +0000)]
[DAGCombiner] Add more rules to fold shuffles.
This patch adds two new rules to the DAGCombiner:
1. shuffle (shuffle A, Undef, M0), B, M1 -> shuffle A, B, M2
2. shuffle (shuffle A, Undef, M0), A, M1 -> shuffle A, Undef, M2
We only do this if the combined shuffle is legal for the target.
Example:
;;
define <4 x float> @test(<4 x float> %a, <4 x float> %b) {
%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32><i32 6, i32 0, i32 1, i32 7>
%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32><i32 1, i32 2, i32 4, i32 5>
ret <4 x i32> %2
}
;;
(using llc -mcpu=corei7 -march=x86-64)
Before, the x86 backend generated:
pshufd $120, %xmm0, %xmm0
shufps $-108, %xmm0, %xmm1
movaps %xmm1, %xmm0
Now the x86 backend generates:
movsd %xmm1, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213069
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NAKAMURA Takumi [Tue, 15 Jul 2014 11:37:03 +0000 (11:37 +0000)]
Prune Redundant libdeps in CMake's target_link_libraries and LLVMBuild.txt.
I checked this with Release+Asserts on x86_64-mingw32. Please restore partially if this were overkill.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213064
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Andrea Di Biagio [Tue, 15 Jul 2014 10:53:44 +0000 (10:53 +0000)]
Silence a warning in conditional expression.
Fixes a gcc warning caused by a typo. A redundant assignment operation was
accidentally used as the third operand of a conditional expression.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213061
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Stepan Dyatkovskiy [Tue, 15 Jul 2014 10:46:51 +0000 (10:46 +0000)]
MergeFunc patch from Björn Steinbrink.
Phabricator ticket: D4246, Don't merge functions with different range metadata on call/invoke.
Thanks!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213060
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Tim Northover [Tue, 15 Jul 2014 10:00:26 +0000 (10:00 +0000)]
AArch64: fall back to generic code for out of range extract/insert.
rdar://problem/
17624784
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213059
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David Majnemer [Tue, 15 Jul 2014 07:11:32 +0000 (07:11 +0000)]
Fix typo in comment
No functionality changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213052
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Juergen Ributzka [Tue, 15 Jul 2014 06:35:53 +0000 (06:35 +0000)]
[FastISel][X86] Remove no longer needed functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213051
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Juergen Ributzka [Tue, 15 Jul 2014 06:35:50 +0000 (06:35 +0000)]
[FastISel][X86] Implement the FastLowerIntrinsicCall hook.
Rename X86VisitIntrinsicCall -> FastLowerIntrinsicCall, which effectively
implements the target hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213050
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Juergen Ributzka [Tue, 15 Jul 2014 06:35:47 +0000 (06:35 +0000)]
[FastISel][X86] Implement the FastLowerCall hook.
This implements the FastLowerCall hook, which is based on the DoSelectCall
function. The implementation is very similar, but the target-independent call
lowering part has been factored out.
This should also enable patchpoint intrinsic lowering for FastISel on X86.
Related to <rdar://problem/
17427052>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213049
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Juergen Ributzka [Tue, 15 Jul 2014 05:23:40 +0000 (05:23 +0000)]
Revert "[FastISel][X86] Remove no longer needed functions."
Revert "[FastISel][X86] Implement the FastLowerIntrinsicCall hook."
Revert "[FastISel][X86] Implement the FastLowerCall hook."
This reverts commit r213035, r213036, and r213037 to make the
buildbots happy again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213048
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Peter Collingbourne [Tue, 15 Jul 2014 04:41:17 +0000 (04:41 +0000)]
[dfsan] Introduce an optimization to reduce the number of union queries.
Specifically, when building a union query, if we are dominated by an identical
query then use the result of that query instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213047
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Peter Collingbourne [Tue, 15 Jul 2014 04:41:14 +0000 (04:41 +0000)]
[dfsan] Move combineShadows to DFSanFunction in preparation for it to use a domtree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213046
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Peter Collingbourne [Tue, 15 Jul 2014 04:40:27 +0000 (04:40 +0000)]
Give SplitBlockAndInsertIfThen the ability to update a domtree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213045
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David Majnemer [Tue, 15 Jul 2014 03:00:41 +0000 (03:00 +0000)]
Some targets don't prefix private symbols with dot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213042
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David Majnemer [Tue, 15 Jul 2014 03:00:39 +0000 (03:00 +0000)]
Specify a more specific triple for constant-pool-remat-0.ll
Instead of specifying 32-bit x86, specify 32-bit x86 linux.
This test is testing a very specific behavior which changed with
WinCOFF's constant pools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213041
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David Majnemer [Tue, 15 Jul 2014 02:44:49 +0000 (02:44 +0000)]
Relax tests expecting to see CPI symbols
WinCOFF doesn't use CPI symbols, it has a different scheme for naming
constant pool entries. Update tests to handle either appearing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213039
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David Majnemer [Tue, 15 Jul 2014 02:34:12 +0000 (02:34 +0000)]
CodeGen: Handle ConstantVector and undef in WinCOFF constant pools
The constant pool entry code for WinCOFF assumed that vector constants
would be formed using ConstantDataVector, it did not expect to see a
ConstantVector. Furthermore, it did not expect undef as one of the
elements of the vector.
ConstantVectors should be handled like ConstantDataVectors, treat Undef
as zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213038
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Juergen Ributzka [Tue, 15 Jul 2014 02:22:56 +0000 (02:22 +0000)]
[FastISel][X86] Remove no longer needed functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213037
91177308-0d34-0410-b5e6-
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Juergen Ributzka [Tue, 15 Jul 2014 02:22:53 +0000 (02:22 +0000)]
[FastISel][X86] Implement the FastLowerIntrinsicCall hook.
Rename X86VisitIntrinsicCall -> FastLowerIntrinsicCall, which effectively
implements the target hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213036
91177308-0d34-0410-b5e6-
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Juergen Ributzka [Tue, 15 Jul 2014 02:22:49 +0000 (02:22 +0000)]
[FastISel][X86] Implement the FastLowerCall hook.
This implements the FastLowerCall hook, which is based on the DoSelectCall
function. The implementation is very similar, but the target-independent call
lowering part has been factored out.
This should also enable patchpoint intrinsic lowering for FastISel on X86.
Related to <rdar://problem/
17427052>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213035
91177308-0d34-0410-b5e6-
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Juergen Ributzka [Tue, 15 Jul 2014 02:22:46 +0000 (02:22 +0000)]
[FastISel] Insert patchpoint instruction before the target generated call instruction.
The patchpoint instruction should have been inserted before the target
generated call instruction to be inside the ADJSTACKDOWN/ADJSTACKUP call
sequence window.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213034
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Juergen Ributzka [Tue, 15 Jul 2014 02:22:43 +0000 (02:22 +0000)]
[FastISel] Fix patchpoint lowering to set the result register.
Always update the value map with the result register (if there is one), for the
patchpoint instruction we created to replace the target-specific call
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213033
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Matt Arsenault [Tue, 15 Jul 2014 02:06:31 +0000 (02:06 +0000)]
R600: Add dag combine for copy of an illegal type.
This helps avoid redundant instructions to unpack, and repack
the vectors. Ideally we could recognize that pattern and eliminate
it. Currently v4i8 and other small element type vectors are scalarized,
so this has the added bonus of avoiding that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213031
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Matt Arsenault [Tue, 15 Jul 2014 01:55:03 +0000 (01:55 +0000)]
Teach computeKnownBits to look through addrspacecast.
This fixes inferring alignment through an addrspacecast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213030
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Andrea Di Biagio [Tue, 15 Jul 2014 01:29:27 +0000 (01:29 +0000)]
Improve test 'CodeGen/X86/combine-vec-shuffle-3.ll'.
Now functions 'test4', 'test9', 'test14' and 'test19' correctly perform
a move of two packed values from the high quadword of vector %b to the low
quadword of vector %a (movhlps idiom).
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213029
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Reid Kleckner [Tue, 15 Jul 2014 01:16:09 +0000 (01:16 +0000)]
Document the maximum LLVM IR alignment, which is 1 << 29 or 0.5 GiB
Add verifier checks. We already check these in the assembly parser, but
a frontend producing IR in memory wouldn't hit those checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213027
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Matt Arsenault [Tue, 15 Jul 2014 00:56:40 +0000 (00:56 +0000)]
Teach GetUnderlyingObject / BasicAA about addrspacecast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213025
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Nick Lewycky [Tue, 15 Jul 2014 00:53:38 +0000 (00:53 +0000)]
Revert r212572 "improve BasicAA CS-CS queries", it causes PR20303.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213024
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Matt Arsenault [Tue, 15 Jul 2014 00:07:27 +0000 (00:07 +0000)]
Convert test to FileCheck.
Check the individual test functions for more useful failure errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213021
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Andrea Di Biagio [Tue, 15 Jul 2014 00:02:32 +0000 (00:02 +0000)]
[DAGCombiner] Avoid calling method 'isShuffleMaskLegal' on illegal vector types.
This patch fixes a crasher in method 'DAGCombiner::visitOR' due to an invalid
call to method 'isShuffleMaskLegal'. On x86, method 'isShuffleMaskLegal'
always expects a legal vector value type in input.
With this patch, we immediately check if the input OR dag node has a legal
vector type; we only try to fold a OR dag node into a single shufflevector
if we know that the resulting shuffle will have a legal type.
This is to avoid calling method 'isShuffleMaskLegal' on a potentially
illegal vector value type.
Added a new test-case to file 'CodeGen/X86/combine-or.ll' to verify that
DAGCombiner doesn't crash in the attempt to check/combine an OR between shuffles
with illegal types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213020
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Matt Arsenault [Mon, 14 Jul 2014 23:40:49 +0000 (23:40 +0000)]
R600: Add denormal handling subtarget features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213018
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Matt Arsenault [Mon, 14 Jul 2014 23:40:43 +0000 (23:40 +0000)]
R600/SI: Default to no single precision denormals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213017
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Alp Toker [Mon, 14 Jul 2014 23:30:31 +0000 (23:30 +0000)]
Revert "Revert "Move clang feature flags settings out of LLVM core and into cfe""
It turns out this commit was fine. The problem was in the legacy build system (fixed r213010).
This reverts commit r213005.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213015
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Lang Hames [Mon, 14 Jul 2014 23:19:50 +0000 (23:19 +0000)]
[RuntimeDyld] Handle endiannes differences between the host and target while
reading MachO files magic numbers in RuntimeDyld.
This is required now that we're testing cross-platform JITing (via
RuntimeDyldChecker), and should fix some issues that David Fang has seen on PPC
builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213012
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Adam Nemet [Mon, 14 Jul 2014 23:18:39 +0000 (23:18 +0000)]
[X86] Specify all TSFlags bit-offsets symbolically
No functional change.
The offsets for the other bitfields are specified symbolically. I need to
increase the size for one of the earlier fields which is easier after this
cleanup.
Why these bits are relative to VEXShift is a bit strange but that is for
another cleanup.
I made sure that the values for the enums are unchanged after this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213011
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David Majnemer [Mon, 14 Jul 2014 22:57:27 +0000 (22:57 +0000)]
CodeGen: Stick constant pool entries in COMDAT sections for WinCOFF
COFF lacks a feature that other object file formats support: mergeable
sections.
To work around this, MSVC sticks constant pool entries in special COMDAT
sections so that each constant is in it's own section. This permits
unused constants to be dropped and it also allows duplicate constants in
different translation units to get merged together.
This fixes PR20262.
Differential Revision: http://reviews.llvm.org/D4482
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213006
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Alp Toker [Mon, 14 Jul 2014 22:54:22 +0000 (22:54 +0000)]
Revert "Move clang feature flags settings out of LLVM core and into cfe"
This broke one of the builds, presumably side-by-side modular CMake.
Investigating.
This reverts commit r212998.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213005
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Alp Toker [Mon, 14 Jul 2014 22:46:45 +0000 (22:46 +0000)]
Fix a -Wunused-local-typedefs warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213002
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Andrea Di Biagio [Mon, 14 Jul 2014 22:46:26 +0000 (22:46 +0000)]
[DAGCombiner] Add more rules to combine shuffle vector dag nodes.
This patch teaches the DAGCombiner how to fold a pair of shuffles
according to rules:
1. shuffle(shuffle A, B, M0), B, M1) -> shuffle(A, B, M2)
2. shuffle(shuffle A, B, M0), A, M1) -> shuffle(A, B, M3)
The new rules would only trigger if the resulting shuffle has legal type and
legal mask.
Added test 'combine-vec-shuffle-3.ll' to verify that DAGCombiner correctly
folds shuffles on x86 when the resulting mask is legal. Also added some negative
cases to verify that we avoid introducing illegal shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213001
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