OSDN Git Service
Brian Paul [Wed, 27 Apr 2016 16:42:39 +0000 (10:42 -0600)]
mesa: improve comment on _mesa_check_disallowed_mapping(), return bool
The old comment was a bit terse. Also, change the function return
type to bool.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Marek Olšák [Fri, 22 Apr 2016 08:18:17 +0000 (10:18 +0200)]
radeonsi: remove needless cache flushes at the end of CP DMA operations
not needed AFAIK
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 22 Apr 2016 08:16:14 +0000 (10:16 +0200)]
radeonsi: remove flushes at the beginning and end of IBs done by the kernel
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Samuel Iglesias Gonsálvez [Tue, 26 Apr 2016 07:35:30 +0000 (09:35 +0200)]
nir: Add lrp lowering for doubles in opt_algebraic
Some hardware (i965 on Broadwell generation, for example) does not support
natively the execution of lrp instruction with double arguments.
Add 'lower_flrp64' flag to lower this instruction in that case.
v2:
- Rename lower_flrp_double to lower_flrp64 (Jason)
- Fix typo (Jason)
- Adapt the code to define bit_size information in the opcodes.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Samuel Iglesias Gonsálvez [Thu, 28 Apr 2016 05:13:10 +0000 (07:13 +0200)]
nir: rename lower_flrp to lower_flrp32
A later patch will add lower_flrp64 option to NIR.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Iago Toral Quiroga [Tue, 5 Jan 2016 09:32:49 +0000 (10:32 +0100)]
nir/lower_double_ops: lower round_even()
At least i965 hardware does not have native support for round_even() on doubles.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Tue, 5 Jan 2016 08:14:51 +0000 (09:14 +0100)]
nir/lower_double_ops: lower fract()
At least i965 hardware does not have native support for fract() on doubles.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Iago Toral Quiroga [Mon, 4 Jan 2016 15:10:11 +0000 (16:10 +0100)]
nir/lower_double_ops: lower ceil()
At least i965 hardware does not have native support for ceil on doubles.
v2 (Sam):
- Improve the lowering pass to remove one bcsel (Jason).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Iago Toral Quiroga [Mon, 4 Jan 2016 15:02:47 +0000 (16:02 +0100)]
nir/lower_double_ops: lower floor()
At least i965 hardware does not have native support for floor on doubles.
v2 (Sam):
- Improve the lowering pass to remove one bcsel (Jason)
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Iago Toral Quiroga [Mon, 4 Jan 2016 11:52:14 +0000 (12:52 +0100)]
nir/lower_double_ops: lower trunc()
At least i965 hardware does not have native support for truncating doubles.
v2:
- Simplified the implementation significantly.
- Fixed the else branch, that was not doing what we wanted.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Connor Abbott [Fri, 31 Jul 2015 18:57:48 +0000 (11:57 -0700)]
nir: add a pass to lower some double operations
v2: Move to compiler/nir (Iago)
v3: Use nir_imm_int() to load the constants (Sam)
v4 (Sam):
- Undo line-wrap (Jason).
- Fix comment (Jason).
- Improve generated code for get_signed_inf() function (Connor).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Connor Abbott [Fri, 31 Jul 2015 17:52:04 +0000 (10:52 -0700)]
nir/builder: add nir_imm_double()
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Samuel Iglesias Gonsálvez [Wed, 23 Mar 2016 09:43:03 +0000 (10:43 +0100)]
nir/builder: Add bit_size info to nir_build_imm()
v2:
- Group num_components and bit_size together (Jason)
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jakob Sinclair [Mon, 25 Apr 2016 07:03:52 +0000 (09:03 +0200)]
radeonsi: check if value is negative
Fixes a Coverity defect by adding checks to see if a value is negative
before using it to index an array. By checking the value first it makes
the code a bit safer but overall should not have a big impact.
CID:
1355598
Signed-off-by: Jakob Sinclair <sinclair.jakob@openmailbox.org>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Michel Dänzer [Thu, 28 Apr 2016 03:57:03 +0000 (12:57 +0900)]
clover: Fix build against clang SVN >= r267772
(Re-pushing previous fix for clang SVN r265359, which was reverted in
the meantime)
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Lars Hamre [Sun, 17 Apr 2016 17:18:32 +0000 (13:18 -0400)]
glsl: fix lowering outputs for early/nested returns
Return statements in conditional blocks were not having their
output varyings lowered correctly.
This patch fixes the following piglit tests:
/spec/glsl-1.10/execution/vs-float-main-return
/spec/glsl-1.10/execution/vs-vec2-main-return
/spec/glsl-1.10/execution/vs-vec3-main-return
Signed-off-by: Lars Hamre <chemecse@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Connor Abbott [Fri, 8 Apr 2016 06:11:44 +0000 (02:11 -0400)]
nir: rewrite nir_foreach_block and friends
Previously, these were functions which took a callback. This meant that
the per-block code had to be in a separate function, and all the data
that you wanted to pass in had to be a single void *. They walked the
control flow tree recursively, doing a depth-first search, and called
the callback in a preorder, matching the order of the original source
code. But since each node in the control flow tree has a pointer to its
parent, we can implement a "get-next" and "get-previous" method that
does the same thing that the recursive function did with no state at
all. This lets us rewrite nir_foreach_block() as a simple for loop,
which lets us greatly simplify its users in some cases. This does
require us to rewrite every user, although the transformation from the
old nir_foreach_block() to the new nir_foreach_block() is mostly
trivial.
One subtlety, though, is that the new nir_foreach_block() won't handle
the case where the current block is deleted, which the old one could.
There's a new nir_foreach_block_safe() which implements the standard
trick for solving this. Most users don't modify control flow, though, so
they won't need it. Right now, only opt_select_peephole needs it.
The old functions are reimplemented in terms of the new macros, although
they'll go away after everything is converted.
v2: keep an implementation of the old functions around
v3 (Jason Ekstrand): A small cosmetic change and a bugfix in the loop
handling of nir_cf_node_cf_tree_last().
v4 (Jason Ekstrand): Use the _safe macro in foreach_block_reverse_call
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Connor Abbott [Tue, 12 Apr 2016 18:52:43 +0000 (14:52 -0400)]
nir/opt_cp: use nir_block_get_following_if()
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jordan Justen [Mon, 25 Apr 2016 23:09:21 +0000 (16:09 -0700)]
vbo: Return INVALID_OPERATION during draw with a mapped buffer
Fixes the OpenGLES 3.1 CTS:
* ESEXT-CTS.draw_elements_base_vertex_tests.invalid_mapped_bos
Because this is triggering the error message after the normal API
validation phase, we don't have the API function name available, and
therefore we generate an error message without the draw call name:
Mesa: User error: GL_INVALID_OPERATION in draw call (vertex buffers are mapped)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95142
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nanley Chery [Fri, 15 Apr 2016 00:14:14 +0000 (17:14 -0700)]
anv/formats: Return proper error code for unsupported formats
Fixes some failures in dEQP-VK.api.info.image_format_properties.* and
enables the test group to execute without assert failing.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94896
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Fri, 15 Apr 2016 20:36:31 +0000 (13:36 -0700)]
anv/device: Set the compressed texture feature flags correctly
Sampling from an ETC2 texture is supported on Bay Trail and
from Gen8 onwards. While ASTC_LDR is supported on Gen9, the
logic to handle such formats has not yet been implemented in
the driver.
Fixes dEQP-VK.api.info.format_properties.compressed_formats.
v2: Enable ETC2 for Bay Trail (Kenneth Graunke)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94896
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 26 Apr 2016 03:58:47 +0000 (20:58 -0700)]
nir/algebraic: Add a bit-size validator
This commit adds a validator that ensures that all expressions passed
through nir_algebraic are 100% non-ambiguous as far as bit-sizes are
concerned. This way it's a compile-time error rather than a hard-to-trace
C exception some time later.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Jason Ekstrand [Tue, 26 Apr 2016 03:59:06 +0000 (20:59 -0700)]
nir/opt_algebraic: Fix some expressions with ambiguous bit sizes
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Mon, 25 Apr 2016 19:41:44 +0000 (12:41 -0700)]
nir/search: Respect the bit_size parameter on nir_search_value
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Mon, 25 Apr 2016 19:23:38 +0000 (12:23 -0700)]
nir/algebraic: Add a mechanism for specifying the bit size of a value
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Mon, 25 Apr 2016 19:00:12 +0000 (12:00 -0700)]
nir/algebraic: Use "uint" instead of "unsigned" for uint types
This is consistent with the rename done for the rest of NIR. Currently,
"bool" is the only type specifier used in nir_opt_algebraic.py so this is
really a no-op.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Mon, 25 Apr 2016 18:36:08 +0000 (11:36 -0700)]
nir/algebraic: Do better error reporting of bad expressions
Previously, if an exception was encountered anywhere, nir_algebraic would
just die in a fire with no indication whatsoever as to where the actual bug
is. This commit makes it print out the particular search-and-replace
expression that is causing problems along with the exception. Also, it
will now report all of the errors it finds and then exit at the end like a
standard C compiler would do.
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Alejandro Piñeiro [Wed, 27 Apr 2016 17:54:40 +0000 (19:54 +0200)]
isl: move -lm at the end of tests_ldadd
The test was failing to build with "undefined reference to `roundf'" errors,
so Make check on mesa was failing.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Topi Pohjolainen [Wed, 27 Apr 2016 09:53:39 +0000 (12:53 +0300)]
i965/blorp/gen8: Fix blitting of interleaved msaa surfaces
Fixes ES31-CTS.gtf.GL31Tests.texture_stencil8.texture_stencil8_multisample.
Current logic divides given layer of one by number of samples (four)
trashing the layer to zero. Layer adjustment is only to be used with
non-interleaved msaa surfaces where samples for particular layer are
in multiple slices.
I copy-pasted a bit of documentation from
brw_blorp.c::brw_blorp_compute_tile_offsets().
Also took the opportunity to fix the comment regarding sampling
as 2D, cube textures are the only exception.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Brian Paul [Mon, 25 Apr 2016 22:00:31 +0000 (16:00 -0600)]
llvmpipe: s/Elements/ARRAY_SIZE/
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Brian Paul [Mon, 25 Apr 2016 21:59:07 +0000 (15:59 -0600)]
tgsi: s/Elements/ARRAY_SIZE/
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Brian Paul [Mon, 25 Apr 2016 21:58:10 +0000 (15:58 -0600)]
os: s/Elements/ARRAY_SIZE/
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Brian Paul [Mon, 25 Apr 2016 21:57:05 +0000 (15:57 -0600)]
hud: s/Elements/ARRAY_SIZE/
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Brian Paul [Mon, 25 Apr 2016 21:56:08 +0000 (15:56 -0600)]
gallivm: s/Elements/ARRAY_SIZE/
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Brian Paul [Mon, 25 Apr 2016 21:55:01 +0000 (15:55 -0600)]
draw: s/Elements/ARRAY_SIZE/
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Brian Paul [Mon, 25 Apr 2016 21:53:04 +0000 (15:53 -0600)]
softpipe: s/Elements/ARRAY_SIZE/
Try to standardize on the later, which is defined in the common util/
directory.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Nicolai Hähnle [Sat, 23 Apr 2016 03:58:38 +0000 (22:58 -0500)]
winsys/radeon: remove use_reusable_pool parameter from buffer_create
All callers set this parameter to true.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Sat, 23 Apr 2016 03:56:13 +0000 (22:56 -0500)]
gallium/radeon: remove use_reusable_pool parameter from r600_init_resource
All callers set it to true.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Sat, 23 Apr 2016 03:50:19 +0000 (22:50 -0500)]
radeon/video: always use the reusable buffer pool
A semantic error was introduced in a past refactoring that caused the bind
parameter to be passed into the use_reusable_pool parameter of buffer_create.
Since this clearly makes no sense, and there is no clear reason why the
cache _shouldn't_ be used, just use the cache always.
Cc: Christian König <christian.koenig@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 22 Apr 2016 22:28:46 +0000 (17:28 -0500)]
radeonsi: work around an MSAA fast stencil clear problem
A piglit test (arb_texture_multisample-stencil-clear) has been sent.
This problem was discovered analyzing
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93767
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 22 Apr 2016 21:59:17 +0000 (16:59 -0500)]
radeonsi: expclear must be disabled on first Z/S clear
The documentation and the HW team say so.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 22 Apr 2016 20:28:47 +0000 (15:28 -0500)]
radeonsi: move blend choice out of loop in si_blit_decompress_color
It does not depend on the level or layer.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 22 Apr 2016 20:27:33 +0000 (15:27 -0500)]
radeonsi: use level mask for early out in si_blit_decompress_color
Mostly for consistency with the other decompress functions, but note that
in the non-DCC decompress case, the function can now early-out in slightly
more (albeit probably rare) cases.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 22 Apr 2016 17:59:47 +0000 (12:59 -0500)]
radeonsi: si_blit_decompress_depth is only used for staging
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 22 Apr 2016 18:46:13 +0000 (13:46 -0500)]
radeonsi: only decompress the required ZS planes from si_blit
This happens to "fix" a rendering bug in KotOR2, because it avoids a still
not quite understood bug with MSAA fast stencil clear decompress. For the
stencil clear bug, I have sent a piglit test (arb_texture_multisample-stencil-clear).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93767
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 22 Apr 2016 18:27:51 +0000 (13:27 -0500)]
radeonsi: decompress Z & S planes in one pass
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 22 Apr 2016 17:55:15 +0000 (12:55 -0500)]
radeonsi: early out of si_blit_decompress_depth_in_place based on dirty mask
Avoid dirtying the db_render_state atom when possible.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 22 Apr 2016 17:46:55 +0000 (12:46 -0500)]
radeonsi: use MIN2 instead of expanded ?: operator
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 22 Apr 2016 20:30:37 +0000 (15:30 -0500)]
radeonsi: fix brace style
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 22 Apr 2016 17:48:19 +0000 (12:48 -0500)]
gallium/util: add u_bit_consecutive for generating a consecutive range of bits
There are some undefined behavior subtleties, so having a function to match
the u_bit_scan_consecutive_range makes sense.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tim Rowley [Wed, 27 Apr 2016 15:12:44 +0000 (10:12 -0500)]
swr: s/Elements/ARRAY_SIZE/
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Nicolai Hähnle [Sun, 17 Apr 2016 22:23:19 +0000 (17:23 -0500)]
radeonsi: emit s_waitcnt for shader memory barriers and volatile
Turns out that this is needed after all to satisfy some strengthened
coherency tests. Depends on support in LLVM, added in r267729.
v2: updated to reflect changes to the LLVM intrinsic
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
Tim Rowley [Sat, 23 Apr 2016 01:41:23 +0000 (19:41 -0600)]
swr: [rasterizer] warning cleanup
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Mon, 18 Apr 2016 20:35:21 +0000 (14:35 -0600)]
swr: [rasterizer core] implement legacy depth bias enable
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Thu, 21 Apr 2016 20:37:19 +0000 (14:37 -0600)]
swr: [rasterizer jitter] support for dumping x86 asm
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Thu, 21 Apr 2016 20:24:33 +0000 (14:24 -0600)]
swr: [rasterizer core] more backend refactoring
BackendPixelRate should be easier to read/maintain now hopefully.
Small perf bump by moving some of the pfn's to inline functions
without template params.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Wed, 20 Apr 2016 21:57:52 +0000 (15:57 -0600)]
swr: [rasterizer jitter] add mSimdInt1Ty
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Thu, 14 Apr 2016 23:03:16 +0000 (17:03 -0600)]
swr: [rasterizer core] backend refactor
Lump all template args into a bundle of traits, and add some
functionality to the MSAA traits.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Brian Paul [Mon, 25 Apr 2016 23:12:50 +0000 (17:12 -0600)]
svga: use the SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS query
Instead of a hard-coded 512. The query typically returns 65536 now.
Fall back to 512 if the query fails as we do for vertex shaders (which
should never happen).
Note that we don't actually enforce this limit in our shaders but it gets
reported via the glGetProgramivARB(GL_MAX_PROGRAM_INSTRUCTIONS_ARB) query.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Hans de Goede [Thu, 31 Mar 2016 06:53:40 +0000 (08:53 +0200)]
nouveau: codegen: LOAD: Take src swizzle into account
The llvm TGSI backend uses pointers in registers and does things
like:
LOAD TEMP[0].y, MEMORY[0], TEMP[0]
Expecting the data at address TEMP[0].x to get loaded to
TEMP[0].y. But this will cause the data at TEMP[0].x + 4 to be
loaded instead.
This commit adds support for a swizzle suffix for the 1st source
operand, which allows using:
LOAD TEMP[0].y, MEMORY[0].xxxx, TEMP[0]
And actually getting the desired behavior
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Hans de Goede [Thu, 21 Apr 2016 11:51:14 +0000 (13:51 +0200)]
nouveau: codegen: LOAD: Do not call fetchSrc(1) if the address is immediate
"off" later gets set to NULL when the address is immediate, so move the
fetchSrc(1) call to the non-immediate branch of the if-else. This brings
handleLOAD's offset handling inline with how it is done in handleSTORE.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Hans de Goede [Thu, 21 Apr 2016 11:31:01 +0000 (13:31 +0200)]
nouveau: codegen: LOAD: Always use component 0 when getting the address
LOAD loads upto 4 components from the specified resource starting at
the passed in x value of the 2nd source operand, the y, z and w
components of the address should not be used.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Stefan Dirsch [Mon, 25 Apr 2016 13:06:25 +0000 (15:06 +0200)]
dri3: Check for dummyContext to see if the glx_context is valid
According to the comments in src/glx/glxcurrent.c __glXGetCurrentContext()
always returns a valid pointer. If no context is made current, it will
contain dummyContext. Thus a test for NULL will always fail.
https://lists.freedesktop.org/archives/mesa-dev/2016-April/113962.html
Signed-off-by: Stefan Dirsch <sndirsch@suse.de>
Reviewed-by: Egbert Eich <eich@freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Egbert Eich [Thu, 21 Apr 2016 13:02:53 +0000 (15:02 +0200)]
dri2: Check for dummyContext to see if the glx_context is valid
According to the comments in src/glx/glxcurrent.c __glXGetCurrentContext()
always returns a valid pointer. If no context is made current, it will
contain dummyContext. Thus a test for NULL will always fail.
https://bugzilla.opensuse.org/show_bug.cgi?id=962609
Tested-by: Olaf Hering <ohering@suse.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Timothy Arceri [Wed, 27 Apr 2016 03:20:45 +0000 (13:20 +1000)]
glsl: move uniform block validation to link_uniform_blocks.cpp
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Kenneth Graunke [Tue, 26 Apr 2016 17:41:21 +0000 (10:41 -0700)]
docs: Mention that {ARB,OES}_texture_stencil8 is supported on i965/gen8+
Thanks to Thomas Helland for reminding me to do this.
Kenneth Graunke [Thu, 3 Mar 2016 09:58:13 +0000 (01:58 -0800)]
i965: Enable ARB_texture_stencil8 and OES_texture_stencil8 on Gen8+.
Stencil texturing is required by ES 3.1. Apparently we never actually
turned it on. Do that now. Also turn on the desktop extension.
Fixes nine dEQP-GLES31.functional tests:
stencil_texturing.format.stencil_index8_2d
texture.border_clamp.formats.stencil_index8.nearest_size_pot
texture.border_clamp.formats.stencil_index8.nearest_size_npot
texture.border_clamp.formats.stencil_index8.gather_size_pot
texture.border_clamp.formats.stencil_index8.gather_size_npot
texture.border_clamp.unused_channels.stencil_index8
state_query.internal_format.renderbuffer.stencil_index8_samples
state_query.internal_format.texture_2d_multisample.stencil_index8_samples
state_query.internal_format.texture_2d_multisample_array.stencil_index8_samples
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Tue, 26 Apr 2016 09:31:20 +0000 (02:31 -0700)]
mesa: Try to fix CopyTex[Sub]Image of stencil textures.
ES prohibits this, but GL appears to allow it. We at least need this
much, or else we'll crash as there's no source to read from.
This fixed crashes in the ES tests before I realized I needed to
prohibit stencil instead.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Tue, 26 Apr 2016 09:29:44 +0000 (02:29 -0700)]
mesa: Disallow CopyTexSubImage on stencil formats in ES.
Fixes
- ES31-CTS.gtf.GL31Tests.texture_stencil8.texture_stencil8
- ES31-CTS.gtf.GL31Tests.texture_stencil8.texture_stencil8_multisample
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Tue, 26 Apr 2016 08:44:51 +0000 (01:44 -0700)]
i965: Fix MapTextureImage for multi-slice/level stencil buffers.
We called intel_miptree_get_image_offset() to get the image offsets
for the current level/slice, but then proceeded to ignore the results
and clobber level/slice 0 every time.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94713
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Sat, 9 Apr 2016 08:27:01 +0000 (01:27 -0700)]
i965: Move TCS output indirect_offset.file check out a level.
I want to add another condition. Moving the indirect_offset.file
check out a level should make this a little easier.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Kenneth Graunke [Sat, 23 Apr 2016 08:54:33 +0000 (01:54 -0700)]
i965/fs: Reduce the response length of sampler messages on Skylake.
Often, we don't need a full 4 channels worth of data from the sampler.
For example, depth comparisons and red textures only return one value.
To handle this, the sampler message header contains a mask which can
be used to disable channels, and reduce the message length (in SIMD16
mode on all hardware, and SIMD8 mode on Broadwell and later).
We've never used it before, since it required setting up a message
header. This meant trading a smaller response length for a larger
message length and additional MOVs to set it up.
However, Skylake introduces a terrific new feature: for headerless
messages, you can simply reduce the response length, and it makes
the implicit header contain an appropriate mask. So to read only
RG, you would simply set the message length to 2 or 4 (SIMD8/16).
This means we can finally take advantage of this at no cost.
total instructions in shared programs:
9091831 ->
9073067 (-0.21%)
instructions in affected programs: 191370 -> 172606 (-9.81%)
helped: 2609
HURT: 0
total cycles in shared programs:
70868114 ->
68454752 (-3.41%)
cycles in affected programs:
35841154 ->
33427792 (-6.73%)
helped: 16357
HURT: 8188
total spills in shared programs: 3492 -> 1707 (-51.12%)
spills in affected programs: 2749 -> 964 (-64.93%)
helped: 74
HURT: 0
total fills in shared programs: 4266 -> 2647 (-37.95%)
fills in affected programs: 3029 -> 1410 (-53.45%)
helped: 74
HURT: 0
LOST: 1
GAINED: 143
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jason Ekstrand [Fri, 9 Oct 2015 15:13:43 +0000 (08:13 -0700)]
nir: Add a helper for figuring out what channels of an SSA def are read
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Fri, 9 Oct 2015 18:24:35 +0000 (11:24 -0700)]
i965/fs: Use inst->regs_written for rlen for texture instructions
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Sat, 10 Oct 2015 01:07:23 +0000 (18:07 -0700)]
i965/fs: Properly report regs_written from SAMPLEINFO
The previous behavior would only allocate one register and then write
four thus potentially stomping three innocent bystanders.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jason Ekstrand [Mon, 12 Oct 2015 21:04:05 +0000 (14:04 -0700)]
i965/blorp: Set regs_written on texturing instructions
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Kenneth Graunke [Sat, 23 Apr 2016 22:50:39 +0000 (15:50 -0700)]
i965: Don't force a header for texture offsets of 0.
Calling textureOffset() with an offset of <0, 0, 0> is equivalent to
calliing texture(). We don't actually need to set up an offset,
which causes a message header to be created.
A fairly common pattern is to sample at a point with a bunch of
offsets, and average them. It's natural to write all the lookups
as textureOffset, but use <0, 0> for the center sample.
shader-db results on Skylake:
total instructions in shared programs:
9092095 ->
9092087 (-0.00%)
instructions in affected programs: 2826 -> 2818 (-0.28%)
helped: 12
HURT: 2
total cycles in shared programs:
70870166 ->
70870144 (-0.00%)
cycles in affected programs: 15924 -> 15902 (-0.14%)
helped: 2
HURT: 0
This also helps prevent code quality regressions in a future patch.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by Jason Ekstrand <jason@jlekstrand.net>
Patrick Rudolph [Mon, 28 Mar 2016 09:52:00 +0000 (11:52 +0200)]
r600g: fix and optimize tgsi_cmp when using ABS and NEG modifier
Some apps set NEG and ABS on the source param to test for zero.
Use ALU_OP3_CNDE insted of ALU_OP3_CNDGE and unset both modifiers.
It also removes the need for a MOV instruction, as ABS isn't
supported on op3.
Tested on AMD CAYMAN and AMD RV770.
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 26 Apr 2016 22:52:32 +0000 (08:52 +1000)]
docs: update softpipe for ARB_compute_shader
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 26 Apr 2016 04:32:52 +0000 (14:32 +1000)]
softpipe: add support for compute shaders. (v2)
This enables ARB_compute_shader on softpipe. I've only
tested this with piglit so far, and I hopefully plan
on integrating it with my vulkan work. I'll get to
testing it with deqp more later.
The basic premise is to create up to 1024 restartable
TGSI machines, and execute workgroups of those machines.
v1.1: free machines.
v2: deqp fixes - add samplers support, finish
atomic operations, fix load/store writemasks.
Acked-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 26 Apr 2016 04:31:24 +0000 (14:31 +1000)]
tgsi/exec: initialise SysSemanticToIndex array to -1
We want to use the SysSemanticToIndex to tell if we've seen
the semantics at all.
Acked-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 26 Apr 2016 04:30:31 +0000 (14:30 +1000)]
tgsi/exec: implement restartable machine.
This lets us restart the machine at a PC value, and exits
the machine when we hit a barrier.
Compute shaders will then execute all the threads up to the
barrier, then restart the machines after the barrier once
all are done.
v2: comment the code a bit, change return types.
Acked-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 26 Apr 2016 04:28:56 +0000 (14:28 +1000)]
tgsi/exec: make inputs/outputs optional for compute shaders.
compute shaders don't need input/outputs so don't bother
allocating memory for these.
Acked-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 26 Apr 2016 04:26:20 +0000 (14:26 +1000)]
tgsi/exec: implement load/store/atomic on MEMORY.
This implements basic load/store/atomic ops on MEMORY types
for compute shaders.
Acked-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 26 Apr 2016 04:24:53 +0000 (14:24 +1000)]
tgsi/exec: split out setting up masks to separate function
This is just a cleanup that will make later changes easier
to make.
Acked-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 26 Apr 2016 04:19:36 +0000 (14:19 +1000)]
tgsi: accept a starting PC value for exec machine.
This will be used later to restart barriered execution
threads in compute, for now we just want to change the API.
Acked-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 25 Apr 2016 23:48:46 +0000 (09:48 +1000)]
tgsi: move to using vector for system values.
For compute support some of the system values are .xyz types,
so move to using a vector instead of a single channel.
[airlied: squash swizzle fix from compute series].
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 26 Apr 2016 01:14:24 +0000 (11:14 +1000)]
tgsi/exec: fix system value handling.
a) SysSemanticToIndex needs to be indexed with the semantic name
not the decl->Declaration.Semantic.
b) doing this in run is too late, as the mappings are all setup
prior to run in the execs.
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Jason Ekstrand [Fri, 22 Apr 2016 21:48:36 +0000 (14:48 -0700)]
i965/blorp: Convert state setup to C
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Fri, 22 Apr 2016 21:51:05 +0000 (14:51 -0700)]
i965/blorp: Make state setup C-safe
Previously they (very rarely) used C++isms that prevented them from being
compiled as C. As of this commit, they can be compiled as either C or C++.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Fri, 22 Apr 2016 23:04:05 +0000 (16:04 -0700)]
i965/blorp: Convert brw_blorp.cpp to a C file
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Fri, 22 Apr 2016 21:39:50 +0000 (14:39 -0700)]
i965/blorp: Make all of brw_blorp.h accessible to C
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Fri, 22 Apr 2016 21:32:48 +0000 (14:32 -0700)]
i965/blorp: Turn brw_blorp_params into a C-style struct
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Fri, 22 Apr 2016 01:10:53 +0000 (18:10 -0700)]
i965/blorp: Turn coord_transform into a C-style struct
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Thu, 21 Apr 2016 23:39:56 +0000 (16:39 -0700)]
i965/blorp: Turn blorp_surface_info into a C-style struct
This commit is mostly mechanical except that it changes where we set the
swizzle. Previously, the blorp_surface_info constructor defaulted the
swizzle to SWIZZLE_XYZW. Now, we memset to zero and fill out the swizzle
when we setup the rest of the struct.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Thu, 21 Apr 2016 23:19:51 +0000 (16:19 -0700)]
i965/blorp: Roll mip_info into surface_info
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Fri, 22 Apr 2016 21:06:08 +0000 (14:06 -0700)]
i965/blorp: Get rid of the blorp_blit_params class
It was really just a wrapper around the function that constructed it.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Fri, 22 Apr 2016 20:46:25 +0000 (13:46 -0700)]
i965/blorp: Remove the hiz params class
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Fri, 22 Apr 2016 19:55:49 +0000 (12:55 -0700)]
i965/blorp: Remove the clear params classes
They didn't really add anything other than a key and extra layers of
function calls. This commit just inlines the extra functions and gets rid
of the extra classes.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Fri, 22 Apr 2016 20:52:30 +0000 (13:52 -0700)]
i965/blorp: Remove the arguments to brw_blorp_params()
No one was using anything other than the defaults.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>