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Andrea Di Biagio [Fri, 12 Oct 2018 11:23:04 +0000 (11:23 +0000)]
[tblgen][llvm-mca] Add the ability to describe move elimination candidates via tablegen.
This patch adds the ability to identify instructions that are "move elimination
candidates". It also allows scheduling models to describe processor register
files that allow move elimination.
A move elimination candidate is an instruction that can be eliminated at
register renaming stage.
Each subtarget can specify which instructions are move elimination candidates
with the help of tablegen class "IsOptimizableRegisterMove" (see
llvm/Target/TargetInstrPredicate.td).
For example, on X86, BtVer2 allows both GPR and MMX/SSE moves to be eliminated.
The definition of 'IsOptimizableRegisterMove' for BtVer2 looks like this:
```
def : IsOptimizableRegisterMove<[
InstructionEquivalenceClass<[
// GPR variants.
MOV32rr, MOV64rr,
// MMX variants.
MMX_MOVQ64rr,
// SSE variants.
MOVAPSrr, MOVUPSrr,
MOVAPDrr, MOVUPDrr,
MOVDQArr, MOVDQUrr,
// AVX variants.
VMOVAPSrr, VMOVUPSrr,
VMOVAPDrr, VMOVUPDrr,
VMOVDQArr, VMOVDQUrr
], CheckNot<CheckSameRegOperand<0, 1>> >
]>;
```
Definitions of IsOptimizableRegisterMove from processor models of a same
Target are processed by the SubtargetEmitter to auto-generate a target-specific
override for each of the following predicate methods:
```
bool TargetSubtargetInfo::isOptimizableRegisterMove(const MachineInstr *MI)
const;
bool MCInstrAnalysis::isOptimizableRegisterMove(const MCInst &MI, unsigned
CPUID) const;
```
By default, those methods return false (i.e. conservatively assume that there
are no move elimination candidates).
Tablegen class RegisterFile has been extended with the following information:
- The set of register classes that allow move elimination.
- Maxium number of moves that can be eliminated every cycle.
- Whether move elimination is restricted to moves from registers that are
known to be zero.
This patch is structured in three part:
A first part (which is mostly boilerplate) adds the new
'isOptimizableRegisterMove' target hooks, and extends existing register file
descriptors in MC by introducing new fields to describe properties related to
move elimination.
A second part, uses the new tablegen constructs to describe move elimination in
the BtVer2 scheduling model.
A third part, teaches llm-mca how to query the new 'isOptimizableRegisterMove'
hook to mark instructions that are candidates for move elimination. It also
teaches class RegisterFile how to describe constraints on move elimination at
PRF granularity.
llvm-mca tests for btver2 show differences before/after this patch.
Differential Revision: https://reviews.llvm.org/D53134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344334
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Simon Pilgrim [Fri, 12 Oct 2018 10:26:59 +0000 (10:26 +0000)]
[X86][AVX] Add examples of shuffles that can be reduced to a cross-lane shuffle followed by a in-lane permute
Suitable for lowering by D53148
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344332
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Simon Pilgrim [Fri, 12 Oct 2018 10:20:16 +0000 (10:20 +0000)]
[X86] Ignore float/double non-temporal loads (PR39256)
Scalar non-temporal loads were asserting instead of just being ignored.
Reduced from https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=10895
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344331
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Tim Northover [Fri, 12 Oct 2018 09:01:59 +0000 (09:01 +0000)]
SCCP: avoid caching DenseMap entry that might be invalidated.
Later calls to getValueState might insert entries into the ValueState map and
cause reallocation, invalidating a reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344327
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Stefan Maksimovic [Fri, 12 Oct 2018 08:18:38 +0000 (08:18 +0000)]
[mips] Mark fmaxl as a long double emulation routine
Failure was discovered upon running
projects/compiler-rt/test/builtins/Unit/divtc3_test.c
in a stage2 compiler build.
When compiling projects/compiler-rt/lib/builtins/divtc3.c,
a call to fmaxl within the divtc3 implementation had its
return values read from registers $2 and $3 instead of $f0 and $f2.
Include fmaxl in the list of long double emulation routines
to have its return value correctly interpreted as f128.
Almost exact issue here: https://reviews.llvm.org/D17760
Differential Revision: https://reviews.llvm.org/D52649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344326
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Eugene Leviant [Fri, 12 Oct 2018 07:24:02 +0000 (07:24 +0000)]
[ThinLTO] Don't import GV which contains blockaddress
Differential revision: https://reviews.llvm.org/D53139
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344325
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Jordan Rupprecht [Fri, 12 Oct 2018 00:36:01 +0000 (00:36 +0000)]
[llvm-objcopy] Add -F|--target compatibility
Summary:
This change adds support for the GNU --target flag, which sets both --input-target and --output-target.
GNU objcopy doesn't do any checking for whether both --target and --{input,output}-target are used, and so it allows both, e.g. "--target A --output-target B" is equivalent to "--input-target A --output-target B" since the later command line flag would override earlier ones. This may be error prone, so I chose to implement it as an error if both are used. I'm not sure if anyone is actually using both.
Reviewers: jakehehrlich, jhenderson, alexshap
Reviewed By: jakehehrlich, alexshap
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53029
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344321
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Sanjay Patel [Thu, 11 Oct 2018 23:56:56 +0000 (23:56 +0000)]
[DAGCombiner] rearrange extract_element+bitcast fold; NFC
I want to add another pattern here that includes scalar_to_vector,
so this makes that patch smaller. I was hoping to remove the
hasOneUse() check because it shouldn't be necessary for common
codegen, but an AMDGPU test has a comment suggesting that the
extra check makes things better on one of those targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344320
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Matthias Braun [Thu, 11 Oct 2018 23:37:58 +0000 (23:37 +0000)]
Revert "DwarfDebug: Pick next location in case of missing location at block begin"
It originally triggered a stepping problem in the debugger, which could
be fixed by adjusting CodeGen/LexicalScopes.cpp however it seems we prefer
the previous behavior anyway.
See the discussion for details: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20181008/593833.html
This reverts commit r343880.
This reverts commit r343874.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344318
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Tom Stellard [Thu, 11 Oct 2018 23:36:46 +0000 (23:36 +0000)]
Revert "AMDGPU/GlobalISel: Implement select for G_INSERT"
This reverts commit r344310.
The test case was failing on some bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344317
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Matthias Braun [Thu, 11 Oct 2018 23:14:35 +0000 (23:14 +0000)]
X86/TargetTransformInfo: Report div/rem constant immediate costs as TCC_Free
DIV/REM by constants should always be expanded into mul/shift/etc.
patterns. Unfortunately the ConstantHoisting pass runs too early at a
point where the pattern isn't expanded yet. However after
ConstantHoisting hoisted some immediate the result may not expand
anymore. Also the hoisting typically doesn't make sense because it
operates on immediates that will change completely during the expansion.
Report DIV/REM as TCC_Free so ConstantHoisting will not touch them.
Differential Revision: https://reviews.llvm.org/D53174
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344315
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Kostya Serebryany [Thu, 11 Oct 2018 23:03:27 +0000 (23:03 +0000)]
merge two near-identical functions createPrivateGlobalForString into one
Summary:
We have two copies of createPrivateGlobalForString (in asan and in esan).
This change merges them into one. NFC
Reviewers: vitalybuka
Reviewed By: vitalybuka
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53178
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344314
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Tom Stellard [Thu, 11 Oct 2018 22:49:54 +0000 (22:49 +0000)]
AMDGPU/GlobalISel: Implement select for G_INSERT
Reviewers: arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D53116
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344310
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Ana Pazos [Thu, 11 Oct 2018 22:49:13 +0000 (22:49 +0000)]
[RISCV] Fix disassembling of fence instruction with invalid field
Summary:
Instruction with 0 in fence field being disassembled as fence , iorw.
Printing "unknown" to match GAS behavior.
This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer
for the RISC-V assembly language.
Reviewers: asb
Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, jfb, PkmX, jocewei, asb
Differential Revision: https://reviews.llvm.org/D51828
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344309
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Richard Trieu [Thu, 11 Oct 2018 22:42:41 +0000 (22:42 +0000)]
Inline variable into assert to avoid unused variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344308
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Alexander Shaposhnikov [Thu, 11 Oct 2018 22:33:50 +0000 (22:33 +0000)]
[llvm-objcopy] Factor out CopyConfig
In this diff we move out CopyConfig from llvm-oobjcopy.cpp into a separate header CopyConfig.h
to enable us (in the future) reuse this class in the other implementations of objcopy (for coff, mach-o).
Additionally this enables us to unload the complexity from llvm-objcopy.cpp a little bit.
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D53006
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344307
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Aaron Smith [Thu, 11 Oct 2018 22:25:55 +0000 (22:25 +0000)]
[llvm-pdbutil] Add missing pdb for test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344306
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Wei Mi [Thu, 11 Oct 2018 22:14:27 +0000 (22:14 +0000)]
[SampleFDO][NFC] Remove debugging log left over in the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344304
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Sanjay Patel [Thu, 11 Oct 2018 22:04:36 +0000 (22:04 +0000)]
[x86] add tests for extract_element; NFC
The transform for this pattern has an unnecessary one-use limitation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344303
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Sanjay Patel [Thu, 11 Oct 2018 21:44:38 +0000 (21:44 +0000)]
[x86] regenerate CHECKs; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344301
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Aaron Smith [Thu, 11 Oct 2018 21:37:18 +0000 (21:37 +0000)]
[llvm-pdbutil] Pretty print PDBSymbolUsingNamespace symbols
Reviewers: rnk, zturner, llvm-commits
Differential Revision: https://reviews.llvm.org/D52799
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344298
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Craig Topper [Thu, 11 Oct 2018 20:36:06 +0000 (20:36 +0000)]
[X86] Type legalize v2f32 loads by using an f64 load and a scalar_to_vector.
On 64-bit targets the generic legalize will use an i64 load and a scalar_to_vector for us. But on 32-bit targets i64 isn't legal and the generic legalizer will end up emitting two 32-bit loads. We have DAG combines that try to put those two loads back together with pretty good success.
This patch instead uses f64 to avoid the splitting entirely. I've made it do the same for 64-bit mode for consistency and to keep the load in the fp domain.
There are a few things in here that look like regressions in 32-bit mode, but I believe they bring us closer to the 64-bit mode codegen. And that the 64-bit mode code could be better. I think those issues should be looked at separately.
Differential Revision: https://reviews.llvm.org/D52528
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344291
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Thomas Lively [Thu, 11 Oct 2018 20:21:22 +0000 (20:21 +0000)]
[WebAssembly][NFC] Remove repetition of Defs = [ARGUMENTS] (fixed)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344287
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Warren Ristow [Thu, 11 Oct 2018 20:19:25 +0000 (20:19 +0000)]
Update test of r344198 to work with release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344286
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Sumanth Gundapaneni [Thu, 11 Oct 2018 19:48:15 +0000 (19:48 +0000)]
[Hexagon] Restrict compound instructions with constant value.
Having a constant value operand in the compound instruction
is not always profitable. This patch improves coremark by ~4% on
Hexagon.
Differential Revision: https://reviews.llvm.org/D53152
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344284
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Sumanth Gundapaneni [Thu, 11 Oct 2018 19:45:07 +0000 (19:45 +0000)]
[Pipeliner] Use the Index from Topo instead of relying on NodeNum. (NFC)
In future, if we may add any new DAG mutations other than artificial dependencies,
the NodeNum may not be valid. Instead the index from topological schedule DAG can be
used as long as we update it with the DAG change.
Differential Revision: https://reviews.llvm.org/D53104
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344283
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Sumanth Gundapaneni [Thu, 11 Oct 2018 19:42:46 +0000 (19:42 +0000)]
[Pipeliner] Fix the Schedule DAG topoligical order.
This patch updates the DAG change to reflect in the topological ordering
of the nodes.
Differential Revision: https://reviews.llvm.org/D53105
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344282
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Thomas Lively [Thu, 11 Oct 2018 18:45:48 +0000 (18:45 +0000)]
[WebAssembly] Revert rL344180, which was breaking expensive checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344280
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Zachary Turner [Thu, 11 Oct 2018 18:45:44 +0000 (18:45 +0000)]
Revert SymbolFileNativePDB plugin.
This was originally causing some test failures on non-Windows
platforms, which required fixes in the compiler and linker. After
those fixes, however, other tests started failing. Reverting
temporarily until I can address everything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344279
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Artem Dergachev [Thu, 11 Oct 2018 18:43:08 +0000 (18:43 +0000)]
Revert r344197 "[MC][ELF] compute entity size for explicit sections"
Revert r344206 "[MC][ELF] Fix section_mergeable_size.ll"
They were causing failures on too many important buildbots for too long.
Please revert eagerly if your fix takes more than a couple of hours to land!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344278
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Leonard Chan [Thu, 11 Oct 2018 18:31:51 +0000 (18:31 +0000)]
[PassManager/Sanitizer] Port of AddresSanitizer pass from legacy to new PassManager
This patch ports the legacy pass manager to the new one to take advantage of
the benefits of the new PM. This involved moving a lot of the declarations for
`AddressSantizer` to a header so that it can be publicly used via
PassRegistry.def which I believe contains all the passes managed by the new PM.
This patch essentially decouples the instrumentation from the legacy PM such
hat it can be used by both legacy and new PM infrastructure.
Differential Revision: https://reviews.llvm.org/D52739
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344274
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Nirav Dave [Thu, 11 Oct 2018 18:28:59 +0000 (18:28 +0000)]
[DAG] Fix Big Endian in Load-Store forwarding
Summary:
Correct offset calculation in load-store forwarding for big-endian
targets.
Reviewers: rnk, RKSimon, waltl
Subscribers: sdardis, nemanjai, hiraditya, jrtc27, atanasyan, jsji, llvm-commits
Differential Revision: https://reviews.llvm.org/D53147
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344272
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Krzysztof Parzyszek [Thu, 11 Oct 2018 18:26:02 +0000 (18:26 +0000)]
[Hexagon] Eliminate potential sources of non-determinism in HCE
Also, avoid comparing GUIDs when ordering global addresses, because
source file location can cause different GUID to be calculated. As a
result, a pair of symbols can compare "less" in one directory, but
"greater" in another.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344271
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Craig Topper [Thu, 11 Oct 2018 18:06:07 +0000 (18:06 +0000)]
[X86] Restore X86ISelDAGToDAG::matchBEXTRFromAnd. Teach address matching to create a BEXTR pattern from a (shl (and X, mask >> C1) if C1 can be folded into addressing mode.
This is an alternative to D53080 since I think using a BEXTR for a shifted mask is definitely an improvement when the shl can be absorbed into addressing mode. The other cases I'm less sure about.
We already have several tricks for handling an and of a shift in address matching. This adds a new case for BEXTR.
I've moved the BEXTR matching code back to X86ISelDAGToDAG to allow it to match. I suppose alternatively we could directly emit a X86ISD::BEXTR node that isel could pattern match. But I'm trying to view BEXTR matching as an isel concern so DAG combine can see 'and' and 'shift' operations that are well understood. We did lose a couple cases from tbm_patterns.ll, but I think there are ways to recover that.
I've also put back the manual load folding code in matchBEXTRFromAnd that I removed a few months ago in r324939. This gives us some more freedom to make decisions based on the ability to fold a load. I haven't done anything with that yet.
Differential Revision: https://reviews.llvm.org/D53126
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344270
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Zachary Turner [Thu, 11 Oct 2018 18:01:55 +0000 (18:01 +0000)]
Better support for POSIX paths in PDBs.
While it doesn't make a *ton* of sense for POSIX paths to be
in PDBs, it's possible to occur in real scenarios involving
cross compilation.
The tools need to be able to handle this, because certain types
of debugging scenarios are possible without a running process
and so don't necessarily require you to be on a Windows system.
These include post-mortem debugging and binary forensics (e.g.
using a debugger to disassemble functions and examine symbols
without running the process).
There's changes in clang, LLD, and lldb in this patch. After
this the cross-platform disassembly and source-list tests pass
on Linux.
Furthermore, the behavior of LLD can now be summarized by a much
simpler rule than before: Unless you specify /pdbsourcepath and
/pdbaltpath, the PDB ends up with paths that are valid within
the context of the machine that the link is performed on.
Differential Revision: https://reviews.llvm.org/D53149
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344269
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Jordan Rupprecht [Thu, 11 Oct 2018 17:55:11 +0000 (17:55 +0000)]
[llvm-nm] Fix crash when running with --print-armap on corrupt archives.
error() in llvm-nm intentionally does not return so that the callee can move on to future files/slices. When printing the archive map, this is not currently handled (the caller assumes that error() returns), so processing continues despite there being an error.
Also, change one return to a break, so that symbols can be printed even if the archive map is corrupt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344268
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Sanjay Patel [Thu, 11 Oct 2018 16:07:25 +0000 (16:07 +0000)]
[DAGCombiner] move comment closer to the corresponding code; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344255
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Andrea Di Biagio [Thu, 11 Oct 2018 14:54:54 +0000 (14:54 +0000)]
[llvm-mca][BtVer2] Add tests for optimizable GPR register moves. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344253
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Amara Emerson [Thu, 11 Oct 2018 14:51:11 +0000 (14:51 +0000)]
[InstCombine] Fix SimplifyLibCalls erasing an instruction while IC still had references to it.
InstCombine keeps a worklist and assumes that optimizations don't
eraseFromParent() the instruction, which SimplifyLibCalls violates. This change
adds a new callback to SimplifyLibCalls to let clients specify their own hander
for erasing actions.
Differential Revision: https://reviews.llvm.org/D52729
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344251
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Diogo N. Sampaio [Thu, 11 Oct 2018 14:10:32 +0000 (14:10 +0000)]
[AARCH64][FIX] Emit data symbol for constant pool data
The ARM64 elf emitter would omit printing data
symbol for zero filled constant data. This patch
overrides the emitFill method as to enforce that
the symbol is correctly printed.
Differential revision: https://reviews.llvm.org/D53132
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344248
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Dylan McKay [Thu, 11 Oct 2018 12:49:50 +0000 (12:49 +0000)]
Generalize an IR verifier check to work with non-zero program address spaces
This commit modifies an existing IR verifier check that
assumes all functions will be located in the default address
space 0.
Rather than using the default paramater value getPointerTo(AddrSpace=0),
explicitly specify the program memory address space from the data layout.
This only affects targets that specify a nonzero address space
in their data layouts. The only in-tree target that does this
is AVR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344243
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David Green [Thu, 11 Oct 2018 11:28:27 +0000 (11:28 +0000)]
[InstCombine] Demand bits of UMin
This is the umin alternative to the umax code from rL344237. We use
DeMorgans law on the umax case to bring us to the same thing on umin,
but using countLeadingOnes, not countLeadingZeros.
Differential Revision: https://reviews.llvm.org/D53036
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344239
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Alex Bradbury [Thu, 11 Oct 2018 11:11:58 +0000 (11:11 +0000)]
[RISCV] Re-generate test/CodeGen/RISCV/vararg.ll after r344142
The improved load-store forwarding committed in r344142 broke this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344238
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David Green [Thu, 11 Oct 2018 11:04:09 +0000 (11:04 +0000)]
[InstCombine] Demand bits of UMax
Use the demanded bits of umax(A,C) to prove we can just use A so long as the
lowest non-zero bit of DemandMask is higher than the highest non-zero bit of C
Differential Revision: https://reviews.llvm.org/D53033
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344237
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David Green [Thu, 11 Oct 2018 10:46:12 +0000 (10:46 +0000)]
[InstCombine] Add tests for demand bits of min/max. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344236
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Andrea Di Biagio [Thu, 11 Oct 2018 10:39:03 +0000 (10:39 +0000)]
[tblgen][CodeGenSchedule] Add a check for invalid RegisterFile definitions with zero physical registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344235
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Florian Hahn [Thu, 11 Oct 2018 09:46:25 +0000 (09:46 +0000)]
[LV] Use SmallVector instead of DenseMap in calculateRegisterUsage (NFC).
We assign indices sequentially for seen instructions, so we can just use
a vector and push back the seen instructions. No need for using a
DenseMap.
Reviewers: hsaito, rengolin, nadav, dcaballe
Reviewed By: rengolin
Differential Revision: https://reviews.llvm.org/D53089
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344233
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Florian Hahn [Thu, 11 Oct 2018 09:27:24 +0000 (09:27 +0000)]
[LV] Ignore more debug info.
We can avoid doing some unnecessary work by skipping debug instructions
in a few loops. It also helps to ensure debug instructions do not
prevent vectorization, although I do not have any concrete test cases
for that.
Reviewers: rengolin, hsaito, dcaballe, aprantl, vsk
Reviewed By: rengolin, dcaballe
Differential Revision: https://reviews.llvm.org/D53091
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344232
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Calixte Denizet [Thu, 11 Oct 2018 08:53:43 +0000 (08:53 +0000)]
[gcov] Display the hit counter for the line of a function definition
Summary:
Right now there is no hit counter on the line of function.
So the idea is add the line of the function to all the lines covered by the entry block.
Tests in compiler-rt/profile will be fixed in another patch: https://reviews.llvm.org/D49854
Reviewers: marco-c, davidxl
Reviewed By: marco-c
Subscribers: sylvestre.ledru, llvm-commits
Differential Revision: https://reviews.llvm.org/D49853
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344228
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Max Kazantsev [Thu, 11 Oct 2018 08:46:39 +0000 (08:46 +0000)]
[NFC] Factor out getOrCreateAddRecExpr method
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344227
91177308-0d34-0410-b5e6-
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Roman Lebedev [Thu, 11 Oct 2018 07:51:13 +0000 (07:51 +0000)]
[X86][BMI1]: X86DAGToDAGISel: select BEXTR from x & ~(-1 << nbits) pattern
Summary:
As discussed in D48491, we can't really do this in the TableGen,
since we need to produce *two* instructions. This only implements
one single pattern. The other 3 patterns will be in follow-ups.
I'm not sure yet if we want to also fuse shift into here
(i.e `(x >> start) & ...`)
Reviewers: RKSimon, craig.topper, spatel
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D52304
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344224
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Max Kazantsev [Thu, 11 Oct 2018 07:22:26 +0000 (07:22 +0000)]
[IndVars] Drop "exact" flag from lshr and udiv when substituting their args
There is a transform that may replace `lshr (x+1), 1` with `lshr x, 1` in case
if it can prove that the result will be the same. However the initial instruction
might have an `exact` flag set, and it now should be dropped unless we prove
that it may hold. Incorrectly set `exact` attribute may then produce poison.
Differential Revision: https://reviews.llvm.org/D53061
Reviewed By: sanjoy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344223
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Martin Storsjo [Thu, 11 Oct 2018 06:53:38 +0000 (06:53 +0000)]
[llvm-nm] Include the text "@FILE" in the output of --help
libtool requires this text to be present, in order to conclude that
the tool supports response files. Also add an explicit test of using
response files with llvm-nm.
Differential Revision: https://reviews.llvm.org/D53064
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344222
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Chris Bieneman [Thu, 11 Oct 2018 04:06:14 +0000 (04:06 +0000)]
[CMake] Temporarily remove the LLVM_ENABLE_IDE option
All uses of this option have been removed, and the intent is to change the purpose and default value of this option. To prevent it from having impacts on users, this patch temporarily removes the option and purges it from CMake caches. In a few days, once this has propagated to contributors I will re-introduce the option with the new default value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344219
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Chris Bieneman [Thu, 11 Oct 2018 04:02:53 +0000 (04:02 +0000)]
[CMake] Unconditionally add .h and .td files to target sources
Previously adding header and table gen files was conditional on using an IDE. Since these files have the `HEADER_FILE_ONLY` attribute applied they are ignored as sources by all non-IDE generators, so there is really no reason not to include them.
Additionally having the CMake always include these files allows the CMake-server to include them in the sources list for targets, which is valuable to anyone using CMake-server integrated tools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344218
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Chris Bieneman [Thu, 11 Oct 2018 04:00:51 +0000 (04:00 +0000)]
[Coverage] Apply filtered paths to summary
Summary:
The script to generate code coverage reports supports passing filter paths to llvm-cov when generating the HTML reports, but doesn't pass those paths to the summary generation as well. This results in a summary report that doesn't match the HTML report.
This patch addresses the problem by also passing the filter paths to the summary report generation.
Reviewers: vsk
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53110
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344217
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Zachary Turner [Thu, 11 Oct 2018 03:42:17 +0000 (03:42 +0000)]
Use fully qualified namespace name.
llvm::detail is not the only namespace named detail. So if
someone has done a `using namespace llvm::support`, for example,
this will fail with an ambiguous namespace name. Granted
people generally shouldn't be using large namespaces like that,
but it's common at local function scopes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344216
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Thomas Lively [Thu, 11 Oct 2018 00:49:24 +0000 (00:49 +0000)]
[WebAssembly][NFC] Use intrinsic dag nodes directly
Summary: Instead of custom lowering to WebAssemblyISD nodes first.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53119
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344211
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Fangrui Song [Thu, 11 Oct 2018 00:08:59 +0000 (00:08 +0000)]
[MC][ELF] Fix section_mergeable_size.ll
Some targets use %progbits instead of @progbits.
Updating that check with a {{[@%]}}progbits regex to make those bots happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344206
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Thomas Lively [Thu, 11 Oct 2018 00:01:25 +0000 (00:01 +0000)]
[WebAssembly] Saturating float to int intrinsics
Summary:
Although the saturating float to int instructions are already
emitted from normal IR, the fpto{s,u}i instructions produce poison
values if the argument cannot fit in the result type. These intrinsics
are therefore necessary to get guaranteed defined saturating behavior.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53004
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344204
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Saleem Abdulrasool [Wed, 10 Oct 2018 23:53:12 +0000 (23:53 +0000)]
llvm-c: Add C APIs to access DebugLoc info
Add thin shims to C interface to provide access to DebugLoc info for
Instructions, GlobalVariables and Functions. Patch by Josh Berdine!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344202
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Richard Smith [Wed, 10 Oct 2018 23:13:47 +0000 (23:13 +0000)]
Add a flag to remap manglings when reading profile data information.
This can be used to preserve profiling information across codebase
changes that have widespread impact on mangled names, but across which
most profiling data should still be usable. For example, when switching
from libstdc++ to libc++, or from the old libstdc++ ABI to the new ABI,
or even from a 32-bit to a 64-bit build.
The user can provide a remapping file specifying parts of mangled names
that should be treated as equivalent (eg, std::__1 should be treated as
equivalent to std::__cxx11), and profile data will be treated as
applying to a particular function if its name is equivalent to the name
of a function in the profile data under the provided equivalences. See
the documentation change for a description of how this is configured.
Remapping is supported for both sample-based profiling and instruction
profiling. We do not support remapping indirect branch target
information, but all other profile data should be remapped
appropriately.
Support is only added for the new pass manager. If someone wants to also
add support for this for the old pass manager, doing so should be
straightforward.
This is the LLVM side of Clang r344199.
Reviewers: davidxl, tejohnson, dlj, erik.pilkington
Subscribers: mehdi_amini, steven_wu, dexonsmith, llvm-commits
Differential Revision: https://reviews.llvm.org/D51249
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344200
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Warren Ristow [Wed, 10 Oct 2018 22:54:31 +0000 (22:54 +0000)]
[LTO] Account for overriding lib calls via the alias attribute
Given a library call that is represented as an llvm intrinsic call, but
later transformed to an actual call, if an overriding definition of that
library routine is provided indirectly via an alias, prevent LTO from
eliminating the definition.
This is a fix for PR38547.
Differential Revision: https://reviews.llvm.org/D52836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344198
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Nick Desaulniers [Wed, 10 Oct 2018 22:52:32 +0000 (22:52 +0000)]
[MC][ELF] compute entity size for explicit sections
Summary:
Global variables might declare themselves to be in explicit sections.
Calculate the entity size always to prevent assembler warnings
"entity size for SHF_MERGE not specified" when sections are to be
marked merge-able.
Fixes PR31828.
Reviewers: rnk, echristo
Reviewed By: rnk
Subscribers: llvm-commits, pirama, srhines
Differential Revision: https://reviews.llvm.org/D53056
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344197
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Craig Topper [Wed, 10 Oct 2018 21:48:34 +0000 (21:48 +0000)]
[X86] Prevent non-temporal loads from folding into instructions by blocking them in X86DAGToDAGISel::IsProfitableToFold rather than with a predicate.
Remove tryFoldVecLoad since tryFoldLoad would call IsProfitableToFold and pick up the new check.
This saves about 5K out of ~600K on the generated isel table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344189
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Chris Bieneman [Wed, 10 Oct 2018 21:36:12 +0000 (21:36 +0000)]
[CMake] NFC. Updating documentation on options
The Ninja pool options are only supported with the Ninja generator and
should be called out as such.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344188
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Richard Smith [Wed, 10 Oct 2018 21:31:01 +0000 (21:31 +0000)]
Support for remapping profile data when symbols change, for sample-based
profiling.
Reviewers: davidxl, tejohnson, dlj, erik.pilkington
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D51248
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344187
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George Burgess IV [Wed, 10 Oct 2018 21:28:44 +0000 (21:28 +0000)]
Replace most users of UnknownSize with LocationSize::unknown(); NFC
Moving away from UnknownSize is part of the effort to migrate us to
LocationSizes (e.g. the cleanup promised in D44748).
This doesn't entirely remove all of the uses of UnknownSize; some uses
require tweaks to assume that UnknownSize isn't just some kind of int.
This patch is intended to just be a trivial replacement for all places
where LocationSize::unknown() will Just Work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344186
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Armando Montanez [Wed, 10 Oct 2018 21:16:57 +0000 (21:16 +0000)]
Test commit: fix typo in comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344185
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Richard Smith [Wed, 10 Oct 2018 21:09:37 +0000 (21:09 +0000)]
Support for remapping profile data when symbols change, for
instrumentation-based profiling.
Reviewers: davidxl, tejohnson, dlj, erik.pilkington
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D51247
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344184
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James Y Knight [Wed, 10 Oct 2018 21:07:02 +0000 (21:07 +0000)]
llvm-ar: Darwin archive format fixes.
* Support writing the DARWIN64 symbol table format.
* In darwin archives, emit a symbol table whenever requested, even
when there are no members, as the apple linker will abort if given
an archive without a symbol table.
Added tests for same, and also simplified and moved the GNU 64-bit
symbol table test into archive-symtab.test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344183
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Roman Lebedev [Wed, 10 Oct 2018 20:50:52 +0000 (20:50 +0000)]
[NFC][X86][AArch64] extract-bits.ll: add tests with constants+storing results.
As noted in https://reviews.llvm.org/D53080#inline-467678,
this *may* get pessimized by that diff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344182
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Sanjay Patel [Wed, 10 Oct 2018 20:47:46 +0000 (20:47 +0000)]
[InstCombine] reverse 'trunc X to <N x i1>' canonicalization; 2nd try
Re-trying r344082 because it unintentionally included extra diffs.
Original commit message:
icmp ne (and X, 1), 0 --> trunc X to N x i1
Ideally, we'd do the same for scalars, but there will likely be
regressions unless we add more trunc folds as we're doing here
for vectors.
The motivating vector case is from PR37549:
https://bugs.llvm.org/show_bug.cgi?id=37549
define <4 x float> @bitwise_select(<4 x float> %x, <4 x float> %y, <4 x float> %z, <4 x float> %w) {
%c = fcmp ole <4 x float> %x, %y
%s = sext <4 x i1> %c to <4 x i32>
%s1 = shufflevector <4 x i32> %s, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
%s2 = shufflevector <4 x i32> %s, <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3>
%cond = or <4 x i32> %s1, %s2
%condtr = trunc <4 x i32> %cond to <4 x i1>
%r = select <4 x i1> %condtr, <4 x float> %z, <4 x float> %w
ret <4 x float> %r
}
Here's a sampling of the vector codegen for that case using
mask+icmp (current behavior) vs. trunc (with this patch):
AVX before:
vcmpleps %xmm1, %xmm0, %xmm0
vpermilps $80, %xmm0, %xmm1 ## xmm1 = xmm0[0,0,1,1]
vpermilps $250, %xmm0, %xmm0 ## xmm0 = xmm0[2,2,3,3]
vorps %xmm0, %xmm1, %xmm0
vandps LCPI0_0(%rip), %xmm0, %xmm0
vxorps %xmm1, %xmm1, %xmm1
vpcmpeqd %xmm1, %xmm0, %xmm0
vblendvps %xmm0, %xmm3, %xmm2, %xmm0
AVX after:
vcmpleps %xmm1, %xmm0, %xmm0
vpermilps $80, %xmm0, %xmm1 ## xmm1 = xmm0[0,0,1,1]
vpermilps $250, %xmm0, %xmm0 ## xmm0 = xmm0[2,2,3,3]
vorps %xmm0, %xmm1, %xmm0
vblendvps %xmm0, %xmm2, %xmm3, %xmm0
AVX512f before:
vcmpleps %xmm1, %xmm0, %xmm0
vpermilps $80, %xmm0, %xmm1 ## xmm1 = xmm0[0,0,1,1]
vpermilps $250, %xmm0, %xmm0 ## xmm0 = xmm0[2,2,3,3]
vorps %xmm0, %xmm1, %xmm0
vpbroadcastd LCPI0_0(%rip), %xmm1 ## xmm1 = [1,1,1,1]
vptestnmd %zmm1, %zmm0, %k1
vblendmps %zmm3, %zmm2, %zmm0 {%k1}
AVX512f after:
vcmpleps %xmm1, %xmm0, %xmm0
vpermilps $80, %xmm0, %xmm1 ## xmm1 = xmm0[0,0,1,1]
vpermilps $250, %xmm0, %xmm0 ## xmm0 = xmm0[2,2,3,3]
vorps %xmm0, %xmm1, %xmm0
vpslld $31, %xmm0, %xmm0
vptestmd %zmm0, %zmm0, %k1
vblendmps %zmm2, %zmm3, %zmm0 {%k1}
AArch64 before:
fcmge v0.4s, v1.4s, v0.4s
zip1 v1.4s, v0.4s, v0.4s
zip2 v0.4s, v0.4s, v0.4s
orr v0.16b, v1.16b, v0.16b
movi v1.4s, #1
and v0.16b, v0.16b, v1.16b
cmeq v0.4s, v0.4s, #0
bsl v0.16b, v3.16b, v2.16b
AArch64 after:
fcmge v0.4s, v1.4s, v0.4s
zip1 v1.4s, v0.4s, v0.4s
zip2 v0.4s, v0.4s, v0.4s
orr v0.16b, v1.16b, v0.16b
bsl v0.16b, v2.16b, v3.16b
PowerPC-le before:
xvcmpgesp 34, 35, 34
vspltisw 0, 1
vmrglw 3, 2, 2
vmrghw 2, 2, 2
xxlor 0, 35, 34
xxlxor 35, 35, 35
xxland 34, 0, 32
vcmpequw 2, 2, 3
xxsel 34, 36, 37, 34
PowerPC-le after:
xvcmpgesp 34, 35, 34
vmrglw 3, 2, 2
vmrghw 2, 2, 2
xxlor 0, 35, 34
xxsel 34, 37, 36, 0
Differential Revision: https://reviews.llvm.org/D52747
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344181
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Thomas Lively [Wed, 10 Oct 2018 20:40:54 +0000 (20:40 +0000)]
[WebAssembly][NFC] Remove repetition of Defs = [ARGUMENTS]
Summary:
By moving that line into the `I` multiclass.
Reviewers: aheejin
Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53093
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344180
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Roman Lebedev [Wed, 10 Oct 2018 20:40:12 +0000 (20:40 +0000)]
[X86] Move X86DAGToDAGISel::matchBEXTRFromAnd() into X86ISelLowering
Summary:
As discussed in [[ https://bugs.llvm.org/show_bug.cgi?id=38938 | PR38938 ]],
we fail to emit `BEXTR` if the mask is shifted.
We can't deal with that in `X86DAGToDAGISel` `before the address mode for the inc is selected`,
and we can't really do it in the normal DAGCombine, because we don't have generic `ISD::BitFieldExtract` node,
and if we simply turn the shifted mask into a normal mask + shift-left, it will be folded back.
So it would seem X86ISelLowering is the place to handle this.
This patch only moves the matchBEXTRFromAnd()
from X86DAGToDAGISel to X86ISelLowering.
It does not add support for the 'shifted mask' pattern.
Reviewers: RKSimon, craig.topper, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52426
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344179
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Sanjay Patel [Wed, 10 Oct 2018 20:39:39 +0000 (20:39 +0000)]
revert r344082: [InstCombine] reverse 'trunc X to <N x i1>' canonicalization
This commit accidentally included the diffs from D53057.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344178
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David Bolvansky [Wed, 10 Oct 2018 20:10:37 +0000 (20:10 +0000)]
[DwarfVerifier] Fixed -Wimplicit-fallthrough warning
Reviewers: JDevlieghere, RKSimon
Reviewed By: JDevlieghere
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52963
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344176
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Thomas Lively [Wed, 10 Oct 2018 19:09:16 +0000 (19:09 +0000)]
[WebAssembly][NFC] Use vnot patfrag to simplify v128.not
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53097
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344175
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Renato Golin [Wed, 10 Oct 2018 18:49:49 +0000 (18:49 +0000)]
[LV] Add a new reduction pattern match
Adding a new reduction pattern match for vectorizing code similar to TSVC s3111:
for (int i = 0; i < N; i++)
if (a[i] > b)
sum += a[i];
This patch adds support for fadd, fsub and fmull, as well as multiple
branches and different (but compatible) instructions (ex. add+sub) in
different branches.
I have forwarded to trunk, added fsub and fmul functionality and
additional tests, but the credit goes to Takahiro, who did most of the
actual work.
Differential Revision: https://reviews.llvm.org/D49168
Patch by Takahiro Miyoshi <takahiro.miyoshi@linaro.org>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344172
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Francis Visoiu Mistrih [Wed, 10 Oct 2018 18:43:42 +0000 (18:43 +0000)]
Reland: [OptRemarks] Add library for parsing optimization remarks
Add a library that parses optimization remarks (currently YAML, so based
on the YAMLParser).
The goal is to be able to provide tools a remark parser that is not
completely dependent on YAML, in case we decide to change the format
later.
It exposes a C API which takes a handler that is called with the remark
structure.
It adds a libLLVMOptRemark.a static library, and it's used in-tree by
the llvm-opt-report tool (from which the parser has been mostly moved
out).
Differential Revision: https://reviews.llvm.org/D52776
Fixed the tests by removing the usage of C++11 strings, which seems not
to be supported by gcc 4.8.4 if they're used as a macro argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344171
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Scott Linder [Wed, 10 Oct 2018 18:14:02 +0000 (18:14 +0000)]
[Support] Remove redundant qualifiers in YAMLTraits (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344166
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Francis Visoiu Mistrih [Wed, 10 Oct 2018 18:07:44 +0000 (18:07 +0000)]
Revert "[OptRemarks] Add library for parsing optimization remarks"
This reverts commit
1cc98e6672b6319fdb00b70dd4474aabdadbe193.
Seems to break bots: http://lab.llvm.org:8011/builders/clang-x86_64-linux-abi-test/builds/33398/steps/build-unified-tree/logs/stdio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344164
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Volkan Keles [Wed, 10 Oct 2018 18:01:48 +0000 (18:01 +0000)]
[GlobalISel] Fix the artifact combiner to fold G_IMPLICIT_DEF properly
Summary:
GlobalISel generates incorrect code because the legalizer artifact
combiner assumes `G_[SZ]EXT (G_IMPLICIT_DEF)` is equivalent to
`G_IMPLICIT_DEF `.
Replace `G_[SZ]EXT (G_IMPLICIT_DEF)` with 0 because the top bits
will be 0 for G_ZEXT and 0/1 for the G_SEXT.
Reviewers: aditya_nandakumar, dsanders, aemerson, javed.absar
Reviewed By: aditya_nandakumar
Subscribers: rovka, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D52996
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344163
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Francis Visoiu Mistrih [Wed, 10 Oct 2018 17:58:09 +0000 (17:58 +0000)]
[OptRemarks] Add library for parsing optimization remarks
Add a library that parses optimization remarks (currently YAML, so based
on the YAMLParser).
The goal is to be able to provide tools a remark parser that is not
completely dependent on YAML, in case we decide to change the format
later.
It exposes a C API which takes a handler that is called with the remark
structure.
It adds a libLLVMOptRemark.a static library, and it's used in-tree by
the llvm-opt-report tool (from which the parser has been mostly moved
out).
Differential Revision: https://reviews.llvm.org/D52776
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344162
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Renato Golin [Wed, 10 Oct 2018 17:55:21 +0000 (17:55 +0000)]
[VPlan] Fix CondBit quoting in dumpBasicBlock
Quotes were being printed for VPInstructions but not the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344161
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Craig Topper [Wed, 10 Oct 2018 17:37:32 +0000 (17:37 +0000)]
Change the timestamp of llvmcache-foo file to meet the thinLTO prune policy
The case will randomly fail if we test it with command "
while llvm-lit test/tools/gold/X86/cache.ll ; do true; done". It is because the llvmcache-foo file is younger than llvmcache-
349F039B8EB076D412007D82778442BED3148C4E and llvmcache-
A8107945C65C2B2BBEE8E61AA604C311D60D58D6. But due to timestamp precision reason their timestamp is the same. Given the same timestamp, the file prune policy is to remove bigger size file first, so mostly foo file is removed for its bigger size. And the files size is under threshold after deleting foo file. That's what test case expect.
However sometimes, the precision is enough to measure that timestamp of llvmcache-
349F039B8EB076D412007D82778442BED3148C4E and llvmcache-
A8107945C65C2B2BBEE8E61AA604C311D60D58D6 are smaller than foo, so llvmcache-
349F039B8EB076D412007D82778442BED3148C4E and llvmcache-
A8107945C65C2B2BBEE8E61AA604C311D60D58D6 are deleted first. Since the files size is still above the file size threshold after deleting the 2 files, the foo file is also deleted. And then the test case fails, because it expect only one file should be deleted instead of 3.
The fix is to change the timestamp of llvmcache-foo file to meet the thinLTO prune policy.
Patch by Luo Yuanke.
Differential Revision: https://reviews.llvm.org/D52452
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344158
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Scott Linder [Wed, 10 Oct 2018 16:35:47 +0000 (16:35 +0000)]
Relax trivial cast requirements in CallPromotionUtils
Differential Revision: https://reviews.llvm.org/D52792
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344153
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Guillaume Chatelet [Wed, 10 Oct 2018 16:16:43 +0000 (16:16 +0000)]
[llvm-exegesis] Fix always true assert
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344151
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Andrea Di Biagio [Wed, 10 Oct 2018 16:08:02 +0000 (16:08 +0000)]
[llvm-mca] Minor refactoring in preparation for a patch that will fully fix PR36671. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344149
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Guillaume Chatelet [Wed, 10 Oct 2018 14:57:32 +0000 (14:57 +0000)]
[llvm-exegesis][NFC] Pass Instruction instead of bare Opcode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344145
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Andrea Di Biagio [Wed, 10 Oct 2018 14:46:54 +0000 (14:46 +0000)]
[llvm-mca][BtVer2] Add two more move-elimination tests. NFC
These should test all the optimizable moves on Jaguar.
A follow-up patch will teach how to recognize these optimizable register moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344144
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Guillaume Chatelet [Wed, 10 Oct 2018 14:22:48 +0000 (14:22 +0000)]
[llvm-exegesis][NFC] Code simplification
Summary: Simplify code by having LLVMState hold the RegisterAliasingTrackerCache.
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D53078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344143
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Nirav Dave [Wed, 10 Oct 2018 14:15:52 +0000 (14:15 +0000)]
[DAGCombine] Improve Load-Store Forwarding
Summary:
Extend analysis forwarding loads from preceeding stores to work with
extended loads and truncated stores to the same address so long as the
load is fully subsumed by the store.
Hexagon's swp-epilog-phis.ll and swp-memrefs-epilog1.ll test are
deleted as they've no longer seem to be relevant.
Reviewers: RKSimon, rnk, kparzysz, javed.absar
Subscribers: sdardis, nemanjai, hiraditya, atanasyan, llvm-commits
Differential Revision: https://reviews.llvm.org/D49200
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344142
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Sanjay Patel [Wed, 10 Oct 2018 13:39:59 +0000 (13:39 +0000)]
[x86] allow single source horizontal op matching (PR39195)
This is intended to restore horizontal codegen to what it looked like before IR demanded elements improved in:
rL343727
As noted in PR39195:
https://bugs.llvm.org/show_bug.cgi?id=39195
...horizontal ops can be worse for performance than a shuffle+regular binop, so I've added a TODO. Ideally, we'd
solve that in a machine instruction pass, but a quicker solution will be adding a 'HasFastHorizontalOp' feature
bit to deal with it here in the DAG.
Differential Revision: https://reviews.llvm.org/D52997
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344141
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Jonas Devlieghere [Wed, 10 Oct 2018 13:27:25 +0000 (13:27 +0000)]
Lift VFS from clang to llvm (NFC)
This patch moves the virtual file system form clang to llvm so it can be
used by more projects.
Concretely the patch:
- Moves VirtualFileSystem.{h|cpp} from clang/Basic to llvm/Support.
- Moves the corresponding unit test from clang to llvm.
- Moves the vfs namespace from clang::vfs to llvm::vfs.
- Formats the lines affected by this change, mostly this is the result of
the added llvm namespace.
RFC on the mailing list:
http://lists.llvm.org/pipermail/llvm-dev/2018-October/126657.html
Differential revision: https://reviews.llvm.org/D52783
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344140
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John Brawn [Wed, 10 Oct 2018 13:03:23 +0000 (13:03 +0000)]
[llvm-exegesis] Fix function return generation so it doesn't return register 0
When fillMachineFunction generates a return on targets without a return opcode
(such as AArch64) it should pass an empty set of registers as the return
registers, not 0 which means register number zero.
Differential Revision: https://reviews.llvm.org/D53074
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344139
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Simon Pilgrim [Wed, 10 Oct 2018 13:00:49 +0000 (13:00 +0000)]
[TargetLowering] SimplifyDemandedBits - rename demanded mask args. NFCI.
Help stop bugs like rL343935 by making the 'original' DemandedBits arg more obviously not the mask that is actually used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344138
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Guillaume Chatelet [Wed, 10 Oct 2018 12:58:40 +0000 (12:58 +0000)]
[llvm-exegesis][NFC] Fix typo
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D53075
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344137
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Simon Pilgrim [Wed, 10 Oct 2018 12:32:13 +0000 (12:32 +0000)]
[TargetLowering] SimplifyDemandedBits - pull out repeated getOperands. NFCI.
Part of a minor cleanup to make all the switch statements more consistent prior to improving vector support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344136
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Carlos Alberto Enciso [Wed, 10 Oct 2018 12:09:34 +0000 (12:09 +0000)]
Revert "[DebugInfo][Dexter] Unreachable line stepped onto after SimplifyCFG."
This reverts commit r344120.
It was causing buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344135
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