OSDN Git Service
Zachary Turner [Fri, 26 Oct 2018 00:17:31 +0000 (00:17 +0000)]
Dump public symbol records in pdb2yaml mode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345348
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Paulsson [Fri, 26 Oct 2018 00:02:33 +0000 (00:02 +0000)]
[SystemZ] Pass the DAG pointer from SystemZAddressingMode::dump().
In order to print the IR slot number for the memory operand, the DAG pointer
must be passed to SDNode::dump().
The isel-debug.ll test updated to also check for the IR Value reference being
printed correctly.
Review: Ulrich Weigand
https://reviews.llvm.org/D53333
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345347
91177308-0d34-0410-b5e6-
96231b3b80d8
Heejin Ahn [Thu, 25 Oct 2018 23:55:10 +0000 (23:55 +0000)]
Reland "[WebAssembly] LSDA info generation"
Summary:
This adds support for LSDA (exception table) generation for wasm EH.
Wasm EH mostly follows the structure of Itanium-style exception tables,
with one exception: a call site table entry in wasm EH corresponds to
not a call site but a landing pad.
In wasm EH, the VM is responsible for stack unwinding. After an
exception occurs and the stack is unwound, the control flow is
transferred to wasm 'catch' instruction by the VM, after which the
personality function is called from the compiler-generated code. (Refer
to WasmEHPrepare pass for more information on this part.)
This patch:
- Changes wasm.landingpad.index intrinsic to take a token argument, to
make this 1:1 match with a catchpad instruction
- Stores landingpad index info and catch type info MachineFunction in
before instruction selection
- Lowers wasm.lsda intrinsic to an MCSymbol pointing to the start of an
exception table
- Adds WasmException class with overridden methods for table generation
- Adds support for LSDA section in Wasm object writer
Reviewers: dschuff, sbc100, rnk
Subscribers: mgorny, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52748
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345345
91177308-0d34-0410-b5e6-
96231b3b80d8
Heejin Ahn [Thu, 25 Oct 2018 23:45:48 +0000 (23:45 +0000)]
[WebAssembly] Support EH instructions in InstPrinter
Summary: This adds support for exception handling instructions to InstPrinter.
Reviewers: dschuff, aardappel
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53634
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345343
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Paulsson [Thu, 25 Oct 2018 23:39:07 +0000 (23:39 +0000)]
Fix in MachineOperand::printIRValueReference().
Handle the case where getCurrentFunction() returns nullptr by passing -1 to
printIRSlotNumber(). This will result in <badref> being printed instead of an
assertion failure.
Review: Francis Visoiu Mistrih
https://reviews.llvm.org/D53333
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345342
91177308-0d34-0410-b5e6-
96231b3b80d8
Bryan Chan [Thu, 25 Oct 2018 23:36:41 +0000 (23:36 +0000)]
[AArch64] Implement FP16FML intrinsics
Add LLVM intrinsics for the ARMv8.2-A FP16FML vector-form instructions. Add a
DAG pattern to define the indexed-form intrinsics in terms of the vector-form
ones, similarly to how the Dot Product intrinsics were implemented.
Based on a patch by Gao Yiling.
Differential Revision: https://reviews.llvm.org/D53632
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345337
91177308-0d34-0410-b5e6-
96231b3b80d8
Heejin Ahn [Thu, 25 Oct 2018 23:35:15 +0000 (23:35 +0000)]
Delete test case. Assertions can't be tested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345336
91177308-0d34-0410-b5e6-
96231b3b80d8
Heejin Ahn [Thu, 25 Oct 2018 23:35:15 +0000 (23:35 +0000)]
Tidy up test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345335
91177308-0d34-0410-b5e6-
96231b3b80d8
Heejin Ahn [Thu, 25 Oct 2018 23:35:14 +0000 (23:35 +0000)]
Address comments
- Add llvm-mc test case (and delete the old one)
- Change report_fatal_error to assertions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345334
91177308-0d34-0410-b5e6-
96231b3b80d8
Heejin Ahn [Thu, 25 Oct 2018 23:35:13 +0000 (23:35 +0000)]
[WebAssembly] Error out when block/loop markers mismatch
Summary:
Currently InstPrinter ignores if there are mismatches between block/loop
and end markers by skipping the case if ControlFlowStack is empty. I
guess it is better to explicitly error out in this case, because this
signals invalid input.
Reviewers: aardappel
Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53620
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345333
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Paulsson [Thu, 25 Oct 2018 22:53:27 +0000 (22:53 +0000)]
[SystemZ] NFC reformatting in SystemZTargetTransformInfo.cpp
Some lines more than 80 characters long reformatted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345331
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Paulsson [Thu, 25 Oct 2018 22:28:25 +0000 (22:28 +0000)]
[SystemZ] Improve getMemoryOpCost() to find foldable loads that are converted.
The SystemZ backend can do arithmetic of memory by loading and then extending
one of the operands. Similarly, a load + truncate can be folded into an
operand.
This patch improves the SystemZ TTI cost function to recognize this.
Review: Ulrich Weigand
https://reviews.llvm.org/D52692
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345327
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Thu, 25 Oct 2018 22:26:25 +0000 (22:26 +0000)]
DebugInfo: Explain why DW_LLE_(GNU_)startx_length is used
This isn't the most object-size efficient encoding, but it's the only
one GDB supports for the pre-standard fission format. I've written fixes
for this twice now... - so perhaps this comment will help me remember
why neither of these have been committed and why I shouldn't try to
write a third fix another year from now...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345326
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Thu, 25 Oct 2018 22:23:27 +0000 (22:23 +0000)]
[x86] add tests for missed load folding; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345325
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Paulsson [Thu, 25 Oct 2018 21:47:22 +0000 (21:47 +0000)]
[SystemZ] Improve handling and cost estimates of vector integer div/rem
Enable the DAG optimization that converts vector div/rem with constants into
multiply+shifts sequences by expanding them early. This is needed since
ISD::SMUL_LOHI is 'Custom' lowered on SystemZ, and will therefore not be
available to BuildSDIV after legalization.
Better cost values for these instructions based on how they will be
implemented (a constant divisor is cheaper).
Review: Ulrich Weigand
https://reviews.llvm.org/D53196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345321
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Thu, 25 Oct 2018 21:35:59 +0000 (21:35 +0000)]
llvm-dwarfdump: loclists: Don't expect an (albeit empty) expression for LLE_base_address
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345320
91177308-0d34-0410-b5e6-
96231b3b80d8
Sumanth Gundapaneni [Thu, 25 Oct 2018 21:27:08 +0000 (21:27 +0000)]
[Pipeliner] Ignore Artificial dependences while computing recurrences.
The artificial dependencies are not real dependencies. In some cases, they
form circuits with bigger MII. However, they are used to schedule instructions
better.
Differential Revision: https://reviews.llvm.org/D53450
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345319
91177308-0d34-0410-b5e6-
96231b3b80d8
Sumanth Gundapaneni [Thu, 25 Oct 2018 21:25:30 +0000 (21:25 +0000)]
[Pipeliner] Remove the unneeded include header(NFC).
Differential Revision: https://reviews.llvm.org/D53451
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345318
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 25 Oct 2018 21:16:06 +0000 (21:16 +0000)]
[X86] Change X86 backend to look for 'min-legal-vector-width' attribute instead of 'required-vector-width' when determining whether 512-bit vectors should be legal.
The required-vector-width attribute was only used for backend testing and has never been generated by clang.
I believe clang is now generating min-legal-vector-width for vector uses in user code.
With this I believe passing -mprefer-vector-width=256 to clang should prevent use of zmm registers in the generated assembly unless the user used a 512-bit intrinsic in their source code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345317
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Thu, 25 Oct 2018 21:12:15 +0000 (21:12 +0000)]
[CodeGen] Remove operands from FENTRY_CALL
FENTRY_CALL is actually not taking any input / output operands. The
machine verifier complains now because the target description says that:
* It needs 1 unknown output
* It needs 1 or more variable inputs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345316
91177308-0d34-0410-b5e6-
96231b3b80d8
David Greene [Thu, 25 Oct 2018 21:10:39 +0000 (21:10 +0000)]
[AArch64] Create proper memoperand for multi-vector stores
Include all of the store's source vector operands when creating the
MachineMemOperand. Previously, we were missing the first operand,
making the store size seem smaller than it really is.
Differential Revision: https://reviews.llvm.org/D52816
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345315
91177308-0d34-0410-b5e6-
96231b3b80d8
Volkan Keles [Thu, 25 Oct 2018 20:01:19 +0000 (20:01 +0000)]
[AArch64][GlobalISel] Simplify a legalizer test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345307
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Thu, 25 Oct 2018 19:06:13 +0000 (19:06 +0000)]
[WebAssembly] Use target-independent saturating add
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53721
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345299
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 25 Oct 2018 18:23:48 +0000 (18:23 +0000)]
[X86] Add some non-AVX512VL command lines to the *vl-vec-test-testn.ll tests.
This will expose some regressions in the WIP and/or/xor promotion removal patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345297
91177308-0d34-0410-b5e6-
96231b3b80d8
Cameron McInally [Thu, 25 Oct 2018 18:09:33 +0000 (18:09 +0000)]
[FPEnv] Last BinaryOperator::isFNeg(...) to m_FNeg(...) changes
Replacing BinaryOperator::isFNeg(...) to avoid regressions when we
separate FNeg from the FSub IR instruction.
Differential Revision: https://reviews.llvm.org/D53650
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345295
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 25 Oct 2018 18:06:25 +0000 (18:06 +0000)]
[X86] Add KNL command lines to movmsk-cmp.ll.
Some of this code looks pretty bad and we should probably still be using movmskb more with avx512f.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345293
91177308-0d34-0410-b5e6-
96231b3b80d8
Volkan Keles [Thu, 25 Oct 2018 17:52:19 +0000 (17:52 +0000)]
[GlobalISel] LegalizerHelper: Fix the incorrect alignment when splitting loads/stores in narrowScalar
Reviewers: dsanders, bogner, jpaquette, aemerson, ab, paquette
Reviewed By: dsanders
Subscribers: rovka, kristof.beyls, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D53664
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345292
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 25 Oct 2018 17:43:36 +0000 (17:43 +0000)]
[LegalizeDAG] Remove dead SINT_TO_FP legalization code
As noticed on D52965, the SINT_TO_FP i64 to f32 legalization code has been dead for years - protected by an assert.
Differential Revision: https://reviews.llvm.org/D53703
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345290
91177308-0d34-0410-b5e6-
96231b3b80d8
Volkan Keles [Thu, 25 Oct 2018 17:37:07 +0000 (17:37 +0000)]
[GISel] LegalizerInfo: Rename MemDesc::Size to SizeInBits to make the value clearer
Requested in D53679.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345288
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 25 Oct 2018 17:29:00 +0000 (17:29 +0000)]
[X86] Remove ProcIntelKNL and replace with a SlowPMADDWD flag to use in the one place it was checked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345286
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 25 Oct 2018 17:28:57 +0000 (17:28 +0000)]
[X86] Remove some uarch tuning flags from KNL that look to have been inherited from SNB/IVB incorrectly
KNL is based on a modified Silvermont core so I don't think these features apply. I think the LEA flag is probably also wrong, but I'm less sure as I barely understand the 3 LEA flags we have currently.
Differential Revision: https://reviews.llvm.org/D53671
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345285
91177308-0d34-0410-b5e6-
96231b3b80d8
Volkan Keles [Thu, 25 Oct 2018 17:23:25 +0000 (17:23 +0000)]
[AArch64][GlobalISel] Fix the LegalityPredicate for lowerIf for G_LOAD/G_STORE
Summary:
Currently, Legalizer is trying to lower G_LOAD with a vector type
that has more than two elements due to the incorrect LegalityPredicate.
This patch fixes the issue by removing the multiplication by 8
as `MemDesc.Size` already contains the size in bits.
Reviewers: dsanders, aemerson
Reviewed By: dsanders
Subscribers: rovka, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D53679
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345282
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrea Di Biagio [Thu, 25 Oct 2018 17:03:51 +0000 (17:03 +0000)]
[llvm-mca] Introduce a new base class for mca::Instruction, and change how read/write information is stored.
This patch introduces a new base class for Instruction named InstructionBase.
Class InstructionBase is responsible for tracking data dependencies with the
help of ReadState and WriteState objects. Class Instruction now derives from
InstructionBase, and adds extra information related to the `InstrStage` as well
as the `RCUTokenID`.
ReadState and WriteState objects are no longer unique pointers. This avoids
extra heap allocation and pointer checks that weren't really needed. Now, those
objects are simply stored into SmallVectors. We use a SmallVector instead of a
std::vector because we expect most instructions to only have a very small number
of reads and writes. By using a simple SmallVector we also avoid extra heap
allocations most of the time.
In a debug build, this improves the performance of llvm-mca by roughly 10% (I
still have to verify the impact in performance on a release build).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345280
91177308-0d34-0410-b5e6-
96231b3b80d8
Evandro Menezes [Thu, 25 Oct 2018 16:45:46 +0000 (16:45 +0000)]
[AArch64] Refactor Exynos feature sets (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345279
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 25 Oct 2018 15:33:47 +0000 (15:33 +0000)]
[ARM] Regenerate vdup tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345276
91177308-0d34-0410-b5e6-
96231b3b80d8
John Brawn [Thu, 25 Oct 2018 15:31:51 +0000 (15:31 +0000)]
[AArch64] Add EXT patterns for 64-bit EXT of a subvector of a 128-bit vector
If we have a 64-bit EXT where one of the operands is a subvector of a 128-bit
vector then in some cases we can eliminate an extract_subvector by converting
to a 128-bit EXT of the 128-bit vector.
Differential Revision: https://reviews.llvm.org/D53582
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345275
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam Parker [Thu, 25 Oct 2018 15:08:29 +0000 (15:08 +0000)]
[ARM] Use Cortex-A57 sched model for Cortex-A72
This mirrors what we already do for AArch64 as the cores are similar.
As discussed in the review, enabling the machine scheduler causes
more variations in performance changes so it is not enabled for now.
This patch improves LNT scores by a geomean of 1.57% at -O3.
Differential Revision: https://reviews.llvm.org/D53562
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345272
91177308-0d34-0410-b5e6-
96231b3b80d8
John Brawn [Thu, 25 Oct 2018 15:00:10 +0000 (15:00 +0000)]
[AArch64] Refactor definition of EXT patterns to use a multiclass
Using a multiclass reduces duplication, and makes it easier to add new patterns
later. This refactoring does add some new patterns, but as far as I can tell
there's no IR that will end up triggering them so this is effectively NFC.
Differential Revision: https://reviews.llvm.org/D53580
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345271
91177308-0d34-0410-b5e6-
96231b3b80d8
John Brawn [Thu, 25 Oct 2018 14:56:48 +0000 (14:56 +0000)]
[AArch64] Do 64-bit vector move of 0 and -1 by extracting from the 128-bit move
Currently a vector move of 0 or -1 will use different instructions depending on
the size of the vector. Using a single instruction (the 128-bit one) for both
gives more opportunity for Machine CSE to eliminate instructions.
Differential Revision: https://reviews.llvm.org/D53579
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345270
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Thu, 25 Oct 2018 14:27:27 +0000 (14:27 +0000)]
[DEBUG_INFO][NVPTX]Fix processing of DBG_VALUES.
Summary:
If the instruction in the eliminateFrameIndex function is a DBG_VALUE
instruction, it requires special processing. The frame register is set
to VRFrame and the offset is based on the object offset.
The code is similar to the code used in
lib/CodeGen/PrologEpilogInserter.cpp.
Reviewers: tra
Subscribers: jholewinski, llvm-commits
Differential Revision: https://reviews.llvm.org/D53657
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345269
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Thu, 25 Oct 2018 14:11:07 +0000 (14:11 +0000)]
[X86] Fix llc invocation on MIR test case
The current state of the llc invocation is:
* Running all the passes from dwarfehprepare to stack coloring
(included)
* It runs it from the LLVM IR included in the file
* It *ADDS* the generated MI from ISel to the MI in the MIR file
* The machine verifier doesn't like it.
Differential Revision: https://reviews.llvm.org/D53698
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345266
91177308-0d34-0410-b5e6-
96231b3b80d8
Amara Emerson [Thu, 25 Oct 2018 14:04:54 +0000 (14:04 +0000)]
[GlobalISel] Use the target preferred type for G_EXTRACT_VECTOR_ELT index.
Allows for better imported pattern re-use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345265
91177308-0d34-0410-b5e6-
96231b3b80d8
Krasimir Georgiev [Thu, 25 Oct 2018 13:38:07 +0000 (13:38 +0000)]
IR: Optimize StructType::get to perform one hash lookup instead of two, NFCI
Summary:
This function was performing two hash lookups when a new struct type was requested: first checking if it exists and second to insert it. This patch updates the function to perform a single hash lookup in this case by updating the value in the hash table in-place in case the struct type was not there before.
Similar to r345151.
Reviewers: bkramer
Reviewed By: bkramer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53689
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345264
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 25 Oct 2018 13:06:20 +0000 (13:06 +0000)]
[CostModel][X86] Add realistic vXi64 uitofp vXf64 costs
Match codegen improvements from D53649/rL345256
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345263
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Bradbury [Thu, 25 Oct 2018 12:45:20 +0000 (12:45 +0000)]
[RISCV] Use PatFrags for variable shift patterns
This follows SystemZ and I think is cleaner vs the multiclass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345262
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 25 Oct 2018 12:42:10 +0000 (12:42 +0000)]
[CostModel][X86] Add realistic i64 uitofp f64 scalar costs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345261
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrea Di Biagio [Thu, 25 Oct 2018 11:51:34 +0000 (11:51 +0000)]
[llvm-mca] Removed a couple of redundant method declarations, and simplified code in ResourcePressureView. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345259
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 25 Oct 2018 11:38:17 +0000 (11:38 +0000)]
Missing semicolon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345257
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 25 Oct 2018 11:15:57 +0000 (11:15 +0000)]
[TargetLowering] Improve vXi64 UINT_TO_FP vXf64 support (P38226)
As suggested on D52965, this patch moves the i64 to f64 UINT_TO_FP expansion code from LegalizeDAG into TargetLowering and makes it available to LegalizeVectorOps as well.
Not only does this help perform X86 lowering as a true vectorization instead of (partially vectorized) scalar conversions, it avoids the HADDPD op from the scalar code which can be slow on most targets.
The AVX512F does have the vcvtusi2sdq scalar operation but we don't unroll to use it as it seems to only help for the v2f64 case - otherwise the unrolling cost will certainly be too high. My feeling is that we should leave it to the vectorizers - and if it generates the vector UINT_TO_FP we should use it.
Differential Revision: https://reviews.llvm.org/D53649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345256
91177308-0d34-0410-b5e6-
96231b3b80d8
George Rimar [Thu, 25 Oct 2018 10:56:44 +0000 (10:56 +0000)]
[llvm-dwarfdump] - Fix incorrect parsing of the DW_LLE_startx_length
As was already mentioned in comments for D53364, DWARF 5
spec says about DW_LLE_startx_length:
"This is a form of bounded location description that has two unsigned ULEB operands.
The first value is an address index (into the .debug_addr section) that indicates the beginning of the address range
over which the location is valid. The second value is the length of the range. ")
Currently, the length is always parsed as U32.
Patch change the behavior to parse DW_LLE_startx_length as ULEB128 for DWARF 5
and keeps it as U32 for DWARF4+(pre-DWARF5) for compatibility.
Differential revision: https://reviews.llvm.org/D53564
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345254
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 25 Oct 2018 10:52:36 +0000 (10:52 +0000)]
[TTI] Add generic SK_Broadcast shuffle costs
I noticed while fixing PR39368 that we don't have generic shuffle costs for broadcast style shuffles.
This patch adds SK_BROADCAST handling, but exposes ARM/AARCH64 lack of handling of this type, which I've added a fix for at the same time.
Differential Revision: https://reviews.llvm.org/D53570
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345253
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 25 Oct 2018 10:45:38 +0000 (10:45 +0000)]
Fix MSVC llvm-exegesis build. NFCI.
MSVC is a bit funny about is_pod.....
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345252
91177308-0d34-0410-b5e6-
96231b3b80d8
Carlos Alberto Enciso [Thu, 25 Oct 2018 09:58:59 +0000 (09:58 +0000)]
[DebugInfo][Dexter] Unreachable line stepped onto after SimplifyCFG.
When SimplifyCFG changes the PHI node into a select instruction, the debug line records becomes ambiguous. It causes the debugger to display unreachable source lines.
Differential Revision: https://reviews.llvm.org/D53287
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345250
91177308-0d34-0410-b5e6-
96231b3b80d8
Gabor Buella [Thu, 25 Oct 2018 08:32:29 +0000 (08:32 +0000)]
Add -instcombine-code-sinking option
Reviewers: craig.topper, andrew.w.kaylor, efriedma
Reviewed By: craig.topper, andrew.w.kaylor, efriedma
Differential Revision: https://reviews.llvm.org/D52709
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345248
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Thu, 25 Oct 2018 08:11:35 +0000 (08:11 +0000)]
[llvm-exegesis] Add missing initializer.
This is a better fix than rL345245.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345246
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Thu, 25 Oct 2018 08:08:58 +0000 (08:08 +0000)]
[llvm-exegesis] Fix VC build of r345243.
"const members cannot be default initialized unless their type has a user defined default constructor"
Make members non-const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345245
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Thu, 25 Oct 2018 08:06:35 +0000 (08:06 +0000)]
[llvm-exegesis] Fix warning in r345243.
warning C4099: 'llvm::exegesis::PfmCountersInfo': type name first seen using 'class' now seen using 'struct'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345244
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Thu, 25 Oct 2018 07:44:01 +0000 (07:44 +0000)]
[MCSched] Bind PFM Counters to the CPUs instead of the SchedModel.
Summary:
The pfm counters are now in the ExegesisTarget rather than the
MCSchedModel (PR39165).
This also compresses the pfm counter tables (PR37068).
Reviewers: RKSimon, gchatelet
Subscribers: mgrang, llvm-commits
Differential Revision: https://reviews.llvm.org/D52932
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345243
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 25 Oct 2018 07:00:09 +0000 (07:00 +0000)]
[X86] Don't use the OriginalDemandedBits to calculate the DemandedMask for PMULUDQ/PMULDQ inputs.
Multiply a is complex operation so just because some bit of the output isn't used doesn't mean that bit of the input isn't used.
We might able to bound it, but it will require some more thought.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345241
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Atanasyan [Thu, 25 Oct 2018 05:39:27 +0000 (05:39 +0000)]
[llvm-readobj] Print ELF header flags names in GNU output
GNU readelf tool prints hex value of the ELF header flags field and the
flags names. This change adds the same functionality to llvm-readobj.
Now llvm-readobj can print MIPS and RISCV flags.
New GNUStyle::printFlags() method is a copy of ScopedPrinter::printFlags()
routine. Probably we can escape code duplication and / or simplify the
printFlags() method. But it's a task for separate commit.
Differential revision: https://reviews.llvm.org/D52027
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345238
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 25 Oct 2018 05:00:20 +0000 (05:00 +0000)]
[X86] Fix typo in comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345236
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Thu, 25 Oct 2018 01:46:07 +0000 (01:46 +0000)]
[WebAssembly] Set LoadExt and TruncStore actions for SIMD types
Summary: Fixes part of the problem reported in bug 39275.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits, alexcrichton
Differential Revision: https://reviews.llvm.org/D53542
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345230
91177308-0d34-0410-b5e6-
96231b3b80d8
Reid Kleckner [Wed, 24 Oct 2018 23:52:33 +0000 (23:52 +0000)]
[X86] Adjust MIR test case to pacify machine verifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345227
91177308-0d34-0410-b5e6-
96231b3b80d8
Reid Kleckner [Wed, 24 Oct 2018 23:52:22 +0000 (23:52 +0000)]
[X86] Fix pipeline tests when enabling MIR verification, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345226
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Wed, 24 Oct 2018 23:36:29 +0000 (23:36 +0000)]
DebugInfo: Reuse common addresses for rnglist base address selections
This makes the offsets larger (since they are further from the base
address) but those are in the .dwo - and allows removing addresses and
relocations from the .o file.
This could be built into the AddressPool more fundamentally, perhaps -
when you ask for an AddressPool entry you could say "or give me some
other entry and an offset I need to use" - though what to do about
situations where the first use of an address in a section is not the
earliest address in that section... is tricky.
At least with range addresses we can be fairly sure we've seen the
earliest address first because we see the start address for the
function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345224
91177308-0d34-0410-b5e6-
96231b3b80d8
Heejin Ahn [Wed, 24 Oct 2018 23:31:24 +0000 (23:31 +0000)]
[WebAssembly] Fix immediate of rethrow when throwing to caller
Summary:
Currently when assigning depths 'rethrow' does not take the whole
control flow stack into accounts but only considers EH pad stacks. When
assigning depth immmediates to rethrows, in normal cases it is done
correctly but when a rethrow instruction throws up to a caller, i.e., we
convert a pseudo RETHROW_TO_CALLER instruction to a rethrow, it
mistakenly compute the whole stack depth.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53619
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345223
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Wed, 24 Oct 2018 23:27:40 +0000 (23:27 +0000)]
[WebAssembly] Retain shuffle types during custom lowering
Summary:
Changing the node type in lowering was violating assumptions made in
the DAG combiner, so don't change the node type any more. This fixes
one of the issues reported in bug 39275.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits, alexcrichton
Differential Revision: https://reviews.llvm.org/D53537
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345221
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Wed, 24 Oct 2018 23:14:59 +0000 (23:14 +0000)]
Make fminimum/fmaximum SDNodes commutative and associative
Reviewers: aheejin, dschuff
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53680
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345220
91177308-0d34-0410-b5e6-
96231b3b80d8
Reid Kleckner [Wed, 24 Oct 2018 22:57:28 +0000 (22:57 +0000)]
[ELF] Fix large code model MIR verifier errors
Instead of using the MOVGOT64r pseudo, use the existing
MO_PIC_BASE_OFFSET support on symbol operands. Now I don't have to
create a "scratch register operand" for the pseudo to use, and the
register allocator can make better decisions.
Fixes some X86 verifier errors tracked in PR27481.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345219
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Wed, 24 Oct 2018 22:49:55 +0000 (22:49 +0000)]
[NFC] Rename minnan and maxnan to minimum and maximum
Summary:
Changes all uses of minnan/maxnan to minimum/maximum
globally. These names emphasize that the semantic difference between
these operations is more than just NaN-propagation.
Reviewers: arsenm, aheejin, dschuff, javed.absar
Subscribers: jholewinski, sdardis, wdng, sbc100, jgravelle-google, jrtc27, atanasyan, llvm-commits
Differential Revision: https://reviews.llvm.org/D53112
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345218
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexander Shaposhnikov [Wed, 24 Oct 2018 22:49:06 +0000 (22:49 +0000)]
[llvm-objcopy] Introduce dispatch mechanism based on the input
In this diff we introduce dispatch mechanism based on
the type of the input (archive, object file, raw binary)
and the format (coff, elf, macho).
We also move the ELF-specific code into the namespace llvm::objcopy::elf.
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D53311
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345217
91177308-0d34-0410-b5e6-
96231b3b80d8
Alina Sbirlea [Wed, 24 Oct 2018 22:46:45 +0000 (22:46 +0000)]
Update MemorySSA in LoopRotate.
Summary:
Teach LoopRotate to preserve MemorySSA.
Enable tests for correctness, dependency disabled by default.
Subscribers: sanjoy, jlebar, Prazek, george.burgess.iv, llvm-commits
Differential Revision: https://reviews.llvm.org/D51718
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345216
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Wed, 24 Oct 2018 22:44:54 +0000 (22:44 +0000)]
llvm-dwarfdump: Account for skeleton addr_base when dumping addresses in split unit in the same file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345215
91177308-0d34-0410-b5e6-
96231b3b80d8
Volodymyr Sapsai [Wed, 24 Oct 2018 22:40:54 +0000 (22:40 +0000)]
[VFS] Remove 'ignore-non-existent-contents' attribute for YAML-based VFS.
'ignore-non-existent-contents' stopped working after r342232 in a way
that the actual attribute value isn't used and it works as if it is
always `true`.
Common use case for VFS iteration is iterating through files in umbrella
directories for modules. Ability to detect if some VFS entries point to
non-existing files is nice but non-critical. Instead of adding back
support for `'ignore-non-existent-contents': false` I am removing the
attribute, because such scenario isn't used widely enough and stricter
checks don't provide enough value to justify the maintenance.
Change is done both in LLVM and Clang, corresponding Clang commit is r345212.
rdar://problem/
45176119
Reviewers: bruno
Reviewed By: bruno
Subscribers: hiraditya, dexonsmith, sammccall, cfe-commits
Differential Revision: https://reviews.llvm.org/D53228
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345213
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Wed, 24 Oct 2018 22:18:54 +0000 (22:18 +0000)]
[SelectionDAG] DAG combiner for fminnan and fmaxnan
Summary: Depends on D52765.
Reviewers: aheejin, dschuff
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52768
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345210
91177308-0d34-0410-b5e6-
96231b3b80d8
Vedant Kumar [Wed, 24 Oct 2018 22:15:41 +0000 (22:15 +0000)]
[HotColdSplitting] Identify larger cold regions using domtree queries
The current splitting algorithm works in three stages:
1) Identify cold blocks, then
2) Use forward/backward propagation to mark hot blocks, then
3) Grow a SESE region of blocks *outside* of the set of hot blocks and
start outlining.
While testing this pass on Apple internal frameworks I noticed that some
kinds of control flow (e.g. loops) are never outlined, even though they
unconditionally lead to / follow cold blocks. I noticed two other issues
related to how cold regions are identified:
- An inconsistency can arise in the internal state of the hotness
propagation stage, as a block may end up in both the ColdBlocks set
and the HotBlocks set. Further inconsistencies can arise as these sets
do not match what's in ProfileSummaryInfo.
- It isn't necessary to limit outlining to single-exit regions.
This patch teaches the splitting algorithm to identify maximal cold
regions and outline them. A maximal cold region is defined as the set of
blocks post-dominated by a cold sink block, or dominated by that sink
block. This approach can successfully outline loops in the cold path. As
a side benefit, it maintains less internal state than the current
approach.
Due to a limitation in CodeExtractor, blocks within the maximal cold
region which aren't dominated by a single entry point (a so-called "max
ancestor") are filtered out.
Results:
- X86 (LNT + -Os + externals): 134KB of TEXT were outlined compared to
47KB pre-patch, or a ~3x improvement. Did not see a performance impact
across two runs.
- AArch64 (LNT + -Os + externals + Apple-internal benchmarks): 149KB
of TEXT were outlined. Ditto re: performance impact.
- Outlining results improve marginally in the internal frameworks I
tested.
Follow-ups:
- Outline more than once per function, outline large single basic
blocks, & try to remove unconditional branches in outlined functions.
Differential Revision: https://reviews.llvm.org/D53627
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345209
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 24 Oct 2018 22:02:05 +0000 (22:02 +0000)]
[InstCombine] add test for fptrunc with vector with undef elt; NFC
This should be fixed with D53650.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345206
91177308-0d34-0410-b5e6-
96231b3b80d8
Paul Robinson [Wed, 24 Oct 2018 21:51:55 +0000 (21:51 +0000)]
Make llvm-dwarfdump -name work on type units.
Differential Revision: https://reviews.llvm.org/D53672
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345203
91177308-0d34-0410-b5e6-
96231b3b80d8
Joel E. Denny [Wed, 24 Oct 2018 21:46:42 +0000 (21:46 +0000)]
[SourceMgr][FileCheck] Obey -color by extending WithColor
(Relands r344930, reverted in r344935, and now hopefully fixed for
Windows.)
While this change specifically targets FileCheck, it affects any tool
using the same SourceMgr facilities.
Previously, -color was documented in FileCheck's -help output, but
-color had no effect. Now, -color obeys its documentation: it forces
colors to be used in FileCheck diagnostics even when stderr is not a
terminal.
-color is especially helpful when combined with FileCheck's -v, which
can produce a long series of diagnostics that you might wish to pipe
to a pager, such as less -R. The WithColor extensions here will also
help to clean up color usage in FileCheck's annotated dump of input,
which is proposed in D52999.
Reviewed By: JDevlieghere, zturner
Differential Revision: https://reviews.llvm.org/D53419
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345202
91177308-0d34-0410-b5e6-
96231b3b80d8
Evandro Menezes [Wed, 24 Oct 2018 21:40:43 +0000 (21:40 +0000)]
[AArch64] Refactor Exynos machine model
Effectively, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345201
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Wed, 24 Oct 2018 21:36:34 +0000 (21:36 +0000)]
[DAG] check more operands for cycles when merging stores.
Until now, we've only checked whether merging stores would cause a cycle via
the value argument, but the address and indexed offset arguments are also
capable of creating cycles in some situations.
The addresses are all base+offset with notionally the same base, but the base
SDNode may still be different (e.g. via an indexed load in one case, and an
ISD::ADD elsewhere). This allows cycles to creep in if one of these sources
depends on another.
The indexed offset is usually undef (representing a non-indexed store), but on
some architectures (e.g. 32-bit ARM-mode ARM) it can be an arbitrary value,
again allowing dependency cycles to creep in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345200
91177308-0d34-0410-b5e6-
96231b3b80d8
Reid Kleckner [Wed, 24 Oct 2018 21:09:34 +0000 (21:09 +0000)]
[X86] Add *SP to tailcall register class to fix verifier error
It's possible to do a tail call to a stack argument. LLVM already
calculates the right stack offset to call through.
Fixes the sibcall* and musttail* verifier failures tracked at PR27481.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345197
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjin Sijaric [Wed, 24 Oct 2018 21:07:38 +0000 (21:07 +0000)]
[MIR] Add hasWinCFI field
Adding hasWinCFI field so that I can add MIR test cases to
https://reviews.llvm.org/D50166.
Differential Revision: https://reviews.llvm.org/D51201
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345196
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Wed, 24 Oct 2018 20:37:40 +0000 (20:37 +0000)]
[ExecutionEngine] Remove some dead code from JITEventListener.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345195
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Davis [Wed, 24 Oct 2018 20:27:47 +0000 (20:27 +0000)]
[llvm-mca] Replace InstRef::isValid with operator bool. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345190
91177308-0d34-0410-b5e6-
96231b3b80d8
Reid Kleckner [Wed, 24 Oct 2018 20:23:57 +0000 (20:23 +0000)]
[MC] Separate masm integer literal lexer support from inline asm
Summary:
This renames the IsParsingMSInlineAsm member variable of AsmLexer to
LexMasmIntegers and moves it up to MCAsmLexer. This is the only behavior
controlled by that variable. I added a public setter, so that it can be
set from outside or from the llvm-mc command line. We may need to
arrange things so that users can get this behavior from clang, but
that's future work.
I also put additional hex literal lexing functionality under this flag
to fix PR32973. It appears that this hex literal parsing wasn't intended
to be enabled in non-masm-style blocks.
Now, masm integers (0b1101 and 0ABCh) work in __asm blocks from clang,
but 0b label references work when using .intel_syntax in standalone .s
files.
However, 0b label references will *not* work from __asm blocks in clang.
They will work from GCC inline asm blocks, which it sounds like is
important for Crypto++ as mentioned in PR36144.
Essentially, we only lex masm literals for inline asm blobs that use
intel syntax. If the .intel_syntax directive is used inside a gnu-style
inline asm statement, masm literals will not be lexed, which is
compatible with gas and llvm-mc standalone .s assembly.
This fixes PR36144 and PR32973.
Reviewers: Gerolf, avt77
Subscribers: eraman, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D53535
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345189
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Wed, 24 Oct 2018 20:19:09 +0000 (20:19 +0000)]
AArch64: add a pass to compress jump-table entries when possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345188
91177308-0d34-0410-b5e6-
96231b3b80d8
Evandro Menezes [Wed, 24 Oct 2018 20:03:24 +0000 (20:03 +0000)]
[AArch64] Refactor Exynos machine model (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345187
91177308-0d34-0410-b5e6-
96231b3b80d8
Evandro Menezes [Wed, 24 Oct 2018 20:03:20 +0000 (20:03 +0000)]
[AArch64] Fix overlapping instructions
Fix overlapping instruction descriptions in the machine model for Exynos M3.
Effectively, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345186
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrea Di Biagio [Wed, 24 Oct 2018 19:37:45 +0000 (19:37 +0000)]
[llvm-mca] Simplify the logic in FetchStage. NFCI
Only method 'getNextInstruction()' needs to interact with the SourceMgr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345185
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 24 Oct 2018 19:24:44 +0000 (19:24 +0000)]
[X86] Explicitly list all KNL features of inheriting from IVB. NFC
I'm not sure all the microarchitectural tuning flags that have been added to IVBFeatures are relevant for KNL. Separating will allow us to see and audit them. There might even be some simplification opportunities in the Sandy Bridge through Icelake inheritance line without KNL using the same chain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345183
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 24 Oct 2018 19:11:28 +0000 (19:11 +0000)]
[X86][SSE] Add SimplifyDemandedBitsForTargetNode PMULDQ/PMULUDQ handling
Add X86 SimplifyDemandedBitsForTargetNode and use it to simplify PMULDQ/PMULUDQ target nodes.
This enables us to repeatedly simplify the node's arguments after the previous approach had to be reverted due to PR39398.
Differential Revision: https://reviews.llvm.org/D53643
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345182
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 24 Oct 2018 19:00:56 +0000 (19:00 +0000)]
[TargetLowering] Add SimplifyDemandedBitsForTargetNode callback
Add a SimplifyDemandedBitsForTargetNode callback to handle target nodes.
Differential Revision: https://reviews.llvm.org/D53643
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345179
91177308-0d34-0410-b5e6-
96231b3b80d8
Teresa Johnson [Wed, 24 Oct 2018 18:53:47 +0000 (18:53 +0000)]
[hot-cold-split] Name split functions with ".cold" suffix
Summary:
The current default of appending "_"+entry block label to the new
extracted cold function breaks demangling. Change the deliminator from
"_" to "." to enable demangling. Because the header block label will
be empty for release compile code, use "extracted" after the "." when
the label is empty.
Additionally, add a mechanism for the client to pass in an alternate
suffix applied after the ".", and have the hot cold split pass use
"cold."+Count, where the Count is currently 1 but can be used to
uniquely number multiple cold functions split out from the same function
with D53588.
Reviewers: sebpop, hiraditya
Subscribers: llvm-commits, erik.pilkington
Differential Revision: https://reviews.llvm.org/D53534
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345178
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 24 Oct 2018 18:44:12 +0000 (18:44 +0000)]
[CostModel][X86] Add vXi8 vector division by constants costs.
ISD::MULHS/ISD::MULHU lowering of vXi8 types means we expand these in TargetLowering BuildSDIV/BuildUDIV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345175
91177308-0d34-0410-b5e6-
96231b3b80d8
Peter Collingbourne [Wed, 24 Oct 2018 18:10:38 +0000 (18:10 +0000)]
ARM: Use BKPT instead of TRAP to implement llvm.debugtrap.
The BKPT instruction is specified to cause a software breakpoint,
and at least on Linux results in a SIGTRAP. This makes it more
suitable for implementing debugtrap than TRAP (aka UDF #254), which
is specified to cause an undefined instruction exception and results
in a SIGILL on Linux.
Moreover, BKPT is not marked as a terminator, which is not only
consistent with the IR instruction but allows the analyzeBlock
function to correctly analyze a basic block containing the instruction,
which fixes an assertion failure in the machine block placement pass
previously triggered by the included test case.
Because BKPT is only supported starting with ARMv5T, we continue to
use UDF #254 when targeting v4T.
Differential Revision: https://reviews.llvm.org/D53614
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345171
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Wed, 24 Oct 2018 17:55:13 +0000 (17:55 +0000)]
[Hexagon] Flip hexagon-autohvx to be true by default
This will allow other generators of LLVM IR to use the auto-vectorizer
without having to change that flag.
Note: on its own, this patch will enable auto-vectorization on Hexagon
in all cases, regardless of the -fvectorize flag. There is a companion
clang patch that together with this one forms an NFC for clang users.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345169
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Kruse [Wed, 24 Oct 2018 17:35:35 +0000 (17:35 +0000)]
[docs] Add rawspeed to test-suite proposals.
rawspeed was suggested by Simon Pilgrim and Roman Lebedev in
llvm.org/PR34216 and reviews.llvm.org/D46714.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345166
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 24 Oct 2018 17:32:09 +0000 (17:32 +0000)]
[X86] Bring back the MOV64r0 pseudo instruction
This patch brings back the MOV64r0 pseudo instruction for zeroing a 64-bit register. This replaces the SUBREG_TO_REG MOV32r0 sequence we use today. Post register allocation we will rewrite the MOV64r0 to a 32-bit xor with an implicit def of the 64-bit register similar to what we do for the various XMM/YMM/ZMM zeroing pseudos.
My main motivation is to enable the spill optimization in foldMemoryOperandImpl. As we were seeing some code that repeatedly did "xor eax, eax; store eax;" to spill several registers with a new xor for each store. With this optimization enabled we get a store of a 0 immediate instead of an xor. Though I admit the ideal solution would be one xor where there are multiple spills. I don't believe we have a test case that shows this optimization in here. I'll see if I can try to reduce one from the code were looking at.
There's definitely some other machine CSE(and maybe other passes) behavior changes exposed by this patch. So it seems like there might be some other deficiencies in SUBREG_TO_REG handling.
Differential Revision: https://reviews.llvm.org/D52757
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345165
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 24 Oct 2018 17:30:29 +0000 (17:30 +0000)]
[CostModel][X86] Enable non-uniform vector division by constants costs.
Non-uniform division/remainder handling was added back at D49248/D50765 - so share the 'mul+sub' costs that already exist for uniform cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345164
91177308-0d34-0410-b5e6-
96231b3b80d8