OSDN Git Service
Craig Topper [Mon, 11 Dec 2017 06:16:26 +0000 (06:16 +0000)]
[X86] Regenerate test with update_llc_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320342
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Craig Topper [Mon, 11 Dec 2017 01:48:10 +0000 (01:48 +0000)]
[X86] Add a test case for masked scatter where the index needs to be legalized from v2i32 while other types are legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320340
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Simon Pilgrim [Sun, 10 Dec 2017 22:11:56 +0000 (22:11 +0000)]
[X86] Add ROL/ROR schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320334
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Simon Pilgrim [Sun, 10 Dec 2017 21:56:24 +0000 (21:56 +0000)]
[X86] Add DIV/MUL/NEG/NOP/NOT/PAUSE schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320333
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Simon Pilgrim [Sun, 10 Dec 2017 21:28:00 +0000 (21:28 +0000)]
[X86] Add DEC/INC schedule tests
Include i686 (non-REX) variant tests as well
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320332
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Simon Pilgrim [Sun, 10 Dec 2017 21:10:28 +0000 (21:10 +0000)]
[X86] Add INS/OUTS schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320331
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Simon Pilgrim [Sun, 10 Dec 2017 20:58:22 +0000 (20:58 +0000)]
[X86] Add CMPS/MOVS/SCAS/STOS schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320330
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Simon Pilgrim [Sun, 10 Dec 2017 20:46:57 +0000 (20:46 +0000)]
[X86] Add CMOV schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320329
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Simon Pilgrim [Sun, 10 Dec 2017 20:22:47 +0000 (20:22 +0000)]
[X86] Add BT/BTC/BTR/BTS schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320328
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Craig Topper [Sun, 10 Dec 2017 19:47:57 +0000 (19:47 +0000)]
[X86] Add VCOMISDZrr, VCOMISSZrr, VUCOMISDZrr, and VUCOMISSZrr to the skylake server sheduler model
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320326
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Craig Topper [Sun, 10 Dec 2017 19:47:56 +0000 (19:47 +0000)]
[X86] Rename some instructions that start with Int_ to have the _Int at the end.
This matches AVX512 version and is more consistent overall. And improves our scheduler models.
In some cases this adds _Int to instructions that didn't have any Int_ before. It's a side effect of the adjustments made to some of the multiclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320325
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Simon Pilgrim [Sun, 10 Dec 2017 19:19:22 +0000 (19:19 +0000)]
[X86][X87] Fix typo in znver1 FIST/FISTT schedule patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320322
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Simon Pilgrim [Sun, 10 Dec 2017 18:53:15 +0000 (18:53 +0000)]
[X86][X87] Add missing x87 scheduler tests
Split off some 'n' instruction versions to make it clearer when WAIT is being inserted
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320321
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Craig Topper [Sun, 10 Dec 2017 17:42:44 +0000 (17:42 +0000)]
[X86] Rename some instructions from 'rb' to 'rrb' to make 'b' a proper suffix. Fix the scheduling information for some of them.
Some of the scheduling information was only present for the 'rb' version' and not the 'rr' version. Now we match 'rr(b?)'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320320
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Craig Topper [Sun, 10 Dec 2017 17:42:43 +0000 (17:42 +0000)]
[X86] Add VCVTQQ2PS to the skylake server scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320319
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Craig Topper [Sun, 10 Dec 2017 17:42:42 +0000 (17:42 +0000)]
[X86] Add VPMULLWZ256 to the skylake server scheduler model
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320318
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Craig Topper [Sun, 10 Dec 2017 17:42:41 +0000 (17:42 +0000)]
[X86] Add 256/512-bit EVEX VPSADBW instructions to skylake server scheduler model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320317
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Craig Topper [Sun, 10 Dec 2017 17:42:39 +0000 (17:42 +0000)]
[X86] Fix a few instructions that were named Z512 instead of just Z.
This makes things consistent with our normal instruction naming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320316
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Craig Topper [Sun, 10 Dec 2017 17:42:38 +0000 (17:42 +0000)]
[X86] Add VPSRLWZrr to skylake server scheduler model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320315
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Craig Topper [Sun, 10 Dec 2017 17:42:37 +0000 (17:42 +0000)]
[X86] Add VPUNPCKLWDZrr to skylake server scheduler model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320314
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Craig Topper [Sun, 10 Dec 2017 17:42:36 +0000 (17:42 +0000)]
[X86] Adjust tablegen includes so we can use Instructions in scheduler models instead of just instregexs.
This separates the CPU specific scheduler model includes to occur after the instructions. Moves the instruction includes between the basic scheduler information and the CPU specific scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320313
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Sanjay Patel [Sun, 10 Dec 2017 17:25:54 +0000 (17:25 +0000)]
[SimplifyLibCalls] propagate FMF when folding pow(x, -1.0) call
Follow-up for a bug that's similar to:
https://bugs.llvm.org/show_bug.cgi?id=35601
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320312
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Sanjay Patel [Sun, 10 Dec 2017 17:21:51 +0000 (17:21 +0000)]
[InstCombine] add test for pow(x, -1.0) with FMF; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320311
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Sanjay Patel [Sun, 10 Dec 2017 16:52:26 +0000 (16:52 +0000)]
[SimplifyLibCalls] propagate FMF when folding pow(x, 2.0) call (PR35601)
This should fix the larger problem with sqrt shown in:
https://bugs.llvm.org/show_bug.cgi?id=35601
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320310
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Sanjay Patel [Sun, 10 Dec 2017 16:43:34 +0000 (16:43 +0000)]
[InstCombine] add test for pow(x, 2.0) with FMF; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320309
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Simon Pilgrim [Sun, 10 Dec 2017 13:49:51 +0000 (13:49 +0000)]
[X86] Flag BroadWell scheduler model as complete
Locally tag COPY as WriteMove, which has caused some reg-reg + reg-mem instruction tests to reorder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320308
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Simon Pilgrim [Sun, 10 Dec 2017 13:41:29 +0000 (13:41 +0000)]
Regenerate some AVX2+ scheduling tests that got missed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320307
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Simon Pilgrim [Sun, 10 Dec 2017 13:00:37 +0000 (13:00 +0000)]
Strip trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320306
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Simon Pilgrim [Sun, 10 Dec 2017 12:59:55 +0000 (12:59 +0000)]
Regenerate some scheduling tests that got missed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320305
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Simon Pilgrim [Sun, 10 Dec 2017 12:43:53 +0000 (12:43 +0000)]
[X86] Flag ZNVER1 scheduler model as complete
We just have to locally tag COPY as WriteMove
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320304
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Simon Pilgrim [Sun, 10 Dec 2017 12:36:29 +0000 (12:36 +0000)]
[X86] Flag SLM scheduler model as complete
We just have to locally tag COPY as WriteMove
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320303
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Simon Pilgrim [Sun, 10 Dec 2017 12:26:35 +0000 (12:26 +0000)]
[X86][AVX[ Tag VZEROALL/VZEROUPPER instructions scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320302
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Simon Pilgrim [Sun, 10 Dec 2017 12:08:04 +0000 (12:08 +0000)]
[X86] Tag SSE4A instructions as SSE INTALU scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320301
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Simon Pilgrim [Sun, 10 Dec 2017 11:51:29 +0000 (11:51 +0000)]
[X86] Flag BTVER2 scheduler model as complete
We just have to locally tag COPY as WriteMove
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320300
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Simon Pilgrim [Sun, 10 Dec 2017 11:34:08 +0000 (11:34 +0000)]
[X86] Tag ADJSTACK instructions as INTALU scheduler class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320299
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Dorit Nuzman [Sun, 10 Dec 2017 11:13:35 +0000 (11:13 +0000)]
[SCEV] Fix wrong Equal predicate created in getAddRecForPhiWithCasts
CreateAddRecFromPHIWithCastsImpl() adds an IncrementNUSW overflow predicate
which allows the PSCEV rewriter to rewrite this scev expression:
(zext i8 {0, + , (trunc i32 step to i8)} to i32)
into
{0, +, (sext i8 (trunc i32 step to i8) to i32)}
But then it adds the wrong Equal predicate:
%step == (zext i8 (trunc i32 %step to i8) to i32).
instead of:
%step == (sext i8 (trunc i32 %step to i8) to i32)
This is fixed here.
Differential Revision: https://reviews.llvm.org/D40641
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320298
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Simon Pilgrim [Sun, 10 Dec 2017 10:08:21 +0000 (10:08 +0000)]
[X86] Tag MORESTACK instructions as ret scheduler class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320296
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Craig Topper [Sun, 10 Dec 2017 09:14:45 +0000 (09:14 +0000)]
[X86] Fix duplicate entries in skylake server scheduler model by changing Z128 to Z256
Based on the fact that the 'Y' version of the instruction is next to this, I assume Z256 is the intended value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320295
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Craig Topper [Sun, 10 Dec 2017 09:14:44 +0000 (09:14 +0000)]
[X86] Add MOVQI2PQIrm, MOVSDmr, and MOVSDrm to scheduler information
The VEX versions were present but not the legacy SSE versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320294
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Craig Topper [Sun, 10 Dec 2017 09:14:42 +0000 (09:14 +0000)]
[X86] Add LEA64_32r to scheduler models for Sandybridge,Haswell,Broadwell,Skylake
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320293
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Craig Topper [Sun, 10 Dec 2017 09:14:41 +0000 (09:14 +0000)]
[X86] Add IN16/OUT16 to scheduling information for Haswell,Broadwell,Skylake
Sandy Bridge is also missing it, but it has other issues. See PR35590.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320292
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Craig Topper [Sun, 10 Dec 2017 09:14:39 +0000 (09:14 +0000)]
[X86] Fix scheduler models to support ADD32ri in addition to ADD32ri8. Similar for all sizes of AND/OR/XOR/SUB/ADC/SBB/CMP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320291
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Craig Topper [Sun, 10 Dec 2017 09:14:38 +0000 (09:14 +0000)]
[X86] Rename some instructions so that 'b' is added as a suffix instead of replacing an 'r'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320290
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Craig Topper [Sun, 10 Dec 2017 09:14:37 +0000 (09:14 +0000)]
[X86] Add CMPSDrr/rm to the scheduler models.
Somehow CMPSSrr/rm was there and the VEX version was there, but this was consistently missing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320289
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Craig Topper [Sun, 10 Dec 2017 09:14:35 +0000 (09:14 +0000)]
[Docs] Fix typo in scheduler model documentation. enumemation->enumeration
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320288
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Tim Northover [Sun, 10 Dec 2017 08:43:19 +0000 (08:43 +0000)]
PowerPC: support external pid instructions in MC layer.
This adds assembly & disassembly support for the e500mc "external pid"
instructions.
See https://reviews.llvm.org/D39249.
Patch by vit9696 <vit9696@avp.su>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320287
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Xinliang David Li [Sun, 10 Dec 2017 07:39:53 +0000 (07:39 +0000)]
[PGO] change arg type to uint64_t to match member field type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320285
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Craig Topper [Sun, 10 Dec 2017 04:07:28 +0000 (04:07 +0000)]
[X86] Rename the rb form of scalar ADD/SUB/MUL/DIV to include _Int since they can only be selected by intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320283
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Craig Topper [Sun, 10 Dec 2017 03:16:38 +0000 (03:16 +0000)]
[X86] Correct the _Int part of more scheduler model instrexes. Put _b in the correct order relative to _Int
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320282
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Craig Topper [Sun, 10 Dec 2017 03:16:36 +0000 (03:16 +0000)]
[X86] Remove ReadAfterLd from several several rb instructions
This affects CVTSD2SS, FMA, RCP28, RSQRT28, and SQRT scalar instructions
'b' here refers to 'sae' not broadcast. These aren't memory instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320281
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Craig Topper [Sun, 10 Dec 2017 01:27:54 +0000 (01:27 +0000)]
[X86] Fix test case I failed ot update in r320279.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320280
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Craig Topper [Sun, 10 Dec 2017 01:24:08 +0000 (01:24 +0000)]
[X86] Fix bad regular expressions in the scheduler models. Question marks should be outside of multicharacter parenthesized expressions
If the question mark is inside the parentheses it only applies to the single character proceeding it.
I had to make a few additional cleanups to fix some duplicate warnings that were exposed by fixing this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320279
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Craig Topper [Sun, 10 Dec 2017 01:24:06 +0000 (01:24 +0000)]
[X86] Make the _Int part of some instregex sheduler patterns optional
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320278
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Craig Topper [Sun, 10 Dec 2017 01:24:05 +0000 (01:24 +0000)]
[X86] Add the commutable floating point min/max pseudo instructions to sandybridge,haswell,broadwell,skylakeclient scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320277
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Simon Pilgrim [Sun, 10 Dec 2017 00:40:37 +0000 (00:40 +0000)]
[X86] Tag PIC setup instruction as jump scheduler class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320276
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Simon Pilgrim [Sun, 10 Dec 2017 00:30:57 +0000 (00:30 +0000)]
[X86] Tag ACQUIRE/RELEASE atomic instructions as microcoded scheduler classes
Note: We may be too pessimistic here and should possibly use something closer to the LOCK arithmetic instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320275
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Simon Pilgrim [Sun, 10 Dec 2017 00:12:57 +0000 (00:12 +0000)]
[X86] Tag TLS instructions as system scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320274
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Simon Pilgrim [Sun, 10 Dec 2017 00:03:16 +0000 (00:03 +0000)]
[X86] Tag ALLOCA/VAARG instructions as system scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320273
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Joel Jones [Sat, 9 Dec 2017 23:59:55 +0000 (23:59 +0000)]
[AArch64] Improve loop unrolling performance on Cavium T99
This patch improves performance on Cavium T99 as shown here (libquantum 0.2.4):
https://docs.google.com/spreadsheets/d/1Lo1o2E1NjrpkwS7DvYYWsiVvPdd93h7KBaqeptMrZPY/edit?usp=sharing
By increasing the LoopMicroOpsBufferSize in the Cavium T99 Scheduler file,
loop unrolling becomes more aggressive. This helps performance on T99.
Test case included.
Patch by Stefan Teleman
Differential Revision: https://reviews.llvm.org/D40695
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320272
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Simon Pilgrim [Sat, 9 Dec 2017 23:42:56 +0000 (23:42 +0000)]
[InstCombine] Fix SimplifyDemandedUseBits SHL handling (PR35515)
Don't assume that the pattern matched SRL can be cast to an Instruction (might be ConstExpr etc.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320270
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Simon Dardis [Sat, 9 Dec 2017 23:25:57 +0000 (23:25 +0000)]
Infer lowest bits of an integer Multiply when the low bits of the operands are known
When the lowest bits of the operands to an integer multiply are known, the low bits of the result are deducible.
Code to deduce known-zero bottom bits already existed, but this change improves on that by deducing known-ones.
Patch by: Pedro Ferreira
Reviewers: craig.topper, sanjoy, efriedma
Differential Revision: https://reviews.llvm.org/D34029
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320269
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Craig Topper [Sat, 9 Dec 2017 23:10:59 +0000 (23:10 +0000)]
[X86] Use KMOV instructions to zero upper bits of vectors when possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320268
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Craig Topper [Sat, 9 Dec 2017 22:44:42 +0000 (22:44 +0000)]
[X86] Improve lowering of vXi1 insert_subvectors to better utilize (insert_subvector zero, vec, 0) for zeroing upper bits.
This can be better recognized during isel when the producer already zeroed the upper bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320267
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Simon Pilgrim [Sat, 9 Dec 2017 21:27:03 +0000 (21:27 +0000)]
[X86] Tag LOCK/REX64/DATA16/DATA32 instruction prefix scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320266
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Simon Pilgrim [Sat, 9 Dec 2017 20:44:51 +0000 (20:44 +0000)]
Strip trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320265
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Simon Pilgrim [Sat, 9 Dec 2017 20:42:27 +0000 (20:42 +0000)]
[X86] Tag FS/GS BASE R/W instruction scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320264
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Simon Pilgrim [Sat, 9 Dec 2017 20:16:37 +0000 (20:16 +0000)]
[X86] Tag REP/REPNE prefix instructions as microcoded scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320263
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Simon Pilgrim [Sat, 9 Dec 2017 20:04:02 +0000 (20:04 +0000)]
[X86] Tag missing EH pseudo instruction scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320262
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Simon Pilgrim [Sat, 9 Dec 2017 19:56:39 +0000 (19:56 +0000)]
[X86] Tag frame pointer XORs instruction scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320261
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Craig Topper [Sat, 9 Dec 2017 19:18:30 +0000 (19:18 +0000)]
[X86] Don't use getTargetConstant for all 0s and all 1s mask vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320260
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Adrian Prantl [Sat, 9 Dec 2017 19:09:59 +0000 (19:09 +0000)]
Remove duplicate option from documentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320258
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Simon Pilgrim [Sat, 9 Dec 2017 16:58:34 +0000 (16:58 +0000)]
[X86] Tag segment prefixes as NOP instruction scheduling classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320257
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Simon Pilgrim [Sat, 9 Dec 2017 16:20:54 +0000 (16:20 +0000)]
[X86][AVX512] Drop a default NoItinerary argument that isn't used any more. NFCI.
Requires re-ordering of AVX512_maskable_custom arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320255
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Simon Pilgrim [Sat, 9 Dec 2017 16:19:18 +0000 (16:19 +0000)]
Fix 'enumeral and non-enumeral type in conditional expression' gcc warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320254
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Simon Pilgrim [Sat, 9 Dec 2017 16:04:57 +0000 (16:04 +0000)]
Fix signed/unsigned gcc warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320253
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Florian Hahn [Sat, 9 Dec 2017 14:25:33 +0000 (14:25 +0000)]
[InlineFunction] Set debug loc for call to forward varargs.
Reviewers: aprantl, dblaikie, rnk
Reviewed By: rnk
Subscribers: eraman, llvm-commits, JDevlieghere
Differential Revision: https://reviews.llvm.org/D40432
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320252
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Craig Topper [Sat, 9 Dec 2017 08:19:07 +0000 (08:19 +0000)]
[X86] When inserting into the upper bits of a vXi1 vector, make sure we shift enough bits if we widened the vector.
We may need to widen the vector to make the shifts legal, but if we do that we need to make sure we shift left/right after accounting for the new size. If not we can't guarantee we are shifting in zeros.
The test cases affected actually show cases where we should move the shifts all together, but that's another problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320248
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Dylan McKay [Sat, 9 Dec 2017 08:01:28 +0000 (08:01 +0000)]
Revert and accidentally committed revert commit
This reverts commit r320245.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320247
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Dylan McKay [Sat, 9 Dec 2017 07:51:43 +0000 (07:51 +0000)]
[AVR] Fix two CodeGen tests
These were broken because of various printing format changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320246
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Dylan McKay [Sat, 9 Dec 2017 07:51:37 +0000 (07:51 +0000)]
Revert "[AVR] Override ParseDirective"
This reverts commit
57c16f9267969ebb09d6448607999b4a9f40c418.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320245
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Craig Topper [Sat, 9 Dec 2017 07:02:19 +0000 (07:02 +0000)]
[X86] Improve lowering of concats of mask vectors to better optimize zero vector inputs.
We were previously using kunpck with zero inputs unnecessarily. And we had cases where we would insert into a zero vector and then insert into larger zero vector incurring two sets of shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320244
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Dylan McKay [Sat, 9 Dec 2017 06:45:36 +0000 (06:45 +0000)]
Relax unaligned access assertion when type is byte aligned
Summary:
This relaxes an assertion inside SelectionDAGBuilder which is overly
restrictive on targets which have no concept of alignment (such as AVR).
In these architectures, all types are aligned to 8-bits.
After this, LLVM will only assert that accesses are aligned on targets
which actually require alignment.
This patch follows from a discussion on llvm-dev a few months ago
http://llvm.
1065342.n5.nabble.com/llvm-dev-Unaligned-atomic-load-store-td112815.html
Reviewers: bogner, nemanjai, joerg, efriedma
Reviewed By: efriedma
Subscribers: efriedma, cactus, llvm-commits
Differential Revision: https://reviews.llvm.org/D39946
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320243
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Jessica Paquette [Sat, 9 Dec 2017 00:43:49 +0000 (00:43 +0000)]
[MachineOutliner] Outline calls
The outliner previously would never outline calls. Calls are pretty common in
files, so it makes sense to outline them. In fact, in the LLVM test suite, if
you count the number of instructions that the outliner misses when you outline
calls vs when you don't, it turns out that, on average, around 6% of the
instructions encountered are calls. So, if we outline calls, we can find more
candidates, and thus save some more space.
This commit adds that functionality and updates the mir test to reflect that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320229
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Wolfgang Pieb [Sat, 9 Dec 2017 00:39:53 +0000 (00:39 +0000)]
[NFC] Change the string offsets table tests to generate the object on the fly
which enables us to remove the test scripts and object files from the repository.
https://reviews.llvm.org/D40914
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320227
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Kamil Rytarowski [Sat, 9 Dec 2017 00:32:09 +0000 (00:32 +0000)]
Register NetBSD/x86_64 in MemorySanitizer.cpp
Summary:
Reuse the Linux new mapping as it is.
Sponsored by <The NetBSD Foundation>
Reviewers: joerg, eugenis, vitalybuka
Reviewed By: vitalybuka
Subscribers: llvm-commits, #sanitizers
Tags: #sanitizers
Differential Revision: https://reviews.llvm.org/D41022
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320219
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Evgeniy Stepanov [Sat, 9 Dec 2017 00:21:41 +0000 (00:21 +0000)]
Hardware-assisted AddressSanitizer (llvm part).
Summary:
This is LLVM instrumentation for the new HWASan tool. It is basically
a stripped down copy of ASan at this point, w/o stack or global
support. Instrumenation adds a global constructor + runtime callbacks
for every load and store.
HWASan comes with its own IR attribute.
A brief design document can be found in
clang/docs/HardwareAssistedAddressSanitizerDesign.rst (submitted earlier).
Reviewers: kcc, pcc, alekseyshl
Subscribers: srhines, mehdi_amini, mgorny, javed.absar, eraman, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D40932
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320217
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Paul Robinson [Sat, 9 Dec 2017 00:17:01 +0000 (00:17 +0000)]
Fix out-of-order stepping behavior in programs with sunk instructions.
MachineSink attempts to place instructions near the basic blocks where
they are needed. Once an instruction has been sunk, its location
relative to other instructions no longer is consistent with the
original source code. In order to ensure correct stepping in the
debugger, the debug location for sunk instructions is either merged
with the insertion point or erased if the target successor block is
empty.
Originally submitted as r318679, revised to fix sanitizer failure and
improve testing.
Patch by Matthew Voss!
Differential Revision: https://reviews.llvm.org/D39933
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320216
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Adrian Prantl [Fri, 8 Dec 2017 23:32:47 +0000 (23:32 +0000)]
dwarfdump: Add support for the --diff option.
--diff Emit the output in a diff-friendly way by omitting offsets and
addresses.
<rdar://problem/
34502625>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320214
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Craig Topper [Fri, 8 Dec 2017 23:30:03 +0000 (23:30 +0000)]
[X86][Mips] Remove unused method declaration from the X86 and Mips AsmPrinters.
Both had a declaration of EmitXRayTable, but there is no method defined in either with that name. There is a emitXRayTable in the base class with a lower case 'e' and they both call that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320213
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Francis Visoiu Mistrih [Fri, 8 Dec 2017 22:53:21 +0000 (22:53 +0000)]
[CodeGen] Move printing MO_Immediate operands to MachineOperand::print
Work towards the unification of MIR and debug output by refactoring the
interfaces.
Add support for operand subreg index as an immediate to debug printing
and use ::print in the MIRPrinter.
Differential Review: https://reviews.llvm.org/D40965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320209
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Duncan P. N. Exon Smith [Fri, 8 Dec 2017 22:42:43 +0000 (22:42 +0000)]
Revert part of "Cleanup some GraphTraits iteration code"
This reverts part of r300656, which caused a regression in
propagateMassToSuccessors by counting edges n^2 times, where n is the
number of edges from the source basic block to the same successor basic
block. The result was both incorrect and very slow to compute for large
values of n (e.g. switches with multiple cases that go to the same basic
block).
Patch by Andrew Scheidecker!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320208
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Richard Smith [Fri, 8 Dec 2017 22:32:35 +0000 (22:32 +0000)]
Avoid constructing an out-of-range value for an enumeration (which results in UB).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320206
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Abderrazek Zaafrani [Fri, 8 Dec 2017 22:04:13 +0000 (22:04 +0000)]
[AArch64] Rename AArch64VecorByElementOpt.cpp into AArch64SIMDInstrOpt.cpp to reflect the recently added features.
The name change is dicsussed in https://reviews.llvm.org/D38196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320204
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Adrian Prantl [Fri, 8 Dec 2017 21:58:18 +0000 (21:58 +0000)]
Generalize llvm::replaceDbgDeclare and actually support the use-case that
is mentioned in the documentation (inserting a deref before the plus_uconst).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320203
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Vedant Kumar [Fri, 8 Dec 2017 21:57:28 +0000 (21:57 +0000)]
[Debugify] Add a pass to test debug info preservation
The Debugify pass synthesizes debug info for IR. It's paired with a
CheckDebugify pass which determines how much of the original debug info
is preserved. These passes make it easier to create targeted tests for
debug info preservation.
Here is the Debugify algorithm:
NextLine = 1
for (Instruction &I : M)
attach DebugLoc(NextLine++) to I
NextVar = 1
for (Instruction &I : M)
if (canAttachDebugValue(I))
attach dbg.value(NextVar++) to I
The CheckDebugify pass expects contiguous ranges of DILocations and
DILocalVariables. If it fails to find all of the expected debug info, it
prints a specific error to stderr which can be FileChecked.
This was discussed on llvm-dev in the thread:
"Passes to add/validate synthetic debug info"
Differential Revision: https://reviews.llvm.org/D40512
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320202
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Florian Hahn [Fri, 8 Dec 2017 21:49:03 +0000 (21:49 +0000)]
[CodeExtractor] Add debug locations for new call and branch instrs.
Summary:
If a partially inlined function has debug info, we have to add debug
locations to the call instruction calling the outlined function.
We use the debug location of the first instruction in the outlined
function, as the introduced call transfers control to this statement and
there is no other equivalent line in the source code.
We also use the same debug location for the branch instruction added
to jump from artificial entry block for the outlined function, which just
jumps to the first actual basic block of the outlined function.
Reviewers: davide, aprantl, rriddle, dblaikie, danielcdh, wmi
Reviewed By: aprantl, rriddle, danielcdh
Subscribers: eraman, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D40413
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320199
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Dan Gohman [Fri, 8 Dec 2017 21:27:00 +0000 (21:27 +0000)]
[WebAssembly] Reapply r319186: "Support bitcasted function addresses with varargs."
This puts the functionality under control of a command-line option which is
off by default to avoid breaking existing setups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320197
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Dan Gohman [Fri, 8 Dec 2017 21:18:21 +0000 (21:18 +0000)]
[WebAssemby] Re-apply r320041: "Support main functions with alternate signatures."
This includes a fix so that it doesn't transform declarations, and it
puts the functionality under control of a command-line option which is off
by default to avoid breaking existing setups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320196
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Evandro Menezes [Fri, 8 Dec 2017 21:09:59 +0000 (21:09 +0000)]
[AArch64] Add Exynos to host detection
Differential revision: https://reviews.llvm.org/D40985
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320195
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Konstantin Zhuravlyov [Fri, 8 Dec 2017 20:52:28 +0000 (20:52 +0000)]
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
- Add gfx704
- Change bonaire to gfx704
- Remove gfx804
- Remove gfx901
- Remove gfx903
Differential Revision: https://reviews.llvm.org/D40046
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320194
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