OSDN Git Service
Vitaly Buka [Mon, 13 May 2019 22:30:53 +0000 (22:30 +0000)]
[gn] Fix build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360629
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Craig Topper [Mon, 13 May 2019 22:17:13 +0000 (22:17 +0000)]
[X86] Use ISD::MERGE_VALUES to return from lowerAtomicArith instead of calling ReplaceAllUsesOfValueWith and returning SDValue().
Returning SDValue() makes the caller think that nothing happened and it will
end up executing the Expand path. This generates extra nodes that will need to
be pruned as dead code.
Returning an ISD::MERGE_VALUES will tell the caller that we'd like to make a
change and it will take care of replacing uses. This will prevent falling into
the Expand path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360627
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Stanislav Mekhanoshin [Mon, 13 May 2019 21:59:03 +0000 (21:59 +0000)]
[AMDGPU] gfx1010 SearchableTableEmitter patch for NSA
This part was accidentally missing from NSA image support commit.
Differential Revision: https://reviews.llvm.org/D61868
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360623
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Nemanja Ivanovic [Mon, 13 May 2019 21:14:36 +0000 (21:14 +0000)]
[Pass Pipeline][NFC] Add a test prior to committing D61726
This patch just adds a test case to show the differences in code emitted
by opt before and after https://reviews.llvm.org/D61726.
Previous attempt to commit this did not include the registered target
requirement so it caused buildbot breaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360620
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Craig Topper [Mon, 13 May 2019 21:01:24 +0000 (21:01 +0000)]
[X86] Various type corrections to the code that creates LOCK_OR32mi8/OR32mi8Locked to the stack for idempotent atomic rmw and atomic fence.
These are updates to match how isel table would emit a LOCK_OR32mi8 node.
-Use i32 for the immediate zero even though only 8 bits are encoded.
-Use i16 for segment register.
-Use LOCK_OR32mi8 for idempotent atomic operations in 32-bit mode to match
64-bit mode. I'm not sure why OR32mi8Locked and LOCK_OR32mi8 both exist. The
only difference seems to be that OR32mi8Locked is marked as UnmodeledSideEffects=1.
-Emit an extra i32 result for the flags output.
I don't know if the types here really matter just noticed it was inconsistent
with normal behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360619
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Lang Hames [Mon, 13 May 2019 20:52:30 +0000 (20:52 +0000)]
[JITLink][MachO] Honor the no-dead-strip flag on nlist entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360618
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David L. Jones [Mon, 13 May 2019 20:32:53 +0000 (20:32 +0000)]
[Support] Ensure redirected outputs don't contain output from previous tests.
stdout may be buffered, and may not flush on every write. Explicitly flushing
before redirecting the output ensures that the captured output does not contain
output from other tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360617
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Nikita Popov [Mon, 13 May 2019 19:40:18 +0000 (19:40 +0000)]
[WebAssembly] Don't assume that zext/sext result is i32/i64 in fast isel (PR41841)
Usually this will abort fast-isel at the instruction using the
non-legal result, but if the only use is in a different basic block,
we'll incorrectly assume that the zext/sext is to i32 (rather than
i128 in this case).
Differential Revision: https://reviews.llvm.org/D61823
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360616
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Stanislav Mekhanoshin [Mon, 13 May 2019 19:30:06 +0000 (19:30 +0000)]
[AMDGPU] gfx1010 tests. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360615
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Stanislav Mekhanoshin [Mon, 13 May 2019 18:05:10 +0000 (18:05 +0000)]
[AMDGPU] Reorder includes per coding standard. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360609
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Stanislav Mekhanoshin [Mon, 13 May 2019 17:52:57 +0000 (17:52 +0000)]
[AMDGPU] Remove now unused V2FP16_ONE constant def. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360608
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Robert Lougher [Mon, 13 May 2019 17:36:46 +0000 (17:36 +0000)]
Revert [X86] Avoid SFB - Fix inconsistent codegen with/without debug info
Revert r360436 as it is causing clang-x64-windows-msvc buildbot to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360606
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Sanjay Patel [Mon, 13 May 2019 17:28:19 +0000 (17:28 +0000)]
[InstCombine] try harder to form rotate (funnel shift) (PR20750)
We have a similar match for patterns ending in a truncate. This
should be ok for all targets because the default expansion would
still likely be better from replacing 2 'and' ops with 1.
Attempt to show the logic equivalence in Alive (which doesn't
currently have funnel-shift in its vocabulary AFAICT):
%shamt = zext i8 %i to i32
%m = and i32 %shamt, 31
%neg = sub i32 0, %shamt
%and4 = and i32 %neg, 31
%shl = shl i32 %v, %m
%shr = lshr i32 %v, %and4
%or = or i32 %shr, %shl
=>
%a = and i8 %i, 31
%shamt2 = zext i8 %a to i32
%neg2 = sub i32 0, %shamt2
%and4 = and i32 %neg2, 31
%shl = shl i32 %v, %shamt2
%shr = lshr i32 %v, %and4
%or = or i32 %shr, %shl
https://rise4fun.com/Alive/V9r
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360605
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Nick Desaulniers [Mon, 13 May 2019 17:27:44 +0000 (17:27 +0000)]
[TargetLowering] Handle multi depth GEPs w/ inline asm constraints
Summary:
X86TargetLowering::LowerAsmOperandForConstraint had better support than
TargetLowering::LowerAsmOperandForConstraint for arbitrary depth
getelementpointers for "i", "n", and "s" extended inline assembly
constraints. Hoist its support from the derived class into the base
class.
Link: https://github.com/ClangBuiltLinux/linux/issues/469
Reviewers: echristo, t.p.northover
Reviewed By: t.p.northover
Subscribers: t.p.northover, E5ten, kees, jyknight, nemanjai, javed.absar, eraman, hiraditya, jsji, llvm-commits, void, craig.topper, nathanchance, srhines
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61560
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360604
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Paul Robinson [Mon, 13 May 2019 17:18:58 +0000 (17:18 +0000)]
Stop defining negative versions of some lit feature keywords:
zlib/nozlib, asan/not_asan, msan/not_msan, ubsan/not_ubsan.
We still have two other ways to express the absence of a feature.
First, we have the '!' operator to invert the sense of a keyword. For
example, given a feature that depends on zlib being unavailable, its
test can say:
REQUIRES: !zlib
Second, if a test doesn't play well with some features, such as
sanitizers, that test can say:
UNSUPPORTED: asan, msan
The different ways of writing these exclusions both have the same
technical effect, but have different implications to the reader.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360603
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Sanjay Patel [Mon, 13 May 2019 17:02:26 +0000 (17:02 +0000)]
[InstCombine] add tests for rotates with narrow shift amount (PR20750); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360601
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Nico Weber [Mon, 13 May 2019 16:59:43 +0000 (16:59 +0000)]
gn build: Fewer dependencies in llvm/lib/Target
The tablegen groups only need public_deps for inc files included
(possibly transitively) in other targets. Move inc files that are
internan to the MCTargetDesc libraries into regular deps.
Related to the changes that merged InstPrinter into MCTargetDesc
(360484, 360486 etc).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360600
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Nico Weber [Mon, 13 May 2019 16:15:40 +0000 (16:15 +0000)]
gn build: Merge r360572
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360597
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Simon Pilgrim [Mon, 13 May 2019 16:10:11 +0000 (16:10 +0000)]
[X86][SSE] LowerBuildVectorv4x32 - don't insert MOVQ for undef elts
Fixes the regression noted in D61782 where a VZEXT_MOVL was being inserted because we weren't discriminating between 'zeroable' and 'all undef' for the upper elts.
Differential Revision: https://reviews.llvm.org/D61782
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360596
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Simon Pilgrim [Mon, 13 May 2019 16:02:45 +0000 (16:02 +0000)]
[X86][SSE] Relax use limits for lowerAddSubToHorizontalOp (PR32433)
Now that we can use HADD/SUB for scalar additions from any pair of extracted elements (D61263), we can relax the one use limit as we will be able to merge multiple uses into using the same HADD/SUB op.
This exposes a couple of missed opportunities in LowerBuildVectorv4x32 which will be committed separately.
Differential Revision: https://reviews.llvm.org/D61782
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360594
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Simon Pilgrim [Mon, 13 May 2019 15:51:26 +0000 (15:51 +0000)]
[TargetLowering] Add SimplifyDemandedBits support for ZERO_EXTEND_VECTOR_INREG
More work for PR39709.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360592
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Craig Topper [Mon, 13 May 2019 15:45:20 +0000 (15:45 +0000)]
[X86] Add test case for mask register variant of PR41619 which should be fixed after r360552
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360591
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Amara Emerson [Mon, 13 May 2019 15:37:18 +0000 (15:37 +0000)]
Revert "[LSR] Tweak setup cost depth threshold to 10."
Changing the threshold might not be the best long term approach. Revert for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360589
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Simon Pilgrim [Mon, 13 May 2019 15:31:27 +0000 (15:31 +0000)]
[X86] Add SimplifyDemandedBits support for PEXTRB/PEXTRW (PR39709)
Test case will be included in a followup - its being used but its tricky to show a case that isn't caught at a later stage anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360588
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Sanjay Patel [Mon, 13 May 2019 14:31:14 +0000 (14:31 +0000)]
[DAGCombiner] narrow vector binop with inserts/extract
We catch most of these patterns (on x86 at least) by matching
a concat vectors opcode early in combining, but the pattern may
emerge later using insert subvector instead.
The AVX1 diffs for add/sub overflow show another missed narrowing
pattern. That one may be falling though the cracks because of
combine ordering and multiple uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360585
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Sanjay Patel [Mon, 13 May 2019 13:32:16 +0000 (13:32 +0000)]
[x86] add test for insert/extract binop; NFC
This pattern is visible in the c-ray benchmark with an AVX target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360582
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Kevin P. Neal [Mon, 13 May 2019 13:23:30 +0000 (13:23 +0000)]
Add constrained fptrunc and fpext intrinsics.
The new fptrunc and fpext intrinsics are constrained versions of the
regular fptrunc and fpext instructions.
Reviewed by: Andrew Kaylor, Craig Topper, Cameron McInally, Conner Abbot
Approved by: Craig Topper
Differential Revision: https://reviews.llvm.org/D55897
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360581
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Simon Pilgrim [Mon, 13 May 2019 12:44:03 +0000 (12:44 +0000)]
TargetLowering::SimplifyDemandedBits - early-out for UNDEF ops. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360579
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Thomas Preud'homme [Mon, 13 May 2019 12:39:08 +0000 (12:39 +0000)]
FileCheck [5/12]: Introduce regular numeric variables
Summary:
This patch is part of a patch series to add support for FileCheck
numeric expressions. This specific patch introduces regular numeric
variables which can be set on the command-line.
This commit introduces regular numeric variable that can be set on the
command-line with the -D option to a numeric value. They can then be
used in CHECK patterns in numeric expression with the same shape as
@LINE numeric expression, ie. VAR, VAR+offset or VAR-offset where offset
is an integer literal.
The commit also enable strict whitespace in the verbose.txt testcase to
check that the position or the location diagnostics. It fixes one of the
existing CHECK in the process which was not accurately testing a
location diagnostic (ie. the diagnostic was correct, not the CHECK).
Copyright:
- Linaro (changes up to diff 183612 of revision D55940)
- GraphCore (changes in later versions of revision D55940 and
in new revision created off D55940)
Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson, rnk
Subscribers: hiraditya, llvm-commits, probinson, dblaikie, grimar, arichardson, tra, rnk, kristina, hfinkel, rogfer01, JonChesterfield
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60385
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360578
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Eugene Leviant [Mon, 13 May 2019 11:53:05 +0000 (11:53 +0000)]
[ThinLTO] Don't internalize weak writeable variables
Variables with linkonce_odr and weak_odr linkage shouldn't be internalized
if they're not readonly. Otherwise we may end up with multiple copies of
such variable, so reads and writes will become inconsistent
Differential revision: https://reviews.llvm.org/D61255
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360577
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Serge Guelton [Mon, 13 May 2019 11:29:25 +0000 (11:29 +0000)]
Simplify llvm-cat help
Only output options that are directly relevant.
Differential Revision: https://reviews.llvm.org/D61740
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360575
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Cullen Rhodes [Mon, 13 May 2019 10:10:24 +0000 (10:10 +0000)]
[AArch64][SVE2] Add SVE2 target features to backend and TargetParser
Summary:
This patch adds the following features defined by Arm SVE2 architecture
extension:
sve2, sve2-aes, sve2-sm4, sve2-sha3, bitperm
For existing CPUs these features are declared as unsupported to prevent
scheduler errors.
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewers: SjoerdMeijer, sdesmalen, ostannard, rovka
Reviewed By: SjoerdMeijer, rovka
Subscribers: rovka, javed.absar, tschuett, kristof.beyls, kristina, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61513
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360573
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Ulrich Weigand [Mon, 13 May 2019 09:47:26 +0000 (09:47 +0000)]
[SystemZ] Model floating-point control register
This adds the FPC (floating-point control register) as a reserved
physical register and models its use by SystemZ instructions.
Note that only the current rounding modes and the IEEE exception
masks are modeled. *Changes* of the FPC due to exceptions (in
particular the IEEE exception flags and the DXC) are not modeled.
At this point, this patch is mostly NFC, but it will prevent
scheduling of floating-point instructions across SPFC/LFPC etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360570
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Sam Parker [Mon, 13 May 2019 09:23:32 +0000 (09:23 +0000)]
[ARM][ParallelDSP] Relax alias checks
When deciding the safety of generating smlad, we checked for any
writes within the block that may alias with any of the loads that
need to be widened. This is overly conservative because it only
matters when there's a potential aliasing write to a location
accessed by a pair of loads.
Now we check for aliasing writes only once, during setup. If two
loads are found to have an aliasing write between them, we don't add
these loads to LoadPairs. This means that later during the transform,
we can safely widened a pair without worrying about aliasing.
However, to maintain correctness, we also need to change the way that
wide loads are inserted because the order is now important.
The MatchSMLAD method has also been changed, absorbing
MatchReductions and AddMACCandidate to hopefully improve readability.
Differential Revision: https://reviews.llvm.org/D6102
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360567
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Clement Courbet [Mon, 13 May 2019 09:07:37 +0000 (09:07 +0000)]
[DAGCombiner] Fix invalid alias analysis.
Summary:
When we know for sure whether two addresses do or do not alias, we
should immediately return from DAGCombiner::isAlias().
I think this comes from a bad copy/paste, Sorry for not catching that during the
code review.
Fixes PR41855.
Reviewers: niravd, gchatelet, EricWF
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61846
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360566
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Clement Courbet [Mon, 13 May 2019 08:15:34 +0000 (08:15 +0000)]
[DAGCombiner][NFC] Commit test to show fix in D61846.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360561
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Fangrui Song [Mon, 13 May 2019 05:51:39 +0000 (05:51 +0000)]
[WebAssembly] Add dependency on WebAssemblyDesc to fix BUILD_SHARED_LIBS=on builds after rL360550
This fixes the link error
ld.lld: error: undefined symbol: llvm::WebAssembly::anyTypeToString(unsigned int)
>>> referenced by WebAssemblyDisassembler.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360558
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Yonghong Song [Mon, 13 May 2019 05:00:23 +0000 (05:00 +0000)]
[BPF] emit BTF sections only if debuginfo available
Currently, without -g, BTF sections may still be emitted with
data sections, e.g., for linux kernel bpf selftest
test_tcp_check_syncookie_kern.c issue discovered by Martin
as shown below.
-bash-4.4$ bpftool btf dump file test_tcp_check_syncookie_kern.o
[1] VAR 'results' type_id=0, linkage=global-alloc
[2] VAR '_license' type_id=0, linkage=global-alloc
[3] DATASEC 'license' size=0 vlen=1
type_id=2 offset=0 size=4
[4] DATASEC 'maps' size=0 vlen=1
type_id=1 offset=0 size=28
Let disable BTF generation if no debuginfo, which is
the original design.
Signed-off-by: Yonghong Song <yhs@fb.com>
Differential Revision: https://reviews.llvm.org/D61826
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360556
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Lang Hames [Mon, 13 May 2019 04:51:31 +0000 (04:51 +0000)]
[JITLink] Track section alignment and make sure it is respected during layout.
Previously we had only honored alignments on individual atoms, but
tools/runtimes may assume that the section alignment is respected too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360555
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David L. Jones [Mon, 13 May 2019 04:07:54 +0000 (04:07 +0000)]
gn build: support host build on ppc64 (a.k.a. powerpc64le)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360553
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Craig Topper [Mon, 13 May 2019 04:03:35 +0000 (04:03 +0000)]
Recommit r358887 "[TargetLowering][AMDGPU][X86] Improve SimplifyDemandedBits bitcast handling"
I've included a new fix in X86RegisterInfo to prevent PR41619 without
reintroducing r359392. We might be able to improve that in the base class
implementation of shouldRewriteCopySrc somehow. But this hopefully enables
forward progress on SimplifyDemandedBits improvements for now.
Original commit message:
This patch adds support for BigBitWidth -> SmallBitWidth bitcasts, splitting the DemandedBits/Elts accordingly.
The AMDGPU backend needed an extra (srl (and x, c1 << c2), c2) -> (and (srl(x, c2), c1) combine to encourage BFE creation, I investigated putting this in DAGComb
but it caused a lot of noise on other targets - some improvements, some regressions.
The X86 changes are all definite wins.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360552
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David L. Jones [Mon, 13 May 2019 03:43:25 +0000 (03:43 +0000)]
gn build: merge r360550
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360551
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David L. Jones [Mon, 13 May 2019 03:32:41 +0000 (03:32 +0000)]
[WebAssembly] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360550
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Nico Weber [Sun, 12 May 2019 23:47:03 +0000 (23:47 +0000)]
gn build: Merge r360540
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360549
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Lang Hames [Sun, 12 May 2019 22:26:33 +0000 (22:26 +0000)]
[JITLink] Add a test for zero-filled content.
Also updates RuntimeDyldChecker and llvm-rtdyld to support zero-fill tests by
returning a content address of zero (but no error) for zero-fill atoms, and
treating loads from zero as returning zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360547
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Lang Hames [Sun, 12 May 2019 22:26:32 +0000 (22:26 +0000)]
[ORC] Fix some typos.
Patch by Praveen Velliengiri. Thanks Praveen!
https://reviews.llvm.org/D61793
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360546
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Simon Pilgrim [Sun, 12 May 2019 15:16:29 +0000 (15:16 +0000)]
[X86][AVX] Split VZEXT_MOVL ymm/zmm if the upper elements are not demanded.
Removes unnecessary vzeroupper noted in D61806
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360543
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Sanjay Patel [Sun, 12 May 2019 14:53:59 +0000 (14:53 +0000)]
[LoopVectorizer] add tests for FP minmax; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360542
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Sanjay Patel [Sun, 12 May 2019 14:43:20 +0000 (14:43 +0000)]
[DAGCombiner] try to move bitcast after extract_subvector
I noticed that we were failing to narrow an x86 ymm math op in a case similar
to the 'madd' test diff. That is because a bitcast is sitting between the math
and the extract subvector and thwarting our pattern matching for narrowing:
t56: v8i32 = add t59, t58
t68: v4i64 = bitcast t56
t73: v2i64 = extract_subvector t68, Constant:i64<2>
t96: v4i32 = bitcast t73
There are a few wins and neutral diffs in the other tests.
Differential Revision: https://reviews.llvm.org/D61806
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360541
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Fangrui Song [Sun, 12 May 2019 04:55:09 +0000 (04:55 +0000)]
[utils] update_test_checks.py: allow opt-8, opt-9
Allow using Debian's opt-8, opt-9 with update_test_checks.py
Patch by Shawn Landden!
Differential Revision: https://reviews.llvm.org/D61148
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360536
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Simon Pilgrim [Sat, 11 May 2019 21:35:50 +0000 (21:35 +0000)]
[X86][SSE] SimplifyDemandedBits - call PEXTRB/PEXTRW SimplifyDemandedVectorElts as well.
See if we can simplify the demanded vector elts from the extraction before trying to simplify the demanded bits.
This helps us with target shuffles and hops in particular.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360535
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Simon Pilgrim [Sat, 11 May 2019 20:56:05 +0000 (20:56 +0000)]
[DAG] Add SimplifyDemandedBits support for BITREVERSE
Pulled out of D58017 while I continue to investigate the BSWAP regression on PPC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360534
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Simon Pilgrim [Sat, 11 May 2019 20:28:20 +0000 (20:28 +0000)]
[X86] Updated shift-mask test targets for D61830
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360533
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Don Hinton [Sat, 11 May 2019 20:27:01 +0000 (20:27 +0000)]
[CommandLine] Add long option flag for cl::ParseCommandLineOptions . Part 5 of 5
Summary:
If passed, the long option flag makes the CommandLine parser
mimic the behavior or GNU getopt_long. Short options are a single
character prefixed by a single dash, and long options are multiple
characters prefixed by a double dash.
This patch was motivated by the discussion in the following thread:
http://lists.llvm.org/pipermail/llvm-dev/2019-April/131786.html
Reviewed By: MaskRay
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61294
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360532
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Simon Pilgrim [Sat, 11 May 2019 19:16:46 +0000 (19:16 +0000)]
[X86] Add scalar shl+lshr -> shift+mask tests (PR40758)
As discussed on D61068, many x86 targets can perform 2 immediate shifts quicker than a shift + mask
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360530
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Simon Pilgrim [Sat, 11 May 2019 19:14:19 +0000 (19:14 +0000)]
[X86] Add avx512f tests for boolean reduction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360529
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Simon Pilgrim [Sat, 11 May 2019 17:12:52 +0000 (17:12 +0000)]
[CostModel][X86] Add min/max reduction costs for all SSE targets
The original costs stopped at SSE42, I've added conservative estimates for everything down to SSE1/SSE2 and moved some of the SSE42 costs to SSE41 (really only the addition of PCMPGT makes any difference).
I've also added missing vXi8 costs (we use PHMINPOSUW for i8/i16 for scarily quick results) and 256-bit vector costs for AVX1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360528
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Puyan Lotfi [Sat, 11 May 2019 17:03:36 +0000 (17:03 +0000)]
[NFC] yaml2obj/yam2elf.cpp whitespace changes: dos2unix removed CRs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360527
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Simon Pilgrim [Sat, 11 May 2019 16:07:12 +0000 (16:07 +0000)]
[X86][SSE] Add SimplifyDemandedVectorElts HADD/HSUB handling.
Still missing PHADDW/PHSUBW tests because PEXTRW doesn't call SimplifyDemandedVectorElts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360526
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Simon Pilgrim [Sat, 11 May 2019 16:02:34 +0000 (16:02 +0000)]
FixupLEAPass::fixupIncDec - non-LEA opcodes should not happen here. NFCI.
Matches what we do in other functions and fixes scan-build warning about uninitialized NewOpcode variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360525
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Craig Topper [Sat, 11 May 2019 16:00:28 +0000 (16:00 +0000)]
[X86] Add CMOV_FR32X/CMOV_FR64X pseudo instructions. Use them in fast isel to fix a machine verifier error after adding test cases.
Fast isel picks the FR32X/FR64X register classes when lowering pseudo select, but it didn't have the right opcode to go with it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360524
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Craig Topper [Sat, 11 May 2019 16:00:19 +0000 (16:00 +0000)]
[X86] Sink some fast isel code into the only if that uses it. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360523
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Craig Topper [Sat, 11 May 2019 16:00:13 +0000 (16:00 +0000)]
[X86] Use TLI.getRegClassFor to simplify some more fast isel code. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360522
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Simon Pilgrim [Sat, 11 May 2019 15:51:14 +0000 (15:51 +0000)]
[MC][X86] Add test cases from PR14056
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360521
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Simon Pilgrim [Sat, 11 May 2019 15:24:34 +0000 (15:24 +0000)]
HexagonConstEvaluator::evaluateHexExt - check incoming opcodes. NFCI.
Only certain extension opcodes are supported - fixes scan build warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360520
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Simon Pilgrim [Sat, 11 May 2019 14:47:54 +0000 (14:47 +0000)]
[X86][SSE] Tweaked HADD/HSUB SimplifyDemandedVectorElts
Try to ensure we LHS and RHS test coverage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360519
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Simon Pilgrim [Sat, 11 May 2019 14:08:34 +0000 (14:08 +0000)]
[X86][SSE] Add integer HADD/HSUB SimplifyDemandedVectorElts tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360518
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Simon Pilgrim [Sat, 11 May 2019 12:46:38 +0000 (12:46 +0000)]
[X86][SSE] Add HADD/HSUB SimplifyDemandedVectorElts tests
Shows missed opportunities to simplify args.
Will add integer HADD/HSUB tests in a future commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360517
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Simon Pilgrim [Sat, 11 May 2019 11:08:24 +0000 (11:08 +0000)]
Fix uninitialized variable analyzer warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360516
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Simon Pilgrim [Sat, 11 May 2019 11:00:37 +0000 (11:00 +0000)]
SelectionDAGISel::CodeGenAndEmitDAG - remove unused variable. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360514
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Craig Topper [Sat, 11 May 2019 05:18:58 +0000 (05:18 +0000)]
[X86] Use getRegClassFor to simplify some code in fast isel. NFCI
No need to select the register class based on type and features. It should
already be setup by X86ISelLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360513
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Craig Topper [Sat, 11 May 2019 04:19:33 +0000 (04:19 +0000)]
[X86] Don't emit MOVNTDQA loads from fast-isel without SSE4.1.
We were checking for SSE4.1 for FP types, but not integer 128-bit types.
Fixes PR41837.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360512
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Craig Topper [Sat, 11 May 2019 04:00:27 +0000 (04:00 +0000)]
[X86] Add a test case for idempotent atomic operations with speculative load hardening. Fix an additional issue found by the test.
This test covers the fix from r360475 as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360511
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Richard Trieu [Sat, 11 May 2019 03:36:16 +0000 (03:36 +0000)]
[SystemZ] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360510
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David L. Jones [Sat, 11 May 2019 03:23:37 +0000 (03:23 +0000)]
gn build: sort tablegen rules for X86 and AArch64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360508
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David L. Jones [Sat, 11 May 2019 03:20:09 +0000 (03:20 +0000)]
gn build: merge r360494 and r360502
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360507
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Richard Trieu [Sat, 11 May 2019 02:59:02 +0000 (02:59 +0000)]
[Sparc] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360506
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Richard Trieu [Sat, 11 May 2019 02:43:58 +0000 (02:43 +0000)]
[RISCV] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360505
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Richard Trieu [Sat, 11 May 2019 02:33:18 +0000 (02:33 +0000)]
[PowerPC] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360502
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Richard Trieu [Sat, 11 May 2019 02:09:13 +0000 (02:09 +0000)]
[NVPTX] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360500
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Richard Trieu [Sat, 11 May 2019 01:58:52 +0000 (01:58 +0000)]
[MSP430] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360498
91177308-0d34-0410-b5e6-
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Richard Trieu [Sat, 11 May 2019 01:38:56 +0000 (01:38 +0000)]
[Mips] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360497
91177308-0d34-0410-b5e6-
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Richard Trieu [Sat, 11 May 2019 01:25:58 +0000 (01:25 +0000)]
[Lanai] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360496
91177308-0d34-0410-b5e6-
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Richard Trieu [Sat, 11 May 2019 01:13:21 +0000 (01:13 +0000)]
[BPF] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360494
91177308-0d34-0410-b5e6-
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Richard Trieu [Sat, 11 May 2019 01:03:03 +0000 (01:03 +0000)]
[AVR] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360493
91177308-0d34-0410-b5e6-
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David L. Jones [Sat, 11 May 2019 00:44:30 +0000 (00:44 +0000)]
gn build: merge r360490
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360492
91177308-0d34-0410-b5e6-
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David L. Jones [Sat, 11 May 2019 00:35:53 +0000 (00:35 +0000)]
gn build: merge r360484 and r360486
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360491
91177308-0d34-0410-b5e6-
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Richard Trieu [Sat, 11 May 2019 00:34:07 +0000 (00:34 +0000)]
[ARM] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360490
91177308-0d34-0410-b5e6-
96231b3b80d8
David L. Jones [Sat, 11 May 2019 00:20:18 +0000 (00:20 +0000)]
gn build: merge r360345
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360489
91177308-0d34-0410-b5e6-
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Richard Trieu [Sat, 11 May 2019 00:13:01 +0000 (00:13 +0000)]
[ARC] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360488
91177308-0d34-0410-b5e6-
96231b3b80d8
Richard Trieu [Sat, 11 May 2019 00:03:35 +0000 (00:03 +0000)]
[AMDGPU] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360487
91177308-0d34-0410-b5e6-
96231b3b80d8
Richard Trieu [Fri, 10 May 2019 23:50:01 +0000 (23:50 +0000)]
[AArch64] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360486
91177308-0d34-0410-b5e6-
96231b3b80d8
Richard Trieu [Fri, 10 May 2019 23:36:49 +0000 (23:36 +0000)]
[XCore] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360485
91177308-0d34-0410-b5e6-
96231b3b80d8
Richard Trieu [Fri, 10 May 2019 23:24:38 +0000 (23:24 +0000)]
[X86] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360484
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Jordan Rupprecht [Fri, 10 May 2019 23:20:02 +0000 (23:20 +0000)]
Revert [DAGCombiner] Avoid creating large tokenfactors in visitTokenFactor
This reverts r360171 (git commit
a9d6c32eafc645c55b07eb50698c428e14c0bffd). A repro showing the asan/msan failures is forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360481
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Philip Reames [Fri, 10 May 2019 22:55:42 +0000 (22:55 +0000)]
Factor out redzone ABI checks [NFCI]
As requested in D58632, cleanup our red zone detection logic in the X86 backend. The existing X86MachineFunctionInfo flag is used to track whether we *use* the redzone (via a particularly optimization?), but there's no common way to check whether the function *has* a red zone.
I'd appreciate careful review of the uses being updated. I think they are NFC, but a careful eye from someone else would be appreciated.
Differential Revision: https://reviews.llvm.org/D61799
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360479
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Lang Hames [Fri, 10 May 2019 22:51:03 +0000 (22:51 +0000)]
[ORC] Make a narrowing-cast explicit to silence a compiler warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360478
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Lang Hames [Fri, 10 May 2019 22:24:37 +0000 (22:24 +0000)]
[JITLink][MachO] Mark atoms in sections 'no-dead-strip' set live by default.
If a MachO section has the no-dead-strip attribute set then its atoms should
be preserved, regardless of whether they're public or referenced elsewhere in
the object.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360477
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Craig Topper [Fri, 10 May 2019 22:03:33 +0000 (22:03 +0000)]
[X86] Disable speculative load hardening for operations with an explicit RSP base.
After D58632, we can create idempotent atomic operations to the top of stack.
This confused speculative load hardening because it thinks accesses should have
virtual register base except for the cases it already excluded.
This commit adds a new exclusion for this case. I'll try to reduce a test case
for this, but this fix was verified to work by the reporter. This should avoid
needing to revert D58632.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360475
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Reid Kleckner [Fri, 10 May 2019 21:53:44 +0000 (21:53 +0000)]
[COFF] Fix .bss section size bug in obj2yaml / yaml2obj
We need to serialize SizeOfRawData through even when there is no data,
as in a .bss section.
Fixes PR41836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360473
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