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Artem Serov [Thu, 21 Jul 2016 09:26:35 +0000 (09:26 +0000)]
Merge \\\"ARM: Port instr simplification of array accesses.\\\" am:
a92938a17b am:
030c9e6e58
am:
6b72efcb55
Change-Id: Ic54cd2045aab213e69e5cd0b30ab0fc5f0629aaf
Vladimir Marko [Thu, 21 Jul 2016 09:26:35 +0000 (09:26 +0000)]
Merge changes Ibcc11ce7,I9867dc11 am:
89b03e0cfb am:
e2d6519d95
am:
2cc7291244
Change-Id: I695e0438f5bf80cd004d627f223b792f5608394a
Vladimir Marko [Thu, 21 Jul 2016 09:24:06 +0000 (09:24 +0000)]
Merge \\"ARM: Port instr simplification of array accesses.\\" am:
a92938a17b
am:
030c9e6e58
Change-Id: I56fe574cc4200517d241939a458375feb38005af
Vladimir Marko [Thu, 21 Jul 2016 09:24:06 +0000 (09:24 +0000)]
Merge changes Ibcc11ce7,I9867dc11 am:
89b03e0cfb
am:
e2d6519d95
Change-Id: I7b6f88b4a8ec4ae6bb7458c30074fdb02d33efac
Artem Serov [Thu, 21 Jul 2016 09:22:09 +0000 (09:22 +0000)]
Merge \"ARM: Port instr simplification of array accesses.\"
am:
a92938a17b
Change-Id: Ia08b62cc89dd2cfecf9c543ed75689f07baf8ced
Vladimir Marko [Thu, 21 Jul 2016 09:22:06 +0000 (09:22 +0000)]
Merge changes Ibcc11ce7,I9867dc11
am:
89b03e0cfb
Change-Id: I841c764e1c9a69778ce840ec025815d20e1a06ab
Vladimir Marko [Thu, 21 Jul 2016 09:17:15 +0000 (09:17 +0000)]
Merge "ARM: Port instr simplification of array accesses."
Artem Serov [Wed, 6 Jul 2016 15:23:04 +0000 (16:23 +0100)]
ARM: Port instr simplification of array accesses.
After changing the addressing mode for array accesses (in
https://android-review.googlesource.com/248406) the 'add'
instruction that calculates the base address for the array can be
shared across accesses to the same array.
Before https://android-review.googlesource.com/248406:
add IP, r[Array], r[Index0], LSL #2
ldr r0, [IP, #12]
add IP, r[Array], r[Index1], LSL #2
ldr r0, [IP, #12]
Before this CL:
add IP. r[Array], #12
ldr r0, [IP, r[Index0], LSL #2]
add IP. r[Array], #12
ldr r0, [IP, r[Index1], LSL #2]
After this CL:
add IP. r[Array], #12
ldr r0, [IP, r[Index0], LSL #2]
ldr r0, [IP, r[Index1], LSL #2]
Link to the original optimization:
https://android-review.googlesource.com/#/c/127310/
Test: Run ART test suite on Nexus 6.
Change-Id: Iee26f9a0a7ca46abb90e3f60d19d22dc8dee4d8f
Vladimir Marko [Thu, 21 Jul 2016 09:15:23 +0000 (09:15 +0000)]
Merge changes Ibcc11ce7,I9867dc11
* changes:
ARM64: Improve Mterp.
ARM64: Fix mterp switch table pointer calculation.
Matthew Gharrity [Thu, 21 Jul 2016 00:20:32 +0000 (00:20 +0000)]
Merge \\\"Revert \\\"Revert \\\"Refactor GetIMTIndex\\\"\\\"\\\" am:
e4b1c86d13 am:
8df507d68a
am:
7d4f6598ac
Change-Id: I31fd4faec60b56c1d4c74efaaac056543a9cb72d
Matthew Gharrity [Thu, 21 Jul 2016 00:18:32 +0000 (00:18 +0000)]
Merge \\"Revert \\"Revert \\"Refactor GetIMTIndex\\"\\"\\" am:
e4b1c86d13
am:
8df507d68a
Change-Id: Ia2def807b2ccf60b6020da2760c94e7954c2700b
Matthew Gharrity [Thu, 21 Jul 2016 00:14:11 +0000 (00:14 +0000)]
Merge \"Revert \"Revert \"Refactor GetIMTIndex\"\"\"
am:
e4b1c86d13
Change-Id: I496ad384317e215aa09e1390079fdfe3f852723e
Treehugger Robot [Thu, 21 Jul 2016 00:04:52 +0000 (00:04 +0000)]
Merge "Revert "Revert "Refactor GetIMTIndex"""
Alex Light [Wed, 20 Jul 2016 22:22:03 +0000 (22:22 +0000)]
Merge \\\"Make stream tracing have a higher thread count on host\\\" am:
ce1ba111bf am:
2aad9683a3
am:
5225fd5ff5
Change-Id: Ic7f043c818fc19b760b2f06a54bd7c9e14afd93a
Alex Light [Wed, 20 Jul 2016 22:19:32 +0000 (22:19 +0000)]
Merge \\"Make stream tracing have a higher thread count on host\\" am:
ce1ba111bf
am:
2aad9683a3
Change-Id: I54ba24e0222f734d131fe1c14310eb3ef806a357
Alex Light [Wed, 20 Jul 2016 22:16:34 +0000 (22:16 +0000)]
Merge \"Make stream tracing have a higher thread count on host\"
am:
ce1ba111bf
Change-Id: Ib482cc8e3eb49aac849a809fb4d47368abfffa77
Treehugger Robot [Wed, 20 Jul 2016 22:08:47 +0000 (22:08 +0000)]
Merge "Make stream tracing have a higher thread count on host"
Alex Light [Wed, 20 Jul 2016 17:43:39 +0000 (10:43 -0700)]
Make stream tracing have a higher thread count on host
Test: mma ART_TEST_TRACE_STREAM=true -j40 test-art-host-run-test-debug-prebuild-optimizing-relocate-stream-cms-checkjni-image-npictest-ndebuggable-001-HelloWorld32
Bug:
30229615
Change-Id: Id396f569b9e21ff764562005624aabc964d4e95a
Matthew Gharrity [Wed, 20 Jul 2016 20:48:57 +0000 (20:48 +0000)]
Merge \\\"Refactor register allocation to be pluggable\\\" am:
8a759904d4 am:
90d0c8adb6
am:
ecf1f2fd5a
Change-Id: I8becd2eb1340b0832a4d07095c73617a10e55139
Matthew Gharrity [Wed, 20 Jul 2016 20:45:56 +0000 (20:45 +0000)]
Merge \\"Refactor register allocation to be pluggable\\" am:
8a759904d4
am:
90d0c8adb6
Change-Id: If03c38d2f9088828d90026a28a36c65b27e09bb0
Matthew Gharrity [Wed, 20 Jul 2016 20:42:58 +0000 (20:42 +0000)]
Merge \"Refactor register allocation to be pluggable\"
am:
8a759904d4
Change-Id: I7dcf31e96d0eb23f794da94c4268804ab22d82dc
Treehugger Robot [Wed, 20 Jul 2016 20:38:30 +0000 (20:38 +0000)]
Merge "Refactor register allocation to be pluggable"
Matthew Gharrity [Wed, 20 Jul 2016 19:53:23 +0000 (19:53 +0000)]
Merge \\\"Fix accidental pass-by-value\\\" am:
27d99ed243 am:
3fa237bc32
am:
e23258c2ba
Change-Id: I4e118883a126df12729b74fa46af7100dbb591a3
Matthew Gharrity [Wed, 20 Jul 2016 19:50:52 +0000 (19:50 +0000)]
Merge \\"Fix accidental pass-by-value\\" am:
27d99ed243
am:
3fa237bc32
Change-Id: I5eaec7a7a98f6179e0bdb0aae1449ebbb4121075
Matthew Gharrity [Wed, 20 Jul 2016 19:48:24 +0000 (19:48 +0000)]
Merge \"Fix accidental pass-by-value\"
am:
27d99ed243
Change-Id: Iab0f6c30f77a0764a11ce094d05a79e81d28685e
Treehugger Robot [Wed, 20 Jul 2016 19:42:28 +0000 (19:42 +0000)]
Merge "Fix accidental pass-by-value"
Richard Uhler [Wed, 20 Jul 2016 18:33:17 +0000 (18:33 +0000)]
Merge changes I328ea51d,I577c5d02 am:
6c81dfeaef am:
f87c76d0dc
am:
5ff249bfca
Change-Id: Ied670089579260c7ff5b7cdc1d0d81d8d6c49a53
Richard Uhler [Wed, 20 Jul 2016 18:30:50 +0000 (18:30 +0000)]
Merge changes I328ea51d,I577c5d02 am:
6c81dfeaef
am:
f87c76d0dc
Change-Id: Id44ec9b26970ce22620975cbbdc4fa25204013cf
Richard Uhler [Wed, 20 Jul 2016 18:28:17 +0000 (18:28 +0000)]
Merge changes I328ea51d,I577c5d02
am:
6c81dfeaef
Change-Id: I18b7d076b1db11560f4ee4488a5c4f5f8093ffa5
Treehugger Robot [Wed, 20 Jul 2016 18:22:10 +0000 (18:22 +0000)]
Merge changes I328ea51d,I577c5d02
* changes:
Compute oat and odex filenames eagerly.
Make a static OatFileAssistant::DexLocationToOatFileName function.
Vladimir Marko [Wed, 20 Jul 2016 13:25:30 +0000 (14:25 +0100)]
ARM64: Improve Mterp.
Several straight-forward optimizations:
- use ubfx instead of SHR+AND,
- do not mask shifting distance,
- use 64-bit LDRSH to avoid subsequent sign extension,
- use CBNZ instead of CMP+BNE for null checks,
- style: use SXTW alias instead of explicit SBFM.
Test: Run ART test suite on Nexus 9 with the interpreter.
Change-Id: Ibcc11ce7f455432ecb789f727da21f269f8370f0
Vladimir Marko [Wed, 20 Jul 2016 16:52:51 +0000 (17:52 +0100)]
ARM64: Fix mterp switch table pointer calculation.
Do not mix 32-bit and 64-bit registers with
add x0, xPC, w0, lsl #1
that ends up compiled as
add x0, xPC, w0, uxtx #1
instead of the required sxtx. Just sing-extend the offset
correctly in previous instructions.
Test: Additional test in 501-regression-packed-switch.
Change-Id: I9867dc1180743e98f9707a312241d2f5b726ca8c
Matthew Gharrity [Wed, 20 Jul 2016 17:13:45 +0000 (10:13 -0700)]
Fix accidental pass-by-value
Change-Id: I245111eabb43368875c1215ca4f3a1f1918492fe
Matthew Gharrity [Thu, 14 Jul 2016 20:24:00 +0000 (13:24 -0700)]
Refactor register allocation to be pluggable
Allow alternate register allocation strategies to be implemented
in subclasses of a common register allocation base class.
Test: m test-art-host
Change-Id: I7c5866aa9ddff8f53fcaf721bad47654ab221b4f
Nicolas Geoffray [Wed, 20 Jul 2016 12:22:52 +0000 (12:22 +0000)]
JIT: Don\'t update the dex cache of another class loader.
am:
ae093d69f5 -s ours
Change-Id: I8da19774b4379e8b21c7e92ec1d98775ff2dee70
Andreas Gampe [Wed, 20 Jul 2016 12:13:51 +0000 (12:13 +0000)]
Merge \\\"ART: Change return types of field access entrypoints\\\" am:
360b4b0137 am:
127d900ccc
am:
415824fa1f
Change-Id: I8ddee9d7e156e5a5c3e3d4f0ad866be5a34e763a
Vladimir Marko [Wed, 20 Jul 2016 12:10:51 +0000 (12:10 +0000)]
Merge \\"ART: Change return types of field access entrypoints\\" am:
360b4b0137
am:
127d900ccc
Change-Id: Ibb1d4ae96a3c6514cdd6a1d1f77d6f9f66f8cee1
Andreas Gampe [Wed, 20 Jul 2016 12:07:24 +0000 (12:07 +0000)]
Merge \"ART: Change return types of field access entrypoints\"
am:
360b4b0137
Change-Id: I98f4f6ea89d48f5405da245c94ff7bddb0b5d588
Nicolas Geoffray [Tue, 19 Jul 2016 16:06:23 +0000 (17:06 +0100)]
JIT: Don't update the dex cache of another class loader.
This only works for properly delegating class loaders. But Java allows
non-delegating ones :(
bug:
29964720
test:612-jit-dex-cache
(cherry picked from commit
491617a612c8a1c890e72d8ba780a151ddee8e11)
(cherry picked from commit
a2d7cbb44e570ec0a9064dc93f57441e6ab9e45a)
Change-Id: I2523ce1fd4cd36dc83394d0f77ffc3f844e80c69
Vladimir Marko [Wed, 20 Jul 2016 12:01:15 +0000 (12:01 +0000)]
Merge "ART: Change return types of field access entrypoints"
Nicolas Geoffray [Wed, 20 Jul 2016 11:05:47 +0000 (11:05 +0000)]
Merge \\\"Fix test after rename.\\\" am:
522da11a6c am:
c8f60fd364
am:
1fb5373e10
Change-Id: I043ecb79c93d74023c21432e6aa3ace920fc24fa
Nicolas Geoffray [Wed, 20 Jul 2016 11:02:47 +0000 (11:02 +0000)]
Merge \\"Fix test after rename.\\" am:
522da11a6c
am:
c8f60fd364
Change-Id: I445afbc70e5c0ba06f2d6687f1876e27e1a92d2e
Nicolas Geoffray [Wed, 20 Jul 2016 10:59:18 +0000 (10:59 +0000)]
Merge \"Fix test after rename.\"
am:
522da11a6c
Change-Id: Iefbef3b21a47951c736522079a780884308a4dc5
Nicolas Geoffray [Wed, 20 Jul 2016 10:53:11 +0000 (10:53 +0000)]
Merge "Fix test after rename."
Nicolas Geoffray [Wed, 20 Jul 2016 10:49:47 +0000 (11:49 +0100)]
Fix test after rename.
bug:
29964720
Change-Id: I37cebc40ca83597b159eefbc492e8cc105996306
Andreas Gampe [Wed, 20 Jul 2016 05:34:53 +0000 (22:34 -0700)]
ART: Change return types of field access entrypoints
Ensure that return types guarantee full-width data as the compiled
code and mterp expect by using size_t and ssize_t.
This fixes Clang no longer sign-/zero-extending small return types.
Bug:
30232671
Test: m ART_TEST_RUN_TEST_NDEBUG=true ART_TEST_INTERPRETER=true test-art-host-run-test
Change-Id: Ic505befc6c94e2dccbc8abf2b13d4c2d662e68d1
Nicolas Geoffray [Wed, 20 Jul 2016 10:41:47 +0000 (10:41 +0000)]
Merge \\\"JIT: Don\\\'t update the dex cache of another class loader.\\\" am:
79e7324514 am:
7dfe12f613
am:
29dd3e14e8
Change-Id: I603ba8da98a32747c5ef6724aa6df3e6efeac8bd
Nicolas Geoffray [Wed, 20 Jul 2016 10:38:47 +0000 (10:38 +0000)]
Merge \\"JIT: Don\\'t update the dex cache of another class loader.\\" am:
79e7324514
am:
7dfe12f613
Change-Id: I6675e34a34104df1b9909e994b245f696f00d0ed
Nicolas Geoffray [Wed, 20 Jul 2016 10:36:17 +0000 (10:36 +0000)]
Merge \"JIT: Don\'t update the dex cache of another class loader.\"
am:
79e7324514
Change-Id: Iebb37f437c9dfd2693e30b76d55eedc3754653c4
Nicolas Geoffray [Wed, 20 Jul 2016 10:30:09 +0000 (10:30 +0000)]
Merge "JIT: Don't update the dex cache of another class loader."
Artem Serov [Wed, 20 Jul 2016 09:34:12 +0000 (09:34 +0000)]
Merge \\\"ARM: Change mem address mode for array accesses.\\\" am:
c17e6d3f0d am:
5ae90905ce
am:
21a75f2188
Change-Id: I200e95a119de5f7728255356b88b1d3adf5f7f27
Vladimir Marko [Wed, 20 Jul 2016 09:31:12 +0000 (09:31 +0000)]
Merge \\"ARM: Change mem address mode for array accesses.\\" am:
c17e6d3f0d
am:
5ae90905ce
Change-Id: I3a2a756aff25f4c112f59cee9d19beeb32e6de59
Artem Serov [Wed, 20 Jul 2016 09:28:14 +0000 (09:28 +0000)]
Merge \"ARM: Change mem address mode for array accesses.\"
am:
c17e6d3f0d
Change-Id: I2d7b575279de5633edb5cfe22167fcfd7cdd8267
Vladimir Marko [Wed, 20 Jul 2016 09:20:55 +0000 (09:20 +0000)]
Merge "ARM: Change mem address mode for array accesses."
Artem Serov [Mon, 11 Jul 2016 13:02:34 +0000 (14:02 +0100)]
ARM: Change mem address mode for array accesses.
Switch from:
add IP, r[Array], r[Index], LSL #2
ldr r0, [IP, #12]
To:
add IP. r[Array], #12
ldr r0, [IP, r[Index], LSL #2]
These is a base for the future TryExtractArrayAccessAddress
optimization port to arm.
Test: aosp_shamu-userdebug boots and passes "m test-art-target".
Change-Id: I6ab01ba3271a8f79599ddd91a6b63cd1b37d2d67
Matthew Gharrity [Wed, 20 Jul 2016 00:25:09 +0000 (00:25 +0000)]
Merge \\\"Refactor SSA deconstruction into its own class\\\" am:
dc4f4d42aa am:
2bb481b75c
am:
6c280af197
Change-Id: I0b1f7f1171593d8d4d1e3e9b1a1f6e0e345cff63
Matthew Gharrity [Wed, 20 Jul 2016 00:22:38 +0000 (00:22 +0000)]
Merge \\"Refactor SSA deconstruction into its own class\\" am:
dc4f4d42aa
am:
2bb481b75c
Change-Id: Icefcb18977b0e343e2faa239aa3a927c7f7ad295
Matthew Gharrity [Wed, 20 Jul 2016 00:05:08 +0000 (00:05 +0000)]
Merge \"Refactor SSA deconstruction into its own class\"
am:
dc4f4d42aa
Change-Id: Ie844ec62bcea08ad24ac0a6682adbf632e4e69e3
Treehugger Robot [Wed, 20 Jul 2016 00:02:38 +0000 (00:02 +0000)]
Merge "Refactor SSA deconstruction into its own class"
Hiroshi Yamauchi [Tue, 19 Jul 2016 23:59:59 +0000 (23:59 +0000)]
Merge \\\"Tune the GC ergnomics for the read barrier config.\\\" am:
0331aa7274 am:
61b07eb778
am:
132fd95bf3
Change-Id: I6b0a64481087f6d9785005db826ef0bd153b38f1
Pirama Arumuga Nainar [Tue, 19 Jul 2016 23:58:23 +0000 (23:58 +0000)]
Merge \\\"Disable warnings triggered in Clang r271374\\\" am:
73e83ec579 am:
8748c04bca
am:
6d59ad82fc
Change-Id: I45c77ca8e06dae3eb924680630845986f08ee91b
Hiroshi Yamauchi [Tue, 19 Jul 2016 23:52:27 +0000 (23:52 +0000)]
Merge \\"Tune the GC ergnomics for the read barrier config.\\" am:
0331aa7274
am:
61b07eb778
Change-Id: Iaf4d2fa18aee0f25987410ffa68b4da2eb586853
Stephen Hines [Tue, 19 Jul 2016 23:50:52 +0000 (23:50 +0000)]
Merge \\"Disable warnings triggered in Clang r271374\\" am:
73e83ec579
am:
8748c04bca
Change-Id: I47c22d97cd2173ffa79b9979b12dd41edc50d01a
Hiroshi Yamauchi [Tue, 19 Jul 2016 23:44:05 +0000 (23:44 +0000)]
Merge \"Tune the GC ergnomics for the read barrier config.\"
am:
0331aa7274
Change-Id: Ib31f3c99bee9236746b8ac5eb5615bd794abeb29
Pirama Arumuga Nainar [Tue, 19 Jul 2016 23:40:18 +0000 (23:40 +0000)]
Merge \"Disable warnings triggered in Clang r271374\"
am:
73e83ec579
Change-Id: I7badac5ae194cda9411ea2856a30e4add8fc1ed8
Mathieu Chartier [Tue, 19 Jul 2016 22:41:49 +0000 (22:41 +0000)]
Merge \"Do allocation fence before pushing on allocation stack\" into nyc-mr1-dev
am:
90e3f84ceb
Change-Id: Ie9184ce246e24be3be2ef78c17be942e1ff9e0fb
TreeHugger Robot [Tue, 19 Jul 2016 22:34:10 +0000 (22:34 +0000)]
Merge "Do allocation fence before pushing on allocation stack" into nyc-mr1-dev
Treehugger Robot [Tue, 19 Jul 2016 22:07:57 +0000 (22:07 +0000)]
Merge "Tune the GC ergnomics for the read barrier config."
Stephen Hines [Tue, 19 Jul 2016 22:02:31 +0000 (22:02 +0000)]
Merge "Disable warnings triggered in Clang r271374"
Matthew Gharrity [Tue, 19 Jul 2016 21:32:52 +0000 (21:32 +0000)]
Revert "Revert "Refactor GetIMTIndex""
Originally reverted in order to revert
https://android-review.googlesource.com/#/c/244190/
but can now be merged again.
This reverts commit
d4ceecc85a5aab2ec23ea1bd010692ba8c8aaa0c.
Test: m test-art-host
Change-Id: Id9205f2b77a378fc0f06088e78c66e81a49f712d
Matthew Gharrity [Mon, 18 Jul 2016 20:38:44 +0000 (13:38 -0700)]
Refactor SSA deconstruction into its own class
Test: m test-art-host
Change-Id: Ie82c2802f76f27512ef922ba583caeccf5675063
Mathieu Chartier [Mon, 18 Jul 2016 18:11:45 +0000 (11:11 -0700)]
Do allocation fence before pushing on allocation stack
Heap::VisitObjects relies on having valid classes for objects in
the allocation stack. If the writes reorder, the thread calling
VisitObjects could see the free list pointer instead of the class
of the object. I believe this is causing crashes in VisitObjects.
Bug:
28790624
Test: Volantis booted
(cherry picked from commit
011dc2c4b9f3a064cba801679aedd3251fe191e3)
Change-Id: Ib620acbcd641ccd59fea9a66f5587c5026110a22
Pirama Arumuga Nainar [Tue, 28 Jun 2016 17:51:10 +0000 (10:51 -0700)]
Disable warnings triggered in Clang r271374
http://b/
28149048
http://b/
29823425
Disable -Wconstant-conversion and -Wundefined-var-template. The second
bug above tracks that these warnings get reenabled.
Test: Tested build, boot and common usage for Arm, Arm64, x86, x86_64,
Mips images in AOSP and internal branch.
Change-Id: Iea20cf6b5dbec3247b55cf8130f88202e786e367
Hiroshi Yamauchi [Tue, 19 Jul 2016 00:07:26 +0000 (17:07 -0700)]
Tune the GC ergnomics for the read barrier config.
Add 1.0 to the heap growth multiplier for the read barrier config, which
reduces the GC frequency down to roughly the same as CMS in one of the
jank tests.
Bug:
29517059
Bug:
12687968
Test: ART run-tests.
Change-Id: I1302a2f17e862f152d2f92bc06a65c9e6defcba0
Nicolas Geoffray [Tue, 19 Jul 2016 16:06:23 +0000 (17:06 +0100)]
JIT: Don't update the dex cache of another class loader.
This only works for properly delegating class loaders. But Java allows
non-delegating ones :(
bug:
29964720
Change-Id: I8b785e6cdfe9a2b77322521a02b8e59ec332ad83
test:612-jit-dex-cache
Richard Uhler [Tue, 19 Apr 2016 20:24:41 +0000 (13:24 -0700)]
Compute oat and odex filenames eagerly.
Because we almost always need both of them anyway, and they aren't
expensive to compute.
Test: oat file assistant tests.
Change-Id: I328ea51da6eb8700329f829a0458b02e12d1ee9e
Richard Uhler [Tue, 19 Apr 2016 20:08:04 +0000 (13:08 -0700)]
Make a static OatFileAssistant::DexLocationToOatFileName function.
So that you can figure out an oat file name without instantiating an
OatFileAssistant object.
Test: oat file assistant tests.
Change-Id: I577c5d02225f926086e9833d45b88d8a92db52fa
Artem Serov [Tue, 19 Jul 2016 12:48:38 +0000 (12:48 +0000)]
Merge \\\"ARM: Fix shifted register offset mem address mode for load signed.\\\" am:
bae13af2fc am:
e743f45582
am:
bae646e1f8
Change-Id: I26703c726142a852f51b8a1f82b23b763d3854b3
Vladimir Marko [Tue, 19 Jul 2016 12:45:38 +0000 (12:45 +0000)]
Merge \\"ARM: Fix shifted register offset mem address mode for load signed.\\" am:
bae13af2fc
am:
e743f45582
Change-Id: I342bc690d3eb3f3dfa52bb4b61e5139d736a9561
Artem Serov [Tue, 19 Jul 2016 12:42:42 +0000 (12:42 +0000)]
Merge \"ARM: Fix shifted register offset mem address mode for load signed.\"
am:
bae13af2fc
Change-Id: I0c647d242f865e8a67dce0ef17388e7113a2f6a7
Vladimir Marko [Tue, 19 Jul 2016 12:37:33 +0000 (12:37 +0000)]
Merge "ARM: Fix shifted register offset mem address mode for load signed."
Artem Serov [Mon, 11 Jul 2016 13:00:46 +0000 (14:00 +0100)]
ARM: Fix shifted register offset mem address mode for load signed.
For example 'ldrsh r0, [sp, r1, LSL #2]' previously
was assembled as 'ldrh'.
Test: New test in assembler_thumb2_test.cc .
Change-Id: I1d30724f0c2745b131876bffefdc0a780d76f6a1
Mathieu Chartier [Mon, 18 Jul 2016 23:08:50 +0000 (23:08 +0000)]
Merge \\\"Do allocation fence before pushing on allocation stack\\\" am:
2be946bbf9 am:
6631f8824f
am:
408ba8505c
Change-Id: I29ce2f11eab46de31642b5b36905371928a7fd19
Mathieu Chartier [Mon, 18 Jul 2016 23:06:21 +0000 (23:06 +0000)]
Merge \\"Do allocation fence before pushing on allocation stack\\" am:
2be946bbf9
am:
6631f8824f
Change-Id: Idf1eaacb7e46ed160d3f6852d7a8ca6aa756fc2c
Mathieu Chartier [Mon, 18 Jul 2016 23:04:22 +0000 (23:04 +0000)]
Merge \"Do allocation fence before pushing on allocation stack\"
am:
2be946bbf9
Change-Id: I9506c94419d6fcddeba63264fbc75c83ac1c4ffa
Treehugger Robot [Mon, 18 Jul 2016 22:53:44 +0000 (22:53 +0000)]
Merge "Do allocation fence before pushing on allocation stack"
Mathieu Chartier [Mon, 18 Jul 2016 18:11:45 +0000 (11:11 -0700)]
Do allocation fence before pushing on allocation stack
Heap::VisitObjects relies on having valid classes for objects in
the allocation stack. If the writes reorder, the thread calling
VisitObjects could see the free list pointer instead of the class
of the object. I believe this is causing crashes in VisitObjects.
Bug:
28790624
Test: Volantis booted
Change-Id: I0f2d4097de1ef3f5caf670ecc977d4d6837872ca
Matthew Gharrity [Mon, 18 Jul 2016 19:54:19 +0000 (19:54 +0000)]
Merge \\\"Rename current register allocator implementation\\\" am:
0c67ddaff8 am:
407e663d22
am:
3f7f91ba69
Change-Id: Id2d9c671fd05d0f43c07a34f265cd704f766fae1
Matthew Gharrity [Mon, 18 Jul 2016 19:50:47 +0000 (19:50 +0000)]
Merge \\"Rename current register allocator implementation\\" am:
0c67ddaff8
am:
407e663d22
Change-Id: Icc223a8ce610b234e6540eaeebdd2fbe6edcb7df
Matthew Gharrity [Mon, 18 Jul 2016 19:47:48 +0000 (19:47 +0000)]
Merge \"Rename current register allocator implementation\"
am:
0c67ddaff8
Change-Id: I7adac5a5f5a9ba63fcb0097d94b31ede77597e98
Treehugger Robot [Mon, 18 Jul 2016 19:35:11 +0000 (19:35 +0000)]
Merge "Rename current register allocator implementation"
Andreas Gampe [Mon, 18 Jul 2016 19:04:46 +0000 (19:04 +0000)]
Merge \\\"ART: Fix run-test script\\\" am:
64a73d790d am:
5af55b212d
am:
ca140282df
Change-Id: Ia81065f5ab19c074c9414f9851f54193d058d97b
Andreas Gampe [Mon, 18 Jul 2016 19:01:13 +0000 (19:01 +0000)]
Merge \\"ART: Fix run-test script\\" am:
64a73d790d
am:
5af55b212d
Change-Id: Id048e0a30393b979e040b0df28603e8e8b2698f8
Andreas Gampe [Mon, 18 Jul 2016 18:57:44 +0000 (18:57 +0000)]
Merge \"ART: Fix run-test script\"
am:
64a73d790d
Change-Id: I9dd051ba4a63c536a1a45ac7a30bc80cd380f5ff
Treehugger Robot [Mon, 18 Jul 2016 18:49:56 +0000 (18:49 +0000)]
Merge "ART: Fix run-test script"
Andreas Gampe [Sat, 25 Jun 2016 05:30:29 +0000 (22:30 -0700)]
ART: Fix run-test script
Don't assume out is under BUILD_TOP.
Test: run-test with OUT_DIR_COMMON_BASE set
Change-Id: Iba408e807e6a15ff60de54d6d4d653814d4b11d0
Chris Larsen [Mon, 18 Jul 2016 15:52:59 +0000 (15:52 +0000)]
Merge \\\"MIPS64: Highest/Lowest Bit Intrinsic Support\\\" am:
4c489f48ef am:
8ef385099a
am:
703de93469
Change-Id: I0ad833938a2365a29e1848ef5b872746c1886158
Roland Levillain [Mon, 18 Jul 2016 15:48:59 +0000 (15:48 +0000)]
Merge \\"MIPS64: Highest/Lowest Bit Intrinsic Support\\" am:
4c489f48ef
am:
8ef385099a
Change-Id: I79e1d52b6a0af68f93296bf517fefeba64cd1b59
Chris Larsen [Mon, 18 Jul 2016 15:45:33 +0000 (15:45 +0000)]
Merge \"MIPS64: Highest/Lowest Bit Intrinsic Support\"
am:
4c489f48ef
Change-Id: Iab39b42ed59a14a8cd02b8a357bb404d65cdd09f
Roland Levillain [Mon, 18 Jul 2016 15:40:34 +0000 (15:40 +0000)]
Merge "MIPS64: Highest/Lowest Bit Intrinsic Support"
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