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Florian Hahn [Fri, 15 Mar 2019 12:17:36 +0000 (12:17 +0000)]
[LSR] Check for signed overflow in NarrowSearchSpaceByDetectingSupersets.
We are adding a sign extended IR value to an int64_t, which can cause
signed overflows, as in the attached test case, where we have a formula
with BaseOffset = -1 and a constant with numeric_limits<int64_t>::min().
If the addition would overflow, skip the simplification for this
formula. Note that the target triple is required to trigger the failure.
Reviewers: qcolombet, gilr, kparzysz, efriedma
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D59211
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356256
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Simon Pilgrim [Fri, 15 Mar 2019 11:24:17 +0000 (11:24 +0000)]
[SPARC] Regenerate label test for D59363
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356253
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Simon Pilgrim [Fri, 15 Mar 2019 11:14:59 +0000 (11:14 +0000)]
[ARM] Remove icmp undef from reduced tests
Pre-commit for D59363 (Add icmp UNDEF handling to SelectionDAG::FoldSetCC)
Approved by @efriedma (Eli Friedman)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356252
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Simon Pilgrim [Fri, 15 Mar 2019 11:13:26 +0000 (11:13 +0000)]
[WebAssembly] Remove icmp undef in stackify test
Pre-commit for D59363 (Add icmp UNDEF handling to SelectionDAG::FoldSetCC)
Approved by @tlively (Thomas Lively)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356251
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Simon Pilgrim [Fri, 15 Mar 2019 11:05:42 +0000 (11:05 +0000)]
[X86][SSE] Attempt to convert SSE shift-by-var to shift-by-imm.
Prep work for PR40203
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356249
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Fangrui Song [Fri, 15 Mar 2019 10:43:51 +0000 (10:43 +0000)]
[llvm-profdata] Deleted unused Cutoffs added by D16005
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356248
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James Henderson [Fri, 15 Mar 2019 10:35:27 +0000 (10:35 +0000)]
[yaml2obj]Allow explicit setting of p_filesz, p_memsz, and p_offset
yaml2obj currently derives the p_filesz, p_memsz, and p_offset values of
program headers from their sections. This makes writing tests for
certain formats more complex, and sometimes impossible. This patch
allows setting these fields explicitly, overriding the default value,
when relevant.
Reviewed by: jakehehrlich, Higuoxing
Differential Revision: https://reviews.llvm.org/D59372
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356247
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Fangrui Song [Fri, 15 Mar 2019 10:34:57 +0000 (10:34 +0000)]
[llvm-readobj] Delete unused variable. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356246
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Fangrui Song [Fri, 15 Mar 2019 10:27:28 +0000 (10:27 +0000)]
[llvm-objcopy] Delete unused parameter from replaceDebugSections. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356245
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Fangrui Song [Fri, 15 Mar 2019 10:20:51 +0000 (10:20 +0000)]
[llvm-objcopy] Don't use {}; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356244
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Sam Parker [Fri, 15 Mar 2019 10:19:32 +0000 (10:19 +0000)]
[ARM][ParallelDSP] Disable for big-endian
Bail early when we don't have a preheader and also if the target is
big endian because it's written with only little endian in mind!
Differential Revision: https://reviews.llvm.org/D59368
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356243
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Petar Avramovic [Fri, 15 Mar 2019 07:07:50 +0000 (07:07 +0000)]
[MIPS GlobalISel] Improve selection of constants
Certain 32 bit constants can be generated with a single instruction
instead of two. Implement materialize32BitImm function for MIPS32.
Differential Revision: https://reviews.llvm.org/D59369
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356238
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Yonghong Song [Fri, 15 Mar 2019 05:51:25 +0000 (05:51 +0000)]
[BPF] do not generate unused local/global types
The kernel currently has a limit for # of types to be 64KB and
the size of string subsection to be 64KB. A simple bcc tool
runqlat.py generates:
. the size of ~33KB type section, roughly ~10K types
. the size of ~17KB string section
The majority type is from the types referenced by local
variables in the bpf program. For example, the kernel "task_struct"
itself recursively brings in ~900 other types.
This patch did the following optimization to avoid generating
unused types:
. do not generate types for local variables unless they are
function arguments.
. do not generate types for external globals.
If an external global is not used in the program, llvm
already removes it from IR, so global variable saving is
typical small. For runqlat.py, only one variable "llvm.used"
is the external global.
The types for locals and external globals can be added back
once there is a usage for them.
After the above optimization, the runqlat.py generates:
. the size of ~1.5KB type section, roughtly 500 types
. the size of ~0.7KB string section
UPDATE:
resubmitted the patch after previous revert with
the following fix:
use Global.hasExternalLinkage() to test "external"
linkage instead of using Global.getInitializer(),
which will assert on external variables.
Signed-off-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356234
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Yonghong Song [Fri, 15 Mar 2019 05:02:19 +0000 (05:02 +0000)]
Revert "[BPF] do not generate unused local/global types"
This reverts commit r356232.
Reason: test failure with ASSERT on enabled build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356233
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Yonghong Song [Fri, 15 Mar 2019 04:42:01 +0000 (04:42 +0000)]
[BPF] do not generate unused local/global types
The kernel currently has a limit for # of types to be 64KB and
the size of string subsection to be 64KB. A simple bcc tool
runqlat.py generates:
. the size of ~33KB type section, roughly ~10K types
. the size of ~17KB string section
The majority type is from the types referenced by local
variables in the bpf program. For example, the kernel "task_struct"
itself recursively brings in ~900 other types.
This patch did the following optimization to avoid generating
unused types:
. do not generate types for local variables unless they are
function arguments.
. do not generate types for external globals.
If an external global is not used in the program, llvm
already removes it from IR, so global variable saving is
typical small. For runqlat.py, only one variable "llvm.used"
is the external global.
The types for locals and external globals can be added back
once there is a usage for them.
After the above optimization, the runqlat.py generates:
. the size of ~1.5KB type section, roughtly 500 types
. the size of ~0.7KB string section
Signed-off-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356232
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Sam Clegg [Fri, 15 Mar 2019 00:20:13 +0000 (00:20 +0000)]
[WebAssembly] Remove unused load/store patterns that use texternalsym
Differential Revision: https://reviews.llvm.org/D59395
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356221
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Matt Arsenault [Thu, 14 Mar 2019 23:45:09 +0000 (23:45 +0000)]
AMDGPU: Remove intrinsic operand assert
Before r355981, this was under LLVM_DEBUG. I don't think the assert is
quite right, but this really should be a verifier check. Instcombine
should not be asserting on this sort of thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356219
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Sanjay Patel [Thu, 14 Mar 2019 23:14:31 +0000 (23:14 +0000)]
[CGP] add another bailout for degenerate code (PR41064)
This is almost the same as:
rL355345
...and should prevent any potential crashing from examples like:
https://bugs.llvm.org/show_bug.cgi?id=41064
...although the bug was masked by:
rL355823
...and I'm not sure how to repro the problem after that change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356218
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Paul Robinson [Thu, 14 Mar 2019 23:09:17 +0000 (23:09 +0000)]
Tighten up tests that use -debugify as a shortcut. NFC
These now verify that a given instruction has a specific source
location, rather than any old location. We want to make sure we
propagate the correct locations from one instruction to another.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356217
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Eli Friedman [Thu, 14 Mar 2019 23:08:19 +0000 (23:08 +0000)]
[MC] Sort FDEs by the associated CIE before emitting them.
This isn't necessary according to the DWARF standard, but it matches the
.eh_frame sections emitted by other tools in practice, and the Android
libunwindstack rejects .eh_frame sections where an FDE refers to a CIE
other than the closest previous CIE. So match the other tools and also
sort accordingly.
I consider this a bug in libunwindstack, but it's easy enough to emit
a compatible .eh_frame section for compatibility with installed
operating systems.
Differential Revision: https://reviews.llvm.org/D58266
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356216
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Matt Arsenault [Thu, 14 Mar 2019 22:54:43 +0000 (22:54 +0000)]
MIR: Allow targets to serialize MachineFunctionInfo
This has been a very painful missing feature that has made producing
reduced testcases difficult. In particular the various registers
determined for stack access during function lowering were necessary to
avoid undefined register errors in a large percentage of
cases. Implement a subset of the important fields that need to be
preserved for AMDGPU.
Most of the changes are to support targets parsing register fields and
properly reporting errors. The biggest sort-of bug remaining is for
fields that can be initialized from the IR section will be overwritten
by a default initialized machineFunctionInfo section. Another
remaining bug is the machineFunctionInfo section is still printed even
if empty.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356215
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Jessica Paquette [Thu, 14 Mar 2019 22:54:29 +0000 (22:54 +0000)]
[AArch64][GlobalISel] Add isel support for G_UADDO on s32s and s64s
This adds instruction selection support for G_UADDO on s32s and s64s.
Also
- Add an instruction selection test
- Update the arm64-xaluo.ll test to show that we generate the correct assembly
Differential Revision: https://reviews.llvm.org/D58734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356214
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Amara Emerson [Thu, 14 Mar 2019 22:48:18 +0000 (22:48 +0000)]
[AArch64][GlobalISel] Implement selection for G_UNMERGE of vectors to vectors.
This re-uses the previous support for extract vector elt to extract the
subvectors.
Differential Revision: https://reviews.llvm.org/D59390
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356213
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Amara Emerson [Thu, 14 Mar 2019 22:48:15 +0000 (22:48 +0000)]
[AArch64][GlobalISel] Add some support for G_CONCAT_VECTORS.
Handles concatenating 2 x v2s32 and 2 x v4s16
Differential Revision: https://reviews.llvm.org/D59390
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356212
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Jordan Rupprecht [Thu, 14 Mar 2019 21:51:42 +0000 (21:51 +0000)]
[llvm-strip] Hook up (unimplemented) --only-keep-debug
For ELF, we accept but ignore --only-keep-debug. Do the same for llvm-strip.
COFF does implement this, so update the test that it is supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356207
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Matt Arsenault [Thu, 14 Mar 2019 21:23:59 +0000 (21:23 +0000)]
AMDGPU: Correct type for waitcnt debug flag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356206
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Adrian Prantl [Thu, 14 Mar 2019 21:23:52 +0000 (21:23 +0000)]
Add test I forgot to git-add in r356163.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356205
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Sam Clegg [Thu, 14 Mar 2019 21:09:14 +0000 (21:09 +0000)]
Line wrap README file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356204
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Nikita Popov [Thu, 14 Mar 2019 21:06:46 +0000 (21:06 +0000)]
[InstCombine] Add tests for range-based saturing math overflow; NFC
Tests for cases where overflow can be determined, but not based on
known bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356203
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Pete Couperus [Thu, 14 Mar 2019 20:50:54 +0000 (20:50 +0000)]
[ARC] Add more load/store variants.
On ARC ISA, general format of load instruction is this:
LD<zz><.x><.aa><.di> a, [b,c]
And general format of store is this:
ST<zz><.aa><.di> c, [b,s9]
Where:
<zz> is data size field and can be one of
<empty> (bits 00) - Word (32-bit), default behavior
B (bits 01) - Byte
H (bits 10) - Half-word (16-bit)
<.x> is data extend mode:
<empty> (bit 0) - If size is not Word(32-bit), then data is zero extended
X (bit 1) - If size is not Word(32-bit), then data is sign extended
<.aa> is address write-back mode:
<empty> (bits 00) - no write-back
.AW (bits 01) - Preincrement, base register updated pre memory transaction
.AB (bits 10) - Postincrement, base register updated post memory transaction
<.di> is cache bypass mode:
<empty> (bit 0) - Cached memory access, default mode
.DI (bit 1) - Non-cached data memory access
This patch adds these load/store instruction variants to the ARC backend.
Patch By Denis Antrushin! <denis@synopsys.com>
Differential Revision: https://reviews.llvm.org/D58980
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356200
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Nico Weber [Thu, 14 Mar 2019 20:41:19 +0000 (20:41 +0000)]
gn build: Add build files for clang-doc
Differential Revision: https://reviews.llvm.org/D59379
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356199
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Sanjay Patel [Thu, 14 Mar 2019 19:41:21 +0000 (19:41 +0000)]
[InstCombine] remove duplicate tests
These got accidentally doubled with rL356191.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356195
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Sunil Srivastava [Thu, 14 Mar 2019 19:26:04 +0000 (19:26 +0000)]
Handle consecutive-double-quotes in Windows argument parsing
Windows command line argument processing treats consecutive double quotes
as a single double-quote. This patch implements this functionality.
Differential Revision: https://reviews.llvm.org/D58662
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356193
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Sanjay Patel [Thu, 14 Mar 2019 19:22:08 +0000 (19:22 +0000)]
[InstCombine] canonicalize funnel shift constant shift amount to be modulo bitwidth
The shift argument is defined to be modulo the bitwidth, so if that argument
is a constant, we can always reduce the constant to its minimal form to allow
better CSE and other follow-on transforms.
We need to be careful to ignore constant expressions here, or we will likely
infinite loop. I'm adding a general vector constant query for that case.
Differential Revision: https://reviews.llvm.org/D59374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356192
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Sanjay Patel [Thu, 14 Mar 2019 19:22:00 +0000 (19:22 +0000)]
[InstCombine] add tests for funnel shift constant shift amount mod bitwidth; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356191
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Alina Sbirlea [Thu, 14 Mar 2019 18:45:17 +0000 (18:45 +0000)]
[MemorySSA] Remove redundant walker assignment [NFC].
Subscribers: llvm-commits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356189
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Philip Reames [Thu, 14 Mar 2019 18:06:15 +0000 (18:06 +0000)]
[Tests] Add tests to demonstrate hoisting of unordered invariant loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356184
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Philip Reames [Thu, 14 Mar 2019 18:02:19 +0000 (18:02 +0000)]
[Tests] Revert an accident change to a test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356183
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Jessica Paquette [Thu, 14 Mar 2019 18:01:30 +0000 (18:01 +0000)]
[GlobalISel][AArch64] Add partial selection support for G_INSERT_VECTOR_ELT
This adds support for inserting elements into packed vectors. It also adds
two tests: one for selection, and one for regbank select.
Unpacked vectors will come in a follow-up.
Differential Revision: https://reviews.llvm.org/D59325
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356182
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Philip Reames [Thu, 14 Mar 2019 17:59:59 +0000 (17:59 +0000)]
Auto-generate an existing test to make it easier to update
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356181
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Pete Couperus [Thu, 14 Mar 2019 17:50:46 +0000 (17:50 +0000)]
[ARC] Better classify add/sub immediate instructions in frame lowering.
Summary:
Some operations have multiple ARC instructions that are applicable.
For instance, "add r0, r0, 123" can be encoded as a "LImm" instruction
with a 32-bit immediate (8-bytes), or as a signed 12-bit immediate instruction
for the case where the source and destination register are the same (4-bytes).
The ARC assembler will choose the shortest encoding, but we should track
the correct instruction in the compiler.
This patch fixes the instruction used in some cases from ARCFrameLowering.
Subscribers: hiraditya, jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59326
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356179
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Max Moroz [Thu, 14 Mar 2019 17:49:27 +0000 (17:49 +0000)]
Speeding up llvm-cov export with multithreaded renderFiles implementation.
Summary:
CoverageExporterJson::renderFiles accounts for most of the execution time given a large profdata file with multiple binaries.
Proposed solution is to generate JSON for each file in parallel and sort at the end to preserve deterministic output. Also added flags to skip generating parts of the output to trim the output size.
Patch by Sajjad Mirza (@sajjadm).
Reviewers: Dor1s, vsk
Reviewed By: Dor1s, vsk
Subscribers: liaoyuke, mgrang, jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59277
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356178
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Sanjay Patel [Thu, 14 Mar 2019 17:39:40 +0000 (17:39 +0000)]
[InstCombine] add tests for funnel shift constant shift amount mod bitwidth; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356175
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Philip Reames [Thu, 14 Mar 2019 17:36:58 +0000 (17:36 +0000)]
[Tests] Add tests for reordering of unordered atomics on invariant locations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356172
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Philip Reames [Thu, 14 Mar 2019 17:20:59 +0000 (17:20 +0000)]
Allow code motion (and thus folding) for atomic (but unordered) memory operands
Building on the work done in D57601, now that we can distinguish between atomic and volatile memory accesses, go ahead and allow code motion of unordered atomics. As seen in the diffs, this allows much better folding of memory operations into using instructions. (Mostly done by the PeepholeOpt pass.)
Note: I have not reviewed all callers of hasOrderedMemoryRef since one of them - isSafeToMove - is very widely used. I'm relying on the documented semantics of each method to judge correctness.
Differential Revision: https://reviews.llvm.org/D59345
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356170
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Philip Reames [Thu, 14 Mar 2019 17:05:18 +0000 (17:05 +0000)]
[Tests] Add negative folding tests w/fences as requested in D59345
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356165
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Craig Topper [Thu, 14 Mar 2019 16:53:24 +0000 (16:53 +0000)]
[X86] Fix the pattern changes from r356121 so that the ROR*r1/ROR*m1 pattern use the rotr opcode.
These instructions used to use rotl with a bitwidth-1 immediate. I changed the immediate to 1,
but failed to change the opcode.
Thankfully this seems to have not caused a functional issue because we now had two rotl by 1 patterns,
but the correct ones were earlier and took priority. So we just missed some optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356164
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Adrian Prantl [Thu, 14 Mar 2019 16:29:54 +0000 (16:29 +0000)]
Add IR debug info support for Elemental, Pure, and Recursive Procedures.
Patch by Eric Schweitz!
Differential Revision: https://reviews.llvm.org/D54043
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356163
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Sam Parker [Thu, 14 Mar 2019 15:36:54 +0000 (15:36 +0000)]
[NFC][ARM] Update test
Change some regex to handle commutable instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356159
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Sanjay Patel [Thu, 14 Mar 2019 15:32:34 +0000 (15:32 +0000)]
[x86] prevent infinite looping from vselect commutation (PR41066)
This is an immediate fix for:
https://bugs.llvm.org/show_bug.cgi?id=41066
...but as noted there and the code comments, we should do better
by stubbing this out sooner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356158
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Pavel Labath [Thu, 14 Mar 2019 15:23:40 +0000 (15:23 +0000)]
YAMLIO: Improve template arg deduction for mapOptional
Summary:
The way c++ template argument deduction works, both arguments are used
to deduce the template type in the three-argument overload of
mapOptional. This is a problem if the types are slightly different, even
if they are implicitly convertible. This is fairly easy to trigger with
integral types, as the default type of most integral constants is int,
which then requires casting the constant to the type of the other
argument.
This patch fixes that by using a separate template type for the default
value, which is then cast to the type of the first argument. To avoid
this conversion triggerring conversions marged as explicit, we use
static_assert to check that the types are implicitly convertible.
Reviewers: zturner, sammccall
Subscribers: kristina, jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59142
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356157
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Matt Arsenault [Thu, 14 Mar 2019 14:19:01 +0000 (14:19 +0000)]
AMDGPU: Scavenge register instead of findUnusedReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356149
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Matt Arsenault [Thu, 14 Mar 2019 14:18:56 +0000 (14:18 +0000)]
GlobalISel: Use multiple returns for intrinsic structs
This is consistent with what SelectionDAG does and is much easier to
work with than the extract sequence with an artificial wide register.
For the AMDGPU control flow intrinsics, this was producing an s128 for
the i64, i1 tuple return. Any legalization that should apply to a real
s128 value would badly obscure the direct values that need to be seen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356147
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Than McIntosh [Thu, 14 Mar 2019 13:56:49 +0000 (13:56 +0000)]
[SampleFDO] add suffix elision control for fcn names
Summary:
Add hooks for determining the policy used to decide whether/how
to chop off symbol 'suffixes' when locating a given function
in a sample profile.
Prior to this change, any function symbols of the form "X.Y" were
elided/truncated into just "X" when looking up things in a sample
profile data file.
With this change, the policy on suffixes can be changed by adding a
new attribute "sample-profile-suffix-elision-policy" to the function:
this attribute can have the value "all" (the default), "selected", or
"none". A value of "all" preserves the previous behavior (chop off
everything after the first "." character, then treat that as the
symbol name). A value of "selected" chops off only the rightmost
".llvm.XXXX" suffix (where "XXX" is any string not containing a "."
char). A value of "none" indicates that names should be left as is.
Subscribers: jdoerfert, wmi, mtrofin, danielcdh, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58832
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356146
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Matt Arsenault [Thu, 14 Mar 2019 13:46:17 +0000 (13:46 +0000)]
Note ImmArg in documentation for adding intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356145
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Matt Arsenault [Thu, 14 Mar 2019 13:46:14 +0000 (13:46 +0000)]
ARM: Add ImmArg to intrinsics
I found these by asserting in clang for any GCCBuiltin that doesn't
require mangling and requires a constant for the builtin. This means
that intrinsics are missing which don't use GCCBuiltin, don't have
builtins defined in clang, or were missing the constant annotation in
the builtin definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356144
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Matt Arsenault [Thu, 14 Mar 2019 13:46:09 +0000 (13:46 +0000)]
AMDGPU: Don't add unnecessary convergent attributes
These are redundant with the intrinsic declaration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356143
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Hans Wennborg [Thu, 14 Mar 2019 12:22:50 +0000 (12:22 +0000)]
gn build: Merge r356080
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356139
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Simon Pilgrim [Thu, 14 Mar 2019 11:56:41 +0000 (11:56 +0000)]
[SystemZ] Remove icmp undef
Prep-work for PR40800 (Add UNDEF handling to SelectionDAG::FoldSetCC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356138
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Simon Pilgrim [Thu, 14 Mar 2019 11:54:46 +0000 (11:54 +0000)]
[SystemZ] Regenerate tests to make complete codegen more obvious
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356137
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James Henderson [Thu, 14 Mar 2019 11:47:41 +0000 (11:47 +0000)]
[llvm-objcopy]Don't implicitly strip sections in segments
This patch changes llvm-objcopy's behaviour to not strip sections that
are in segments, if they otherwise would be due to a stripping operation
(--strip-all, --strip-sections, --strip-non-alloc). This preserves the
segment contents. It does not change the behaviour of --strip-all-gnu
(although we could choose to do so), because GNU objcopy's behaviour in
this case seems to be to strip the section, nor does it prevent removing
of sections in segments with --remove-section (if a user REALLY wants to
remove a section, we should probably let them, although I could be
persuaded that warning might be appropriate). Tests have been added to
show this latter behaviour.
This fixes https://bugs.llvm.org/show_bug.cgi?id=41006.
Reviewed by: grimar, rupprecht, jakehehrlich
Differential Revision: https://reviews.llvm.org/D59293
This is a reland of r356129, attempting to fix greendragon failures
due to a suspected compatibility issue with od on the greendragon bots
versus other versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356136
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Sam Parker [Thu, 14 Mar 2019 11:38:55 +0000 (11:38 +0000)]
Fix for buildbots
Remove unused private field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356135
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James Henderson [Thu, 14 Mar 2019 11:23:04 +0000 (11:23 +0000)]
Revert r356129 due to greendragon bot failures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356133
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Sam Parker [Thu, 14 Mar 2019 11:14:13 +0000 (11:14 +0000)]
[ARM][ParallelDSP] Enable multiple uses of loads
When choosing whether a pair of loads can be combined into a single
wide load, we check that the load only has a sext user and that sext
also only has one user. But this can prevent the transformation in
the cases when parallel macs use the same loaded data multiple times.
To enable this, we need to fix up any other uses after creating the
wide load: generating a trunc and a shift + trunc pair to recreate
the narrow values. We also need to keep a record of which loads have
already been widened.
Differential Revision: https://reviews.llvm.org/D59215
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356132
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Sam Parker [Thu, 14 Mar 2019 11:05:07 +0000 (11:05 +0000)]
[NFC][LSR] Cleanup Cost API
Create members for Loop, ScalarEvolution, DominatorTree,
TargetTransformInfo and Formula.
Differential Revision: https://reviews.llvm.org/D58389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356131
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Sam Parker [Thu, 14 Mar 2019 10:57:40 +0000 (10:57 +0000)]
[ARM] Run ARMParallelDSP in the IRPasses phase
Run EarlyCSE before ParallelDSP and do this in the backend IR opt
phase.
Differential Revision: https://reviews.llvm.org/D59257
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356130
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James Henderson [Thu, 14 Mar 2019 10:20:27 +0000 (10:20 +0000)]
[llvm-objcopy]Don't implicitly strip sections in segments
This patch changes llvm-objcopy's behaviour to not strip sections that
are in segments, if they otherwise would be due to a stripping operation
(--strip-all, --strip-sections, --strip-non-alloc). This preserves the
segment contents. It does not change the behaviour of --strip-all-gnu
(although we could choose to do so), because GNU objcopy's behaviour in
this case seems to be to strip the section, nor does it prevent removing
of sections in segments with --remove-section (if a user REALLY wants to
remove a section, we should probably let them, although I could be
persuaded that warning might be appropriate). Tests have been added to
show this latter behaviour.
This fixes https://bugs.llvm.org/show_bug.cgi?id=41006.
Reviewed by: grimar, rupprecht, jakehehrlich
Differential Revision: https://reviews.llvm.org/D59293
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356129
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Hans Wennborg [Thu, 14 Mar 2019 10:10:25 +0000 (10:10 +0000)]
gn build: Merge r356082
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356128
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Alex Bradbury [Thu, 14 Mar 2019 08:31:35 +0000 (08:31 +0000)]
[RISCV] Fix rL356123
The wrong version of the patch was committed. This fixes typos that broke the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356124
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Alex Bradbury [Thu, 14 Mar 2019 08:28:48 +0000 (08:28 +0000)]
[RISCV][NFC] Rename callee saved regs 'CSR' to CSR_ILP32_LP64 and minor RISCVRegisterInfo refactoring
The CSR renaming further prepares the way for an upcoming patch adding support for more
RISC-V ABIs.
Modify RISCVRegisterInfo::getCalleeSavedRegs and
RISCVRegisterInfo::getReservedRegs to do MF->getSubtarget<RISCVSubtarget>()
once rather than multiple times.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356123
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Alex Bradbury [Thu, 14 Mar 2019 08:17:44 +0000 (08:17 +0000)]
[RISCV] Extend test/CodeGen/RISCV/callee-saved-* to test getCalleePreservedRegs
Add a caller which exhausts regs then calls another function. This allows
getCalleePreservedRegs to be tested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356122
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Craig Topper [Thu, 14 Mar 2019 07:07:26 +0000 (07:07 +0000)]
[X86] Add patterns for rotr by immediate to fix PR41057.
Prior to the introduction of funnel shift intrinsics we could count on rotate
by immediates prefering to use rotl since that's what MatchRotate would check
first. The or+shift pattern doesn't have a direction so one must be chosen
arbitrarily.
With funnel shift, there is a direction and fshr will try to use rotr first.
While fshl will try to use rotl first.
This patch adds the isel patterns for rotr to complement the rotl patterns. I've
put the rotr by 1 patterns in the instruction patterns. And moved the rotl by
bitwidth-1 patterns to separate Pat patterns.
Fixes PR41057.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356121
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Craig Topper [Thu, 14 Mar 2019 07:07:24 +0000 (07:07 +0000)]
[X86] Add various test cases for PR41057. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356120
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Quentin Colombet [Thu, 14 Mar 2019 01:37:13 +0000 (01:37 +0000)]
[GlobalISel][Utils] Add a getConstantVRegVal variant that looks through instrs
getConstantVRegVal used to only look for G_CONSTANT when looking at
unboxing the value of a vreg. However, constants are sometimes not
directly used and are hidden behind trunc, s|zext or copy chain of
computation.
In particular this may be introduced by the legalization process that
doesn't want to simplify these patterns because it can lead to infine
loop when legalizing a constant.
To circumvent that problem, add a new variant of getConstantVRegVal,
named getConstantVRegValWithLookThrough, that allow to look through
extensions.
Differential Revision: https://reviews.llvm.org/D59227
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356116
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Douglas Yung [Thu, 14 Mar 2019 01:24:35 +0000 (01:24 +0000)]
Fixup tests to check for any MCInst number instead of a specific one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356115
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Craig Topper [Thu, 14 Mar 2019 01:13:15 +0000 (01:13 +0000)]
[ResetMachineFunctionPass] Add visited functions statistics info
Adding a "NumFunctionsVisited" for collecting the visited function number.
It can be used to collect function pass rate in some tests,
the pass rate = (NumberVisited - NumberReset)/NumberVisited.
e.g. it can be used for caculating GlobalISel pass rate in Test-Suite.
Patch by Tianyang Zhu (zhutianyang)
Differential Revision: https://reviews.llvm.org/D59285
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356114
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Craig Topper [Thu, 14 Mar 2019 00:23:31 +0000 (00:23 +0000)]
[X86] Add 64-bit mode command lines to rot32.ll so that it will demonstrate PR41055 for 32 bit. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356112
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Jordan Rupprecht [Wed, 13 Mar 2019 23:40:16 +0000 (23:40 +0000)]
[llvm-objcopy][NFC] Remove unnecessary llvm-objcopy.h #includes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356109
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Jessica Paquette [Wed, 13 Mar 2019 23:29:54 +0000 (23:29 +0000)]
[AArch64][GlobalISel] Gardening: Simplify subregister copy in selectBuildVector
NFC. Some more preliminary factoring for G_INSERT_VECTOR_ELT.
Also better code-reuse, etc., etc.
Differential Revision: https://reviews.llvm.org/D59323
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356107
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Jessica Paquette [Wed, 13 Mar 2019 23:22:23 +0000 (23:22 +0000)]
[GlobalISel][AArch64] Gardening: Factor out vector inserts
Factor out the vector insert code in `selectBuildVector`. Replace part of it
with `emitScalarToVector`, since it was pretty much equivalent.
This will make implementing G_INSERT_VECTOR_ELT easier.
Differential Revision: https://reviews.llvm.org/D59322
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356106
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Jordan Rupprecht [Wed, 13 Mar 2019 22:26:01 +0000 (22:26 +0000)]
[llvm-objcopy] Cleanup errors from CopyConfig and remove llvm-objcopy.h dependency
error() was previously cleaned up from CopyConfig, but new uses were introduced.
This also tweaks the error message for --add-symbol to report all invalid flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356105
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Jason Liu [Wed, 13 Mar 2019 21:50:25 +0000 (21:50 +0000)]
[AIX][CMake] Changes for building on AIX with XL and GCC
Summary:
In support of IBM's efforts to produce a viable C and C++ LLVM compiler for AIX
(ref: RFC at http://lists.llvm.org/pipermail/llvm-dev/2019-February/130175.html),
this patch adds customizations to the CMake files in order to properly
invoke the host toolchain for the build on AIX.
Additional changes to enable a successful build will follow.
Patch by Xing Xue
Reviewers: hubert.reinterpretcast, jasonliu, sfertile
Reviewed by: hubert.reinterpretcast
Differential Revision: https://reviews.llvm.org/D58250
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356104
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Sam Clegg [Wed, 13 Mar 2019 21:29:20 +0000 (21:29 +0000)]
[WebAssembly] Improve support for "needed" list in dylink section
This change adds basic support for shared library dependencies
via the dylink section.
See https://github.com/WebAssembly/tool-conventions/pull/77
Differential Revision: https://reviews.llvm.org/D59237
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356102
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Jessica Paquette [Wed, 13 Mar 2019 21:19:29 +0000 (21:19 +0000)]
[GlobalISel][AArch64] Gardening: Factor out code to find lane indices
Some more refactoring for G_INSERT_VECTOR_ELT.
Factor out the code used to find a lane index from `selectExtractElt`. Put it
into a more general-purpose `getConstantValueForReg` function.
This will be shared with the code for G_INSERT_VECTOR_ELT.
Differential Revision: https://reviews.llvm.org/D59324
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356101
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Stanislav Mekhanoshin [Wed, 13 Mar 2019 21:15:52 +0000 (21:15 +0000)]
[AMDGPU] Silence gcc 7 warnings
Differential Revision: https://reviews.llvm.org/D59330
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356100
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Matt Arsenault [Wed, 13 Mar 2019 19:46:34 +0000 (19:46 +0000)]
Verifier: Make sure masked load/store alignment is a power of 2
The same should also be done for scatter/gather, but the verifier
doesn't check those at all now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356094
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Matt Arsenault [Wed, 13 Mar 2019 19:46:34 +0000 (19:46 +0000)]
PowerPC: Add ImmArg to intrinsics
I found these by asserting in clang for any GCCBuiltin that doesn't
require mangling and requires a constant for the builtin. This means
that intrinsics are missing which don't use GCCBuiltin, don't have
builtins defined in clang, or were missing the constant annotation in
the builtin definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356093
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Matt Arsenault [Wed, 13 Mar 2019 19:46:33 +0000 (19:46 +0000)]
Hexagon: Add ImmArg to intrinsics
I found these by asserting in clang for any GCCBuiltin that doesn't
require mangling and requires a constant for the builtin. This means
that intrinsics are missing which don't use GCCBuiltin, don't have
builtins defined in clang, or were missing the constant annotation in
the builtin definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356092
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Matt Arsenault [Wed, 13 Mar 2019 19:46:32 +0000 (19:46 +0000)]
SystemZ: Add ImmArg to intrinsics
I found these by asserting in clang for any GCCBuiltin that doesn't
require mangling and requires a constant for the builtin. This means
that intrinsics are missing which don't use GCCBuiltin, don't have
builtins defined in clang, or were missing the constant annotation in
the builtin definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356091
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Matt Arsenault [Wed, 13 Mar 2019 19:07:59 +0000 (19:07 +0000)]
Mips: Add ImmArg to intrinsics
I found these by asserting in clang for any GCCBuiltin that doesn't
require mangling and requires a constant for the builtin. This means
that intrinsics are missing which don't use GCCBuiltin, don't have
builtins defined in clang, or were missing the constant annotation in
the builtin definition.
I'm not sure what's going on with the immediates.ll test. It seems to
be intended to test invalid cases like this, but then tries to handle
some of them anyway. I've moved the cases that were inconsistent with
the GCCBuiltin definition so they don't test the codegen anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356085
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Simon Pilgrim [Wed, 13 Mar 2019 19:07:54 +0000 (19:07 +0000)]
[X86] Remove icmp undef in more reduced tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356084
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Simon Pilgrim [Wed, 13 Mar 2019 19:04:45 +0000 (19:04 +0000)]
[X86] Regenerate tail call tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356083
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Tim Renouf [Wed, 13 Mar 2019 18:56:33 +0000 (18:56 +0000)]
[MsgPack] Removed MsgPackTypes
Summary:
MsgPackTypes has been replaced by the lighter-weight MsgPackDocument.
Differential Revision: https://reviews.llvm.org/D57025
Change-Id: Ia7069880ef29f55490abbe5d8ae15f25cc1490a4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356082
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Tim Renouf [Wed, 13 Mar 2019 18:55:50 +0000 (18:55 +0000)]
[AMDGPU] Switched HSA metadata to use MsgPackDocument
Summary:
MsgPackDocument is the lighter-weight replacement for MsgPackTypes. This
commit switches AMDGPU HSA metadata processing to use MsgPackDocument
instead of MsgPackTypes.
Differential Revision: https://reviews.llvm.org/D57024
Change-Id: I0751668013abe8c87db01db1170831a76079b3a6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356081
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Tim Renouf [Wed, 13 Mar 2019 18:54:47 +0000 (18:54 +0000)]
[MsgPack] New MsgPackDocument class
Summary:
A class that exposes a simple in-memory representation of a document of
MsgPack objects, that can be read from and written to MsgPack, read from
and written to YAML, and inspected and modified in memory. This is
intended to be a lighter-weight (in terms of memory allocations)
replacement for MsgPackTypes.
Two subsequent changes will:
1. switch AMDGPU HSA metadata to using MsgPackDocument instead of
MsgPackTypes;
2. add MsgPack AMDGPU PAL metadata via MsgPackDocument.
Differential Revision: https://reviews.llvm.org/D57023
Change-Id: Ie15a054831d5a6467c5867c064c8f8f6b80270e1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356080
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Craig Topper [Wed, 13 Mar 2019 18:48:50 +0000 (18:48 +0000)]
[X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b()
The feature flag alone can't be trusted since it can be passed via -mattr. Need to ensure 64-bit mode as well.
We had a 64 bit mode check on the instruction to make the assembler work correctly. But we weren't guarding any of our lowering code or the hooks for the AtomicExpandPass.
I've added 32-bit command lines to atomic128.ll with and without cx16. The tests there would all previously fail if -mattr=cx16 was passed to them. I had to move one test case for f128 to a new file as it seems to have a different 32-bit mode or possibly sse issue.
Differential Revision: https://reviews.llvm.org/D59308
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356078
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Simon Pilgrim [Wed, 13 Mar 2019 18:36:59 +0000 (18:36 +0000)]
[X86] Avoid icmp undef in reduced tests
Because we don't currently simplify icmp with undef in DAG, bugpoint loves to introduce them during reduction.
This is a small step towards re-adding non-undef values into some of the simpler tests so that they should still test correctly and emit similar/same codegen.
Prep work for PR40800 ([SelectionDAG] Add UNDEF handling to SelectionDAG::FoldSetCC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356076
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Alex Bradbury [Wed, 13 Mar 2019 18:25:23 +0000 (18:25 +0000)]
[RISCV] Regenerate test/CodeGen/RISCV/legalize-fneg.ll after rL356068
rL356068 caused some minor re-orderings. Regenerate legalize-fneg.ll to
reflect this, and remove the NOLIB check lines (they're redundant given that
the RV32I and RV64I check lines generated by update_llc_test_checks.py already
demonstrate there is no libcall).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356074
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Simon Pilgrim [Wed, 13 Mar 2019 18:18:24 +0000 (18:18 +0000)]
Regenerate test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356071
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Nirav Dave [Wed, 13 Mar 2019 17:44:40 +0000 (17:44 +0000)]
[DAGCombiner] Fix Comment. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356069
91177308-0d34-0410-b5e6-
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