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Ilia Mirkin [Sun, 31 Dec 2017 07:36:39 +0000 (02:36 -0500)]
st/dri: only expose config formats that are display targets
In the case of NVIDIA hardware, ABGR is displayable but ARGB is not.
Only advertise the one set in the visuals list.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Ilia Mirkin [Sun, 31 Dec 2017 06:05:06 +0000 (01:05 -0500)]
mesa: add xbgr support adjacent to xrgb
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Daniel Stone <daniels@collabora.com>
Timothy Arceri [Fri, 16 Feb 2018 00:41:17 +0000 (11:41 +1100)]
st/shader_cache: copy nir pointer to gl_program after deserializing
This fixes a crash when running the arb_get_program_binary-api-errors
piglit test twice.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Thu, 15 Feb 2018 23:14:05 +0000 (10:14 +1100)]
radeonsi: add nir shader cache support
In future we might want to try avoid calling nir_serialize() but
this works for now.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Thu, 15 Feb 2018 05:58:07 +0000 (16:58 +1100)]
radeonsi: rename variables tgsi_binary -> ir_binary
This better represents that the ir could be either tgsi or nir.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Emil Velikov [Mon, 19 Feb 2018 22:10:18 +0000 (22:10 +0000)]
docs: update calendar, add news and link release notes to 17.3.5
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Mon, 19 Feb 2018 22:07:23 +0000 (22:07 +0000)]
docs: add sha256 checksums for 17.3.5
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
164a993112cc7278d46b7ec8f7f617eb683b212c)
Emil Velikov [Mon, 19 Feb 2018 22:01:35 +0000 (22:01 +0000)]
docs: add release notes for 17.3.5
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
2529d77179065b983d69c620c7f71281aefe4f98)
Marek Olšák [Mon, 19 Feb 2018 16:55:34 +0000 (17:55 +0100)]
radeonsi: fix regression from 32-bit pointers on CI
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Samuel Pitoiset [Fri, 16 Feb 2018 09:28:37 +0000 (10:28 +0100)]
radv: compact varyings after removing unused ones
It makes no sense to compact before, and the description of
nir_compact_varyings() confirms that.
Polaris10:
Totals from affected shaders:
SGPRS: 108528 -> 108128 (-0.37 %)
VGPRS: 74548 -> 74500 (-0.06 %)
Spilled SGPRs: 844 -> 814 (-3.55 %)
Code Size:
3007328 ->
2992932 (-0.48 %) bytes
Max Waves: 16019 -> 16009 (-0.06 %)
Vega10:
Totals from affected shaders:
SGPRS: 106088 -> 106232 (0.14 %)
VGPRS: 74652 -> 74700 (0.06 %)
Spilled SGPRs: 692 -> 658 (-4.91 %)
Code Size:
2967708 ->
2953028 (-0.49 %) bytes
Max Waves: 18178 -> 18162 (-0.09 %)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Timothy Arceri [Fri, 16 Feb 2018 05:14:29 +0000 (16:14 +1100)]
radeonsi/nir: fix gl_FragCoord for pixel_center_integer
Fixes piglit test glsl-arb-fragment-coord-conventions
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Fri, 16 Feb 2018 05:10:58 +0000 (16:10 +1100)]
glsl/nir: add pixel_center_integer to shader info
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ilia Mirkin [Sat, 10 Feb 2018 18:39:56 +0000 (13:39 -0500)]
gm107/ir: avoid using kepler instruction capabilities
Split up the op properties table into generation-specific bits, and only
use the kepler ones on kepler. Fixes some CTS images tests.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Ilia Mirkin [Sat, 13 Jan 2018 17:32:41 +0000 (12:32 -0500)]
nvc0: add support for bindless on maxwell+
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 13 Jan 2018 17:28:16 +0000 (12:28 -0500)]
gm107/ir: change how SUQ works in preparation for bindless
All this information can be retrieved from the TIC directly. Avoid
having to dip into the constbuf information about the image.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Kenneth Graunke [Fri, 15 Aug 2014 05:36:45 +0000 (22:36 -0700)]
i965: Use absolute addressing for constant buffer 0 on Kernel 4.16+.
By default, 3DSTATE_CONSTANT_* Constant Buffer 0 is relative to dynamic
state base address. This makes it unusable for pushing UBOs.
There is a bit in the INSTPM register (or CS_DEBUG_MODE2 on Skylake)
which controls whether buffer 0 is relative to dynamic state base
address, or simply a normal pointer. Setting that gives us full
flexibility. This lets us push up to 4 UBO ranges.
We can't currently write this on Haswell and earlier, and will need
to update the kernel command parser, and then do the whole version
checking song and dance. We also need a brand new kernel that supports
context isolation - on older kernels, newly created contexts inherit
register state from whatever happened to be running. So, setting this
would have catastrophic impact on other drivers such as libva, Beignet,
or older Mesa.
See commit
8ec5a4e4a4a32f4de351c5fc2bf0eb615b6eef1b where we did this
once before, but had to revert it in commit
013d33122028f2492da90a03a.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Kenneth Graunke [Fri, 16 Feb 2018 19:03:58 +0000 (11:03 -0800)]
i965: Stop restoring the default L3 configuration on Kernel 4.16+.
Kernel 4.16 has proper context isolation, which means we can change
the L3 configuration without worrying about that leaking to other
newly created contexts, breaking the assumptions of other userspace.
So, disable our workaround to reprogram it back to the default.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Mikko Perttunen [Thu, 15 Feb 2018 18:13:20 +0000 (20:13 +0200)]
nvc0: Use GP100_COMPUTE_CLASS on GP10B
GP10B requires the use of GP100_COMPUTE_CLASS instead of
GP104_COMPUTE_CLASS as is used for other non-GP100 chips.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Daniel Stone [Thu, 15 Feb 2018 15:04:51 +0000 (15:04 +0000)]
i965: Fix aux-surface size check
The previous commit reworked the checks intel_from_planar() to check the
right individual cases for regular/planar/aux buffers, and do size
checks in all cases.
Unfortunately, the aux size check was broken, and required the aux
surface to be allocated with the correct aux stride, but full image
height (!).
As the ISL aux surface is not recorded in the DRIimage, we cannot easily
access it to check. Instead, store the aux size from when we do have the
ISL surface to hand, and check against that later when we go to access
the aux surface.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Fixes:
c2c4e5bae3ba ("i965: Fix bugs in intel_from_planar")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Marek Olšák [Mon, 1 Jan 2018 20:04:22 +0000 (21:04 +0100)]
radeonsi: implement 32-bit pointers in user data SGPRs (v2)
User SGPRs changes:
VS: 14 -> 9
TCS: 14 -> 10
TES: 10 -> 6
GS: 8 -> 4
GSCOPY: 2 -> 1
PS: 9 -> 5
Merged VS-TCS: 24 -> 16
Merged VS-GS: 18 -> 11
Merged TES-GS: 18 -> 11
SGPRS:
2170102 ->
2158430 (-0.54 %)
VGPRS:
1645656 ->
1641516 (-0.25 %)
Spilled SGPRs: 9078 -> 8810 (-2.95 %)
Spilled VGPRs: 130 -> 114 (-12.31 %)
Scratch size: 1508 -> 1492 (-1.06 %) dwords per thread
Code Size:
52094872 ->
52692540 (1.15 %) bytes
Max Waves: 371848 -> 372723 (0.24 %)
v2: - the shader cache needs to take address32_hi into account
- set amdgpu-32bit-address-high-bits
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (v1)
Marek Olšák [Sun, 31 Dec 2017 21:58:57 +0000 (22:58 +0100)]
radeonsi: disallow constant buffers with a 64-bit address in slot 0
State trackers must use a user buffer or const_uploader,
or set pipe_resource::flags same as const_uploader->flags.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Sun, 31 Dec 2017 21:51:14 +0000 (22:51 +0100)]
radeonsi: move const_uploader allocations to 32-bit address space
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Sun, 31 Dec 2017 21:34:45 +0000 (22:34 +0100)]
winsys/radeon: implement and enable 32-bit VM allocations
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Sun, 31 Dec 2017 21:02:35 +0000 (22:02 +0100)]
winsys/radeon: add struct radeon_vm_heap
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Sun, 31 Dec 2017 20:36:37 +0000 (21:36 +0100)]
winsys/amdgpu: enable 32-bit VM allocations
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Sun, 31 Dec 2017 20:32:36 +0000 (21:32 +0100)]
gallium/radeon: add 32-bit address space heaps
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Fri, 2 Feb 2018 17:22:15 +0000 (18:22 +0100)]
ac: query high bits of 32-bit address space
Marek Olšák [Sat, 27 Jan 2018 01:05:23 +0000 (02:05 +0100)]
gallium: use PIPE_CAP_CONSTBUF0_FLAGS
Marek Olšák [Sat, 27 Jan 2018 00:52:08 +0000 (01:52 +0100)]
gallium: allow drivers to impose BO flags restrictions on constant buffer 0
Required by radeonsi for optimal behavior.
Alexander von Gluck IV [Fri, 16 Feb 2018 22:56:31 +0000 (16:56 -0600)]
meson: Add Haiku platform support v4
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Anuj Phogat [Thu, 15 Feb 2018 23:35:42 +0000 (15:35 -0800)]
anv/icl: Add render target flush after uploading binding table
The PIPE_CONTROL command description says:
"Whenever a Binding Table Index (BTI) used by a Render Taget Message
points to a different RENDER_SURFACE_STATE, SW must issue a Render
Target Cache Flush by enabling this bit. When render target flush
is set due to new association of BTI, PS Scoreboard Stall bit must
be set in this packet."
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Anuj Phogat [Tue, 13 Feb 2018 21:48:34 +0000 (13:48 -0800)]
anv/icl: Enable float blend optimization
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Anuj Phogat [Fri, 26 May 2017 19:32:23 +0000 (12:32 -0700)]
anv/icl: Use gen11 functions
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Anuj Phogat [Fri, 26 May 2017 18:10:26 +0000 (11:10 -0700)]
anv/icl: Build anv libs for gen11
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Anuj Phogat [Fri, 26 May 2017 19:31:58 +0000 (12:31 -0700)]
anv/icl: Generate gen11 entry point functions
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Anuj Phogat [Fri, 26 May 2017 22:40:55 +0000 (15:40 -0700)]
anv/icl: Don't use DISPATCH_MODE_SIMD4X2
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Anuj Phogat [Fri, 26 May 2017 22:42:02 +0000 (15:42 -0700)]
anv/icl: Don't use SingleVertexDispatch
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Anuj Phogat [Fri, 26 May 2017 22:37:03 +0000 (15:37 -0700)]
anv/icl: Don't set ResetGatewayTimer
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Anuj Phogat [Fri, 26 May 2017 17:57:45 +0000 (10:57 -0700)]
anv/icl: Add #define genX
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Anuj Phogat [Fri, 26 May 2017 17:55:22 +0000 (10:55 -0700)]
anv/icl: Add gen11 mocs defines
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Sun, 19 Jun 2016 06:05:51 +0000 (23:05 -0700)]
i965: Implement GenerateMipmap directly, rather than using Meta.
Meta is awful and we'd like to stop using it. Implementing this using
BLORP allows us to stop trashing a bunch of GL state every time.
This follows the structure of st_generate_mipmap().
compute_num_levels is lifted directly from there.
Improves performance in Gl41HdrBloom by about 11.794% +/- 1.01919% (n=3)
on Kabylake GT2 at 1280x720 (the difference seems much smaller at higher
resolutions).
v2 (idr): Don't try depth or depth-stencil blorp blits on Gen4 or Gen5
because it's not implemented yet.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Kenneth Graunke [Sun, 19 Jun 2016 07:36:48 +0000 (00:36 -0700)]
mesa: Move compute_num_levels from st_gen_mipmap.c to mipmap.c.
I want to use compute_num_levels inside i965. Rather than duplicating
it, move it from mesa/st to core Mesa, and make it non-static.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Dylan Baker [Fri, 16 Feb 2018 17:07:25 +0000 (09:07 -0800)]
meson: freedreno depends on nir
This fixes a race condition in building targets that link in freedreno.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105120
Fixes:
0bbecc5a8548883f76a7 ("meson: define driver dependencies")
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Acked-by: Mark Janes <mark.a.janes@intel.com>
George Kyriazis [Tue, 13 Feb 2018 16:41:48 +0000 (10:41 -0600)]
swr/rast: blend_epi32() should return Integer, not Float
fix gcc8 compiler error for KNL.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105029
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Tue, 13 Feb 2018 18:53:39 +0000 (12:53 -0600)]
swr/rast: Normalize path for debug metadata
in template gen_llvm.hpp
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Mon, 12 Feb 2018 23:54:30 +0000 (17:54 -0600)]
swr/rast: Consolidate archrast Draw events
Consolidate archrst draw events into single draw event with an attribute
that represents the type of draw
- Add handlers for new private proto versions of DrawInstancedEvent,
DrawIndexedInstancedEvent, DrawInstancedSplitEvent, and
DrawIndexedInstancedSplitEvent
- Convert the draw events to generic DrawInfoEvents
- parse_proto_event_fields() replaces 'AR_DRAW_TYPE' as a field type with
'uint32_t'. This draw type is actually an enum, but can be represented
as an unsigned integer.
- is_draw_or_dispatch() recognizes DrawInfoEvent as a draw event
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Fri, 9 Feb 2018 20:04:14 +0000 (14:04 -0600)]
swr/rast: Add semantics for translating address
Added support for another full translation path in fetch jitter.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Fri, 9 Feb 2018 17:37:17 +0000 (11:37 -0600)]
swr/rast: Convert C Sampler intrinsics
Convert portions of the C sampler to the rasty SIMD lib.
Also fix SRL call with a non-immediate. Don't count on the compiler
automagically converting an srli call to srl if the shift count isn't
an immediate.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Wed, 7 Feb 2018 22:51:41 +0000 (16:51 -0600)]
swr/rast: Make SIMDLib templated types easier to use
"typename SIMD_T::TypeName" --> "TypeName<SIMD_T>"
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Wed, 7 Feb 2018 07:02:00 +0000 (01:02 -0600)]
swr/rast: Be more explicit when fetching next component
Use a new function to denote that we want to get offset to next component
and hide the fact that GEP is used underneath.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Wed, 7 Feb 2018 06:39:54 +0000 (00:39 -0600)]
swr/rast: Fix bug related to passing AR handle
We were passing a garbage handle. Let's not do that.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Tue, 6 Feb 2018 23:28:12 +0000 (17:28 -0600)]
swr/rast: Fix primitive replication issue in tesselation PA.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Fri, 2 Feb 2018 23:03:01 +0000 (17:03 -0600)]
swr/rast: Use llvm intrinsic masked gather
Use llvm intrinsic masked.gather instead of manual unroll for the cases
where we have vector of pointers. Improves llvm IR debug experience by
reducing a ton of IR to a single intrinsic call. Also seems to reduce
overall stack use considerably.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Fri, 2 Feb 2018 07:12:29 +0000 (01:12 -0600)]
swr/rast: Misc cleanup
Together with correct detection of clipDistance NaNs when no cullDistance is set
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Fri, 2 Feb 2018 04:12:22 +0000 (22:12 -0600)]
swr/rast: Renamed variable in vertexbufferstate
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Mon, 12 Feb 2018 19:38:45 +0000 (13:38 -0600)]
swr/rast: Fix GATHERPS to avoid assertions.
With the pBase type change, LLVM was asserting because of wrong types.
Cast appropriately.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Fri, 2 Feb 2018 01:28:58 +0000 (19:28 -0600)]
swr/rast: More precise user clip distance interpolation
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Thu, 1 Feb 2018 23:43:04 +0000 (17:43 -0600)]
swr/rast: Cull prims when all verts have negative clip distances
Performance optimization, and fixes some clipping issues.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Thu, 1 Feb 2018 21:37:36 +0000 (15:37 -0600)]
swr/rast: whitespace and comment cleanup
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Wed, 31 Jan 2018 23:07:59 +0000 (17:07 -0600)]
swr/rast: Fix invalid number of attributes
Fix invalid number of attributes passed into tesselation PA.
Needs to take into account any offsets from the shader.
Innocuous issue, but removes an assert firing in debug.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Wed, 31 Jan 2018 19:22:19 +0000 (13:22 -0600)]
swr/rast: Add clipper stats.
Clipper event is now:
event ClipperEvent
{
uint32_t drawId;
uint32_t trivialRejectCount;
uint32_t trivialAcceptCount;
uint32_t mustClipCount;
};
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Wed, 31 Jan 2018 07:09:53 +0000 (01:09 -0600)]
swr/rast: Separate event types to public and private
Split into two proto files and modify appropriate build rules for
configure / scons / meson builds.
There are private internal events (proxy) that communicate information
from rasterizer to ArchRast. ArchRast can use these events to calculate
a final answer and then emit other public events which will be saved to
file. Users will use the public proto file and not the private one.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Wed, 31 Jan 2018 06:18:32 +0000 (00:18 -0600)]
swr/rast: Clean up event types and remove BE events
Begin/End events not needed anymore.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Wed, 7 Feb 2018 01:42:06 +0000 (19:42 -0600)]
swr/rast: Removed unused variable
Gets rid of zillions of unused variable warnings, made worse by templates.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Tue, 30 Jan 2018 23:29:48 +0000 (17:29 -0600)]
swr/rast: Separate RDTSC code from archrast
Renamed rdstc defines more appropriately
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Mon, 29 Jan 2018 18:41:20 +0000 (12:41 -0600)]
swr/rast: Cleanup of mpPrivateContext in Builder
Provide access functions for mpPrivateContext in Builder.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Sat, 27 Jan 2018 06:19:07 +0000 (00:19 -0600)]
swr/rast: Remove some JIT debug code
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Sat, 27 Jan 2018 01:20:41 +0000 (19:20 -0600)]
swr/rast: Don't include private context in gather args
Move mpPrivateContext to compensate
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Fri, 26 Jan 2018 22:01:56 +0000 (16:01 -0600)]
swr/rast: Cleanup knob definitions
Rename some of the categories and move some options around.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Thu, 25 Jan 2018 03:54:46 +0000 (21:54 -0600)]
swr/rast: Add missing parameter to a few gather functions
We now pass pDrawContext as a default parameter
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Philipp Zabel [Mon, 12 Feb 2018 14:25:26 +0000 (15:25 +0100)]
etnaviv: add useful information to BO import errors
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Daniel Stone [Thu, 15 Feb 2018 09:17:52 +0000 (09:17 +0000)]
egl/wayland: Always use in-tree wayland-egl-backend.h
A recent patchset to Wayland[0] migrated Mesa's libwayland-egl backend
into Wayland itself, so implementations could provide backends. Mesa
still uses its own, and the two have already diverged[1].
The include from egl_dri2.h could pick up either the installed Wayland
wayland-egl-backend.h (with a 'driver_private' member), or the Mesa
internal wayland-egl-backend.h (with a 'private' member), failing the
build in the first instance.
Add an explicit directory prefix to the include, so we always get our
in-tree version.
[0]: https://patchwork.freedesktop.org/series/31663/
[1]: https://cgit.freedesktop.org/wayland/wayland/commit/?id=
9fa60983b579
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105103
Fixes:
198af27c679c ("wayland-egl: rename wayland-egl-{priv,backend}.h")
Daniel Stone [Thu, 25 Jan 2018 08:29:38 +0000 (08:29 +0000)]
meson: Move Wayland dmabuf to wayland-drm
As the comment notes: linux-dmabuf has nothing to do with wayland-drm,
but we need a single place to build these files we can use from both EGL
and Vulkan, which is guaranteed to be included before both EGL and
Vulkan WSI.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk>
Eric Engestrom [Thu, 15 Feb 2018 11:10:22 +0000 (11:10 +0000)]
egl/wayland: check for invalid format index
v2: just tell the compiler to assume the format will always be found, as
it comes from the table itself to begin with. (DanielS)
CID:
1429516
Fixes:
d32b23f3830099a328b91 "egl/wayland: Add bpp to visual map"
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Eric Engestrom [Thu, 15 Feb 2018 10:59:24 +0000 (10:59 +0000)]
glsl: fix sizeof(pointer) bug
Doesn't really change anything to the test though ¯\_(ツ)_/¯
CID:
1429511
Fixes:
e8495646afb06a9dd7786 "glsl/tests: changes to test_disk_cache_create test"
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Timothy Arceri [Thu, 15 Feb 2018 04:08:49 +0000 (15:08 +1100)]
radeonsi/nir: set TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL correctly
We set this for post_depth_coverage in addition to early_fragment_tests.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Dave Airlie [Wed, 14 Feb 2018 02:52:27 +0000 (12:52 +1000)]
virgl: remap query types to hw support.
The gallium query types changed, so we need to remap from the
gallium ones to the virgl ones.
Fixes:
dEQP-GLES3.functional.transform_feedback.basic_types*
"This also fixes:
dEQP-GLES3.functional.transform_feedback.array.separate*
dEQP-GLES3.functional.transform_feedback.array_element*
dEQP-GLES3.functional.transform_feedback.interpolation.*
Gallium's p_defines.h and virglrenderer's p_defines.h have diverged
quite a bit, so not including
PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE there makes sense for now."
- Gurchetan Singh
Fixes:
3f6b3d9db (gallium: add PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE)
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Tested-by: Gurchetan Singh <gurchetansingh@chromium.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Anuj Phogat [Wed, 17 Jan 2018 22:33:17 +0000 (14:33 -0800)]
i965/icl: Add render target flush after uploading binding table
From PIPE_CONTROL command description in gfxspecs:
"Whenever a Binding Table Index (BTI) used by a Render Taget Message
points to a different RENDER_SURFACE_STATE, SW must issue a Render
Target Cache Flush by enabling this bit. When render target flush
is set due to new association of BTI, PS Scoreboard Stall bit must
be set in this packet."
V2: Move the PIPE_CONTROL to update_renderbuffer_surfaces() in
brw_wm_surface_state.c (Ken).
Fixes a fulsim error and a GPU hang described in below JIRA.
JIRA: MD5-322
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Anuj Phogat [Fri, 3 Nov 2017 21:48:29 +0000 (14:48 -0700)]
i965/icl: Enable float blend optimization and Wa3DStateMode
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Anuj Phogat [Wed, 14 Feb 2018 22:30:27 +0000 (14:30 -0800)]
intel/common/icl: Add has_sample_with_hiz flag in gen_device_info
Sampling from hiz is enabled in i965 for GEN9+ but this feature has
been removed from gen11. So, this new flag will be useful to turn
the feature on/off for different gen h/w. It will be used later
in a patch adding device info for gen11.
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Anuj Phogat [Wed, 7 Feb 2018 00:47:04 +0000 (16:47 -0800)]
i965/icl: Add assertions to check dispatch mode is SIMD8
SIMD4x2 dispatch mode has been removed in GEN11. We're not using
it anyways in Mesa. Adding few asserts to make it explicit.
Use GEN_GEN macro in place of devinfo->gen (Ken)
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Anuj Phogat [Fri, 18 Aug 2017 19:11:38 +0000 (12:11 -0700)]
i965/icl: Update switch statements
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Anuj Phogat [Thu, 20 Jul 2017 23:21:03 +0000 (16:21 -0700)]
i965/icl: Update the assert in brw_memory_barrier()
Nothing is changed here from gen10 to gen11. So, just update
the assert.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Anuj Phogat [Wed, 10 May 2017 17:49:04 +0000 (10:49 -0700)]
i965/icl: Define and use icl mocs settings
Gen11 MOCS settings are duplicate of Gen10 MOCS settings.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Anuj Phogat [Fri, 5 May 2017 20:55:10 +0000 (13:55 -0700)]
i965/icl: Update the comment for maximum number of threads per PSD
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Anuj Phogat [Thu, 20 Jul 2017 23:00:36 +0000 (16:00 -0700)]
i965/icl: Build and use gen11 functions for genxml state-upload and blorp
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Anuj Phogat [Wed, 24 May 2017 20:58:37 +0000 (13:58 -0700)]
i965/icl: Don't set ResetGatewayTimer
This field is removed in gen11+
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Anuj Phogat [Tue, 27 Jun 2017 21:46:26 +0000 (14:46 -0700)]
intel/icl: Do StateCacheInvalidation for indirect clear color
StateCacheInvalidation is required on all gen7+ platforms. We
don't need to update this check for every new gen h/w unless
this requirement is changed. So, dropping the check for latest
gen h/w.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Anuj Phogat [Thu, 20 Jul 2017 22:59:49 +0000 (15:59 -0700)]
intel/isl/icl: Build and use gen11 surface state emit functions
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Anuj Phogat [Fri, 19 May 2017 19:13:40 +0000 (12:13 -0700)]
intel/isl/icl: Add the maximum surface size limit
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Anuj Phogat [Tue, 16 May 2017 23:47:07 +0000 (16:47 -0700)]
intel/genxml/icl: Update genx_bits header
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Anuj Phogat [Wed, 10 May 2017 17:50:15 +0000 (10:50 -0700)]
intel/genxml/icl: Generate packing headers
Move build system changes in to one patch (Ken, Emil)
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Anuj Phogat [Thu, 15 Feb 2018 18:39:00 +0000 (10:39 -0800)]
intel/genxml/icl: Add gen11.xml
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Kenneth Graunke [Mon, 12 Feb 2018 15:14:22 +0000 (07:14 -0800)]
i965: Drop EXEC_OBJECT_CAPTURE defines.
These only existed to avoid making people update libdrm for new uABI
headers. A while ago we imported those headers into the Mesa repo,
so the dependency is gone and these are no longer useful.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jan Vesely [Thu, 15 Feb 2018 19:00:38 +0000 (14:00 -0500)]
clover: Fix build after llvm r325155 and r325160
r325155 ("Pass a reference to a module to the bitcode writer.")
and
r325160 ("Pass module reference to CloneModule")
change function interface from pointer to reference.
v2: Fix indentation (tab instead of spaces)
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Bas Nieuwenhuizen [Thu, 15 Feb 2018 20:24:35 +0000 (21:24 +0100)]
radv: Always lower indirect derefs after nir_lower_global_vars_to_local.
Otherwise new local variables can cause hangs on vega.
CC: <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105098
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Dylan Baker [Wed, 17 Jan 2018 18:20:54 +0000 (10:20 -0800)]
meson: fix xvmc target linkage
This needs to link the state tracker with --whole-archive to expose the
right symbols.
v4: - Always add libswdri and libswkmsdri to the link_with list
Fixes:
22a817af8a89eb3c7 ("meson: build gallium xvmc state tracker")
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Dylan Baker [Wed, 17 Jan 2018 18:12:19 +0000 (10:12 -0800)]
meson: Fix xa target linkage
This needs to use --whole-archive (link_whole in meson) to properly
expose symbols.
v4: - Always add libswdri and libswkmsdri to link_with list
Fixes:
0ba909f0f111824 ("meson: build gallium xa state tracker")
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Dylan Baker [Wed, 17 Jan 2018 18:12:19 +0000 (10:12 -0800)]
meson: Fix omx-bellagio target linkage
This needs to use --whole-archive (link_whole in meson) to properly
expose symbols.
v4: - Always add libswdri and libswkmsdri to link_with
Fixes:
1d36dc674d528b93b ("meson: build gallium omx state tracker")
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Dylan Baker [Wed, 17 Jan 2018 17:49:55 +0000 (09:49 -0800)]
meson: fix va target linkage
The state tracker needs to be linked with whole-archive (like
autotools). As a result there are symbols from libswdri and libswkmsdri
that are needed, so link those as well.
v4: - Always add libswdri and libswkmsdri to link_with list
Fixes:
5a785d51a6d6 ("meson: build gallium va state tracker")
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>