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Sanjay Patel [Fri, 25 Sep 2015 21:49:48 +0000 (21:49 +0000)]
merge vector stores into wider vector stores and fix AArch64 misaligned access TLI hook (PR21711)
This is a redo of D7208 ( r227242 - http://llvm.org/viewvc/llvm-project?view=revision&revision=227242 ).
The patch was reverted because an AArch64 target could infinite loop after the change in DAGCombiner
to merge vector stores. That happened because AArch64's allowsMisalignedMemoryAccesses() wasn't telling
the truth. It reported all unaligned memory accesses as fast, but then split some 128-bit unaligned
accesses up in performSTORECombine() because they are slow.
This patch attempts to fix the problem in AArch's allowsMisalignedMemoryAccesses() while preserving
existing (perhaps questionable) lowering behavior.
The x86 test shows that store merging is working as intended for a target with fast 32-byte unaligned
stores.
Differential Revision: http://reviews.llvm.org/D12635
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248622
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Matthias Braun [Fri, 25 Sep 2015 21:41:40 +0000 (21:41 +0000)]
PrologueEpilogInserter: Fix missing live-ins when savepoint equals restorepoint
The algorithm would not modify the live-in list of blocks below the save
block point which is correct unless it happens to be a restore point at
the same time.
Also fixes the benign issue of live-in registers being added twice in
some cases.
The testcase is based on a test submitted by Kit Barton.
Differential Revision: http://reviews.llvm.org/D13176
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248620
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Tom Stellard [Fri, 25 Sep 2015 21:41:28 +0000 (21:41 +0000)]
AMDGPU/SI: Use .hsatext section instead of .text for HSA
Reviewers: arsenm, grosbach, rafael
Subscribers: arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D12424
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248619
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Tom Stellard [Fri, 25 Sep 2015 21:41:14 +0000 (21:41 +0000)]
MCAsmInfo: Allow targets to specify when the .section directive should be omitted
Summary:
The default behavior is to omit the .section directive for .text, .data,
and sometimes .bss, but some targets may want to omit this directive for
other sections too.
The AMDGPU backend will uses this to emit a simplified syntax for section
switches. For example if the section directive is not omitted (current
behavior), section switches to .hsatext will be printed like this:
.section .hsatext,#alloc,#execinstr,#write
This is actually wrong, because .hsatext has some custom STT_* flags,
which MC doesn't know how to print or parse.
If the section directive is omitted (made possible by this commit),
section switches will be printed like this:
.hsatext
The motivation for this patch is to make it possible to emit sections
with custom STT_* flags without having to teach MC about all the target
specific STT_* flags.
Reviewers: rafael, grosbach
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D12423
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248618
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Matthias Braun [Fri, 25 Sep 2015 21:25:19 +0000 (21:25 +0000)]
MachineBasicBlock: Factor out common code into isReturnBlock()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248617
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Sanjoy Das [Fri, 25 Sep 2015 21:16:50 +0000 (21:16 +0000)]
Revert two SCEV changes that caused test failures in clang.
r248606: "[SCEV] Exploit A < B => (A+K) < (B+K) when possible"
r248608: "[SCEV] Teach isLoopBackedgeGuardedByCond to exploit trip counts."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248614
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Justin Bogner [Fri, 25 Sep 2015 21:03:46 +0000 (21:03 +0000)]
ADCE: Fix typo in file comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248613
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Matt Arsenault [Fri, 25 Sep 2015 20:22:12 +0000 (20:22 +0000)]
PeepholeOptimizer: Remove redundant copies
If a virtual register is copied and another copy was already
seen, replace with the previous copy. This only handles the
simplest cases for now.
This pattern shows up from various operand restrictions
AMDGPU has which require inserting copies depending
on the register class of the operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248611
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Chad Rosier [Fri, 25 Sep 2015 20:20:22 +0000 (20:20 +0000)]
Simplify code. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248610
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Sanjay Patel [Fri, 25 Sep 2015 20:12:43 +0000 (20:12 +0000)]
more space; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248609
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Sanjoy Das [Fri, 25 Sep 2015 19:59:57 +0000 (19:59 +0000)]
[SCEV] Teach isLoopBackedgeGuardedByCond to exploit trip counts.
Summary:
If the trip count of a specific backedge is `N`, then we know that
backedge is effectively guarded by the condition `{0,+,1} u< N`. This
change teaches SCEV to use this condition to prove things in
`isLoopBackedgeGuardedByCond`.
Depends on D12948
Depends on D12949
Reviewers: atrick, reames, majnemer, hfinkel
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D12950
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248608
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Sanjoy Das [Fri, 25 Sep 2015 19:59:52 +0000 (19:59 +0000)]
[SCEV] Extract helper function from isImpliedCond; NFC
Summary:
This new helper routine will be used in a subsequent change.
Reviewers: hfinkel
Subscribers: hfinkel, sanjoy, llvm-commits
Differential Revision: http://reviews.llvm.org/D12949
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248607
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Sanjoy Das [Fri, 25 Sep 2015 19:59:49 +0000 (19:59 +0000)]
[SCEV] Exploit A < B => (A+K) < (B+K) when possible
Summary:
This change teaches SCEV's `isImpliedCond` two new identities:
A u< B u< -C => (A + C) u< (B + C)
A s< B s< INT_MIN - C => (A + C) s< (B + C)
While these are useful on their own, they're really intended to support
D12950.
Reviewers: atrick, reames, majnemer, nlewycky, hfinkel
Subscribers: aadg, sanjoy, llvm-commits
Differential Revision: http://reviews.llvm.org/D12948
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248606
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Matt Arsenault [Fri, 25 Sep 2015 18:21:47 +0000 (18:21 +0000)]
AMDGPU: Add some more tests for literal operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248600
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Matt Arsenault [Fri, 25 Sep 2015 18:09:15 +0000 (18:09 +0000)]
AMDGPU: Make getNamedOperandIdx declaration readonly
This matches how it is defined in the generated implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248598
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Chad Rosier [Fri, 25 Sep 2015 17:48:17 +0000 (17:48 +0000)]
[AArch64] Add support for generating pre- and post-index load/store pairs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248593
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Matt Arsenault [Fri, 25 Sep 2015 17:41:20 +0000 (17:41 +0000)]
AMDGPU: Disable some passes that are not meaningful
Don't run passes related to stack maps, garbage collection,
exceptions since these aren't useful for GPUs.
There might be a few more to turn off that I'm less sure about
(e.g. ShrinkWrapping) or I'm not sure how to disable
(SafeStack and StackProtector)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248591
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Matt Arsenault [Fri, 25 Sep 2015 17:27:08 +0000 (17:27 +0000)]
AMDGPU: Handle i64->v2i32 loads/stores in PreprocessISelDAG
This fixes a select error when the i64 source was also
bitcasted to v2i32 in the original source.
Instead of awkwardly trying to select the modified source value and
the store, replace before isel begins.
Uses a worklist to avoid possible problems from mutating the DAG,
although it seems to work OK without it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248589
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Matt Arsenault [Fri, 25 Sep 2015 17:21:28 +0000 (17:21 +0000)]
AMDGPU: Fix recomputing dominator tree unnecessarily
SIFixSGPRCopies does not modify the CFG, but this was
being recomputed before running SIFoldOperands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248587
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Matt Arsenault [Fri, 25 Sep 2015 17:08:42 +0000 (17:08 +0000)]
AMDGPU: Re-justify workaround and fix worked around problem
When buffer resource descriptors were built, the upper two components
of the descriptor were first composed into a 64-bit register because
legalizeOperands assumed all operands had the same register class.
Fix that problem, but keep the workaround. I'm not sure anything
actually is actually emitting such a REG_SEQUENCE now.
If multiple resource descriptors are set up with different base
pointers, this is copied with a single s_mov_b64. We probably
should fix this better by recognizing a pair of s_mov_b32 later,
but for now delete the dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248585
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Matt Arsenault [Fri, 25 Sep 2015 17:08:40 +0000 (17:08 +0000)]
AMDGPU: Don't create REG_SEQUENCE with SGPR dest and VGPR sources
This avoids needting to re-legalize the new REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248584
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Matt Arsenault [Fri, 25 Sep 2015 16:58:27 +0000 (16:58 +0000)]
AMDGPU: Fix not adding exec to defs of cmpx instruction pseudos
This was only set on the final _si/_vi version, but not
on the pseudos most of codegen sees.
No test since these instructions aren't used yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248583
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Matt Arsenault [Fri, 25 Sep 2015 16:58:25 +0000 (16:58 +0000)]
AMDGPU: Improve accuracy of instruction rates for VOPC
These were all using the default 32-bit VALU write class,
but the i64/f64 compares are half rate.
I'm not sure this is really correct, because they are still using
the write to VALU write class, even though they really write
to the SALU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248582
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James Molloy [Fri, 25 Sep 2015 15:39:29 +0000 (15:39 +0000)]
[GlobalsAA] Teach GlobalsAA about nocapture
Arguments to function calls marked "nocapture" can be marked as
non-escaping. However, nocapture is defined in terms of the lifetime
of the callee, and if the callee can directly or indirectly recurse to
the caller, the semantics of nocapture are invalid.
Therefore, we eagerly discover which SCC each function belongs to,
and later can check if callee and caller of a callsite belong to
the same SCC, in which case there could be recursion.
This means that we can't be so optimistic in
getModRefInfo(ImmutableCallsite) - previously we assumed all call
arguments never aliased with an escaping global. Now we need to check,
because a global could now be passed as an argument but still not
escape.
This also solves a related conformance problem: MemCpyOptimizer can
turn non-escaping stores of globals into calls to intrinsics like
llvm.memcpy/llvm/memset. This confuses GlobalsAA, which knows the
global can't escape and so returns NoModRef when queried, when
obviously a memcpy/memset call does indeed reference and modify its
arguments.
This fixes PR24800, PR24801, and PR24802.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248576
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Saleem Abdulrasool [Fri, 25 Sep 2015 05:41:02 +0000 (05:41 +0000)]
ARM: make -Asserts,-Werror=unused-variable build happy
The value was only used in an assertion. Sink the variable usage into the
assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248562
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Saleem Abdulrasool [Fri, 25 Sep 2015 05:15:46 +0000 (05:15 +0000)]
ARM: address WoA division limitation
We now emit the compiler generated divide by zero check that was needed for the
MSVC routines. We construct a psuedo-instruction for the DBZ check as the
operation requires splitting up the BB. For the 64-bit operations, we need to
custom expand the node as we need to insert the DBZ check and then emit the
libcall to the appropriate name. Because this is target specific, it seemed
better to reproduce the expansion operation from the target-agnostic type
legalization rather than sink this there to avoid the duplication. The division
library calls now match MSVC semantically.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248561
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Matt Arsenault [Fri, 25 Sep 2015 00:28:43 +0000 (00:28 +0000)]
AMDGPU: Remove unused includes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248553
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Sanjoy Das [Fri, 25 Sep 2015 00:05:40 +0000 (00:05 +0000)]
[LangRef] Unbreak the docs Sphinx build.
r248551 introduced some breakage due to incorrectly terminated
``literals`` s.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248552
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Sanjoy Das [Thu, 24 Sep 2015 23:34:52 +0000 (23:34 +0000)]
[Bitcode][Asm] Teach LLVM to read and write operand bundles.
Summary:
This also adds the first set of tests for operand bundles.
The optimizer has not been audited to ensure that it does the right
thing with operand bundles.
Depends on D12456.
Reviewers: reames, chandlerc, majnemer, dexonsmith, kmod, JosephTremoulet, rnk, bogner
Subscribers: maksfb, llvm-commits
Differential Revision: http://reviews.llvm.org/D12457
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248551
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Ed Maste [Thu, 24 Sep 2015 23:01:16 +0000 (23:01 +0000)]
Restore test coverage for other than ELFOSABI_NONE
Add a FreeBSD test to restore testing of ELF OSABI other than
ELFOSABI_NONE after r248534.
Differential Revision: http://reviews.llvm.org/D13146
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248550
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Matt Arsenault [Thu, 24 Sep 2015 22:36:49 +0000 (22:36 +0000)]
Fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248549
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Chad Rosier [Thu, 24 Sep 2015 21:27:49 +0000 (21:27 +0000)]
[AArch64] Improve the readability of the ld/st optimization pass. NFC.
In this context, MI is an add/sub instruction not a loads/store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248540
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Simon Pilgrim [Thu, 24 Sep 2015 21:02:17 +0000 (21:02 +0000)]
[X86][SSE2] Fix zero/any extension shuffles that don't start from the first element
Fix for D12561 - we weren't correctly ensuring that the base element for extension was moved to start on a boundary suitable for UNPCKL/H
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248536
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Rafael Espindola [Thu, 24 Sep 2015 20:57:24 +0000 (20:57 +0000)]
Use ELFOSABI_NONE instead of ELFOSABI_LINUX.
The doesn't seem to be a difference and ELFOSABI_NONE seems to be far more
common:
* Linux doesn't care when loading and puts ELFOSABI_NONE on core dumps.
* Gold and bfd ld produce files with ELFOSABI_NONE.
* Gold and bfd ld seems to ignore EI_OSABI other than for freebsd.
* Gas puts ELFOSABI_NONE in most .o files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248534
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Matt Arsenault [Thu, 24 Sep 2015 19:52:27 +0000 (19:52 +0000)]
AMDGPU: Add s_dcache_* instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248533
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Matt Arsenault [Thu, 24 Sep 2015 19:52:21 +0000 (19:52 +0000)]
AMDGPU: Add cache invalidation instructions.
These are necessary for implementing mem_fence for
OpenCL 2.0.
The VI assembler tests are disabled since it seems to be
using the wrong encoding or opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248532
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Matt Arsenault [Thu, 24 Sep 2015 19:52:15 +0000 (19:52 +0000)]
AMDGPU: Run mubuf assembler test for CI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248531
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Chad Rosier [Thu, 24 Sep 2015 19:21:42 +0000 (19:21 +0000)]
[AArch64] The paired post-increment store instruction has an output register.
The pre- and post-increment version update the base register, but the post-
version was defined incorrectly. There is no test case as we don't currently
generate these instructions, but I plan on changing that in the near future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248528
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Sanjoy Das [Thu, 24 Sep 2015 19:14:18 +0000 (19:14 +0000)]
[IR] Add operand bundles to CallInst and InvokeInst.
Summary:
This change teaches `CallInst`s and `InvokeInst`s to maintain a set of
operand bundles as part of its operands. `CallInst`s and `InvokeInst`s
with operand bundles co-allocate some space before their `Use` array to
hold meta information about which of its operands are part of an operand
bundle.
The strings corresponding to the bundle tags are interned into
`LLVMContextImpl::BundleTagCache`
This change does not include any parsing / bitcode support. That's the
next change.
Depends on D12455.
Reviewers: reames, chandlerc, majnemer, dexonsmith, kmod, JosephTremoulet, rnk, bogner
Subscribers: MatzeB, sanjoy, llvm-commits
Differential Revision: http://reviews.llvm.org/D12456
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248527
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Artyom Skrobov [Thu, 24 Sep 2015 17:31:16 +0000 (17:31 +0000)]
[ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.def
Currently, the availability of DSP instructions (ACLE 6.4.7) is handled in a
hand-rolled tricky condition block in tools/clang/lib/Basic/Targets.cpp, with
a FIXME: attached.
This patch changes the handling of +t2dsp to be in line with other
architecture extensions.
Following a revert of r248152 and new review comments, this patch also includes
renaming FeatureDSPThumb2 -> FeatureDSP, hasThumb2DSP() -> hasDSP(), etc.
The spelling of "t2dsp" is preserved, pending a further investigation of its
possible external usage.
Differential Revision: http://reviews.llvm.org/D12937
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248519
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Adrian Prantl [Thu, 24 Sep 2015 16:10:14 +0000 (16:10 +0000)]
dsymutil: Fix the condition to distinguish module imports form definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248512
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James Molloy [Thu, 24 Sep 2015 16:06:32 +0000 (16:06 +0000)]
[ValueTracking] Teach isKnownNonZero a new trick
If the shifter operand is a constant, and all of the bits shifted out
are known to be zero, then if X is known non-zero at least one
non-zero bit must remain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248508
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Benjamin Kramer [Thu, 24 Sep 2015 14:52:52 +0000 (14:52 +0000)]
[objdump] Make iterator operator* return a reference.
This is closer to the expected behavior of an iterator and avoids awkward
warnings from clang's -Wrange-loop-analysis below.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248497
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Mohammad Shahid [Thu, 24 Sep 2015 14:37:25 +0000 (14:37 +0000)]
Regression Test: Deletes redundant/invalid test.
Removes absdiff_expand.ll regression test file which is invalid.
Diffrential Revision: http://reviews.llvm.org/D11678
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248493
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Daniel Sanders [Thu, 24 Sep 2015 12:10:23 +0000 (12:10 +0000)]
[mips] Use PredicateControl for the MSA ASE instructions. NFC.
Reviewers: vkalintiris
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D13092
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248486
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Mohammad Shahid [Thu, 24 Sep 2015 10:35:03 +0000 (10:35 +0000)]
Codegen: Fix llvm.*absdiff semantic.
Fixes the overflow case of llvm.*absdiff intrinsic also updats the tests and LangRef.rst accordingly.
Differential Revision: http://reviews.llvm.org/D11678
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248483
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Charlie Turner [Thu, 24 Sep 2015 10:24:58 +0000 (10:24 +0000)]
[InstCombine] Recognize another bswap idiom.
Summary:
The byte-swap recognizer can now notice that this
```
uint32_t bswap(uint32_t x)
{
x = (x & 0x0000FFFF) << 16 | (x & 0xFFFF0000) >> 16;
x = (x & 0x00FF00FF) << 8 | (x & 0xFF00FF00) >> 8;
return x;
}
```
is a bswap. Fixes PR23863.
Reviewers: nlewycky, hfinkel, hans, jmolloy, rengolin
Subscribers: majnemer, rengolin, llvm-commits
Differential Revision: http://reviews.llvm.org/D12637
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248482
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Matt Arsenault [Thu, 24 Sep 2015 08:36:14 +0000 (08:36 +0000)]
Introduce target hook for optimizing register copies
Allow a target to do something other than search for copies
that will avoid cross register bank copies.
Implement for SI by only rewriting the most basic copies,
so it should look through anything like a subregister extract.
I'm not entirely satisified with this because it seems like
eliminating a reg_sequence that isn't fully used should work
generically for all targets without them having to override
something. However, it seems to be tricky to have a simple
implementation of this without rewriting to invalid kinds
of subregister copies on some targets.
I'm not sure if there is currently a generic way to easily check
if a subregister index would be valid for the current use.
The current set of TargetRegisterInfo::get*Class functions don't
quite behave like I would expect (e.g. getSubClassWithSubReg
returns the maximal register class rather than the minimal), so
I'm not sure how to make the generic test keep searching if
SrcRC:SrcSubReg is a valid replacement for DefRC:DefSubReg. Making
the default implementation to check for simple copies breaks
a variety of ARM and x86 tests by producing illegal subregister uses.
The ARM tests are not actually changed since it should still be using
the same sharesSameRegisterFile implementation, this just relaxes
them to not check for specific registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248478
91177308-0d34-0410-b5e6-
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Matt Arsenault [Thu, 24 Sep 2015 07:51:28 +0000 (07:51 +0000)]
AMDGPU: Return after instruction is processed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248476
91177308-0d34-0410-b5e6-
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Matt Arsenault [Thu, 24 Sep 2015 07:51:25 +0000 (07:51 +0000)]
AMDGPU: Remove another unnecessary check from commuteInstruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248475
91177308-0d34-0410-b5e6-
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Matt Arsenault [Thu, 24 Sep 2015 07:51:23 +0000 (07:51 +0000)]
AMDGPU: Add readonly to InstrMapping functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248474
91177308-0d34-0410-b5e6-
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Matt Arsenault [Thu, 24 Sep 2015 07:51:20 +0000 (07:51 +0000)]
TableGen: Add LLVM_READONLY to generated InstrMapping functions
These just read from a generated table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248473
91177308-0d34-0410-b5e6-
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Matt Arsenault [Thu, 24 Sep 2015 07:51:17 +0000 (07:51 +0000)]
AMDGPU: Fix printing trailing whitespace for mubuf atomics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248472
91177308-0d34-0410-b5e6-
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Matt Arsenault [Thu, 24 Sep 2015 07:51:12 +0000 (07:51 +0000)]
Remove dead declaration
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248471
91177308-0d34-0410-b5e6-
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Matt Arsenault [Thu, 24 Sep 2015 07:22:38 +0000 (07:22 +0000)]
Use new TokenFactor chain when merging stores
If the stores are storing values from loads which partially
alias the stores, we could end up placing the merged loads
and stores on the same chain which has the potential to break.
Each store may have a different chain dependency on only some
of the original loads. Create a new TokenFactor to capture all
of the required dependencies of the stores rather than assuming
all stores can use the same chain.
The testcase is a situation where this happens, although
it does not have an observable change from this. The DAG nodes
just happened to not be reordered before despite this missing
chain dependency.
This is based on an off-list report for an out of tree target
which regressed due to r246307 and I haven't managed to find a case
where the nodes do end up reordered with an in tree target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248468
91177308-0d34-0410-b5e6-
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Matt Arsenault [Thu, 24 Sep 2015 07:16:37 +0000 (07:16 +0000)]
AMDGPU: Reduce number of copies emitted
Instead of always inserting a copy in case
the super register is itself a subregister,
only extract to the super reg class if this is
actually the case.
This shouldn't really change codegen, but
makes looking at the output of SIFixSGPRCopies
easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248467
91177308-0d34-0410-b5e6-
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Justin Bogner [Thu, 24 Sep 2015 05:29:31 +0000 (05:29 +0000)]
Fix a think-o in which functions these should surround
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248465
91177308-0d34-0410-b5e6-
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Justin Bogner [Thu, 24 Sep 2015 05:20:04 +0000 (05:20 +0000)]
Add some NDEBUG checks I accidentally dropped in r248462
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248464
91177308-0d34-0410-b5e6-
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Justin Bogner [Thu, 24 Sep 2015 04:59:24 +0000 (04:59 +0000)]
BasicAA: Move BasicAAResult::alias out-of-line. NFC
This makes the header more readable and cleans up some unnecessary
header differences between NDEBUG and !NDEBUG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248462
91177308-0d34-0410-b5e6-
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Michael Zolotukhin [Thu, 24 Sep 2015 03:50:17 +0000 (03:50 +0000)]
Add CFG Simplification pass after Loop Unswitching.
Loop unswitching produces conditional branches with constant condition,
and it's beneficial for later passes to clean this up with simplify-cfg.
We do this after the second invocation of loop-unswitch, but not after
the first one. Not doing so might cause problem for passes like
LoopUnroll, whose estimate of loop body size would be less accurate.
Reviewers: hfinkel
Differential Revision: http://reviews.llvm.org/D13064
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248460
91177308-0d34-0410-b5e6-
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Evgeniy Stepanov [Thu, 24 Sep 2015 01:23:51 +0000 (01:23 +0000)]
[safestack] Fix compiler crash in the presence of stack restores.
A use can be emitted before def in a function with stack restore
points but no static allocas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248455
91177308-0d34-0410-b5e6-
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Sanjoy Das [Thu, 24 Sep 2015 01:00:49 +0000 (01:00 +0000)]
[IR] Teach `llvm::User` to co-allocate a descriptor.
Summary:
With this change, subclasses of `llvm::User` will be able to co-allocate
a variable number of bytes (called a "descriptor") with the `llvm::User`
instance. The co-allocated descriptor can later be accessed using
`llvm::User::getDescriptor`. This will be used in later changes to
implement operand bundles.
This change steals one bit from `NumUserOperands`, but given that it is
still 28 bits wide I don't think this will be a practical issue.
This change does not allow allocating hung off uses with descriptors.
This only for simplicity, not for any fundamental reason; and we can
easily add this functionality later if needed.
Reviewers: reames, chandlerc, dexonsmith, kmod, majnemer, pete, JosephTremoulet
Subscribers: pete, sanjoy, llvm-commits
Differential Revision: http://reviews.llvm.org/D12455
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248453
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Adrian Prantl [Thu, 24 Sep 2015 00:35:14 +0000 (00:35 +0000)]
Add REQUIRES: default_triple to these testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248452
91177308-0d34-0410-b5e6-
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Rui Ueyama [Thu, 24 Sep 2015 00:23:07 +0000 (00:23 +0000)]
Remove iterator_range::end.
Because the current proposal does not include that member function,
and we are trying to keep in line with that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248451
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Rui Ueyama [Wed, 23 Sep 2015 23:58:29 +0000 (23:58 +0000)]
Add iterator_range::end() predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248447
91177308-0d34-0410-b5e6-
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Michael Zolotukhin [Wed, 23 Sep 2015 23:12:43 +0000 (23:12 +0000)]
[Unroll] When completely unrolling the loop, replace conditinal branches with unconditional.
Nothing is expected to change, except we do less redundant work in
clean-up.
Reviewers: hfinkel
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D12951
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248444
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Wei Mi [Wed, 23 Sep 2015 22:40:45 +0000 (22:40 +0000)]
Put profile variables of COMDAT functions to it's own COMDAT group.
In -fprofile-instr-generate compilation, to remove the redundant profile
variables for the COMDAT functions, these variables are placed in the same
COMDAT group as its associated function. This way when the COMDAT function
is not picked by the linker, those profile variables will also not be
output in the final binary. This may cause warning when mix link objects
built w and wo -fprofile-instr-generate.
This patch puts the profile variables for COMDAT functions to its own COMDAT
group to avoid the problem.
Patch by xur.
Differential Revision: http://reviews.llvm.org/D12248
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248440
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Sanjay Patel [Wed, 23 Sep 2015 22:28:18 +0000 (22:28 +0000)]
set div/rem default values to 'expensive' in TargetTransformInfo's cost model
...because that's what the cost model was intended to do.
As discussed in D12882, this fix has a temporary unintended consequence for
SimplifyCFG: it causes us to not speculate an fdiv. However, two wrongs make
PR24818 right, and two wrongs make PR24343 act right even though it's really
still wrong.
I intend to correct SimplifyCFG and add to CodeGenPrepare to account for this
cost model change and preserve the righteousness for the bug report cases.
https://llvm.org/bugs/show_bug.cgi?id=24818
https://llvm.org/bugs/show_bug.cgi?id=24343
Differential Revision: http://reviews.llvm.org/D12882
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248439
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Tim Northover [Wed, 23 Sep 2015 22:21:09 +0000 (22:21 +0000)]
ARM: fix folding stack adjustment (again again again...)
This time, the issue is that we weren't accounting for the possibility that
aligned DPRs could have been stored after the final "push" in a prologue. When
that happened we effectively moved a "sub sp, #N" from below the aligned stores
to above them, and everything went to pot.
To make it worse, I'd actually committed something testing that we produced
wrong code, so the test update is tiny.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248437
91177308-0d34-0410-b5e6-
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Adrian Prantl [Wed, 23 Sep 2015 20:44:37 +0000 (20:44 +0000)]
dsymutil: Don't prune forward declarations inside a module definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248428
91177308-0d34-0410-b5e6-
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Adrian Prantl [Wed, 23 Sep 2015 19:53:10 +0000 (19:53 +0000)]
Fix this dsymutil testcase by not passing in a path to the modulemap file,
so the lookup works as expected after prepending the oso-prepend-path.
This manifested only on Windows, because "/" is not a relative path there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248423
91177308-0d34-0410-b5e6-
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Philip Reames [Wed, 23 Sep 2015 19:48:43 +0000 (19:48 +0000)]
Remove handling of AddrSpaceCast in stripAndAccumulateInBoundsConstantOffsets
Patch by: simoncook
Unlike BitCasts, AddrSpaceCasts do not always produce an output the same size as its input, which was previously assumed. This fixes cases where two address spaces do not have the same size pointer, as an assertion failure would occur when trying to prove deferenceability. LoopUnswitch is used in the particular test, but LICM also exhibits the same problem.
Differential Revision: http://reviews.llvm.org/D13008
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248422
91177308-0d34-0410-b5e6-
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Lawrence Hu [Wed, 23 Sep 2015 19:25:30 +0000 (19:25 +0000)]
Swap loop invariant GEP with loop variant GEP to allow more LICM.
This patch changes the order of GEPs generated by Splitting GEPs
pass, specially when one of the GEPs has constant and the base is
loop invariant, then we will generate the GEP with constant first
when beneficial, to expose more cases for LICM.
If originally Splitting GEP generate the following:
do.body.i:
%idxprom.i = sext i32 %shr.i to i64
%2 = bitcast %typeD* %s to i8*
%3 = shl i64 %idxprom.i, 2
%uglygep = getelementptr i8, i8* %2, i64 %3
%uglygep7 = getelementptr i8, i8* %uglygep, i64 1032
...
Now it genereates:
do.body.i:
%idxprom.i = sext i32 %shr.i to i64
%2 = bitcast %typeD* %s to i8*
%3 = shl i64 %idxprom.i, 2
%uglygep = getelementptr i8, i8* %2, i64 1032
%uglygep7 = getelementptr i8, i8* %uglygep, i64 %3
...
For no-loop cases, the original way of generating GEPs seems to
expose more CSE cases, so we don't change the logic for no-loop
cases, and only limit our change to the specific case we are
interested in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248420
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Akira Hatanaka [Wed, 23 Sep 2015 18:40:57 +0000 (18:40 +0000)]
[InstCombine] Preserve metadata when merging loads that are phi
arguments.
Make sure InstCombiner::FoldPHIArgLoadIntoPHI doesn't drop the following
metadata:
MD_tbaa
MD_alias_scope
MD_noalias
MD_invariant_load
MD_nonnull
MD_range
rdar://problem/
17617709
Differential Revision: http://reviews.llvm.org/D12710
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248419
91177308-0d34-0410-b5e6-
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Philip Reames [Wed, 23 Sep 2015 18:39:37 +0000 (18:39 +0000)]
[docs] Update DominatorTree docs to clarify expectations around unreachable blocks
Note: I'm am not trying to describe what "should be"; I'm only describing what is true today.
This came out of my recent question to llvm-dev titled: When can the dominator tree not contain a node for a basic block?
Differential Revision: http://reviews.llvm.org/D13078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248417
91177308-0d34-0410-b5e6-
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Sanjay Patel [Wed, 23 Sep 2015 18:33:42 +0000 (18:33 +0000)]
[x86] replace integer 'xor' ops with packed SSE FP 'xor' ops when operating on FP scalars
Turn this:
movd %xmm0, %eax
movd %xmm1, %ecx
xorl %eax, %ecx
movd %ecx, %xmm0
into this:
xorps %xmm1, %xmm0
This is related to, but does not solve:
https://llvm.org/bugs/show_bug.cgi?id=22428
This is an extension of:
http://reviews.llvm.org/rL248395
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248415
91177308-0d34-0410-b5e6-
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Sanjay Patel [Wed, 23 Sep 2015 18:19:07 +0000 (18:19 +0000)]
[x86] replace integer 'or' ops with packed SSE FP 'or' ops when operating on FP scalars
Turn this:
movd %xmm0, %eax
movd %xmm1, %ecx
orl %eax, %ecx
movd %ecx, %xmm0
into this:
orps %xmm1, %xmm0
This is related to, but does not solve:
https://llvm.org/bugs/show_bug.cgi?id=22428
This is an extension of:
http://reviews.llvm.org/rL248395
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248409
91177308-0d34-0410-b5e6-
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Adrian Prantl [Wed, 23 Sep 2015 18:09:01 +0000 (18:09 +0000)]
Fix the order of operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248406
91177308-0d34-0410-b5e6-
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Evgeniy Stepanov [Wed, 23 Sep 2015 18:07:56 +0000 (18:07 +0000)]
Android support for SafeStack.
Add two new ways of accessing the unsafe stack pointer:
* At a fixed offset from the thread TLS base. This is very similar to
StackProtector cookies, but we plan to extend it to other backends
(ARM in particular) soon. Bionic-side implementation here:
https://android-review.googlesource.com/170988.
* Via a function call, as a fallback for platforms that provide
neither a fixed TLS slot, nor a reasonable TLS implementation (i.e.
not emutls).
This is a re-commit of a change in r248357 that was reverted in
r248358.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248405
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Sanjay Patel [Wed, 23 Sep 2015 18:03:37 +0000 (18:03 +0000)]
move call to convertIntLogicToFPLogic up; NFCI
The BEXTR comments didn't make sense before, we may want to extend the
FP logic transform to work on vectors, and this way is more beautiful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248404
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Adrian Prantl [Wed, 23 Sep 2015 17:59:45 +0000 (17:59 +0000)]
Temporarily make testcase more verbose to debug a msvc buildbot failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248403
91177308-0d34-0410-b5e6-
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Chen Li [Wed, 23 Sep 2015 17:58:44 +0000 (17:58 +0000)]
[Bug 24848] Use range metadata to constant fold comparisons with constant values
Summary:
This is the first part of fixing bug 24848 https://llvm.org/bugs/show_bug.cgi?id=24848.
When range metadata is provided, it should be used to constant fold comparisons with constant values.
Reviewers: sanjoy, hfinkel
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D12988
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248402
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Sanjay Patel [Wed, 23 Sep 2015 17:39:41 +0000 (17:39 +0000)]
[x86] move code for converting int logic to FP logic to a helper function; NFCI
This is a follow-on to:
http://reviews.llvm.org/rL248395
so we can add the call to the or/xor combines too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248399
91177308-0d34-0410-b5e6-
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Adrian Prantl [Wed, 23 Sep 2015 17:35:52 +0000 (17:35 +0000)]
dsymutil: Resolve forward decls for types defined in clang modules.
This patch extends llvm-dsymutil's ODR type uniquing machinery to also
resolve forward decls for types defined in clang modules.
http://reviews.llvm.org/D13038
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248398
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Adrian Prantl [Wed, 23 Sep 2015 17:11:10 +0000 (17:11 +0000)]
dsymutil: print a warning when there is a module hash mismatch.
This also updates the module binaries in the test directory because
their module hash mismatched.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248396
91177308-0d34-0410-b5e6-
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Sanjay Patel [Wed, 23 Sep 2015 17:00:06 +0000 (17:00 +0000)]
[x86] replace integer 'and' ops with packed SSE FP 'and' ops when operating on FP scalars
Turn this:
movd %xmm0, %eax
movd %xmm1, %ecx
andl %eax, %ecx
movd %ecx, %xmm0
into this:
andps %xmm1, %xmm0
This is related to, but does not solve:
https://llvm.org/bugs/show_bug.cgi?id=22428
Differential Revision: http://reviews.llvm.org/D13065
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248395
91177308-0d34-0410-b5e6-
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Dan Gohman [Wed, 23 Sep 2015 16:59:10 +0000 (16:59 +0000)]
[WebAssembly] Fix hasAddr64 being used before being initializer.
This reverts r248388 and fixes the underlying bug: hasAddr64 was initialized
in runOnMachineFunction, but runOnMachineFunction isn't ever called in
CodeGen/WebAssembly/global.ll since that testcase has no functions. The fix
here is to use AsmPrinter's getPointerSize() as needed to determine the
pointer size instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248394
91177308-0d34-0410-b5e6-
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Vedant Kumar [Wed, 23 Sep 2015 15:49:08 +0000 (15:49 +0000)]
[Inline] Use AssumptionCache from the right Function
This changes the behavior of AddAligntmentAssumptions to match its
comment. I.e, prove the asserted alignment in the context of the caller,
not the callee.
Thanks to Mehdi Amini for seeing the issue here! Also to Artur Pilipenko
who also saw a fix for the issue.
rdar://
22521387
Differential Revision: http://reviews.llvm.org/D12997
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248390
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Alexander Kornienko [Wed, 23 Sep 2015 15:41:25 +0000 (15:41 +0000)]
Fix CodeGen/WebAssembly/global.ll test under ASAN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248388
91177308-0d34-0410-b5e6-
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David Majnemer [Wed, 23 Sep 2015 15:41:09 +0000 (15:41 +0000)]
[DeadArgElim] Split the invoke successor edge
Invoking a function which returns an aggregate can sometimes be
transformed to return a scalar value. However, this means that we need
to create an insertvalue instruction(s) to recreate the correct
aggregate type. We achieved this by inserting an insertvalue
instruction at the invoke's normal successor. However, this is not
feasible if the normal successor uses the invoke's return value inside a
PHI node.
Instead, split the edge between the invoke and the unwind successor and
create the insertvalue instruction in the new basic block. The new
basic block's successor will be the old invoke successor which leaves
us with IR which is well behaved.
This fixes PR24906.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248387
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Chad Rosier [Wed, 23 Sep 2015 13:51:44 +0000 (13:51 +0000)]
[AArch64] Refactor pre- and post-index merge fuctions into a single function. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248377
91177308-0d34-0410-b5e6-
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Igor Laevsky [Wed, 23 Sep 2015 11:38:44 +0000 (11:38 +0000)]
[DeadStoreElimination] Remove dead zero store to calloc initialized memory
This change allows dead store elimination to remove zero and null stores into memory freshly allocated with calloc-like function.
Differential Revision: http://reviews.llvm.org/D13021
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248374
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Benjamin Kramer [Wed, 23 Sep 2015 10:38:59 +0000 (10:38 +0000)]
[dsymutil] Plug a memory leak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248372
91177308-0d34-0410-b5e6-
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Oliver Stannard [Wed, 23 Sep 2015 09:19:54 +0000 (09:19 +0000)]
[ARM] Add option to force fast-isel
The ARM backend has some logic that only allows the fast-isel to be enabled for
subtargets where it is known to be stable. This adds a backend option to
override this and force the fast-isel to be used for any target, to allow it to
be tested.
This is an ARM-specific option, because no other backend disables the fast-isel
on a per-subtarget basis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248369
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 23 Sep 2015 08:48:33 +0000 (08:48 +0000)]
[X86][SSE] Replace 128-bit SSE41 PMOVSX intrinsics with native IR
This patches removes the x86.sse41.pmovsx* intrinsics, provides a suitable upgrade path and updates relevant tests to sign extend a subvector instead.
LLVM counterpart to D12835
Differential Revision: http://reviews.llvm.org/D13002
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248368
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Sanjoy Das [Wed, 23 Sep 2015 01:59:04 +0000 (01:59 +0000)]
[SCEV] Introduce ScalarEvolution::getOne and getZero.
Summary:
It is fairly common to call SE->getConstant(Ty, 0) or
SE->getConstant(Ty, 1); this change makes such uses a little bit
briefer.
I've refactored the call sites I could find easily to use getZero /
getOne.
Reviewers: hfinkel, majnemer, reames
Subscribers: sanjoy, llvm-commits
Differential Revision: http://reviews.llvm.org/D12947
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248362
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Evgeniy Stepanov [Wed, 23 Sep 2015 01:23:22 +0000 (01:23 +0000)]
Revert "Android support for SafeStack."
test/Transforms/SafeStack/abi.ll breaks when target is not supported;
needs refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248358
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Evgeniy Stepanov [Wed, 23 Sep 2015 01:03:51 +0000 (01:03 +0000)]
Android support for SafeStack.
Add two new ways of accessing the unsafe stack pointer:
* At a fixed offset from the thread TLS base. This is very similar to
StackProtector cookies, but we plan to extend it to other backends
(ARM in particular) soon. Bionic-side implementation here:
https://android-review.googlesource.com/170988.
* Via a function call, as a fallback for platforms that provide
neither a fixed TLS slot, nor a reasonable TLS implementation (i.e.
not emutls).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248357
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Cong Hou [Wed, 23 Sep 2015 00:34:56 +0000 (00:34 +0000)]
Add a test case for the fix of profile update issue when lowering switch statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248356
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Cong Hou [Wed, 23 Sep 2015 00:20:27 +0000 (00:20 +0000)]
Fixed an issue on updating profile data when lowering switch statement.
Fixed the issue that when there is an edge from the jump table to the default statement, we should check it directly instead of checking if the sibling of the jump table header is a successor of the jump table header, which may not be the default statment but a successor of it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248354
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